src/hotspot/share/c1/c1_LinearScan.cpp

*** 1,7 ****
--- 1,8 ----
  /*
   * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
+  * Copyright (c) 2015-2018, Azul Systems, Inc. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 177,202 ****
  bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
    return i->reg_num() < LinearScan::nof_cpu_regs;
  }
  
  bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
! #if defined(__SOFTFP__) || defined(E500V2)
    return i->reg_num() >= LIR_OprDesc::vreg_base;
  #else
!   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
  #endif // __SOFTFP__ or E500V2
  }
  
  bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
    return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
  }
  
  bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
! #if defined(__SOFTFP__) || defined(E500V2)
    return false;
  #else
!   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
  #endif // __SOFTFP__ or E500V2
  }
  
  bool LinearScan::is_in_fpu_register(const Interval* i) {
    // fixed intervals not needed for FPU stack allocation
--- 178,203 ----
  bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
    return i->reg_num() < LinearScan::nof_cpu_regs;
  }
  
  bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
! #if !defined(AARCH32) && (defined(__SOFTFP__) || defined(E500V2))
    return i->reg_num() >= LIR_OprDesc::vreg_base;
  #else
!   return i->reg_num() >= LIR_OprDesc::vreg_base && (AARCH32_ONLY(!hasFPU() ||) (i->type() != T_FLOAT && i->type() != T_DOUBLE));
  #endif // __SOFTFP__ or E500V2
  }
  
  bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
    return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
  }
  
  bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
! #if !defined(AARCH32) && (defined(__SOFTFP__) || defined(E500V2))
    return false;
  #else
!   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE) AARCH32_ONLY(&& hasFPU());
  #endif // __SOFTFP__ or E500V2
  }
  
  bool LinearScan::is_in_fpu_register(const Interval* i) {
    // fixed intervals not needed for FPU stack allocation
*** 2098,2116 ****
--- 2099,2132 ----
          return LIR_OprFact::single_cpu_metadata(assigned_reg);
        }
  
  #ifdef __SOFTFP__
        case T_FLOAT:  // fall through
+ #if defined(AARCH32)
+       if(hasFPU()) {
+         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
+         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
+         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
+       }
+ #endif
  #endif // __SOFTFP__
        case T_INT: {
          assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
          assert(interval->assigned_regHi() == any_reg, "must not have hi register");
          return LIR_OprFact::single_cpu(assigned_reg);
        }
  
  #ifdef __SOFTFP__
        case T_DOUBLE:  // fall through
+ #if defined(AARCH32)
+         if(hasFPU()) {
+             assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
+             assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
+             assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
+             return LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
+         }
+ #endif
  #endif // __SOFTFP__
        case T_LONG: {
          int assigned_regHi = interval->assigned_regHi();
          assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
          assert(num_physical_regs(T_LONG) == 1 ||
*** 2174,2184 ****
  #ifdef SPARC
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
! #elif defined(ARM32)
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
  #else
--- 2190,2200 ----
  #ifdef SPARC
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
! #elif defined(ARM32) || defined(AARCH32)
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
  #else
*** 2772,2782 ****
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef SPARC
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
  #endif
! #ifdef ARM32
        assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef PPC32
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
  #endif
--- 2788,2798 ----
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef SPARC
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
  #endif
! #if defined(ARM32) || defined(AARCH32)
        assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef PPC32
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
  #endif