1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "runtime/java.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "vm_version_aarch64.hpp"
  33 #ifdef TARGET_OS_FAMILY_linux
  34 # include "os_linux.inline.hpp"
  35 #endif
  36 
  37 #ifndef BUILTIN_SIM
  38 #include <sys/auxv.h>
  39 #include <asm/hwcap.h>
  40 #else
  41 #define getauxval(hwcap) 0
  42 #endif
  43 
  44 #ifndef HWCAP_AES
  45 #define HWCAP_AES   (1<<3)
  46 #endif
  47 
  48 #ifndef HWCAP_SHA1
  49 #define HWCAP_SHA1  (1<<5)
  50 #endif
  51 
  52 #ifndef HWCAP_SHA2
  53 #define HWCAP_SHA2  (1<<6)
  54 #endif
  55 
  56 #ifndef HWCAP_CRC32
  57 #define HWCAP_CRC32 (1<<7)
  58 #endif
  59 
  60 int VM_Version::_cpu;
  61 int VM_Version::_model;
  62 int VM_Version::_stepping;
  63 int VM_Version::_cpuFeatures;
  64 const char*           VM_Version::_features_str = "";
  65 
  66 static BufferBlob* stub_blob;
  67 static const int stub_size = 550;
  68 
  69 extern "C" {
  70   typedef void (*getPsrInfo_stub_t)(void*);
  71 }
  72 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
  73 
  74 
  75 class VM_Version_StubGenerator: public StubCodeGenerator {
  76  public:
  77 
  78   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  79 
  80   address generate_getPsrInfo() {
  81     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
  82 #   define __ _masm->
  83     address start = __ pc();
  84 
  85 #ifdef BUILTIN_SIM
  86     __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
  87 #endif
  88 
  89     // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
  90 
  91     address entry = __ pc();
  92 
  93     // TODO : redefine fields in CpuidInfo and generate
  94     // code to fill them in
  95 
  96     __ ret(lr);
  97 
  98 #   undef __
  99 
 100     return start;
 101   }
 102 };
 103 
 104 
 105 void VM_Version::get_processor_features() {
 106   _supports_cx8 = true;
 107   _supports_atomic_getset4 = true;
 108   _supports_atomic_getadd4 = true;
 109   _supports_atomic_getset8 = true;
 110   _supports_atomic_getadd8 = true;
 111 
 112   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 113     FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
 114   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 115     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
 116   FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
 117   FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
 118   FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
 119   FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
 120 
 121   unsigned long auxv = getauxval(AT_HWCAP);
 122 
 123   char buf[512];
 124 
 125   strcpy(buf, "simd");
 126   if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
 127   if (auxv & HWCAP_AES)   strcat(buf, ", aes");
 128   if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
 129   if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
 130 
 131   _features_str = strdup(buf);
 132 
 133   if (FLAG_IS_DEFAULT(UseCRC32)) {
 134     UseCRC32 = (auxv & HWCAP_CRC32) != 0;
 135   }
 136   if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
 137     warning("UseCRC32 specified, but not supported on this CPU");
 138   }
 139   if (auxv & HWCAP_AES) {
 140     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
 141     UseAESIntrinsics =
 142         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
 143     if (UseAESIntrinsics && !UseAES) {
 144       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
 145       UseAES = true;
 146     }
 147   } else {
 148     if (UseAES) {
 149       warning("UseAES specified, but not supported on this CPU");
 150     }
 151     if (UseAESIntrinsics) {
 152       warning("UseAESIntrinsics specified, but not supported on this CPU");
 153     }
 154   }
 155 
 156   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 157     UseCRC32Intrinsics = true;
 158   }
 159 
 160   if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
 161     if (FLAG_IS_DEFAULT(UseSHA)) {
 162       FLAG_SET_DEFAULT(UseSHA, true);
 163     }
 164   } else if (UseSHA) {
 165     warning("SHA instructions are not available on this CPU");
 166     FLAG_SET_DEFAULT(UseSHA, false);
 167   }
 168 
 169   if (!UseSHA) {
 170     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 171     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 172     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 173   } else {
 174     if (auxv & HWCAP_SHA1) {
 175       if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 176         FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 177       }
 178     } else if (UseSHA1Intrinsics) {
 179       warning("SHA1 instruction is not available on this CPU.");
 180       FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 181     }
 182     if (auxv & HWCAP_SHA2) {
 183       if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 184         FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 185       }
 186     } else if (UseSHA256Intrinsics) {
 187       warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
 188       FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 189     }
 190     if (UseSHA512Intrinsics) {
 191       warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
 192       FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 193     }
 194   }
 195 
 196 #ifdef COMPILER2
 197   if (FLAG_IS_DEFAULT(OptoScheduling)) {
 198     OptoScheduling = true;
 199   }
 200 #endif
 201 }
 202 
 203 void VM_Version::initialize() {
 204   ResourceMark rm;
 205 
 206   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
 207   if (stub_blob == NULL) {
 208     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
 209   }
 210 
 211   CodeBuffer c(stub_blob);
 212   VM_Version_StubGenerator g(&c);
 213   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
 214                                    g.generate_getPsrInfo());
 215 
 216   get_processor_features();
 217 }