1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.hpp" 30 31 // MacroAssembler extends Assembler by frequently used macros. 32 // 33 // Instructions for which a 'better' code sequence exists depending 34 // on arguments should also go in here. 35 36 class MacroAssembler: public Assembler { 37 friend class LIR_Assembler; 38 39 using Assembler::mov; 40 41 protected: 42 43 // Support for VM calls 44 // 45 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 46 // may customize this version by overriding it for its purposes (e.g., to save/restore 47 // additional registers when doing a VM call). 48 #ifdef CC_INTERP 49 // c++ interpreter never wants to use interp_masm version of call_VM 50 #define VIRTUAL 51 #else 52 #define VIRTUAL virtual 53 #endif 54 55 VIRTUAL void call_VM_leaf_base( 56 address entry_point, // the entry point 57 int number_of_arguments, // the number of arguments to pop after the call 58 Label *retaddr = NULL 59 ); 60 61 VIRTUAL void call_VM_leaf_base( 62 address entry_point, // the entry point 63 int number_of_arguments, // the number of arguments to pop after the call 64 Label &retaddr) { 65 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 66 } 67 68 // This is the base routine called by the different versions of call_VM. The interpreter 69 // may customize this version by overriding it for its purposes (e.g., to save/restore 70 // additional registers when doing a VM call). 71 // 72 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 73 // returns the register which contains the thread upon return. If a thread register has been 74 // specified, the return value will correspond to that register. If no last_java_sp is specified 75 // (noreg) than rsp will be used instead. 76 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 77 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 78 Register java_thread, // the thread if computed before ; use noreg otherwise 79 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 80 address entry_point, // the entry point 81 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 82 bool check_exceptions // whether to check for pending exceptions after return 83 ); 84 85 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 86 // The implementation is only non-empty for the InterpreterMacroAssembler, 87 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 88 virtual void check_and_handle_popframe(Register java_thread); 89 virtual void check_and_handle_earlyret(Register java_thread); 90 91 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 92 93 // Maximum size of class area in Metaspace when compressed 94 uint64_t use_XOR_for_compressed_class_base; 95 96 public: 97 MacroAssembler(CodeBuffer* code) : Assembler(code) { 98 use_XOR_for_compressed_class_base 99 = (operand_valid_for_logical_immediate(false /*is32*/, 100 (uint64_t)Universe::narrow_klass_base()) 101 && ((uint64_t)Universe::narrow_klass_base() 102 > (1u << log2_intptr(CompressedClassSpaceSize)))); 103 } 104 105 // Biased locking support 106 // lock_reg and obj_reg must be loaded up with the appropriate values. 107 // swap_reg is killed. 108 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 109 // be killed; if not supplied, push/pop will be used internally to 110 // allocate a temporary (inefficient, avoid if possible). 111 // Optional slow case is for implementations (interpreter and C1) which branch to 112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 113 // Returns offset of first potentially-faulting instruction for null 114 // check info (currently consumed only by C1). If 115 // swap_reg_contains_mark is true then returns -1 as it is assumed 116 // the calling code has already passed any potential faults. 117 int biased_locking_enter(Register lock_reg, Register obj_reg, 118 Register swap_reg, Register tmp_reg, 119 bool swap_reg_contains_mark, 120 Label& done, Label* slow_case = NULL, 121 BiasedLockingCounters* counters = NULL); 122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 123 124 125 // Helper functions for statistics gathering. 126 // Unconditional atomic increment. 127 void atomic_incw(Register counter_addr, Register tmp); 128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) { 129 lea(tmp1, counter_addr); 130 atomic_incw(tmp1, tmp2); 131 } 132 // Load Effective Address 133 void lea(Register r, const Address &a) { 134 InstructionMark im(this); 135 code_section()->relocate(inst_mark(), a.rspec()); 136 a.lea(this, r); 137 } 138 139 void addmw(Address a, Register incr, Register scratch) { 140 ldrw(scratch, a); 141 addw(scratch, scratch, incr); 142 strw(scratch, a); 143 } 144 145 // Add constant to memory word 146 void addmw(Address a, int imm, Register scratch) { 147 ldrw(scratch, a); 148 if (imm > 0) 149 addw(scratch, scratch, (unsigned)imm); 150 else 151 subw(scratch, scratch, (unsigned)-imm); 152 strw(scratch, a); 153 } 154 155 // Frame creation and destruction shared between JITs. 156 void build_frame(int framesize); 157 void remove_frame(int framesize); 158 159 virtual void _call_Unimplemented(address call_site) { 160 mov(rscratch2, call_site); 161 haltsim(); 162 } 163 164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 165 166 virtual void notify(int type); 167 168 // aliases defined in AARCH64 spec 169 170 template<class T> 171 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 172 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); } 173 174 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } 175 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } 176 177 void cset(Register Rd, Assembler::Condition cond) { 178 csinc(Rd, zr, zr, ~cond); 179 } 180 void csetw(Register Rd, Assembler::Condition cond) { 181 csincw(Rd, zr, zr, ~cond); 182 } 183 184 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 185 csneg(Rd, Rn, Rn, ~cond); 186 } 187 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 188 csnegw(Rd, Rn, Rn, ~cond); 189 } 190 191 inline void movw(Register Rd, Register Rn) { 192 if (Rd == sp || Rn == sp) { 193 addw(Rd, Rn, 0U); 194 } else { 195 orrw(Rd, zr, Rn); 196 } 197 } 198 inline void mov(Register Rd, Register Rn) { 199 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 200 if (Rd == Rn) { 201 } else if (Rd == sp || Rn == sp) { 202 add(Rd, Rn, 0U); 203 } else { 204 orr(Rd, zr, Rn); 205 } 206 } 207 208 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 209 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 210 211 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); } 212 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); } 213 214 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 215 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 216 } 217 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 218 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 219 } 220 221 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 222 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 223 } 224 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 225 bfm(Rd, Rn, lsb , (lsb + width - 1)); 226 } 227 228 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 229 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 230 } 231 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 232 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 233 } 234 235 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 236 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 237 } 238 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 239 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 240 } 241 242 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 243 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 244 } 245 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 246 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 247 } 248 249 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 250 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 251 } 252 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 253 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 254 } 255 256 inline void asrw(Register Rd, Register Rn, unsigned imm) { 257 sbfmw(Rd, Rn, imm, 31); 258 } 259 260 inline void asr(Register Rd, Register Rn, unsigned imm) { 261 sbfm(Rd, Rn, imm, 63); 262 } 263 264 inline void lslw(Register Rd, Register Rn, unsigned imm) { 265 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 266 } 267 268 inline void lsl(Register Rd, Register Rn, unsigned imm) { 269 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 270 } 271 272 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 273 ubfmw(Rd, Rn, imm, 31); 274 } 275 276 inline void lsr(Register Rd, Register Rn, unsigned imm) { 277 ubfm(Rd, Rn, imm, 63); 278 } 279 280 inline void rorw(Register Rd, Register Rn, unsigned imm) { 281 extrw(Rd, Rn, Rn, imm); 282 } 283 284 inline void ror(Register Rd, Register Rn, unsigned imm) { 285 extr(Rd, Rn, Rn, imm); 286 } 287 288 inline void sxtbw(Register Rd, Register Rn) { 289 sbfmw(Rd, Rn, 0, 7); 290 } 291 inline void sxthw(Register Rd, Register Rn) { 292 sbfmw(Rd, Rn, 0, 15); 293 } 294 inline void sxtb(Register Rd, Register Rn) { 295 sbfm(Rd, Rn, 0, 7); 296 } 297 inline void sxth(Register Rd, Register Rn) { 298 sbfm(Rd, Rn, 0, 15); 299 } 300 inline void sxtw(Register Rd, Register Rn) { 301 sbfm(Rd, Rn, 0, 31); 302 } 303 304 inline void uxtbw(Register Rd, Register Rn) { 305 ubfmw(Rd, Rn, 0, 7); 306 } 307 inline void uxthw(Register Rd, Register Rn) { 308 ubfmw(Rd, Rn, 0, 15); 309 } 310 inline void uxtb(Register Rd, Register Rn) { 311 ubfm(Rd, Rn, 0, 7); 312 } 313 inline void uxth(Register Rd, Register Rn) { 314 ubfm(Rd, Rn, 0, 15); 315 } 316 inline void uxtw(Register Rd, Register Rn) { 317 ubfm(Rd, Rn, 0, 31); 318 } 319 320 inline void cmnw(Register Rn, Register Rm) { 321 addsw(zr, Rn, Rm); 322 } 323 inline void cmn(Register Rn, Register Rm) { 324 adds(zr, Rn, Rm); 325 } 326 327 inline void cmpw(Register Rn, Register Rm) { 328 subsw(zr, Rn, Rm); 329 } 330 inline void cmp(Register Rn, Register Rm) { 331 subs(zr, Rn, Rm); 332 } 333 334 inline void negw(Register Rd, Register Rn) { 335 subw(Rd, zr, Rn); 336 } 337 338 inline void neg(Register Rd, Register Rn) { 339 sub(Rd, zr, Rn); 340 } 341 342 inline void negsw(Register Rd, Register Rn) { 343 subsw(Rd, zr, Rn); 344 } 345 346 inline void negs(Register Rd, Register Rn) { 347 subs(Rd, zr, Rn); 348 } 349 350 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 351 addsw(zr, Rn, Rm, kind, shift); 352 } 353 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 354 adds(zr, Rn, Rm, kind, shift); 355 } 356 357 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 358 subsw(zr, Rn, Rm, kind, shift); 359 } 360 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 361 subs(zr, Rn, Rm, kind, shift); 362 } 363 364 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 365 subw(Rd, zr, Rn, kind, shift); 366 } 367 368 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 369 sub(Rd, zr, Rn, kind, shift); 370 } 371 372 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 373 subsw(Rd, zr, Rn, kind, shift); 374 } 375 376 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 377 subs(Rd, zr, Rn, kind, shift); 378 } 379 380 inline void mnegw(Register Rd, Register Rn, Register Rm) { 381 msubw(Rd, Rn, Rm, zr); 382 } 383 inline void mneg(Register Rd, Register Rn, Register Rm) { 384 msub(Rd, Rn, Rm, zr); 385 } 386 387 inline void mulw(Register Rd, Register Rn, Register Rm) { 388 maddw(Rd, Rn, Rm, zr); 389 } 390 inline void mul(Register Rd, Register Rn, Register Rm) { 391 madd(Rd, Rn, Rm, zr); 392 } 393 394 inline void smnegl(Register Rd, Register Rn, Register Rm) { 395 smsubl(Rd, Rn, Rm, zr); 396 } 397 inline void smull(Register Rd, Register Rn, Register Rm) { 398 smaddl(Rd, Rn, Rm, zr); 399 } 400 401 inline void umnegl(Register Rd, Register Rn, Register Rm) { 402 umsubl(Rd, Rn, Rm, zr); 403 } 404 inline void umull(Register Rd, Register Rn, Register Rm) { 405 umaddl(Rd, Rn, Rm, zr); 406 } 407 408 // macro assembly operations needed for aarch64 409 410 // first two private routines for loading 32 bit or 64 bit constants 411 private: 412 413 void mov_immediate64(Register dst, u_int64_t imm64); 414 void mov_immediate32(Register dst, u_int32_t imm32); 415 416 int push(unsigned int bitset, Register stack); 417 int pop(unsigned int bitset, Register stack); 418 419 void mov(Register dst, Address a); 420 421 public: 422 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 423 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 424 425 // now mov instructions for loading absolute addresses and 32 or 426 // 64 bit integers 427 428 inline void mov(Register dst, address addr) 429 { 430 mov_immediate64(dst, (u_int64_t)addr); 431 } 432 433 inline void mov(Register dst, u_int64_t imm64) 434 { 435 mov_immediate64(dst, imm64); 436 } 437 438 inline void movw(Register dst, u_int32_t imm32) 439 { 440 mov_immediate32(dst, imm32); 441 } 442 443 inline void mov(Register dst, long l) 444 { 445 mov(dst, (u_int64_t)l); 446 } 447 448 inline void mov(Register dst, int i) 449 { 450 mov(dst, (long)i); 451 } 452 453 void movptr(Register r, uintptr_t imm64); 454 455 // macro instructions for accessing and updating floating point 456 // status register 457 // 458 // FPSR : op1 == 011 459 // CRn == 0100 460 // CRm == 0100 461 // op2 == 001 462 463 inline void get_fpsr(Register reg) 464 { 465 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 466 } 467 468 inline void set_fpsr(Register reg) 469 { 470 msr(0b011, 0b0100, 0b0100, 0b001, reg); 471 } 472 473 inline void clear_fpsr() 474 { 475 msr(0b011, 0b0100, 0b0100, 0b001, zr); 476 } 477 478 // idiv variant which deals with MINLONG as dividend and -1 as divisor 479 int corrected_idivl(Register result, Register ra, Register rb, 480 bool want_remainder, Register tmp = rscratch1); 481 int corrected_idivq(Register result, Register ra, Register rb, 482 bool want_remainder, Register tmp = rscratch1); 483 484 // Support for NULL-checks 485 // 486 // Generates code that causes a NULL OS exception if the content of reg is NULL. 487 // If the accessed location is M[reg + offset] and the offset is known, provide the 488 // offset. No explicit code generation is needed if the offset is within a certain 489 // range (0 <= offset <= page_size). 490 491 virtual void null_check(Register reg, int offset = -1); 492 static bool needs_explicit_null_check(intptr_t offset); 493 494 static address target_addr_for_insn(address insn_addr, unsigned insn); 495 static address target_addr_for_insn(address insn_addr) { 496 unsigned insn = *(unsigned*)insn_addr; 497 return target_addr_for_insn(insn_addr, insn); 498 } 499 500 // Required platform-specific helpers for Label::patch_instructions. 501 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 502 static int pd_patch_instruction_size(address branch, address target); 503 static void pd_patch_instruction(address branch, address target) { 504 pd_patch_instruction_size(branch, target); 505 } 506 static address pd_call_destination(address branch) { 507 return target_addr_for_insn(branch); 508 } 509 #ifndef PRODUCT 510 static void pd_print_patched_instruction(address branch); 511 #endif 512 513 static int patch_oop(address insn_addr, address o); 514 515 void emit_trampoline_stub(int insts_call_instruction_offset, address target); 516 517 // The following 4 methods return the offset of the appropriate move instruction 518 519 // Support for fast byte/short loading with zero extension (depending on particular CPU) 520 int load_unsigned_byte(Register dst, Address src); 521 int load_unsigned_short(Register dst, Address src); 522 523 // Support for fast byte/short loading with sign extension (depending on particular CPU) 524 int load_signed_byte(Register dst, Address src); 525 int load_signed_short(Register dst, Address src); 526 527 int load_signed_byte32(Register dst, Address src); 528 int load_signed_short32(Register dst, Address src); 529 530 // Support for sign-extension (hi:lo = extend_sign(lo)) 531 void extend_sign(Register hi, Register lo); 532 533 // Load and store values by size and signed-ness 534 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 535 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 536 537 // Support for inc/dec with optimal instruction selection depending on value 538 539 // x86_64 aliases an unqualified register/address increment and 540 // decrement to call incrementq and decrementq but also supports 541 // explicitly sized calls to incrementq/decrementq or 542 // incrementl/decrementl 543 544 // for aarch64 the proper convention would be to use 545 // increment/decrement for 64 bit operatons and 546 // incrementw/decrementw for 32 bit operations. so when porting 547 // x86_64 code we can leave calls to increment/decrement as is, 548 // replace incrementq/decrementq with increment/decrement and 549 // replace incrementl/decrementl with incrementw/decrementw. 550 551 // n.b. increment/decrement calls with an Address destination will 552 // need to use a scratch register to load the value to be 553 // incremented. increment/decrement calls which add or subtract a 554 // constant value greater than 2^12 will need to use a 2nd scratch 555 // register to hold the constant. so, a register increment/decrement 556 // may trash rscratch2 and an address increment/decrement trash 557 // rscratch and rscratch2 558 559 void decrementw(Address dst, int value = 1); 560 void decrementw(Register reg, int value = 1); 561 562 void decrement(Register reg, int value = 1); 563 void decrement(Address dst, int value = 1); 564 565 void incrementw(Address dst, int value = 1); 566 void incrementw(Register reg, int value = 1); 567 568 void increment(Register reg, int value = 1); 569 void increment(Address dst, int value = 1); 570 571 572 // Alignment 573 void align(int modulus); 574 575 // Stack frame creation/removal 576 void enter() 577 { 578 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 579 mov(rfp, sp); 580 } 581 void leave() 582 { 583 mov(sp, rfp); 584 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 585 } 586 587 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 588 // The pointer will be loaded into the thread register. 589 void get_thread(Register thread); 590 591 592 // Support for VM calls 593 // 594 // It is imperative that all calls into the VM are handled via the call_VM macros. 595 // They make sure that the stack linkage is setup correctly. call_VM's correspond 596 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 597 598 599 void call_VM(Register oop_result, 600 address entry_point, 601 bool check_exceptions = true); 602 void call_VM(Register oop_result, 603 address entry_point, 604 Register arg_1, 605 bool check_exceptions = true); 606 void call_VM(Register oop_result, 607 address entry_point, 608 Register arg_1, Register arg_2, 609 bool check_exceptions = true); 610 void call_VM(Register oop_result, 611 address entry_point, 612 Register arg_1, Register arg_2, Register arg_3, 613 bool check_exceptions = true); 614 615 // Overloadings with last_Java_sp 616 void call_VM(Register oop_result, 617 Register last_java_sp, 618 address entry_point, 619 int number_of_arguments = 0, 620 bool check_exceptions = true); 621 void call_VM(Register oop_result, 622 Register last_java_sp, 623 address entry_point, 624 Register arg_1, bool 625 check_exceptions = true); 626 void call_VM(Register oop_result, 627 Register last_java_sp, 628 address entry_point, 629 Register arg_1, Register arg_2, 630 bool check_exceptions = true); 631 void call_VM(Register oop_result, 632 Register last_java_sp, 633 address entry_point, 634 Register arg_1, Register arg_2, Register arg_3, 635 bool check_exceptions = true); 636 637 void get_vm_result (Register oop_result, Register thread); 638 void get_vm_result_2(Register metadata_result, Register thread); 639 640 // These always tightly bind to MacroAssembler::call_VM_base 641 // bypassing the virtual implementation 642 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 643 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 644 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 645 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 646 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 647 648 void call_VM_leaf(address entry_point, 649 int number_of_arguments = 0); 650 void call_VM_leaf(address entry_point, 651 Register arg_1); 652 void call_VM_leaf(address entry_point, 653 Register arg_1, Register arg_2); 654 void call_VM_leaf(address entry_point, 655 Register arg_1, Register arg_2, Register arg_3); 656 657 // These always tightly bind to MacroAssembler::call_VM_leaf_base 658 // bypassing the virtual implementation 659 void super_call_VM_leaf(address entry_point); 660 void super_call_VM_leaf(address entry_point, Register arg_1); 661 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 662 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 663 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 664 665 // last Java Frame (fills frame anchor) 666 void set_last_Java_frame(Register last_java_sp, 667 Register last_java_fp, 668 address last_java_pc, 669 Register scratch); 670 671 void set_last_Java_frame(Register last_java_sp, 672 Register last_java_fp, 673 Label &last_java_pc, 674 Register scratch); 675 676 void set_last_Java_frame(Register last_java_sp, 677 Register last_java_fp, 678 Register last_java_pc, 679 Register scratch); 680 681 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc); 682 683 // thread in the default location (r15_thread on 64bit) 684 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 685 686 // Stores 687 void store_check(Register obj); // store check for obj - register is destroyed afterwards 688 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 689 690 #if INCLUDE_ALL_GCS 691 692 void g1_write_barrier_pre(Register obj, 693 Register pre_val, 694 Register thread, 695 Register tmp, 696 bool tosca_live, 697 bool expand_call); 698 699 void g1_write_barrier_post(Register store_addr, 700 Register new_val, 701 Register thread, 702 Register tmp, 703 Register tmp2); 704 705 #endif // INCLUDE_ALL_GCS 706 707 // split store_check(Register obj) to enhance instruction interleaving 708 void store_check_part_1(Register obj); 709 void store_check_part_2(Register obj); 710 711 // oop manipulations 712 void load_klass(Register dst, Register src); 713 void store_klass(Register dst, Register src); 714 void cmp_klass(Register oop, Register trial_klass, Register tmp); 715 716 void load_heap_oop(Register dst, Address src); 717 718 void load_heap_oop_not_null(Register dst, Address src); 719 void store_heap_oop(Address dst, Register src); 720 721 // currently unimplemented 722 // Used for storing NULL. All other oop constants should be 723 // stored using routines that take a jobject. 724 void store_heap_oop_null(Address dst); 725 726 void load_prototype_header(Register dst, Register src); 727 728 void store_klass_gap(Register dst, Register src); 729 730 // This dummy is to prevent a call to store_heap_oop from 731 // converting a zero (like NULL) into a Register by giving 732 // the compiler two choices it can't resolve 733 734 void store_heap_oop(Address dst, void* dummy); 735 736 void encode_heap_oop(Register d, Register s); 737 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 738 void decode_heap_oop(Register d, Register s); 739 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 740 void encode_heap_oop_not_null(Register r); 741 void decode_heap_oop_not_null(Register r); 742 void encode_heap_oop_not_null(Register dst, Register src); 743 void decode_heap_oop_not_null(Register dst, Register src); 744 745 void set_narrow_oop(Register dst, jobject obj); 746 747 void encode_klass_not_null(Register r); 748 void decode_klass_not_null(Register r); 749 void encode_klass_not_null(Register dst, Register src); 750 void decode_klass_not_null(Register dst, Register src); 751 752 void set_narrow_klass(Register dst, Klass* k); 753 754 // if heap base register is used - reinit it with the correct value 755 void reinit_heapbase(); 756 757 DEBUG_ONLY(void verify_heapbase(const char* msg);) 758 759 void push_CPU_state(); 760 void pop_CPU_state() ; 761 762 // Round up to a power of two 763 void round_to(Register reg, int modulus); 764 765 // allocation 766 void eden_allocate( 767 Register obj, // result: pointer to object after successful allocation 768 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 769 int con_size_in_bytes, // object size in bytes if known at compile time 770 Register t1, // temp register 771 Label& slow_case // continuation point if fast allocation fails 772 ); 773 void tlab_allocate( 774 Register obj, // result: pointer to object after successful allocation 775 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 776 int con_size_in_bytes, // object size in bytes if known at compile time 777 Register t1, // temp register 778 Register t2, // temp register 779 Label& slow_case // continuation point if fast allocation fails 780 ); 781 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 782 void verify_tlab(); 783 784 void incr_allocated_bytes(Register thread, 785 Register var_size_in_bytes, int con_size_in_bytes, 786 Register t1 = noreg); 787 788 // interface method calling 789 void lookup_interface_method(Register recv_klass, 790 Register intf_klass, 791 RegisterOrConstant itable_index, 792 Register method_result, 793 Register scan_temp, 794 Label& no_such_interface); 795 796 // virtual method calling 797 // n.b. x86 allows RegisterOrConstant for vtable_index 798 void lookup_virtual_method(Register recv_klass, 799 RegisterOrConstant vtable_index, 800 Register method_result); 801 802 // Test sub_klass against super_klass, with fast and slow paths. 803 804 // The fast path produces a tri-state answer: yes / no / maybe-slow. 805 // One of the three labels can be NULL, meaning take the fall-through. 806 // If super_check_offset is -1, the value is loaded up from super_klass. 807 // No registers are killed, except temp_reg. 808 void check_klass_subtype_fast_path(Register sub_klass, 809 Register super_klass, 810 Register temp_reg, 811 Label* L_success, 812 Label* L_failure, 813 Label* L_slow_path, 814 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 815 816 // The rest of the type check; must be wired to a corresponding fast path. 817 // It does not repeat the fast path logic, so don't use it standalone. 818 // The temp_reg and temp2_reg can be noreg, if no temps are available. 819 // Updates the sub's secondary super cache as necessary. 820 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 821 void check_klass_subtype_slow_path(Register sub_klass, 822 Register super_klass, 823 Register temp_reg, 824 Register temp2_reg, 825 Label* L_success, 826 Label* L_failure, 827 bool set_cond_codes = false); 828 829 // Simplified, combined version, good for typical uses. 830 // Falls through on failure. 831 void check_klass_subtype(Register sub_klass, 832 Register super_klass, 833 Register temp_reg, 834 Label& L_success); 835 836 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 837 838 839 // Debugging 840 841 // only if +VerifyOops 842 void verify_oop(Register reg, const char* s = "broken oop"); 843 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 844 845 // TODO: verify method and klass metadata (compare against vptr?) 846 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 847 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 848 849 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 850 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 851 852 // only if +VerifyFPU 853 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 854 855 // prints msg, dumps registers and stops execution 856 void stop(const char* msg); 857 858 // prints msg and continues 859 void warn(const char* msg); 860 861 static void debug64(char* msg, int64_t pc, int64_t regs[]); 862 863 void untested() { stop("untested"); } 864 865 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 866 867 void should_not_reach_here() { stop("should not reach here"); } 868 869 // Stack overflow checking 870 void bang_stack_with_offset(int offset) { 871 // stack grows down, caller passes positive offset 872 assert(offset > 0, "must bang with negative offset"); 873 mov(rscratch2, -offset); 874 str(zr, Address(sp, rscratch2)); 875 } 876 877 // Writes to stack successive pages until offset reached to check for 878 // stack overflow + shadow pages. Also, clobbers tmp 879 void bang_stack_size(Register size, Register tmp); 880 881 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 882 Register tmp, 883 int offset); 884 885 // Support for serializing memory accesses between threads 886 void serialize_memory(Register thread, Register tmp); 887 888 // Arithmetics 889 890 void addptr(Address dst, int32_t src) { 891 lea(rscratch2, dst); 892 ldr(rscratch1, Address(rscratch2)); 893 add(rscratch1, rscratch1, src); 894 str(rscratch1, Address(rscratch2)); 895 } 896 897 void cmpptr(Register src1, Address src2); 898 899 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 900 Label &suceed, Label *fail); 901 902 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 903 Label &suceed, Label *fail); 904 905 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 906 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 907 908 void atomic_xchg(Register prev, Register newv, Register addr); 909 void atomic_xchgw(Register prev, Register newv, Register addr); 910 911 void orptr(Address adr, RegisterOrConstant src) { 912 ldr(rscratch2, adr); 913 if (src.is_register()) 914 orr(rscratch2, rscratch2, src.as_register()); 915 else 916 orr(rscratch2, rscratch2, src.as_constant()); 917 str(rscratch2, adr); 918 } 919 920 // Calls 921 922 void trampoline_call(Address entry, CodeBuffer *cbuf = NULL); 923 924 static bool far_branches() { 925 return ReservedCodeCacheSize > branch_range; 926 } 927 928 // Jumps that can reach anywhere in the code cache. 929 // Trashes tmp. 930 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 931 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 932 933 static int far_branch_size() { 934 if (far_branches()) { 935 return 3 * 4; // adrp, add, br 936 } else { 937 return 4; 938 } 939 } 940 941 // Emit the CompiledIC call idiom 942 void ic_call(address entry); 943 944 public: 945 946 // Data 947 948 void mov_metadata(Register dst, Metadata* obj); 949 Address allocate_metadata_address(Metadata* obj); 950 Address constant_oop_address(jobject obj); 951 952 void movoop(Register dst, jobject obj, bool immediate = false); 953 954 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 955 void kernel_crc32(Register crc, Register buf, Register len, 956 Register table0, Register table1, Register table2, Register table3, 957 Register tmp, Register tmp2, Register tmp3); 958 959 #undef VIRTUAL 960 961 // Stack push and pop individual 64 bit registers 962 void push(Register src); 963 void pop(Register dst); 964 965 // push all registers onto the stack 966 void pusha(); 967 void popa(); 968 969 void repne_scan(Register addr, Register value, Register count, 970 Register scratch); 971 void repne_scanw(Register addr, Register value, Register count, 972 Register scratch); 973 974 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 975 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 976 977 // If a constant does not fit in an immediate field, generate some 978 // number of MOV instructions and then perform the operation 979 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 980 add_sub_imm_insn insn1, 981 add_sub_reg_insn insn2); 982 // Seperate vsn which sets the flags 983 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 984 add_sub_imm_insn insn1, 985 add_sub_reg_insn insn2); 986 987 #define WRAP(INSN) \ 988 void INSN(Register Rd, Register Rn, unsigned imm) { \ 989 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 990 } \ 991 \ 992 void INSN(Register Rd, Register Rn, Register Rm, \ 993 enum shift_kind kind, unsigned shift = 0) { \ 994 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 995 } \ 996 \ 997 void INSN(Register Rd, Register Rn, Register Rm) { \ 998 Assembler::INSN(Rd, Rn, Rm); \ 999 } \ 1000 \ 1001 void INSN(Register Rd, Register Rn, Register Rm, \ 1002 ext::operation option, int amount = 0) { \ 1003 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1004 } 1005 1006 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) 1007 1008 #undef WRAP 1009 #define WRAP(INSN) \ 1010 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1011 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1012 } \ 1013 \ 1014 void INSN(Register Rd, Register Rn, Register Rm, \ 1015 enum shift_kind kind, unsigned shift = 0) { \ 1016 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1017 } \ 1018 \ 1019 void INSN(Register Rd, Register Rn, Register Rm) { \ 1020 Assembler::INSN(Rd, Rn, Rm); \ 1021 } \ 1022 \ 1023 void INSN(Register Rd, Register Rn, Register Rm, \ 1024 ext::operation option, int amount = 0) { \ 1025 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1026 } 1027 1028 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) 1029 1030 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1031 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1032 1033 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); 1034 1035 void tableswitch(Register index, jint lowbound, jint highbound, 1036 Label &jumptable, Label &jumptable_end, int stride = 1) { 1037 adr(rscratch1, jumptable); 1038 subsw(rscratch2, index, lowbound); 1039 subsw(zr, rscratch2, highbound - lowbound); 1040 br(Assembler::HS, jumptable_end); 1041 add(rscratch1, rscratch1, rscratch2, 1042 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1043 br(rscratch1); 1044 } 1045 1046 // Form an address from base + offset in Rd. Rd may or may not 1047 // actually be used: you must use the Address that is returned. It 1048 // is up to you to ensure that the shift provided matches the size 1049 // of your data. 1050 Address form_address(Register Rd, Register base, long byte_offset, int shift); 1051 1052 // Prolog generator routines to support switch between x86 code and 1053 // generated ARM code 1054 1055 // routine to generate an x86 prolog for a stub function which 1056 // bootstraps into the generated ARM code which directly follows the 1057 // stub 1058 // 1059 1060 public: 1061 // enum used for aarch64--x86 linkage to define return type of x86 function 1062 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; 1063 1064 #ifdef BUILTIN_SIM 1065 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); 1066 #else 1067 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } 1068 #endif 1069 1070 // special version of call_VM_leaf_base needed for aarch64 simulator 1071 // where we need to specify both the gp and fp arg counts and the 1072 // return type so that the linkage routine from aarch64 to x86 and 1073 // back knows which aarch64 registers to copy to x86 registers and 1074 // which x86 result register to copy back to an aarch64 register 1075 1076 void call_VM_leaf_base1( 1077 address entry_point, // the entry point 1078 int number_of_gp_arguments, // the number of gp reg arguments to pass 1079 int number_of_fp_arguments, // the number of fp reg arguments to pass 1080 ret_type type, // the return type for the call 1081 Label* retaddr = NULL 1082 ); 1083 1084 void ldr_constant(Register dest, const Address &const_addr) { 1085 if (NearCpool) { 1086 ldr(dest, const_addr); 1087 } else { 1088 unsigned long offset; 1089 adrp(dest, InternalAddress(const_addr.target()), offset); 1090 ldr(dest, Address(dest, offset)); 1091 } 1092 } 1093 1094 address read_polling_page(Register r, address page, relocInfo::relocType rtype); 1095 address read_polling_page(Register r, relocInfo::relocType rtype); 1096 1097 // Used by aarch64.ad to control code generation 1098 static bool use_acq_rel_for_volatile_fields(); 1099 1100 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1101 void update_byte_crc32(Register crc, Register val, Register table); 1102 void update_word_crc32(Register crc, Register v, Register tmp, 1103 Register table0, Register table1, Register table2, Register table3, 1104 bool upper = false); 1105 1106 void string_compare(Register str1, Register str2, 1107 Register cnt1, Register cnt2, Register result, 1108 Register tmp1); 1109 void string_equals(Register str1, Register str2, 1110 Register cnt, Register result, 1111 Register tmp1); 1112 void char_arrays_equals(Register ary1, Register ary2, 1113 Register result, Register tmp1); 1114 void encode_iso_array(Register src, Register dst, 1115 Register len, Register result, 1116 FloatRegister Vtmp1, FloatRegister Vtmp2, 1117 FloatRegister Vtmp3, FloatRegister Vtmp4); 1118 void string_indexof(Register str1, Register str2, 1119 Register cnt1, Register cnt2, 1120 Register tmp1, Register tmp2, 1121 Register tmp3, Register tmp4, 1122 int int_cnt1, Register result); 1123 private: 1124 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1125 Register src1, Register src2); 1126 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1127 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1128 } 1129 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1130 Register y, Register y_idx, Register z, 1131 Register carry, Register product, 1132 Register idx, Register kdx); 1133 void multiply_128_x_128_loop(Register y, Register z, 1134 Register carry, Register carry2, 1135 Register idx, Register jdx, 1136 Register yz_idx1, Register yz_idx2, 1137 Register tmp, Register tmp3, Register tmp4, 1138 Register tmp7, Register product_hi); 1139 public: 1140 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1141 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1142 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1143 // ISB may be needed because of a safepoint 1144 void maybe_isb() { isb(); } 1145 1146 private: 1147 // Return the effective address r + (r1 << ext) + offset. 1148 // Uses rscratch2. 1149 Address offsetted_address(Register r, Register r1, Address::extend ext, 1150 int offset, int size); 1151 }; 1152 1153 // Used by aarch64.ad to control code generation 1154 #define treat_as_volatile(MEM_NODE) \ 1155 (MacroAssembler::use_acq_rel_for_volatile_fields() ? (MEM_NODE)->is_volatile() : false) 1156 1157 #ifdef ASSERT 1158 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1159 #endif 1160 1161 /** 1162 * class SkipIfEqual: 1163 * 1164 * Instantiating this class will result in assembly code being output that will 1165 * jump around any code emitted between the creation of the instance and it's 1166 * automatic destruction at the end of a scope block, depending on the value of 1167 * the flag passed to the constructor, which will be checked at run-time. 1168 */ 1169 class SkipIfEqual { 1170 private: 1171 MacroAssembler* _masm; 1172 Label _label; 1173 1174 public: 1175 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1176 ~SkipIfEqual(); 1177 }; 1178 1179 struct tableswitch { 1180 Register _reg; 1181 int _insn_index; jint _first_key; jint _last_key; 1182 Label _after; 1183 Label _branches; 1184 }; 1185 1186 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP