src/cpu/aarch64/vm/assembler_aarch64.hpp

rev 8896 : 8134869: AARCH64: GHASH intrinsic is not optimal
Summary: Rewrite intrinsic to make better use of SIMD instructions
Reviewed-by: duke

*** 1208,1218 ****
      rf((Register)Rt, 0);                                                \
    }
  
    INSN(ldrs, 0b00, 1);
    INSN(ldrd, 0b01, 1);
!   INSN(ldrq, 0x10, 1);
  
  #undef INSN
  
  #define INSN(NAME, opc, V)                                              \
    void NAME(address dest, prfop op = PLDL1KEEP) {                       \
--- 1208,1218 ----
      rf((Register)Rt, 0);                                                \
    }
  
    INSN(ldrs, 0b00, 1);
    INSN(ldrd, 0b01, 1);
!   INSN(ldrq, 0b10, 1);
  
  #undef INSN
  
  #define INSN(NAME, opc, V)                                              \
    void NAME(address dest, prfop op = PLDL1KEEP) {                       \
*** 2297,2306 ****
--- 2297,2307 ----
    INSN(tbl, 0);
    INSN(tbx, 1);
  
  #undef INSN
  
+   // AdvSIMD two-reg misc
  #define INSN(NAME, U, opcode)                                                       \
    void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
         starti;                                                                      \
         assert((ASSERTION), MSG);                                                    \
         f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
*** 2314,2327 ****
--- 2315,2337 ----
    INSN(rev64, 0, 0b00000);
  #undef ASSERTION
  
  #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
    INSN(rev32, 1, 0b00000);
+ private:
+   INSN(_rbit, 1, 0b00101);
+ public:
+ 
  #undef ASSERTION
  
  #define ASSERTION (T == T8B || T == T16B)
    INSN(rev16, 0, 0b00001);
+   // RBIT only allows T8B and T16B but encodes them oddly.  Argh...
+   void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
+     assert((ASSERTION), MSG);
+     _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
+   }
  #undef ASSERTION
  
  #undef MSG
  
  #undef INSN