src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

rev 8905 : 8135157: DMB elimination in AArch64 C2 synchronization implementation
Summary: Reduce memory barrier usage in C2 fast lock and unlock.
Reviewed-by: kvn
Contributed-by: wei.tang@linaro.org, aph@redhat.com

*** 915,924 ****
--- 915,926 ----
      str(rscratch1, Address(rscratch2));
    }
  
    void cmpptr(Register src1, Address src2);
  
+   // Various forms of CAS
+ 
    void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
                    Label &suceed, Label *fail);
  
    void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
                    Label &suceed, Label *fail);
*** 936,945 ****
--- 938,964 ----
      else
        orr(rscratch2, rscratch2, src.as_constant());
      str(rscratch2, adr);
    }
  
+   // A generic CAS; success or failure is in the EQ flag.
+   template <typename T1, typename T2>
+   void cmpxchg(Register addr, Register expected, Register new_val,
+                T1 load_insn,
+                void (MacroAssembler::*cmp_insn)(Register, Register),
+                T2 store_insn,
+                Register tmp = rscratch1) {
+     Label retry_load, done;
+     bind(retry_load);
+     (this->*load_insn)(tmp, addr);
+     (this->*cmp_insn)(tmp, expected);
+     br(Assembler::NE, done);
+     (this->*store_insn)(tmp, new_val, addr);
+     cbnzw(tmp, retry_load);
+     bind(done);
+   }
+ 
    // Calls
  
    address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
  
    static bool far_branches() {