src/cpu/aarch64/vm/macroAssembler_aarch64.hpp

rev 9428 : 8144028: Use AArch64 bit-test instructions in C2
Reviewed-by: kvn

*** 213,224 ****
    }
  
    inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
    inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
  
!   inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
!   inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
  
    inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
      bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
    }
    inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
--- 213,227 ----
    }
  
    inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
    inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
  
!   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
!   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
! 
!   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
!   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
  
    inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
      bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
    }
    inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {