1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "asm/assembler.hpp" 30 #include "asm/assembler.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 33 #include "compiler/disassembler.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "nativeInst_aarch64.hpp" 36 #include "oops/klass.inline.hpp" 37 #include "oops/oop.inline.hpp" 38 #include "opto/compile.hpp" 39 #include "opto/node.hpp" 40 #include "runtime/biasedLocking.hpp" 41 #include "runtime/icache.hpp" 42 #include "runtime/interfaceSupport.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/thread.hpp" 45 46 #if INCLUDE_ALL_GCS 47 #include "gc/g1/g1CollectedHeap.inline.hpp" 48 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 49 #include "gc/g1/heapRegion.hpp" 50 #endif 51 52 #ifdef PRODUCT 53 #define BLOCK_COMMENT(str) /* nothing */ 54 #define STOP(error) stop(error) 55 #else 56 #define BLOCK_COMMENT(str) block_comment(str) 57 #define STOP(error) block_comment(error); stop(error) 58 #endif 59 60 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 61 62 // Patch any kind of instruction; there may be several instructions. 63 // Return the total length (in bytes) of the instructions. 64 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 65 int instructions = 1; 66 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); 67 long offset = (target - branch) >> 2; 68 unsigned insn = *(unsigned*)branch; 69 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 70 // Load register (literal) 71 Instruction_aarch64::spatch(branch, 23, 5, offset); 72 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 73 // Unconditional branch (immediate) 74 Instruction_aarch64::spatch(branch, 25, 0, offset); 75 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 76 // Conditional branch (immediate) 77 Instruction_aarch64::spatch(branch, 23, 5, offset); 78 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 79 // Compare & branch (immediate) 80 Instruction_aarch64::spatch(branch, 23, 5, offset); 81 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 82 // Test & branch (immediate) 83 Instruction_aarch64::spatch(branch, 18, 5, offset); 84 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 85 // PC-rel. addressing 86 offset = target-branch; 87 int shift = Instruction_aarch64::extract(insn, 31, 31); 88 if (shift) { 89 u_int64_t dest = (u_int64_t)target; 90 uint64_t pc_page = (uint64_t)branch >> 12; 91 uint64_t adr_page = (uint64_t)target >> 12; 92 unsigned offset_lo = dest & 0xfff; 93 offset = adr_page - pc_page; 94 95 // We handle 4 types of PC relative addressing 96 // 1 - adrp Rx, target_page 97 // ldr/str Ry, [Rx, #offset_in_page] 98 // 2 - adrp Rx, target_page 99 // add Ry, Rx, #offset_in_page 100 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 101 // movk Rx, #imm16<<32 102 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 103 // In the first 3 cases we must check that Rx is the same in the adrp and the 104 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 105 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 106 // to be followed by a random unrelated ldr/str, add or movk instruction. 107 // 108 unsigned insn2 = ((unsigned*)branch)[1]; 109 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 110 Instruction_aarch64::extract(insn, 4, 0) == 111 Instruction_aarch64::extract(insn2, 9, 5)) { 112 // Load/store register (unsigned immediate) 113 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 114 Instruction_aarch64::patch(branch + sizeof (unsigned), 115 21, 10, offset_lo >> size); 116 guarantee(((dest >> size) << size) == dest, "misaligned target"); 117 instructions = 2; 118 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 119 Instruction_aarch64::extract(insn, 4, 0) == 120 Instruction_aarch64::extract(insn2, 4, 0)) { 121 // add (immediate) 122 Instruction_aarch64::patch(branch + sizeof (unsigned), 123 21, 10, offset_lo); 124 instructions = 2; 125 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 126 Instruction_aarch64::extract(insn, 4, 0) == 127 Instruction_aarch64::extract(insn2, 4, 0)) { 128 // movk #imm16<<32 129 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 130 offset &= (1<<20)-1; 131 instructions = 2; 132 } 133 } 134 int offset_lo = offset & 3; 135 offset >>= 2; 136 Instruction_aarch64::spatch(branch, 23, 5, offset); 137 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 138 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 139 u_int64_t dest = (u_int64_t)target; 140 // Move wide constant 141 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 142 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 143 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 144 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 145 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 146 assert(target_addr_for_insn(branch) == target, "should be"); 147 instructions = 3; 148 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 149 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 150 // nothing to do 151 assert(target == 0, "did not expect to relocate target for polling page load"); 152 } else { 153 ShouldNotReachHere(); 154 } 155 return instructions * NativeInstruction::instruction_size; 156 } 157 158 int MacroAssembler::patch_oop(address insn_addr, address o) { 159 int instructions; 160 unsigned insn = *(unsigned*)insn_addr; 161 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 162 163 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 164 // narrow OOPs by setting the upper 16 bits in the first 165 // instruction. 166 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 167 // Move narrow OOP 168 narrowOop n = oopDesc::encode_heap_oop((oop)o); 169 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 170 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 171 instructions = 2; 172 } else { 173 // Move wide OOP 174 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 175 uintptr_t dest = (uintptr_t)o; 176 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 177 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 178 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 179 instructions = 3; 180 } 181 return instructions * NativeInstruction::instruction_size; 182 } 183 184 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 185 long offset = 0; 186 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 187 // Load register (literal) 188 offset = Instruction_aarch64::sextract(insn, 23, 5); 189 return address(((uint64_t)insn_addr + (offset << 2))); 190 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 191 // Unconditional branch (immediate) 192 offset = Instruction_aarch64::sextract(insn, 25, 0); 193 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 194 // Conditional branch (immediate) 195 offset = Instruction_aarch64::sextract(insn, 23, 5); 196 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 197 // Compare & branch (immediate) 198 offset = Instruction_aarch64::sextract(insn, 23, 5); 199 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 200 // Test & branch (immediate) 201 offset = Instruction_aarch64::sextract(insn, 18, 5); 202 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 203 // PC-rel. addressing 204 offset = Instruction_aarch64::extract(insn, 30, 29); 205 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 206 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 207 if (shift) { 208 offset <<= shift; 209 uint64_t target_page = ((uint64_t)insn_addr) + offset; 210 target_page &= ((uint64_t)-1) << shift; 211 // Return the target address for the following sequences 212 // 1 - adrp Rx, target_page 213 // ldr/str Ry, [Rx, #offset_in_page] 214 // 2 - adrp Rx, target_page 215 // add Ry, Rx, #offset_in_page 216 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 217 // movk Rx, #imm12<<32 218 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 219 // 220 // In the first two cases we check that the register is the same and 221 // return the target_page + the offset within the page. 222 // Otherwise we assume it is a page aligned relocation and return 223 // the target page only. 224 // 225 unsigned insn2 = ((unsigned*)insn_addr)[1]; 226 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 227 Instruction_aarch64::extract(insn, 4, 0) == 228 Instruction_aarch64::extract(insn2, 9, 5)) { 229 // Load/store register (unsigned immediate) 230 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 231 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 232 return address(target_page + (byte_offset << size)); 233 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 234 Instruction_aarch64::extract(insn, 4, 0) == 235 Instruction_aarch64::extract(insn2, 4, 0)) { 236 // add (immediate) 237 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 238 return address(target_page + byte_offset); 239 } else { 240 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 241 Instruction_aarch64::extract(insn, 4, 0) == 242 Instruction_aarch64::extract(insn2, 4, 0)) { 243 target_page = (target_page & 0xffffffff) | 244 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 245 } 246 return (address)target_page; 247 } 248 } else { 249 ShouldNotReachHere(); 250 } 251 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 252 u_int32_t *insns = (u_int32_t *)insn_addr; 253 // Move wide constant: movz, movk, movk. See movptr(). 254 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 255 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 256 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 257 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 258 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 259 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 260 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 261 return 0; 262 } else { 263 ShouldNotReachHere(); 264 } 265 return address(((uint64_t)insn_addr + (offset << 2))); 266 } 267 268 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 269 dsb(Assembler::SY); 270 } 271 272 273 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 274 bool clear_pc) { 275 // we must set sp to zero to clear frame 276 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 277 // must clear fp, so that compiled frames are not confused; it is 278 // possible that we need it only for debugging 279 if (clear_fp) { 280 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 281 } 282 283 if (clear_pc) { 284 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 285 } 286 } 287 288 // Calls to C land 289 // 290 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 291 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 292 // has to be reset to 0. This is required to allow proper stack traversal. 293 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 294 Register last_java_fp, 295 Register last_java_pc, 296 Register scratch) { 297 298 if (last_java_pc->is_valid()) { 299 str(last_java_pc, Address(rthread, 300 JavaThread::frame_anchor_offset() 301 + JavaFrameAnchor::last_Java_pc_offset())); 302 } 303 304 // determine last_java_sp register 305 if (last_java_sp == sp) { 306 mov(scratch, sp); 307 last_java_sp = scratch; 308 } else if (!last_java_sp->is_valid()) { 309 last_java_sp = esp; 310 } 311 312 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 313 314 // last_java_fp is optional 315 if (last_java_fp->is_valid()) { 316 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 317 } 318 } 319 320 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 321 Register last_java_fp, 322 address last_java_pc, 323 Register scratch) { 324 if (last_java_pc != NULL) { 325 adr(scratch, last_java_pc); 326 } else { 327 // FIXME: This is almost never correct. We should delete all 328 // cases of set_last_Java_frame with last_java_pc=NULL and use the 329 // correct return address instead. 330 adr(scratch, pc()); 331 } 332 333 str(scratch, Address(rthread, 334 JavaThread::frame_anchor_offset() 335 + JavaFrameAnchor::last_Java_pc_offset())); 336 337 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 338 } 339 340 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 341 Register last_java_fp, 342 Label &L, 343 Register scratch) { 344 if (L.is_bound()) { 345 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 346 } else { 347 InstructionMark im(this); 348 L.add_patch_at(code(), locator()); 349 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); 350 } 351 } 352 353 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 354 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 355 assert(CodeCache::find_blob(entry.target()) != NULL, 356 "destination of far call not found in code cache"); 357 if (far_branches()) { 358 unsigned long offset; 359 // We can use ADRP here because we know that the total size of 360 // the code cache cannot exceed 2Gb. 361 adrp(tmp, entry, offset); 362 add(tmp, tmp, offset); 363 if (cbuf) cbuf->set_insts_mark(); 364 blr(tmp); 365 } else { 366 if (cbuf) cbuf->set_insts_mark(); 367 bl(entry); 368 } 369 } 370 371 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 372 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 373 assert(CodeCache::find_blob(entry.target()) != NULL, 374 "destination of far call not found in code cache"); 375 if (far_branches()) { 376 unsigned long offset; 377 // We can use ADRP here because we know that the total size of 378 // the code cache cannot exceed 2Gb. 379 adrp(tmp, entry, offset); 380 add(tmp, tmp, offset); 381 if (cbuf) cbuf->set_insts_mark(); 382 br(tmp); 383 } else { 384 if (cbuf) cbuf->set_insts_mark(); 385 b(entry); 386 } 387 } 388 389 int MacroAssembler::biased_locking_enter(Register lock_reg, 390 Register obj_reg, 391 Register swap_reg, 392 Register tmp_reg, 393 bool swap_reg_contains_mark, 394 Label& done, 395 Label* slow_case, 396 BiasedLockingCounters* counters) { 397 assert(UseBiasedLocking, "why call this otherwise?"); 398 assert_different_registers(lock_reg, obj_reg, swap_reg); 399 400 if (PrintBiasedLockingStatistics && counters == NULL) 401 counters = BiasedLocking::counters(); 402 403 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 404 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 405 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 406 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 407 Address saved_mark_addr(lock_reg, 0); 408 409 // Biased locking 410 // See whether the lock is currently biased toward our thread and 411 // whether the epoch is still valid 412 // Note that the runtime guarantees sufficient alignment of JavaThread 413 // pointers to allow age to be placed into low bits 414 // First check to see whether biasing is even enabled for this object 415 Label cas_label; 416 int null_check_offset = -1; 417 if (!swap_reg_contains_mark) { 418 null_check_offset = offset(); 419 ldr(swap_reg, mark_addr); 420 } 421 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); 422 cmp(tmp_reg, markOopDesc::biased_lock_pattern); 423 br(Assembler::NE, cas_label); 424 // The bias pattern is present in the object's header. Need to check 425 // whether the bias owner and the epoch are both still current. 426 load_prototype_header(tmp_reg, obj_reg); 427 orr(tmp_reg, tmp_reg, rthread); 428 eor(tmp_reg, swap_reg, tmp_reg); 429 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 430 if (counters != NULL) { 431 Label around; 432 cbnz(tmp_reg, around); 433 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 434 b(done); 435 bind(around); 436 } else { 437 cbz(tmp_reg, done); 438 } 439 440 Label try_revoke_bias; 441 Label try_rebias; 442 443 // At this point we know that the header has the bias pattern and 444 // that we are not the bias owner in the current epoch. We need to 445 // figure out more details about the state of the header in order to 446 // know what operations can be legally performed on the object's 447 // header. 448 449 // If the low three bits in the xor result aren't clear, that means 450 // the prototype header is no longer biased and we have to revoke 451 // the bias on this object. 452 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); 453 cbnz(rscratch1, try_revoke_bias); 454 455 // Biasing is still enabled for this data type. See whether the 456 // epoch of the current bias is still valid, meaning that the epoch 457 // bits of the mark word are equal to the epoch bits of the 458 // prototype header. (Note that the prototype header's epoch bits 459 // only change at a safepoint.) If not, attempt to rebias the object 460 // toward the current thread. Note that we must be absolutely sure 461 // that the current epoch is invalid in order to do this because 462 // otherwise the manipulations it performs on the mark word are 463 // illegal. 464 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); 465 cbnz(rscratch1, try_rebias); 466 467 // The epoch of the current bias is still valid but we know nothing 468 // about the owner; it might be set or it might be clear. Try to 469 // acquire the bias of the object using an atomic operation. If this 470 // fails we will go in to the runtime to revoke the object's bias. 471 // Note that we first construct the presumed unbiased header so we 472 // don't accidentally blow away another thread's valid bias. 473 { 474 Label here; 475 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 476 andr(swap_reg, swap_reg, rscratch1); 477 orr(tmp_reg, swap_reg, rthread); 478 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 479 // If the biasing toward our thread failed, this means that 480 // another thread succeeded in biasing it toward itself and we 481 // need to revoke that bias. The revocation will occur in the 482 // interpreter runtime in the slow case. 483 bind(here); 484 if (counters != NULL) { 485 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 486 tmp_reg, rscratch1, rscratch2); 487 } 488 } 489 b(done); 490 491 bind(try_rebias); 492 // At this point we know the epoch has expired, meaning that the 493 // current "bias owner", if any, is actually invalid. Under these 494 // circumstances _only_, we are allowed to use the current header's 495 // value as the comparison value when doing the cas to acquire the 496 // bias in the current epoch. In other words, we allow transfer of 497 // the bias from one thread to another directly in this situation. 498 // 499 // FIXME: due to a lack of registers we currently blow away the age 500 // bits in this situation. Should attempt to preserve them. 501 { 502 Label here; 503 load_prototype_header(tmp_reg, obj_reg); 504 orr(tmp_reg, rthread, tmp_reg); 505 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 506 // If the biasing toward our thread failed, then another thread 507 // succeeded in biasing it toward itself and we need to revoke that 508 // bias. The revocation will occur in the runtime in the slow case. 509 bind(here); 510 if (counters != NULL) { 511 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 512 tmp_reg, rscratch1, rscratch2); 513 } 514 } 515 b(done); 516 517 bind(try_revoke_bias); 518 // The prototype mark in the klass doesn't have the bias bit set any 519 // more, indicating that objects of this data type are not supposed 520 // to be biased any more. We are going to try to reset the mark of 521 // this object to the prototype value and fall through to the 522 // CAS-based locking scheme. Note that if our CAS fails, it means 523 // that another thread raced us for the privilege of revoking the 524 // bias of this particular object, so it's okay to continue in the 525 // normal locking code. 526 // 527 // FIXME: due to a lack of registers we currently blow away the age 528 // bits in this situation. Should attempt to preserve them. 529 { 530 Label here, nope; 531 load_prototype_header(tmp_reg, obj_reg); 532 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 533 bind(here); 534 535 // Fall through to the normal CAS-based lock, because no matter what 536 // the result of the above CAS, some thread must have succeeded in 537 // removing the bias bit from the object's header. 538 if (counters != NULL) { 539 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 540 rscratch1, rscratch2); 541 } 542 bind(nope); 543 } 544 545 bind(cas_label); 546 547 return null_check_offset; 548 } 549 550 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 551 assert(UseBiasedLocking, "why call this otherwise?"); 552 553 // Check for biased locking unlock case, which is a no-op 554 // Note: we do not have to check the thread ID for two reasons. 555 // First, the interpreter checks for IllegalMonitorStateException at 556 // a higher level. Second, if the bias was revoked while we held the 557 // lock, the object could not be rebiased toward another thread, so 558 // the bias bit would be clear. 559 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 560 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); 561 cmp(temp_reg, markOopDesc::biased_lock_pattern); 562 br(Assembler::EQ, done); 563 } 564 565 566 // added to make this compile 567 568 REGISTER_DEFINITION(Register, noreg); 569 570 static void pass_arg0(MacroAssembler* masm, Register arg) { 571 if (c_rarg0 != arg ) { 572 masm->mov(c_rarg0, arg); 573 } 574 } 575 576 static void pass_arg1(MacroAssembler* masm, Register arg) { 577 if (c_rarg1 != arg ) { 578 masm->mov(c_rarg1, arg); 579 } 580 } 581 582 static void pass_arg2(MacroAssembler* masm, Register arg) { 583 if (c_rarg2 != arg ) { 584 masm->mov(c_rarg2, arg); 585 } 586 } 587 588 static void pass_arg3(MacroAssembler* masm, Register arg) { 589 if (c_rarg3 != arg ) { 590 masm->mov(c_rarg3, arg); 591 } 592 } 593 594 void MacroAssembler::call_VM_base(Register oop_result, 595 Register java_thread, 596 Register last_java_sp, 597 address entry_point, 598 int number_of_arguments, 599 bool check_exceptions) { 600 // determine java_thread register 601 if (!java_thread->is_valid()) { 602 java_thread = rthread; 603 } 604 605 // determine last_java_sp register 606 if (!last_java_sp->is_valid()) { 607 last_java_sp = esp; 608 } 609 610 // debugging support 611 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 612 assert(java_thread == rthread, "unexpected register"); 613 #ifdef ASSERT 614 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 615 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 616 #endif // ASSERT 617 618 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 619 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 620 621 // push java thread (becomes first argument of C function) 622 623 mov(c_rarg0, java_thread); 624 625 // set last Java frame before call 626 assert(last_java_sp != rfp, "can't use rfp"); 627 628 Label l; 629 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 630 631 // do the call, remove parameters 632 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 633 634 // reset last Java frame 635 // Only interpreter should have to clear fp 636 reset_last_Java_frame(true, true); 637 638 // C++ interp handles this in the interpreter 639 check_and_handle_popframe(java_thread); 640 check_and_handle_earlyret(java_thread); 641 642 if (check_exceptions) { 643 // check for pending exceptions (java_thread is set upon return) 644 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 645 Label ok; 646 cbz(rscratch1, ok); 647 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 648 br(rscratch1); 649 bind(ok); 650 } 651 652 // get oop result if there is one and reset the value in the thread 653 if (oop_result->is_valid()) { 654 get_vm_result(oop_result, java_thread); 655 } 656 } 657 658 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 659 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 660 } 661 662 // Maybe emit a call via a trampoline. If the code cache is small 663 // trampolines won't be emitted. 664 665 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 666 assert(entry.rspec().type() == relocInfo::runtime_call_type 667 || entry.rspec().type() == relocInfo::opt_virtual_call_type 668 || entry.rspec().type() == relocInfo::static_call_type 669 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 670 671 unsigned int start_offset = offset(); 672 if (far_branches() && !Compile::current()->in_scratch_emit_size()) { 673 address stub = emit_trampoline_stub(start_offset, entry.target()); 674 if (stub == NULL) { 675 return NULL; // CodeCache is full 676 } 677 } 678 679 if (cbuf) cbuf->set_insts_mark(); 680 relocate(entry.rspec()); 681 if (!far_branches()) { 682 bl(entry.target()); 683 } else { 684 bl(pc()); 685 } 686 // just need to return a non-null address 687 return pc(); 688 } 689 690 691 // Emit a trampoline stub for a call to a target which is too far away. 692 // 693 // code sequences: 694 // 695 // call-site: 696 // branch-and-link to <destination> or <trampoline stub> 697 // 698 // Related trampoline stub for this call site in the stub section: 699 // load the call target from the constant pool 700 // branch (LR still points to the call site above) 701 702 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 703 address dest) { 704 address stub = start_a_stub(Compile::MAX_stubs_size/2); 705 if (stub == NULL) { 706 return NULL; // CodeBuffer::expand failed 707 } 708 709 // Create a trampoline stub relocation which relates this trampoline stub 710 // with the call instruction at insts_call_instruction_offset in the 711 // instructions code-section. 712 align(wordSize); 713 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 714 + insts_call_instruction_offset)); 715 const int stub_start_offset = offset(); 716 717 // Now, create the trampoline stub's code: 718 // - load the call 719 // - call 720 Label target; 721 ldr(rscratch1, target); 722 br(rscratch1); 723 bind(target); 724 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 725 "should be"); 726 emit_int64((int64_t)dest); 727 728 const address stub_start_addr = addr_at(stub_start_offset); 729 730 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 731 732 end_a_stub(); 733 return stub; 734 } 735 736 address MacroAssembler::ic_call(address entry, jint method_index) { 737 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 738 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 739 // unsigned long offset; 740 // ldr_constant(rscratch2, const_ptr); 741 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 742 return trampoline_call(Address(entry, rh)); 743 } 744 745 // Implementation of call_VM versions 746 747 void MacroAssembler::call_VM(Register oop_result, 748 address entry_point, 749 bool check_exceptions) { 750 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 751 } 752 753 void MacroAssembler::call_VM(Register oop_result, 754 address entry_point, 755 Register arg_1, 756 bool check_exceptions) { 757 pass_arg1(this, arg_1); 758 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 759 } 760 761 void MacroAssembler::call_VM(Register oop_result, 762 address entry_point, 763 Register arg_1, 764 Register arg_2, 765 bool check_exceptions) { 766 assert(arg_1 != c_rarg2, "smashed arg"); 767 pass_arg2(this, arg_2); 768 pass_arg1(this, arg_1); 769 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 770 } 771 772 void MacroAssembler::call_VM(Register oop_result, 773 address entry_point, 774 Register arg_1, 775 Register arg_2, 776 Register arg_3, 777 bool check_exceptions) { 778 assert(arg_1 != c_rarg3, "smashed arg"); 779 assert(arg_2 != c_rarg3, "smashed arg"); 780 pass_arg3(this, arg_3); 781 782 assert(arg_1 != c_rarg2, "smashed arg"); 783 pass_arg2(this, arg_2); 784 785 pass_arg1(this, arg_1); 786 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 787 } 788 789 void MacroAssembler::call_VM(Register oop_result, 790 Register last_java_sp, 791 address entry_point, 792 int number_of_arguments, 793 bool check_exceptions) { 794 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 795 } 796 797 void MacroAssembler::call_VM(Register oop_result, 798 Register last_java_sp, 799 address entry_point, 800 Register arg_1, 801 bool check_exceptions) { 802 pass_arg1(this, arg_1); 803 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 804 } 805 806 void MacroAssembler::call_VM(Register oop_result, 807 Register last_java_sp, 808 address entry_point, 809 Register arg_1, 810 Register arg_2, 811 bool check_exceptions) { 812 813 assert(arg_1 != c_rarg2, "smashed arg"); 814 pass_arg2(this, arg_2); 815 pass_arg1(this, arg_1); 816 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 817 } 818 819 void MacroAssembler::call_VM(Register oop_result, 820 Register last_java_sp, 821 address entry_point, 822 Register arg_1, 823 Register arg_2, 824 Register arg_3, 825 bool check_exceptions) { 826 assert(arg_1 != c_rarg3, "smashed arg"); 827 assert(arg_2 != c_rarg3, "smashed arg"); 828 pass_arg3(this, arg_3); 829 assert(arg_1 != c_rarg2, "smashed arg"); 830 pass_arg2(this, arg_2); 831 pass_arg1(this, arg_1); 832 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 833 } 834 835 836 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 837 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 838 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 839 verify_oop(oop_result, "broken oop in call_VM_base"); 840 } 841 842 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 843 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 844 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 845 } 846 847 void MacroAssembler::align(int modulus) { 848 while (offset() % modulus != 0) nop(); 849 } 850 851 // these are no-ops overridden by InterpreterMacroAssembler 852 853 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 854 855 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 856 857 858 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 859 Register tmp, 860 int offset) { 861 intptr_t value = *delayed_value_addr; 862 if (value != 0) 863 return RegisterOrConstant(value + offset); 864 865 // load indirectly to solve generation ordering problem 866 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 867 868 if (offset != 0) 869 add(tmp, tmp, offset); 870 871 return RegisterOrConstant(tmp); 872 } 873 874 875 void MacroAssembler:: notify(int type) { 876 if (type == bytecode_start) { 877 // set_last_Java_frame(esp, rfp, (address)NULL); 878 Assembler:: notify(type); 879 // reset_last_Java_frame(true, false); 880 } 881 else 882 Assembler:: notify(type); 883 } 884 885 // Look up the method for a megamorphic invokeinterface call. 886 // The target method is determined by <intf_klass, itable_index>. 887 // The receiver klass is in recv_klass. 888 // On success, the result will be in method_result, and execution falls through. 889 // On failure, execution transfers to the given label. 890 void MacroAssembler::lookup_interface_method(Register recv_klass, 891 Register intf_klass, 892 RegisterOrConstant itable_index, 893 Register method_result, 894 Register scan_temp, 895 Label& L_no_such_interface) { 896 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 897 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 898 "caller must use same register for non-constant itable index as for method"); 899 900 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 901 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; 902 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 903 int scan_step = itableOffsetEntry::size() * wordSize; 904 int vte_size = vtableEntry::size() * wordSize; 905 assert(vte_size == wordSize, "else adjust times_vte_scale"); 906 907 ldrw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); 908 909 // %%% Could store the aligned, prescaled offset in the klassoop. 910 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 911 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 912 add(scan_temp, scan_temp, vtable_base); 913 if (HeapWordsPerLong > 1) { 914 // Round up to align_object_offset boundary 915 // see code for instanceKlass::start_of_itable! 916 round_to(scan_temp, BytesPerLong); 917 } 918 919 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 920 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 921 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 922 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 923 if (itentry_off) 924 add(recv_klass, recv_klass, itentry_off); 925 926 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 927 // if (scan->interface() == intf) { 928 // result = (klass + scan->offset() + itable_index); 929 // } 930 // } 931 Label search, found_method; 932 933 for (int peel = 1; peel >= 0; peel--) { 934 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 935 cmp(intf_klass, method_result); 936 937 if (peel) { 938 br(Assembler::EQ, found_method); 939 } else { 940 br(Assembler::NE, search); 941 // (invert the test to fall through to found_method...) 942 } 943 944 if (!peel) break; 945 946 bind(search); 947 948 // Check that the previous entry is non-null. A null entry means that 949 // the receiver class doesn't implement the interface, and wasn't the 950 // same as when the caller was compiled. 951 cbz(method_result, L_no_such_interface); 952 add(scan_temp, scan_temp, scan_step); 953 } 954 955 bind(found_method); 956 957 // Got a hit. 958 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 959 ldr(method_result, Address(recv_klass, scan_temp)); 960 } 961 962 // virtual method calling 963 void MacroAssembler::lookup_virtual_method(Register recv_klass, 964 RegisterOrConstant vtable_index, 965 Register method_result) { 966 const int base = InstanceKlass::vtable_start_offset() * wordSize; 967 assert(vtableEntry::size() * wordSize == 8, 968 "adjust the scaling in the code below"); 969 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 970 971 if (vtable_index.is_register()) { 972 lea(method_result, Address(recv_klass, 973 vtable_index.as_register(), 974 Address::lsl(LogBytesPerWord))); 975 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 976 } else { 977 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 978 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes)); 979 } 980 } 981 982 void MacroAssembler::check_klass_subtype(Register sub_klass, 983 Register super_klass, 984 Register temp_reg, 985 Label& L_success) { 986 Label L_failure; 987 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 988 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 989 bind(L_failure); 990 } 991 992 993 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 994 Register super_klass, 995 Register temp_reg, 996 Label* L_success, 997 Label* L_failure, 998 Label* L_slow_path, 999 RegisterOrConstant super_check_offset) { 1000 assert_different_registers(sub_klass, super_klass, temp_reg); 1001 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1002 if (super_check_offset.is_register()) { 1003 assert_different_registers(sub_klass, super_klass, 1004 super_check_offset.as_register()); 1005 } else if (must_load_sco) { 1006 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1007 } 1008 1009 Label L_fallthrough; 1010 int label_nulls = 0; 1011 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1012 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1013 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1014 assert(label_nulls <= 1, "at most one NULL in the batch"); 1015 1016 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1017 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1018 Address super_check_offset_addr(super_klass, sco_offset); 1019 1020 // Hacked jmp, which may only be used just before L_fallthrough. 1021 #define final_jmp(label) \ 1022 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1023 else b(label) /*omit semi*/ 1024 1025 // If the pointers are equal, we are done (e.g., String[] elements). 1026 // This self-check enables sharing of secondary supertype arrays among 1027 // non-primary types such as array-of-interface. Otherwise, each such 1028 // type would need its own customized SSA. 1029 // We move this check to the front of the fast path because many 1030 // type checks are in fact trivially successful in this manner, 1031 // so we get a nicely predicted branch right at the start of the check. 1032 cmp(sub_klass, super_klass); 1033 br(Assembler::EQ, *L_success); 1034 1035 // Check the supertype display: 1036 if (must_load_sco) { 1037 ldrw(temp_reg, super_check_offset_addr); 1038 super_check_offset = RegisterOrConstant(temp_reg); 1039 } 1040 Address super_check_addr(sub_klass, super_check_offset); 1041 ldr(rscratch1, super_check_addr); 1042 cmp(super_klass, rscratch1); // load displayed supertype 1043 1044 // This check has worked decisively for primary supers. 1045 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1046 // (Secondary supers are interfaces and very deeply nested subtypes.) 1047 // This works in the same check above because of a tricky aliasing 1048 // between the super_cache and the primary super display elements. 1049 // (The 'super_check_addr' can address either, as the case requires.) 1050 // Note that the cache is updated below if it does not help us find 1051 // what we need immediately. 1052 // So if it was a primary super, we can just fail immediately. 1053 // Otherwise, it's the slow path for us (no success at this point). 1054 1055 if (super_check_offset.is_register()) { 1056 br(Assembler::EQ, *L_success); 1057 cmp(super_check_offset.as_register(), sc_offset); 1058 if (L_failure == &L_fallthrough) { 1059 br(Assembler::EQ, *L_slow_path); 1060 } else { 1061 br(Assembler::NE, *L_failure); 1062 final_jmp(*L_slow_path); 1063 } 1064 } else if (super_check_offset.as_constant() == sc_offset) { 1065 // Need a slow path; fast failure is impossible. 1066 if (L_slow_path == &L_fallthrough) { 1067 br(Assembler::EQ, *L_success); 1068 } else { 1069 br(Assembler::NE, *L_slow_path); 1070 final_jmp(*L_success); 1071 } 1072 } else { 1073 // No slow path; it's a fast decision. 1074 if (L_failure == &L_fallthrough) { 1075 br(Assembler::EQ, *L_success); 1076 } else { 1077 br(Assembler::NE, *L_failure); 1078 final_jmp(*L_success); 1079 } 1080 } 1081 1082 bind(L_fallthrough); 1083 1084 #undef final_jmp 1085 } 1086 1087 // These two are taken from x86, but they look generally useful 1088 1089 // scans count pointer sized words at [addr] for occurence of value, 1090 // generic 1091 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1092 Register scratch) { 1093 Label Lloop, Lexit; 1094 cbz(count, Lexit); 1095 bind(Lloop); 1096 ldr(scratch, post(addr, wordSize)); 1097 cmp(value, scratch); 1098 br(EQ, Lexit); 1099 sub(count, count, 1); 1100 cbnz(count, Lloop); 1101 bind(Lexit); 1102 } 1103 1104 // scans count 4 byte words at [addr] for occurence of value, 1105 // generic 1106 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1107 Register scratch) { 1108 Label Lloop, Lexit; 1109 cbz(count, Lexit); 1110 bind(Lloop); 1111 ldrw(scratch, post(addr, wordSize)); 1112 cmpw(value, scratch); 1113 br(EQ, Lexit); 1114 sub(count, count, 1); 1115 cbnz(count, Lloop); 1116 bind(Lexit); 1117 } 1118 1119 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1120 Register super_klass, 1121 Register temp_reg, 1122 Register temp2_reg, 1123 Label* L_success, 1124 Label* L_failure, 1125 bool set_cond_codes) { 1126 assert_different_registers(sub_klass, super_klass, temp_reg); 1127 if (temp2_reg != noreg) 1128 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1129 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1130 1131 Label L_fallthrough; 1132 int label_nulls = 0; 1133 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1134 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1135 assert(label_nulls <= 1, "at most one NULL in the batch"); 1136 1137 // a couple of useful fields in sub_klass: 1138 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1139 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1140 Address secondary_supers_addr(sub_klass, ss_offset); 1141 Address super_cache_addr( sub_klass, sc_offset); 1142 1143 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1144 1145 // Do a linear scan of the secondary super-klass chain. 1146 // This code is rarely used, so simplicity is a virtue here. 1147 // The repne_scan instruction uses fixed registers, which we must spill. 1148 // Don't worry too much about pre-existing connections with the input regs. 1149 1150 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1151 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1152 1153 // Get super_klass value into r0 (even if it was in r5 or r2). 1154 RegSet pushed_registers; 1155 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1156 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1157 1158 if (super_klass != r0 || UseCompressedOops) { 1159 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1160 } 1161 1162 push(pushed_registers, sp); 1163 1164 #ifndef PRODUCT 1165 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1166 Address pst_counter_addr(rscratch2); 1167 ldr(rscratch1, pst_counter_addr); 1168 add(rscratch1, rscratch1, 1); 1169 str(rscratch1, pst_counter_addr); 1170 #endif //PRODUCT 1171 1172 // We will consult the secondary-super array. 1173 ldr(r5, secondary_supers_addr); 1174 // Load the array length. 1175 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1176 // Skip to start of data. 1177 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1178 1179 cmp(sp, zr); // Clear Z flag; SP is never zero 1180 // Scan R2 words at [R5] for an occurrence of R0. 1181 // Set NZ/Z based on last compare. 1182 repne_scan(r5, r0, r2, rscratch1); 1183 1184 // Unspill the temp. registers: 1185 pop(pushed_registers, sp); 1186 1187 br(Assembler::NE, *L_failure); 1188 1189 // Success. Cache the super we found and proceed in triumph. 1190 str(super_klass, super_cache_addr); 1191 1192 if (L_success != &L_fallthrough) { 1193 b(*L_success); 1194 } 1195 1196 #undef IS_A_TEMP 1197 1198 bind(L_fallthrough); 1199 } 1200 1201 1202 void MacroAssembler::verify_oop(Register reg, const char* s) { 1203 if (!VerifyOops) return; 1204 1205 // Pass register number to verify_oop_subroutine 1206 const char* b = NULL; 1207 { 1208 ResourceMark rm; 1209 stringStream ss; 1210 ss.print("verify_oop: %s: %s", reg->name(), s); 1211 b = code_string(ss.as_string()); 1212 } 1213 BLOCK_COMMENT("verify_oop {"); 1214 1215 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1216 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1217 1218 mov(r0, reg); 1219 mov(rscratch1, (address)b); 1220 1221 // call indirectly to solve generation ordering problem 1222 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1223 ldr(rscratch2, Address(rscratch2)); 1224 blr(rscratch2); 1225 1226 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1227 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1228 1229 BLOCK_COMMENT("} verify_oop"); 1230 } 1231 1232 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1233 if (!VerifyOops) return; 1234 1235 const char* b = NULL; 1236 { 1237 ResourceMark rm; 1238 stringStream ss; 1239 ss.print("verify_oop_addr: %s", s); 1240 b = code_string(ss.as_string()); 1241 } 1242 BLOCK_COMMENT("verify_oop_addr {"); 1243 1244 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1245 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1246 1247 // addr may contain sp so we will have to adjust it based on the 1248 // pushes that we just did. 1249 if (addr.uses(sp)) { 1250 lea(r0, addr); 1251 ldr(r0, Address(r0, 4 * wordSize)); 1252 } else { 1253 ldr(r0, addr); 1254 } 1255 mov(rscratch1, (address)b); 1256 1257 // call indirectly to solve generation ordering problem 1258 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1259 ldr(rscratch2, Address(rscratch2)); 1260 blr(rscratch2); 1261 1262 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1263 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1264 1265 BLOCK_COMMENT("} verify_oop_addr"); 1266 } 1267 1268 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1269 int extra_slot_offset) { 1270 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1271 int stackElementSize = Interpreter::stackElementSize; 1272 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1273 #ifdef ASSERT 1274 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1275 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1276 #endif 1277 if (arg_slot.is_constant()) { 1278 return Address(esp, arg_slot.as_constant() * stackElementSize 1279 + offset); 1280 } else { 1281 add(rscratch1, esp, arg_slot.as_register(), 1282 ext::uxtx, exact_log2(stackElementSize)); 1283 return Address(rscratch1, offset); 1284 } 1285 } 1286 1287 void MacroAssembler::call_VM_leaf_base(address entry_point, 1288 int number_of_arguments, 1289 Label *retaddr) { 1290 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); 1291 } 1292 1293 void MacroAssembler::call_VM_leaf_base1(address entry_point, 1294 int number_of_gp_arguments, 1295 int number_of_fp_arguments, 1296 ret_type type, 1297 Label *retaddr) { 1298 Label E, L; 1299 1300 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1301 1302 // We add 1 to number_of_arguments because the thread in arg0 is 1303 // not counted 1304 mov(rscratch1, entry_point); 1305 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); 1306 if (retaddr) 1307 bind(*retaddr); 1308 1309 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1310 maybe_isb(); 1311 } 1312 1313 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1314 call_VM_leaf_base(entry_point, number_of_arguments); 1315 } 1316 1317 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1318 pass_arg0(this, arg_0); 1319 call_VM_leaf_base(entry_point, 1); 1320 } 1321 1322 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1323 pass_arg0(this, arg_0); 1324 pass_arg1(this, arg_1); 1325 call_VM_leaf_base(entry_point, 2); 1326 } 1327 1328 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1329 Register arg_1, Register arg_2) { 1330 pass_arg0(this, arg_0); 1331 pass_arg1(this, arg_1); 1332 pass_arg2(this, arg_2); 1333 call_VM_leaf_base(entry_point, 3); 1334 } 1335 1336 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1337 pass_arg0(this, arg_0); 1338 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1339 } 1340 1341 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1342 1343 assert(arg_0 != c_rarg1, "smashed arg"); 1344 pass_arg1(this, arg_1); 1345 pass_arg0(this, arg_0); 1346 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1347 } 1348 1349 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1350 assert(arg_0 != c_rarg2, "smashed arg"); 1351 assert(arg_1 != c_rarg2, "smashed arg"); 1352 pass_arg2(this, arg_2); 1353 assert(arg_0 != c_rarg1, "smashed arg"); 1354 pass_arg1(this, arg_1); 1355 pass_arg0(this, arg_0); 1356 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1357 } 1358 1359 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1360 assert(arg_0 != c_rarg3, "smashed arg"); 1361 assert(arg_1 != c_rarg3, "smashed arg"); 1362 assert(arg_2 != c_rarg3, "smashed arg"); 1363 pass_arg3(this, arg_3); 1364 assert(arg_0 != c_rarg2, "smashed arg"); 1365 assert(arg_1 != c_rarg2, "smashed arg"); 1366 pass_arg2(this, arg_2); 1367 assert(arg_0 != c_rarg1, "smashed arg"); 1368 pass_arg1(this, arg_1); 1369 pass_arg0(this, arg_0); 1370 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1371 } 1372 1373 void MacroAssembler::null_check(Register reg, int offset) { 1374 if (needs_explicit_null_check(offset)) { 1375 // provoke OS NULL exception if reg = NULL by 1376 // accessing M[reg] w/o changing any registers 1377 // NOTE: this is plenty to provoke a segv 1378 ldr(zr, Address(reg)); 1379 } else { 1380 // nothing to do, (later) access of M[reg + offset] 1381 // will provoke OS NULL exception if reg = NULL 1382 } 1383 } 1384 1385 // MacroAssembler protected routines needed to implement 1386 // public methods 1387 1388 void MacroAssembler::mov(Register r, Address dest) { 1389 code_section()->relocate(pc(), dest.rspec()); 1390 u_int64_t imm64 = (u_int64_t)dest.target(); 1391 movptr(r, imm64); 1392 } 1393 1394 // Move a constant pointer into r. In AArch64 mode the virtual 1395 // address space is 48 bits in size, so we only need three 1396 // instructions to create a patchable instruction sequence that can 1397 // reach anywhere. 1398 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1399 #ifndef PRODUCT 1400 { 1401 char buffer[64]; 1402 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1403 block_comment(buffer); 1404 } 1405 #endif 1406 assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); 1407 movz(r, imm64 & 0xffff); 1408 imm64 >>= 16; 1409 movk(r, imm64 & 0xffff, 16); 1410 imm64 >>= 16; 1411 movk(r, imm64 & 0xffff, 32); 1412 } 1413 1414 // Macro to mov replicated immediate to vector register. 1415 // Vd will get the following values for different arrangements in T 1416 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1417 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1418 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1419 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1420 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1421 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1422 // T1D/T2D: invalid 1423 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 1424 assert(T != T1D && T != T2D, "invalid arrangement"); 1425 if (T == T8B || T == T16B) { 1426 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1427 movi(Vd, T, imm32 & 0xff, 0); 1428 return; 1429 } 1430 u_int32_t nimm32 = ~imm32; 1431 if (T == T4H || T == T8H) { 1432 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1433 imm32 &= 0xffff; 1434 nimm32 &= 0xffff; 1435 } 1436 u_int32_t x = imm32; 1437 int movi_cnt = 0; 1438 int movn_cnt = 0; 1439 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1440 x = nimm32; 1441 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1442 if (movn_cnt < movi_cnt) imm32 = nimm32; 1443 unsigned lsl = 0; 1444 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1445 if (movn_cnt < movi_cnt) 1446 mvni(Vd, T, imm32 & 0xff, lsl); 1447 else 1448 movi(Vd, T, imm32 & 0xff, lsl); 1449 imm32 >>= 8; lsl += 8; 1450 while (imm32) { 1451 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1452 if (movn_cnt < movi_cnt) 1453 bici(Vd, T, imm32 & 0xff, lsl); 1454 else 1455 orri(Vd, T, imm32 & 0xff, lsl); 1456 lsl += 8; imm32 >>= 8; 1457 } 1458 } 1459 1460 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) 1461 { 1462 #ifndef PRODUCT 1463 { 1464 char buffer[64]; 1465 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1466 block_comment(buffer); 1467 } 1468 #endif 1469 if (operand_valid_for_logical_immediate(false, imm64)) { 1470 orr(dst, zr, imm64); 1471 } else { 1472 // we can use a combination of MOVZ or MOVN with 1473 // MOVK to build up the constant 1474 u_int64_t imm_h[4]; 1475 int zero_count = 0; 1476 int neg_count = 0; 1477 int i; 1478 for (i = 0; i < 4; i++) { 1479 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1480 if (imm_h[i] == 0) { 1481 zero_count++; 1482 } else if (imm_h[i] == 0xffffL) { 1483 neg_count++; 1484 } 1485 } 1486 if (zero_count == 4) { 1487 // one MOVZ will do 1488 movz(dst, 0); 1489 } else if (neg_count == 4) { 1490 // one MOVN will do 1491 movn(dst, 0); 1492 } else if (zero_count == 3) { 1493 for (i = 0; i < 4; i++) { 1494 if (imm_h[i] != 0L) { 1495 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1496 break; 1497 } 1498 } 1499 } else if (neg_count == 3) { 1500 // one MOVN will do 1501 for (int i = 0; i < 4; i++) { 1502 if (imm_h[i] != 0xffffL) { 1503 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1504 break; 1505 } 1506 } 1507 } else if (zero_count == 2) { 1508 // one MOVZ and one MOVK will do 1509 for (i = 0; i < 3; i++) { 1510 if (imm_h[i] != 0L) { 1511 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1512 i++; 1513 break; 1514 } 1515 } 1516 for (;i < 4; i++) { 1517 if (imm_h[i] != 0L) { 1518 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1519 } 1520 } 1521 } else if (neg_count == 2) { 1522 // one MOVN and one MOVK will do 1523 for (i = 0; i < 4; i++) { 1524 if (imm_h[i] != 0xffffL) { 1525 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1526 i++; 1527 break; 1528 } 1529 } 1530 for (;i < 4; i++) { 1531 if (imm_h[i] != 0xffffL) { 1532 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1533 } 1534 } 1535 } else if (zero_count == 1) { 1536 // one MOVZ and two MOVKs will do 1537 for (i = 0; i < 4; i++) { 1538 if (imm_h[i] != 0L) { 1539 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1540 i++; 1541 break; 1542 } 1543 } 1544 for (;i < 4; i++) { 1545 if (imm_h[i] != 0x0L) { 1546 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1547 } 1548 } 1549 } else if (neg_count == 1) { 1550 // one MOVN and two MOVKs will do 1551 for (i = 0; i < 4; i++) { 1552 if (imm_h[i] != 0xffffL) { 1553 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1554 i++; 1555 break; 1556 } 1557 } 1558 for (;i < 4; i++) { 1559 if (imm_h[i] != 0xffffL) { 1560 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1561 } 1562 } 1563 } else { 1564 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1565 movz(dst, (u_int32_t)imm_h[0], 0); 1566 for (i = 1; i < 4; i++) { 1567 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1568 } 1569 } 1570 } 1571 } 1572 1573 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) 1574 { 1575 #ifndef PRODUCT 1576 { 1577 char buffer[64]; 1578 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); 1579 block_comment(buffer); 1580 } 1581 #endif 1582 if (operand_valid_for_logical_immediate(true, imm32)) { 1583 orrw(dst, zr, imm32); 1584 } else { 1585 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1586 // constant 1587 u_int32_t imm_h[2]; 1588 imm_h[0] = imm32 & 0xffff; 1589 imm_h[1] = ((imm32 >> 16) & 0xffff); 1590 if (imm_h[0] == 0) { 1591 movzw(dst, imm_h[1], 16); 1592 } else if (imm_h[0] == 0xffff) { 1593 movnw(dst, imm_h[1] ^ 0xffff, 16); 1594 } else if (imm_h[1] == 0) { 1595 movzw(dst, imm_h[0], 0); 1596 } else if (imm_h[1] == 0xffff) { 1597 movnw(dst, imm_h[0] ^ 0xffff, 0); 1598 } else { 1599 // use a MOVZ and MOVK (makes it easier to debug) 1600 movzw(dst, imm_h[0], 0); 1601 movkw(dst, imm_h[1], 16); 1602 } 1603 } 1604 } 1605 1606 // Form an address from base + offset in Rd. Rd may or may 1607 // not actually be used: you must use the Address that is returned. 1608 // It is up to you to ensure that the shift provided matches the size 1609 // of your data. 1610 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { 1611 if (Address::offset_ok_for_immed(byte_offset, shift)) 1612 // It fits; no need for any heroics 1613 return Address(base, byte_offset); 1614 1615 // Don't do anything clever with negative or misaligned offsets 1616 unsigned mask = (1 << shift) - 1; 1617 if (byte_offset < 0 || byte_offset & mask) { 1618 mov(Rd, byte_offset); 1619 add(Rd, base, Rd); 1620 return Address(Rd); 1621 } 1622 1623 // See if we can do this with two 12-bit offsets 1624 { 1625 unsigned long word_offset = byte_offset >> shift; 1626 unsigned long masked_offset = word_offset & 0xfff000; 1627 if (Address::offset_ok_for_immed(word_offset - masked_offset) 1628 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1629 add(Rd, base, masked_offset << shift); 1630 word_offset -= masked_offset; 1631 return Address(Rd, word_offset << shift); 1632 } 1633 } 1634 1635 // Do it the hard way 1636 mov(Rd, byte_offset); 1637 add(Rd, base, Rd); 1638 return Address(Rd); 1639 } 1640 1641 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1642 Label retry_load; 1643 bind(retry_load); 1644 // flush and load exclusive from the memory location 1645 ldxrw(tmp, counter_addr); 1646 addw(tmp, tmp, 1); 1647 // if we store+flush with no intervening write tmp wil be zero 1648 stxrw(tmp2, tmp, counter_addr); 1649 cbnzw(tmp2, retry_load); 1650 } 1651 1652 1653 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1654 bool want_remainder, Register scratch) 1655 { 1656 // Full implementation of Java idiv and irem. The function 1657 // returns the (pc) offset of the div instruction - may be needed 1658 // for implicit exceptions. 1659 // 1660 // constraint : ra/rb =/= scratch 1661 // normal case 1662 // 1663 // input : ra: dividend 1664 // rb: divisor 1665 // 1666 // result: either 1667 // quotient (= ra idiv rb) 1668 // remainder (= ra irem rb) 1669 1670 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1671 1672 int idivl_offset = offset(); 1673 if (! want_remainder) { 1674 sdivw(result, ra, rb); 1675 } else { 1676 sdivw(scratch, ra, rb); 1677 Assembler::msubw(result, scratch, rb, ra); 1678 } 1679 1680 return idivl_offset; 1681 } 1682 1683 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1684 bool want_remainder, Register scratch) 1685 { 1686 // Full implementation of Java ldiv and lrem. The function 1687 // returns the (pc) offset of the div instruction - may be needed 1688 // for implicit exceptions. 1689 // 1690 // constraint : ra/rb =/= scratch 1691 // normal case 1692 // 1693 // input : ra: dividend 1694 // rb: divisor 1695 // 1696 // result: either 1697 // quotient (= ra idiv rb) 1698 // remainder (= ra irem rb) 1699 1700 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1701 1702 int idivq_offset = offset(); 1703 if (! want_remainder) { 1704 sdiv(result, ra, rb); 1705 } else { 1706 sdiv(scratch, ra, rb); 1707 Assembler::msub(result, scratch, rb, ra); 1708 } 1709 1710 return idivq_offset; 1711 } 1712 1713 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1714 address prev = pc() - NativeMembar::instruction_size; 1715 if (prev == code()->last_membar()) { 1716 NativeMembar *bar = NativeMembar_at(prev); 1717 // We are merging two memory barrier instructions. On AArch64 we 1718 // can do this simply by ORing them together. 1719 bar->set_kind(bar->get_kind() | order_constraint); 1720 BLOCK_COMMENT("merged membar"); 1721 } else { 1722 code()->set_last_membar(pc()); 1723 dmb(Assembler::barrier(order_constraint)); 1724 } 1725 } 1726 1727 // MacroAssembler routines found actually to be needed 1728 1729 void MacroAssembler::push(Register src) 1730 { 1731 str(src, Address(pre(esp, -1 * wordSize))); 1732 } 1733 1734 void MacroAssembler::pop(Register dst) 1735 { 1736 ldr(dst, Address(post(esp, 1 * wordSize))); 1737 } 1738 1739 // Note: load_unsigned_short used to be called load_unsigned_word. 1740 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1741 int off = offset(); 1742 ldrh(dst, src); 1743 return off; 1744 } 1745 1746 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1747 int off = offset(); 1748 ldrb(dst, src); 1749 return off; 1750 } 1751 1752 int MacroAssembler::load_signed_short(Register dst, Address src) { 1753 int off = offset(); 1754 ldrsh(dst, src); 1755 return off; 1756 } 1757 1758 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1759 int off = offset(); 1760 ldrsb(dst, src); 1761 return off; 1762 } 1763 1764 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1765 int off = offset(); 1766 ldrshw(dst, src); 1767 return off; 1768 } 1769 1770 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1771 int off = offset(); 1772 ldrsbw(dst, src); 1773 return off; 1774 } 1775 1776 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1777 switch (size_in_bytes) { 1778 case 8: ldr(dst, src); break; 1779 case 4: ldrw(dst, src); break; 1780 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1781 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1782 default: ShouldNotReachHere(); 1783 } 1784 } 1785 1786 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1787 switch (size_in_bytes) { 1788 case 8: str(src, dst); break; 1789 case 4: strw(src, dst); break; 1790 case 2: strh(src, dst); break; 1791 case 1: strb(src, dst); break; 1792 default: ShouldNotReachHere(); 1793 } 1794 } 1795 1796 void MacroAssembler::decrementw(Register reg, int value) 1797 { 1798 if (value < 0) { incrementw(reg, -value); return; } 1799 if (value == 0) { return; } 1800 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1801 /* else */ { 1802 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1803 movw(rscratch2, (unsigned)value); 1804 subw(reg, reg, rscratch2); 1805 } 1806 } 1807 1808 void MacroAssembler::decrement(Register reg, int value) 1809 { 1810 if (value < 0) { increment(reg, -value); return; } 1811 if (value == 0) { return; } 1812 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1813 /* else */ { 1814 assert(reg != rscratch2, "invalid dst for register decrement"); 1815 mov(rscratch2, (unsigned long)value); 1816 sub(reg, reg, rscratch2); 1817 } 1818 } 1819 1820 void MacroAssembler::decrementw(Address dst, int value) 1821 { 1822 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1823 ldrw(rscratch1, dst); 1824 decrementw(rscratch1, value); 1825 strw(rscratch1, dst); 1826 } 1827 1828 void MacroAssembler::decrement(Address dst, int value) 1829 { 1830 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1831 ldr(rscratch1, dst); 1832 decrement(rscratch1, value); 1833 str(rscratch1, dst); 1834 } 1835 1836 void MacroAssembler::incrementw(Register reg, int value) 1837 { 1838 if (value < 0) { decrementw(reg, -value); return; } 1839 if (value == 0) { return; } 1840 if (value < (1 << 12)) { addw(reg, reg, value); return; } 1841 /* else */ { 1842 assert(reg != rscratch2, "invalid dst for register increment"); 1843 movw(rscratch2, (unsigned)value); 1844 addw(reg, reg, rscratch2); 1845 } 1846 } 1847 1848 void MacroAssembler::increment(Register reg, int value) 1849 { 1850 if (value < 0) { decrement(reg, -value); return; } 1851 if (value == 0) { return; } 1852 if (value < (1 << 12)) { add(reg, reg, value); return; } 1853 /* else */ { 1854 assert(reg != rscratch2, "invalid dst for register increment"); 1855 movw(rscratch2, (unsigned)value); 1856 add(reg, reg, rscratch2); 1857 } 1858 } 1859 1860 void MacroAssembler::incrementw(Address dst, int value) 1861 { 1862 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1863 ldrw(rscratch1, dst); 1864 incrementw(rscratch1, value); 1865 strw(rscratch1, dst); 1866 } 1867 1868 void MacroAssembler::increment(Address dst, int value) 1869 { 1870 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1871 ldr(rscratch1, dst); 1872 increment(rscratch1, value); 1873 str(rscratch1, dst); 1874 } 1875 1876 1877 void MacroAssembler::pusha() { 1878 push(0x7fffffff, sp); 1879 } 1880 1881 void MacroAssembler::popa() { 1882 pop(0x7fffffff, sp); 1883 } 1884 1885 // Push lots of registers in the bit set supplied. Don't push sp. 1886 // Return the number of words pushed 1887 int MacroAssembler::push(unsigned int bitset, Register stack) { 1888 int words_pushed = 0; 1889 1890 // Scan bitset to accumulate register pairs 1891 unsigned char regs[32]; 1892 int count = 0; 1893 for (int reg = 0; reg <= 30; reg++) { 1894 if (1 & bitset) 1895 regs[count++] = reg; 1896 bitset >>= 1; 1897 } 1898 regs[count++] = zr->encoding_nocheck(); 1899 count &= ~1; // Only push an even nuber of regs 1900 1901 if (count) { 1902 stp(as_Register(regs[0]), as_Register(regs[1]), 1903 Address(pre(stack, -count * wordSize))); 1904 words_pushed += 2; 1905 } 1906 for (int i = 2; i < count; i += 2) { 1907 stp(as_Register(regs[i]), as_Register(regs[i+1]), 1908 Address(stack, i * wordSize)); 1909 words_pushed += 2; 1910 } 1911 1912 assert(words_pushed == count, "oops, pushed != count"); 1913 1914 return count; 1915 } 1916 1917 int MacroAssembler::pop(unsigned int bitset, Register stack) { 1918 int words_pushed = 0; 1919 1920 // Scan bitset to accumulate register pairs 1921 unsigned char regs[32]; 1922 int count = 0; 1923 for (int reg = 0; reg <= 30; reg++) { 1924 if (1 & bitset) 1925 regs[count++] = reg; 1926 bitset >>= 1; 1927 } 1928 regs[count++] = zr->encoding_nocheck(); 1929 count &= ~1; 1930 1931 for (int i = 2; i < count; i += 2) { 1932 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 1933 Address(stack, i * wordSize)); 1934 words_pushed += 2; 1935 } 1936 if (count) { 1937 ldp(as_Register(regs[0]), as_Register(regs[1]), 1938 Address(post(stack, count * wordSize))); 1939 words_pushed += 2; 1940 } 1941 1942 assert(words_pushed == count, "oops, pushed != count"); 1943 1944 return count; 1945 } 1946 #ifdef ASSERT 1947 void MacroAssembler::verify_heapbase(const char* msg) { 1948 #if 0 1949 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 1950 assert (Universe::heap() != NULL, "java heap should be initialized"); 1951 if (CheckCompressedOops) { 1952 Label ok; 1953 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 1954 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 1955 br(Assembler::EQ, ok); 1956 stop(msg); 1957 bind(ok); 1958 pop(1 << rscratch1->encoding(), sp); 1959 } 1960 #endif 1961 } 1962 #endif 1963 1964 void MacroAssembler::stop(const char* msg) { 1965 address ip = pc(); 1966 pusha(); 1967 mov(c_rarg0, (address)msg); 1968 mov(c_rarg1, (address)ip); 1969 mov(c_rarg2, sp); 1970 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); 1971 // call(c_rarg3); 1972 blrt(c_rarg3, 3, 0, 1); 1973 hlt(0); 1974 } 1975 1976 // If a constant does not fit in an immediate field, generate some 1977 // number of MOV instructions and then perform the operation. 1978 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1979 add_sub_imm_insn insn1, 1980 add_sub_reg_insn insn2) { 1981 assert(Rd != zr, "Rd = zr and not setting flags?"); 1982 if (operand_valid_for_add_sub_immediate((int)imm)) { 1983 (this->*insn1)(Rd, Rn, imm); 1984 } else { 1985 if (uabs(imm) < (1 << 24)) { 1986 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 1987 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 1988 } else { 1989 assert_different_registers(Rd, Rn); 1990 mov(Rd, (uint64_t)imm); 1991 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 1992 } 1993 } 1994 } 1995 1996 // Seperate vsn which sets the flags. Optimisations are more restricted 1997 // because we must set the flags correctly. 1998 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1999 add_sub_imm_insn insn1, 2000 add_sub_reg_insn insn2) { 2001 if (operand_valid_for_add_sub_immediate((int)imm)) { 2002 (this->*insn1)(Rd, Rn, imm); 2003 } else { 2004 assert_different_registers(Rd, Rn); 2005 assert(Rd != zr, "overflow in immediate operand"); 2006 mov(Rd, (uint64_t)imm); 2007 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2008 } 2009 } 2010 2011 2012 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2013 if (increment.is_register()) { 2014 add(Rd, Rn, increment.as_register()); 2015 } else { 2016 add(Rd, Rn, increment.as_constant()); 2017 } 2018 } 2019 2020 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2021 if (increment.is_register()) { 2022 addw(Rd, Rn, increment.as_register()); 2023 } else { 2024 addw(Rd, Rn, increment.as_constant()); 2025 } 2026 } 2027 2028 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2029 if (decrement.is_register()) { 2030 sub(Rd, Rn, decrement.as_register()); 2031 } else { 2032 sub(Rd, Rn, decrement.as_constant()); 2033 } 2034 } 2035 2036 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2037 if (decrement.is_register()) { 2038 subw(Rd, Rn, decrement.as_register()); 2039 } else { 2040 subw(Rd, Rn, decrement.as_constant()); 2041 } 2042 } 2043 2044 void MacroAssembler::reinit_heapbase() 2045 { 2046 if (UseCompressedOops) { 2047 if (Universe::is_fully_initialized()) { 2048 mov(rheapbase, Universe::narrow_ptrs_base()); 2049 } else { 2050 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2051 ldr(rheapbase, Address(rheapbase)); 2052 } 2053 } 2054 } 2055 2056 // this simulates the behaviour of the x86 cmpxchg instruction using a 2057 // load linked/store conditional pair. we use the acquire/release 2058 // versions of these instructions so that we flush pending writes as 2059 // per Java semantics. 2060 2061 // n.b the x86 version assumes the old value to be compared against is 2062 // in rax and updates rax with the value located in memory if the 2063 // cmpxchg fails. we supply a register for the old value explicitly 2064 2065 // the aarch64 load linked/store conditional instructions do not 2066 // accept an offset. so, unlike x86, we must provide a plain register 2067 // to identify the memory word to be compared/exchanged rather than a 2068 // register+offset Address. 2069 2070 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2071 Label &succeed, Label *fail) { 2072 // oldv holds comparison value 2073 // newv holds value to write in exchange 2074 // addr identifies memory word to compare against/update 2075 // tmp returns 0/1 for success/failure 2076 Label retry_load, nope; 2077 2078 bind(retry_load); 2079 // flush and load exclusive from the memory location 2080 // and fail if it is not what we expect 2081 ldaxr(tmp, addr); 2082 cmp(tmp, oldv); 2083 br(Assembler::NE, nope); 2084 // if we store+flush with no intervening write tmp wil be zero 2085 stlxr(tmp, newv, addr); 2086 cbzw(tmp, succeed); 2087 // retry so we only ever return after a load fails to compare 2088 // ensures we don't return a stale value after a failed write. 2089 b(retry_load); 2090 // if the memory word differs we return it in oldv and signal a fail 2091 bind(nope); 2092 membar(AnyAny); 2093 mov(oldv, tmp); 2094 if (fail) 2095 b(*fail); 2096 } 2097 2098 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2099 Label &succeed, Label *fail) { 2100 // oldv holds comparison value 2101 // newv holds value to write in exchange 2102 // addr identifies memory word to compare against/update 2103 // tmp returns 0/1 for success/failure 2104 Label retry_load, nope; 2105 2106 bind(retry_load); 2107 // flush and load exclusive from the memory location 2108 // and fail if it is not what we expect 2109 ldaxrw(tmp, addr); 2110 cmp(tmp, oldv); 2111 br(Assembler::NE, nope); 2112 // if we store+flush with no intervening write tmp wil be zero 2113 stlxrw(tmp, newv, addr); 2114 cbzw(tmp, succeed); 2115 // retry so we only ever return after a load fails to compare 2116 // ensures we don't return a stale value after a failed write. 2117 b(retry_load); 2118 // if the memory word differs we return it in oldv and signal a fail 2119 bind(nope); 2120 membar(AnyAny); 2121 mov(oldv, tmp); 2122 if (fail) 2123 b(*fail); 2124 } 2125 2126 static bool different(Register a, RegisterOrConstant b, Register c) { 2127 if (b.is_constant()) 2128 return a != c; 2129 else 2130 return a != b.as_register() && a != c && b.as_register() != c; 2131 } 2132 2133 #define ATOMIC_OP(LDXR, OP, IOP, STXR) \ 2134 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \ 2135 Register result = rscratch2; \ 2136 if (prev->is_valid()) \ 2137 result = different(prev, incr, addr) ? prev : rscratch2; \ 2138 \ 2139 Label retry_load; \ 2140 bind(retry_load); \ 2141 LDXR(result, addr); \ 2142 OP(rscratch1, result, incr); \ 2143 STXR(rscratch2, rscratch1, addr); \ 2144 cbnzw(rscratch2, retry_load); \ 2145 if (prev->is_valid() && prev != result) { \ 2146 IOP(prev, rscratch1, incr); \ 2147 } \ 2148 } 2149 2150 ATOMIC_OP(ldxr, add, sub, stxr) 2151 ATOMIC_OP(ldxrw, addw, subw, stxrw) 2152 2153 #undef ATOMIC_OP 2154 2155 #define ATOMIC_XCHG(OP, LDXR, STXR) \ 2156 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2157 Register result = rscratch2; \ 2158 if (prev->is_valid()) \ 2159 result = different(prev, newv, addr) ? prev : rscratch2; \ 2160 \ 2161 Label retry_load; \ 2162 bind(retry_load); \ 2163 LDXR(result, addr); \ 2164 STXR(rscratch1, newv, addr); \ 2165 cbnzw(rscratch1, retry_load); \ 2166 if (prev->is_valid() && prev != result) \ 2167 mov(prev, result); \ 2168 } 2169 2170 ATOMIC_XCHG(xchg, ldxr, stxr) 2171 ATOMIC_XCHG(xchgw, ldxrw, stxrw) 2172 2173 #undef ATOMIC_XCHG 2174 2175 void MacroAssembler::incr_allocated_bytes(Register thread, 2176 Register var_size_in_bytes, 2177 int con_size_in_bytes, 2178 Register t1) { 2179 if (!thread->is_valid()) { 2180 thread = rthread; 2181 } 2182 assert(t1->is_valid(), "need temp reg"); 2183 2184 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2185 if (var_size_in_bytes->is_valid()) { 2186 add(t1, t1, var_size_in_bytes); 2187 } else { 2188 add(t1, t1, con_size_in_bytes); 2189 } 2190 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2191 } 2192 2193 #ifndef PRODUCT 2194 extern "C" void findpc(intptr_t x); 2195 #endif 2196 2197 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2198 { 2199 // In order to get locks to work, we need to fake a in_VM state 2200 if (ShowMessageBoxOnError ) { 2201 JavaThread* thread = JavaThread::current(); 2202 JavaThreadState saved_state = thread->thread_state(); 2203 thread->set_thread_state(_thread_in_vm); 2204 #ifndef PRODUCT 2205 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2206 ttyLocker ttyl; 2207 BytecodeCounter::print(); 2208 } 2209 #endif 2210 if (os::message_box(msg, "Execution stopped, print registers?")) { 2211 ttyLocker ttyl; 2212 tty->print_cr(" pc = 0x%016lx", pc); 2213 #ifndef PRODUCT 2214 tty->cr(); 2215 findpc(pc); 2216 tty->cr(); 2217 #endif 2218 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2219 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2220 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2221 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2222 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2223 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2224 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2225 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2226 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2227 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2228 tty->print_cr("r10 = 0x%016lx", regs[10]); 2229 tty->print_cr("r11 = 0x%016lx", regs[11]); 2230 tty->print_cr("r12 = 0x%016lx", regs[12]); 2231 tty->print_cr("r13 = 0x%016lx", regs[13]); 2232 tty->print_cr("r14 = 0x%016lx", regs[14]); 2233 tty->print_cr("r15 = 0x%016lx", regs[15]); 2234 tty->print_cr("r16 = 0x%016lx", regs[16]); 2235 tty->print_cr("r17 = 0x%016lx", regs[17]); 2236 tty->print_cr("r18 = 0x%016lx", regs[18]); 2237 tty->print_cr("r19 = 0x%016lx", regs[19]); 2238 tty->print_cr("r20 = 0x%016lx", regs[20]); 2239 tty->print_cr("r21 = 0x%016lx", regs[21]); 2240 tty->print_cr("r22 = 0x%016lx", regs[22]); 2241 tty->print_cr("r23 = 0x%016lx", regs[23]); 2242 tty->print_cr("r24 = 0x%016lx", regs[24]); 2243 tty->print_cr("r25 = 0x%016lx", regs[25]); 2244 tty->print_cr("r26 = 0x%016lx", regs[26]); 2245 tty->print_cr("r27 = 0x%016lx", regs[27]); 2246 tty->print_cr("r28 = 0x%016lx", regs[28]); 2247 tty->print_cr("r30 = 0x%016lx", regs[30]); 2248 tty->print_cr("r31 = 0x%016lx", regs[31]); 2249 BREAKPOINT; 2250 } 2251 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 2252 } else { 2253 ttyLocker ttyl; 2254 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 2255 msg); 2256 assert(false, "DEBUG MESSAGE: %s", msg); 2257 } 2258 } 2259 2260 #ifdef BUILTIN_SIM 2261 // routine to generate an x86 prolog for a stub function which 2262 // bootstraps into the generated ARM code which directly follows the 2263 // stub 2264 // 2265 // the argument encodes the number of general and fp registers 2266 // passed by the caller and the callng convention (currently just 2267 // the number of general registers and assumes C argument passing) 2268 2269 extern "C" { 2270 int aarch64_stub_prolog_size(); 2271 void aarch64_stub_prolog(); 2272 void aarch64_prolog(); 2273 } 2274 2275 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, 2276 address *prolog_ptr) 2277 { 2278 int calltype = (((ret_type & 0x3) << 8) | 2279 ((fp_arg_count & 0xf) << 4) | 2280 (gp_arg_count & 0xf)); 2281 2282 // the addresses for the x86 to ARM entry code we need to use 2283 address start = pc(); 2284 // printf("start = %lx\n", start); 2285 int byteCount = aarch64_stub_prolog_size(); 2286 // printf("byteCount = %x\n", byteCount); 2287 int instructionCount = (byteCount + 3)/ 4; 2288 // printf("instructionCount = %x\n", instructionCount); 2289 for (int i = 0; i < instructionCount; i++) { 2290 nop(); 2291 } 2292 2293 memcpy(start, (void*)aarch64_stub_prolog, byteCount); 2294 2295 // write the address of the setup routine and the call format at the 2296 // end of into the copied code 2297 u_int64_t *patch_end = (u_int64_t *)(start + byteCount); 2298 if (prolog_ptr) 2299 patch_end[-2] = (u_int64_t)prolog_ptr; 2300 patch_end[-1] = calltype; 2301 } 2302 #endif 2303 2304 void MacroAssembler::push_call_clobbered_registers() { 2305 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2306 2307 // Push v0-v7, v16-v31. 2308 for (int i = 30; i >= 0; i -= 2) { 2309 if (i <= v7->encoding() || i >= v16->encoding()) { 2310 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2311 Address(pre(sp, -2 * wordSize))); 2312 } 2313 } 2314 } 2315 2316 void MacroAssembler::pop_call_clobbered_registers() { 2317 2318 for (int i = 0; i < 32; i += 2) { 2319 if (i <= v7->encoding() || i >= v16->encoding()) { 2320 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2321 Address(post(sp, 2 * wordSize))); 2322 } 2323 } 2324 2325 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2326 } 2327 2328 void MacroAssembler::push_CPU_state(bool save_vectors) { 2329 push(0x3fffffff, sp); // integer registers except lr & sp 2330 2331 if (!save_vectors) { 2332 for (int i = 30; i >= 0; i -= 2) 2333 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2334 Address(pre(sp, -2 * wordSize))); 2335 } else { 2336 for (int i = 30; i >= 0; i -= 2) 2337 stpq(as_FloatRegister(i), as_FloatRegister(i+1), 2338 Address(pre(sp, -4 * wordSize))); 2339 } 2340 } 2341 2342 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2343 if (!restore_vectors) { 2344 for (int i = 0; i < 32; i += 2) 2345 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2346 Address(post(sp, 2 * wordSize))); 2347 } else { 2348 for (int i = 0; i < 32; i += 2) 2349 ldpq(as_FloatRegister(i), as_FloatRegister(i+1), 2350 Address(post(sp, 4 * wordSize))); 2351 } 2352 2353 pop(0x3fffffff, sp); // integer registers except lr & sp 2354 } 2355 2356 /** 2357 * Helpers for multiply_to_len(). 2358 */ 2359 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2360 Register src1, Register src2) { 2361 adds(dest_lo, dest_lo, src1); 2362 adc(dest_hi, dest_hi, zr); 2363 adds(dest_lo, dest_lo, src2); 2364 adc(final_dest_hi, dest_hi, zr); 2365 } 2366 2367 // Generate an address from (r + r1 extend offset). "size" is the 2368 // size of the operand. The result may be in rscratch2. 2369 Address MacroAssembler::offsetted_address(Register r, Register r1, 2370 Address::extend ext, int offset, int size) { 2371 if (offset || (ext.shift() % size != 0)) { 2372 lea(rscratch2, Address(r, r1, ext)); 2373 return Address(rscratch2, offset); 2374 } else { 2375 return Address(r, r1, ext); 2376 } 2377 } 2378 2379 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2380 { 2381 assert(offset >= 0, "spill to negative address?"); 2382 // Offset reachable ? 2383 // Not aligned - 9 bits signed offset 2384 // Aligned - 12 bits unsigned offset shifted 2385 Register base = sp; 2386 if ((offset & (size-1)) && offset >= (1<<8)) { 2387 add(tmp, base, offset & ((1<<12)-1)); 2388 base = tmp; 2389 offset &= -1<<12; 2390 } 2391 2392 if (offset >= (1<<12) * size) { 2393 add(tmp, base, offset & (((1<<12)-1)<<12)); 2394 base = tmp; 2395 offset &= ~(((1<<12)-1)<<12); 2396 } 2397 2398 return Address(base, offset); 2399 } 2400 2401 /** 2402 * Multiply 64 bit by 64 bit first loop. 2403 */ 2404 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2405 Register y, Register y_idx, Register z, 2406 Register carry, Register product, 2407 Register idx, Register kdx) { 2408 // 2409 // jlong carry, x[], y[], z[]; 2410 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2411 // huge_128 product = y[idx] * x[xstart] + carry; 2412 // z[kdx] = (jlong)product; 2413 // carry = (jlong)(product >>> 64); 2414 // } 2415 // z[xstart] = carry; 2416 // 2417 2418 Label L_first_loop, L_first_loop_exit; 2419 Label L_one_x, L_one_y, L_multiply; 2420 2421 subsw(xstart, xstart, 1); 2422 br(Assembler::MI, L_one_x); 2423 2424 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2425 ldr(x_xstart, Address(rscratch1)); 2426 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2427 2428 bind(L_first_loop); 2429 subsw(idx, idx, 1); 2430 br(Assembler::MI, L_first_loop_exit); 2431 subsw(idx, idx, 1); 2432 br(Assembler::MI, L_one_y); 2433 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2434 ldr(y_idx, Address(rscratch1)); 2435 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2436 bind(L_multiply); 2437 2438 // AArch64 has a multiply-accumulate instruction that we can't use 2439 // here because it has no way to process carries, so we have to use 2440 // separate add and adc instructions. Bah. 2441 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2442 mul(product, x_xstart, y_idx); 2443 adds(product, product, carry); 2444 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2445 2446 subw(kdx, kdx, 2); 2447 ror(product, product, 32); // back to big-endian 2448 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2449 2450 b(L_first_loop); 2451 2452 bind(L_one_y); 2453 ldrw(y_idx, Address(y, 0)); 2454 b(L_multiply); 2455 2456 bind(L_one_x); 2457 ldrw(x_xstart, Address(x, 0)); 2458 b(L_first_loop); 2459 2460 bind(L_first_loop_exit); 2461 } 2462 2463 /** 2464 * Multiply 128 bit by 128. Unrolled inner loop. 2465 * 2466 */ 2467 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2468 Register carry, Register carry2, 2469 Register idx, Register jdx, 2470 Register yz_idx1, Register yz_idx2, 2471 Register tmp, Register tmp3, Register tmp4, 2472 Register tmp6, Register product_hi) { 2473 2474 // jlong carry, x[], y[], z[]; 2475 // int kdx = ystart+1; 2476 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2477 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2478 // jlong carry2 = (jlong)(tmp3 >>> 64); 2479 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2480 // carry = (jlong)(tmp4 >>> 64); 2481 // z[kdx+idx+1] = (jlong)tmp3; 2482 // z[kdx+idx] = (jlong)tmp4; 2483 // } 2484 // idx += 2; 2485 // if (idx > 0) { 2486 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2487 // z[kdx+idx] = (jlong)yz_idx1; 2488 // carry = (jlong)(yz_idx1 >>> 64); 2489 // } 2490 // 2491 2492 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2493 2494 lsrw(jdx, idx, 2); 2495 2496 bind(L_third_loop); 2497 2498 subsw(jdx, jdx, 1); 2499 br(Assembler::MI, L_third_loop_exit); 2500 subw(idx, idx, 4); 2501 2502 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2503 2504 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2505 2506 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2507 2508 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2509 ror(yz_idx2, yz_idx2, 32); 2510 2511 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2512 2513 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2514 umulh(tmp4, product_hi, yz_idx1); 2515 2516 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2517 ror(rscratch2, rscratch2, 32); 2518 2519 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2520 umulh(carry2, product_hi, yz_idx2); 2521 2522 // propagate sum of both multiplications into carry:tmp4:tmp3 2523 adds(tmp3, tmp3, carry); 2524 adc(tmp4, tmp4, zr); 2525 adds(tmp3, tmp3, rscratch1); 2526 adcs(tmp4, tmp4, tmp); 2527 adc(carry, carry2, zr); 2528 adds(tmp4, tmp4, rscratch2); 2529 adc(carry, carry, zr); 2530 2531 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2532 ror(tmp4, tmp4, 32); 2533 stp(tmp4, tmp3, Address(tmp6, 0)); 2534 2535 b(L_third_loop); 2536 bind (L_third_loop_exit); 2537 2538 andw (idx, idx, 0x3); 2539 cbz(idx, L_post_third_loop_done); 2540 2541 Label L_check_1; 2542 subsw(idx, idx, 2); 2543 br(Assembler::MI, L_check_1); 2544 2545 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2546 ldr(yz_idx1, Address(rscratch1, 0)); 2547 ror(yz_idx1, yz_idx1, 32); 2548 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2549 umulh(tmp4, product_hi, yz_idx1); 2550 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2551 ldr(yz_idx2, Address(rscratch1, 0)); 2552 ror(yz_idx2, yz_idx2, 32); 2553 2554 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2555 2556 ror(tmp3, tmp3, 32); 2557 str(tmp3, Address(rscratch1, 0)); 2558 2559 bind (L_check_1); 2560 2561 andw (idx, idx, 0x1); 2562 subsw(idx, idx, 1); 2563 br(Assembler::MI, L_post_third_loop_done); 2564 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2565 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2566 umulh(carry2, tmp4, product_hi); 2567 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2568 2569 add2_with_carry(carry2, tmp3, tmp4, carry); 2570 2571 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2572 extr(carry, carry2, tmp3, 32); 2573 2574 bind(L_post_third_loop_done); 2575 } 2576 2577 /** 2578 * Code for BigInteger::multiplyToLen() instrinsic. 2579 * 2580 * r0: x 2581 * r1: xlen 2582 * r2: y 2583 * r3: ylen 2584 * r4: z 2585 * r5: zlen 2586 * r10: tmp1 2587 * r11: tmp2 2588 * r12: tmp3 2589 * r13: tmp4 2590 * r14: tmp5 2591 * r15: tmp6 2592 * r16: tmp7 2593 * 2594 */ 2595 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 2596 Register z, Register zlen, 2597 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 2598 Register tmp5, Register tmp6, Register product_hi) { 2599 2600 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 2601 2602 const Register idx = tmp1; 2603 const Register kdx = tmp2; 2604 const Register xstart = tmp3; 2605 2606 const Register y_idx = tmp4; 2607 const Register carry = tmp5; 2608 const Register product = xlen; 2609 const Register x_xstart = zlen; // reuse register 2610 2611 // First Loop. 2612 // 2613 // final static long LONG_MASK = 0xffffffffL; 2614 // int xstart = xlen - 1; 2615 // int ystart = ylen - 1; 2616 // long carry = 0; 2617 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2618 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 2619 // z[kdx] = (int)product; 2620 // carry = product >>> 32; 2621 // } 2622 // z[xstart] = (int)carry; 2623 // 2624 2625 movw(idx, ylen); // idx = ylen; 2626 movw(kdx, zlen); // kdx = xlen+ylen; 2627 mov(carry, zr); // carry = 0; 2628 2629 Label L_done; 2630 2631 movw(xstart, xlen); 2632 subsw(xstart, xstart, 1); 2633 br(Assembler::MI, L_done); 2634 2635 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 2636 2637 Label L_second_loop; 2638 cbzw(kdx, L_second_loop); 2639 2640 Label L_carry; 2641 subw(kdx, kdx, 1); 2642 cbzw(kdx, L_carry); 2643 2644 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2645 lsr(carry, carry, 32); 2646 subw(kdx, kdx, 1); 2647 2648 bind(L_carry); 2649 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2650 2651 // Second and third (nested) loops. 2652 // 2653 // for (int i = xstart-1; i >= 0; i--) { // Second loop 2654 // carry = 0; 2655 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 2656 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 2657 // (z[k] & LONG_MASK) + carry; 2658 // z[k] = (int)product; 2659 // carry = product >>> 32; 2660 // } 2661 // z[i] = (int)carry; 2662 // } 2663 // 2664 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 2665 2666 const Register jdx = tmp1; 2667 2668 bind(L_second_loop); 2669 mov(carry, zr); // carry = 0; 2670 movw(jdx, ylen); // j = ystart+1 2671 2672 subsw(xstart, xstart, 1); // i = xstart-1; 2673 br(Assembler::MI, L_done); 2674 2675 str(z, Address(pre(sp, -4 * wordSize))); 2676 2677 Label L_last_x; 2678 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 2679 subsw(xstart, xstart, 1); // i = xstart-1; 2680 br(Assembler::MI, L_last_x); 2681 2682 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 2683 ldr(product_hi, Address(rscratch1)); 2684 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 2685 2686 Label L_third_loop_prologue; 2687 bind(L_third_loop_prologue); 2688 2689 str(ylen, Address(sp, wordSize)); 2690 stp(x, xstart, Address(sp, 2 * wordSize)); 2691 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 2692 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 2693 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 2694 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 2695 2696 addw(tmp3, xlen, 1); 2697 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2698 subsw(tmp3, tmp3, 1); 2699 br(Assembler::MI, L_done); 2700 2701 lsr(carry, carry, 32); 2702 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2703 b(L_second_loop); 2704 2705 // Next infrequent code is moved outside loops. 2706 bind(L_last_x); 2707 ldrw(product_hi, Address(x, 0)); 2708 b(L_third_loop_prologue); 2709 2710 bind(L_done); 2711 } 2712 2713 /** 2714 * Emits code to update CRC-32 with a byte value according to constants in table 2715 * 2716 * @param [in,out]crc Register containing the crc. 2717 * @param [in]val Register containing the byte to fold into the CRC. 2718 * @param [in]table Register containing the table of crc constants. 2719 * 2720 * uint32_t crc; 2721 * val = crc_table[(val ^ crc) & 0xFF]; 2722 * crc = val ^ (crc >> 8); 2723 * 2724 */ 2725 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 2726 eor(val, val, crc); 2727 andr(val, val, 0xff); 2728 ldrw(val, Address(table, val, Address::lsl(2))); 2729 eor(crc, val, crc, Assembler::LSR, 8); 2730 } 2731 2732 /** 2733 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 2734 * 2735 * @param [in,out]crc Register containing the crc. 2736 * @param [in]v Register containing the 32-bit to fold into the CRC. 2737 * @param [in]table0 Register containing table 0 of crc constants. 2738 * @param [in]table1 Register containing table 1 of crc constants. 2739 * @param [in]table2 Register containing table 2 of crc constants. 2740 * @param [in]table3 Register containing table 3 of crc constants. 2741 * 2742 * uint32_t crc; 2743 * v = crc ^ v 2744 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 2745 * 2746 */ 2747 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 2748 Register table0, Register table1, Register table2, Register table3, 2749 bool upper) { 2750 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 2751 uxtb(tmp, v); 2752 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 2753 ubfx(tmp, v, 8, 8); 2754 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 2755 eor(crc, crc, tmp); 2756 ubfx(tmp, v, 16, 8); 2757 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 2758 eor(crc, crc, tmp); 2759 ubfx(tmp, v, 24, 8); 2760 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 2761 eor(crc, crc, tmp); 2762 } 2763 2764 /** 2765 * @param crc register containing existing CRC (32-bit) 2766 * @param buf register pointing to input byte buffer (byte*) 2767 * @param len register containing number of bytes 2768 * @param table register that will contain address of CRC table 2769 * @param tmp scratch register 2770 */ 2771 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 2772 Register table0, Register table1, Register table2, Register table3, 2773 Register tmp, Register tmp2, Register tmp3) { 2774 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 2775 unsigned long offset; 2776 2777 ornw(crc, zr, crc); 2778 2779 if (UseCRC32) { 2780 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 2781 2782 subs(len, len, 64); 2783 br(Assembler::GE, CRC_by64_loop); 2784 adds(len, len, 64-4); 2785 br(Assembler::GE, CRC_by4_loop); 2786 adds(len, len, 4); 2787 br(Assembler::GT, CRC_by1_loop); 2788 b(L_exit); 2789 2790 BIND(CRC_by4_loop); 2791 ldrw(tmp, Address(post(buf, 4))); 2792 subs(len, len, 4); 2793 crc32w(crc, crc, tmp); 2794 br(Assembler::GE, CRC_by4_loop); 2795 adds(len, len, 4); 2796 br(Assembler::LE, L_exit); 2797 BIND(CRC_by1_loop); 2798 ldrb(tmp, Address(post(buf, 1))); 2799 subs(len, len, 1); 2800 crc32b(crc, crc, tmp); 2801 br(Assembler::GT, CRC_by1_loop); 2802 b(L_exit); 2803 2804 align(CodeEntryAlignment); 2805 BIND(CRC_by64_loop); 2806 subs(len, len, 64); 2807 ldp(tmp, tmp3, Address(post(buf, 16))); 2808 crc32x(crc, crc, tmp); 2809 crc32x(crc, crc, tmp3); 2810 ldp(tmp, tmp3, Address(post(buf, 16))); 2811 crc32x(crc, crc, tmp); 2812 crc32x(crc, crc, tmp3); 2813 ldp(tmp, tmp3, Address(post(buf, 16))); 2814 crc32x(crc, crc, tmp); 2815 crc32x(crc, crc, tmp3); 2816 ldp(tmp, tmp3, Address(post(buf, 16))); 2817 crc32x(crc, crc, tmp); 2818 crc32x(crc, crc, tmp3); 2819 br(Assembler::GE, CRC_by64_loop); 2820 adds(len, len, 64-4); 2821 br(Assembler::GE, CRC_by4_loop); 2822 adds(len, len, 4); 2823 br(Assembler::GT, CRC_by1_loop); 2824 BIND(L_exit); 2825 ornw(crc, zr, crc); 2826 return; 2827 } 2828 2829 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2830 if (offset) add(table0, table0, offset); 2831 add(table1, table0, 1*256*sizeof(juint)); 2832 add(table2, table0, 2*256*sizeof(juint)); 2833 add(table3, table0, 3*256*sizeof(juint)); 2834 2835 if (UseNeon) { 2836 cmp(len, 64); 2837 br(Assembler::LT, L_by16); 2838 eor(v16, T16B, v16, v16); 2839 2840 Label L_fold; 2841 2842 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 2843 2844 ld1(v0, v1, T2D, post(buf, 32)); 2845 ld1r(v4, T2D, post(tmp, 8)); 2846 ld1r(v5, T2D, post(tmp, 8)); 2847 ld1r(v6, T2D, post(tmp, 8)); 2848 ld1r(v7, T2D, post(tmp, 8)); 2849 mov(v16, T4S, 0, crc); 2850 2851 eor(v0, T16B, v0, v16); 2852 sub(len, len, 64); 2853 2854 BIND(L_fold); 2855 pmull(v22, T8H, v0, v5, T8B); 2856 pmull(v20, T8H, v0, v7, T8B); 2857 pmull(v23, T8H, v0, v4, T8B); 2858 pmull(v21, T8H, v0, v6, T8B); 2859 2860 pmull2(v18, T8H, v0, v5, T16B); 2861 pmull2(v16, T8H, v0, v7, T16B); 2862 pmull2(v19, T8H, v0, v4, T16B); 2863 pmull2(v17, T8H, v0, v6, T16B); 2864 2865 uzp1(v24, v20, v22, T8H); 2866 uzp2(v25, v20, v22, T8H); 2867 eor(v20, T16B, v24, v25); 2868 2869 uzp1(v26, v16, v18, T8H); 2870 uzp2(v27, v16, v18, T8H); 2871 eor(v16, T16B, v26, v27); 2872 2873 ushll2(v22, T4S, v20, T8H, 8); 2874 ushll(v20, T4S, v20, T4H, 8); 2875 2876 ushll2(v18, T4S, v16, T8H, 8); 2877 ushll(v16, T4S, v16, T4H, 8); 2878 2879 eor(v22, T16B, v23, v22); 2880 eor(v18, T16B, v19, v18); 2881 eor(v20, T16B, v21, v20); 2882 eor(v16, T16B, v17, v16); 2883 2884 uzp1(v17, v16, v20, T2D); 2885 uzp2(v21, v16, v20, T2D); 2886 eor(v17, T16B, v17, v21); 2887 2888 ushll2(v20, T2D, v17, T4S, 16); 2889 ushll(v16, T2D, v17, T2S, 16); 2890 2891 eor(v20, T16B, v20, v22); 2892 eor(v16, T16B, v16, v18); 2893 2894 uzp1(v17, v20, v16, T2D); 2895 uzp2(v21, v20, v16, T2D); 2896 eor(v28, T16B, v17, v21); 2897 2898 pmull(v22, T8H, v1, v5, T8B); 2899 pmull(v20, T8H, v1, v7, T8B); 2900 pmull(v23, T8H, v1, v4, T8B); 2901 pmull(v21, T8H, v1, v6, T8B); 2902 2903 pmull2(v18, T8H, v1, v5, T16B); 2904 pmull2(v16, T8H, v1, v7, T16B); 2905 pmull2(v19, T8H, v1, v4, T16B); 2906 pmull2(v17, T8H, v1, v6, T16B); 2907 2908 ld1(v0, v1, T2D, post(buf, 32)); 2909 2910 uzp1(v24, v20, v22, T8H); 2911 uzp2(v25, v20, v22, T8H); 2912 eor(v20, T16B, v24, v25); 2913 2914 uzp1(v26, v16, v18, T8H); 2915 uzp2(v27, v16, v18, T8H); 2916 eor(v16, T16B, v26, v27); 2917 2918 ushll2(v22, T4S, v20, T8H, 8); 2919 ushll(v20, T4S, v20, T4H, 8); 2920 2921 ushll2(v18, T4S, v16, T8H, 8); 2922 ushll(v16, T4S, v16, T4H, 8); 2923 2924 eor(v22, T16B, v23, v22); 2925 eor(v18, T16B, v19, v18); 2926 eor(v20, T16B, v21, v20); 2927 eor(v16, T16B, v17, v16); 2928 2929 uzp1(v17, v16, v20, T2D); 2930 uzp2(v21, v16, v20, T2D); 2931 eor(v16, T16B, v17, v21); 2932 2933 ushll2(v20, T2D, v16, T4S, 16); 2934 ushll(v16, T2D, v16, T2S, 16); 2935 2936 eor(v20, T16B, v22, v20); 2937 eor(v16, T16B, v16, v18); 2938 2939 uzp1(v17, v20, v16, T2D); 2940 uzp2(v21, v20, v16, T2D); 2941 eor(v20, T16B, v17, v21); 2942 2943 shl(v16, T2D, v28, 1); 2944 shl(v17, T2D, v20, 1); 2945 2946 eor(v0, T16B, v0, v16); 2947 eor(v1, T16B, v1, v17); 2948 2949 subs(len, len, 32); 2950 br(Assembler::GE, L_fold); 2951 2952 mov(crc, 0); 2953 mov(tmp, v0, T1D, 0); 2954 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2955 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2956 mov(tmp, v0, T1D, 1); 2957 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2958 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2959 mov(tmp, v1, T1D, 0); 2960 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2961 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2962 mov(tmp, v1, T1D, 1); 2963 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2964 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2965 2966 add(len, len, 32); 2967 } 2968 2969 BIND(L_by16); 2970 subs(len, len, 16); 2971 br(Assembler::GE, L_by16_loop); 2972 adds(len, len, 16-4); 2973 br(Assembler::GE, L_by4_loop); 2974 adds(len, len, 4); 2975 br(Assembler::GT, L_by1_loop); 2976 b(L_exit); 2977 2978 BIND(L_by4_loop); 2979 ldrw(tmp, Address(post(buf, 4))); 2980 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 2981 subs(len, len, 4); 2982 br(Assembler::GE, L_by4_loop); 2983 adds(len, len, 4); 2984 br(Assembler::LE, L_exit); 2985 BIND(L_by1_loop); 2986 subs(len, len, 1); 2987 ldrb(tmp, Address(post(buf, 1))); 2988 update_byte_crc32(crc, tmp, table0); 2989 br(Assembler::GT, L_by1_loop); 2990 b(L_exit); 2991 2992 align(CodeEntryAlignment); 2993 BIND(L_by16_loop); 2994 subs(len, len, 16); 2995 ldp(tmp, tmp3, Address(post(buf, 16))); 2996 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2997 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 2998 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 2999 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 3000 br(Assembler::GE, L_by16_loop); 3001 adds(len, len, 16-4); 3002 br(Assembler::GE, L_by4_loop); 3003 adds(len, len, 4); 3004 br(Assembler::GT, L_by1_loop); 3005 BIND(L_exit); 3006 ornw(crc, zr, crc); 3007 } 3008 3009 /** 3010 * @param crc register containing existing CRC (32-bit) 3011 * @param buf register pointing to input byte buffer (byte*) 3012 * @param len register containing number of bytes 3013 * @param table register that will contain address of CRC table 3014 * @param tmp scratch register 3015 */ 3016 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3017 Register table0, Register table1, Register table2, Register table3, 3018 Register tmp, Register tmp2, Register tmp3) { 3019 Label L_exit; 3020 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 3021 3022 subs(len, len, 64); 3023 br(Assembler::GE, CRC_by64_loop); 3024 adds(len, len, 64-4); 3025 br(Assembler::GE, CRC_by4_loop); 3026 adds(len, len, 4); 3027 br(Assembler::GT, CRC_by1_loop); 3028 b(L_exit); 3029 3030 BIND(CRC_by4_loop); 3031 ldrw(tmp, Address(post(buf, 4))); 3032 subs(len, len, 4); 3033 crc32cw(crc, crc, tmp); 3034 br(Assembler::GE, CRC_by4_loop); 3035 adds(len, len, 4); 3036 br(Assembler::LE, L_exit); 3037 BIND(CRC_by1_loop); 3038 ldrb(tmp, Address(post(buf, 1))); 3039 subs(len, len, 1); 3040 crc32cb(crc, crc, tmp); 3041 br(Assembler::GT, CRC_by1_loop); 3042 b(L_exit); 3043 3044 align(CodeEntryAlignment); 3045 BIND(CRC_by64_loop); 3046 subs(len, len, 64); 3047 ldp(tmp, tmp3, Address(post(buf, 16))); 3048 crc32cx(crc, crc, tmp); 3049 crc32cx(crc, crc, tmp3); 3050 ldp(tmp, tmp3, Address(post(buf, 16))); 3051 crc32cx(crc, crc, tmp); 3052 crc32cx(crc, crc, tmp3); 3053 ldp(tmp, tmp3, Address(post(buf, 16))); 3054 crc32cx(crc, crc, tmp); 3055 crc32cx(crc, crc, tmp3); 3056 ldp(tmp, tmp3, Address(post(buf, 16))); 3057 crc32cx(crc, crc, tmp); 3058 crc32cx(crc, crc, tmp3); 3059 br(Assembler::GE, CRC_by64_loop); 3060 adds(len, len, 64-4); 3061 br(Assembler::GE, CRC_by4_loop); 3062 adds(len, len, 4); 3063 br(Assembler::GT, CRC_by1_loop); 3064 BIND(L_exit); 3065 return; 3066 } 3067 3068 SkipIfEqual::SkipIfEqual( 3069 MacroAssembler* masm, const bool* flag_addr, bool value) { 3070 _masm = masm; 3071 unsigned long offset; 3072 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3073 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3074 _masm->cbzw(rscratch1, _label); 3075 } 3076 3077 SkipIfEqual::~SkipIfEqual() { 3078 _masm->bind(_label); 3079 } 3080 3081 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3082 Address adr; 3083 switch(dst.getMode()) { 3084 case Address::base_plus_offset: 3085 // This is the expected mode, although we allow all the other 3086 // forms below. 3087 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3088 break; 3089 default: 3090 lea(rscratch2, dst); 3091 adr = Address(rscratch2); 3092 break; 3093 } 3094 ldr(rscratch1, adr); 3095 add(rscratch1, rscratch1, src); 3096 str(rscratch1, adr); 3097 } 3098 3099 void MacroAssembler::cmpptr(Register src1, Address src2) { 3100 unsigned long offset; 3101 adrp(rscratch1, src2, offset); 3102 ldr(rscratch1, Address(rscratch1, offset)); 3103 cmp(src1, rscratch1); 3104 } 3105 3106 void MacroAssembler::store_check(Register obj, Address dst) { 3107 store_check(obj); 3108 } 3109 3110 void MacroAssembler::store_check(Register obj) { 3111 // Does a store check for the oop in register obj. The content of 3112 // register obj is destroyed afterwards. 3113 3114 BarrierSet* bs = Universe::heap()->barrier_set(); 3115 assert(bs->kind() == BarrierSet::CardTableForRS || 3116 bs->kind() == BarrierSet::CardTableExtension, 3117 "Wrong barrier set kind"); 3118 3119 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 3120 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3121 3122 lsr(obj, obj, CardTableModRefBS::card_shift); 3123 3124 assert(CardTableModRefBS::dirty_card_val() == 0, "must be"); 3125 3126 load_byte_map_base(rscratch1); 3127 3128 if (UseCondCardMark) { 3129 Label L_already_dirty; 3130 membar(StoreLoad); 3131 ldrb(rscratch2, Address(obj, rscratch1)); 3132 cbz(rscratch2, L_already_dirty); 3133 strb(zr, Address(obj, rscratch1)); 3134 bind(L_already_dirty); 3135 } else { 3136 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) { 3137 membar(StoreStore); 3138 } 3139 strb(zr, Address(obj, rscratch1)); 3140 } 3141 } 3142 3143 void MacroAssembler::load_klass(Register dst, Register src) { 3144 if (UseCompressedClassPointers) { 3145 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3146 decode_klass_not_null(dst); 3147 } else { 3148 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3149 } 3150 } 3151 3152 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3153 if (UseCompressedClassPointers) { 3154 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3155 if (Universe::narrow_klass_base() == NULL) { 3156 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); 3157 return; 3158 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3159 && Universe::narrow_klass_shift() == 0) { 3160 // Only the bottom 32 bits matter 3161 cmpw(trial_klass, tmp); 3162 return; 3163 } 3164 decode_klass_not_null(tmp); 3165 } else { 3166 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3167 } 3168 cmp(trial_klass, tmp); 3169 } 3170 3171 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3172 load_klass(dst, src); 3173 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3174 } 3175 3176 void MacroAssembler::store_klass(Register dst, Register src) { 3177 // FIXME: Should this be a store release? concurrent gcs assumes 3178 // klass length is valid if klass field is not null. 3179 if (UseCompressedClassPointers) { 3180 encode_klass_not_null(src); 3181 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3182 } else { 3183 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3184 } 3185 } 3186 3187 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3188 if (UseCompressedClassPointers) { 3189 // Store to klass gap in destination 3190 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3191 } 3192 } 3193 3194 // Algorithm must match oop.inline.hpp encode_heap_oop. 3195 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3196 #ifdef ASSERT 3197 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3198 #endif 3199 verify_oop(s, "broken oop in encode_heap_oop"); 3200 if (Universe::narrow_oop_base() == NULL) { 3201 if (Universe::narrow_oop_shift() != 0) { 3202 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3203 lsr(d, s, LogMinObjAlignmentInBytes); 3204 } else { 3205 mov(d, s); 3206 } 3207 } else { 3208 subs(d, s, rheapbase); 3209 csel(d, d, zr, Assembler::HS); 3210 lsr(d, d, LogMinObjAlignmentInBytes); 3211 3212 /* Old algorithm: is this any worse? 3213 Label nonnull; 3214 cbnz(r, nonnull); 3215 sub(r, r, rheapbase); 3216 bind(nonnull); 3217 lsr(r, r, LogMinObjAlignmentInBytes); 3218 */ 3219 } 3220 } 3221 3222 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3223 #ifdef ASSERT 3224 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3225 if (CheckCompressedOops) { 3226 Label ok; 3227 cbnz(r, ok); 3228 stop("null oop passed to encode_heap_oop_not_null"); 3229 bind(ok); 3230 } 3231 #endif 3232 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3233 if (Universe::narrow_oop_base() != NULL) { 3234 sub(r, r, rheapbase); 3235 } 3236 if (Universe::narrow_oop_shift() != 0) { 3237 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3238 lsr(r, r, LogMinObjAlignmentInBytes); 3239 } 3240 } 3241 3242 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3243 #ifdef ASSERT 3244 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3245 if (CheckCompressedOops) { 3246 Label ok; 3247 cbnz(src, ok); 3248 stop("null oop passed to encode_heap_oop_not_null2"); 3249 bind(ok); 3250 } 3251 #endif 3252 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3253 3254 Register data = src; 3255 if (Universe::narrow_oop_base() != NULL) { 3256 sub(dst, src, rheapbase); 3257 data = dst; 3258 } 3259 if (Universe::narrow_oop_shift() != 0) { 3260 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3261 lsr(dst, data, LogMinObjAlignmentInBytes); 3262 data = dst; 3263 } 3264 if (data == src) 3265 mov(dst, src); 3266 } 3267 3268 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3269 #ifdef ASSERT 3270 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3271 #endif 3272 if (Universe::narrow_oop_base() == NULL) { 3273 if (Universe::narrow_oop_shift() != 0 || d != s) { 3274 lsl(d, s, Universe::narrow_oop_shift()); 3275 } 3276 } else { 3277 Label done; 3278 if (d != s) 3279 mov(d, s); 3280 cbz(s, done); 3281 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3282 bind(done); 3283 } 3284 verify_oop(d, "broken oop in decode_heap_oop"); 3285 } 3286 3287 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3288 assert (UseCompressedOops, "should only be used for compressed headers"); 3289 assert (Universe::heap() != NULL, "java heap should be initialized"); 3290 // Cannot assert, unverified entry point counts instructions (see .ad file) 3291 // vtableStubs also counts instructions in pd_code_size_limit. 3292 // Also do not verify_oop as this is called by verify_oop. 3293 if (Universe::narrow_oop_shift() != 0) { 3294 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3295 if (Universe::narrow_oop_base() != NULL) { 3296 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3297 } else { 3298 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3299 } 3300 } else { 3301 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3302 } 3303 } 3304 3305 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3306 assert (UseCompressedOops, "should only be used for compressed headers"); 3307 assert (Universe::heap() != NULL, "java heap should be initialized"); 3308 // Cannot assert, unverified entry point counts instructions (see .ad file) 3309 // vtableStubs also counts instructions in pd_code_size_limit. 3310 // Also do not verify_oop as this is called by verify_oop. 3311 if (Universe::narrow_oop_shift() != 0) { 3312 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3313 if (Universe::narrow_oop_base() != NULL) { 3314 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3315 } else { 3316 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3317 } 3318 } else { 3319 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3320 if (dst != src) { 3321 mov(dst, src); 3322 } 3323 } 3324 } 3325 3326 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3327 if (Universe::narrow_klass_base() == NULL) { 3328 if (Universe::narrow_klass_shift() != 0) { 3329 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3330 lsr(dst, src, LogKlassAlignmentInBytes); 3331 } else { 3332 if (dst != src) mov(dst, src); 3333 } 3334 return; 3335 } 3336 3337 if (use_XOR_for_compressed_class_base) { 3338 if (Universe::narrow_klass_shift() != 0) { 3339 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3340 lsr(dst, dst, LogKlassAlignmentInBytes); 3341 } else { 3342 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3343 } 3344 return; 3345 } 3346 3347 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3348 && Universe::narrow_klass_shift() == 0) { 3349 movw(dst, src); 3350 return; 3351 } 3352 3353 #ifdef ASSERT 3354 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 3355 #endif 3356 3357 Register rbase = dst; 3358 if (dst == src) rbase = rheapbase; 3359 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3360 sub(dst, src, rbase); 3361 if (Universe::narrow_klass_shift() != 0) { 3362 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3363 lsr(dst, dst, LogKlassAlignmentInBytes); 3364 } 3365 if (dst == src) reinit_heapbase(); 3366 } 3367 3368 void MacroAssembler::encode_klass_not_null(Register r) { 3369 encode_klass_not_null(r, r); 3370 } 3371 3372 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3373 Register rbase = dst; 3374 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3375 3376 if (Universe::narrow_klass_base() == NULL) { 3377 if (Universe::narrow_klass_shift() != 0) { 3378 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3379 lsl(dst, src, LogKlassAlignmentInBytes); 3380 } else { 3381 if (dst != src) mov(dst, src); 3382 } 3383 return; 3384 } 3385 3386 if (use_XOR_for_compressed_class_base) { 3387 if (Universe::narrow_klass_shift() != 0) { 3388 lsl(dst, src, LogKlassAlignmentInBytes); 3389 eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); 3390 } else { 3391 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3392 } 3393 return; 3394 } 3395 3396 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3397 && Universe::narrow_klass_shift() == 0) { 3398 if (dst != src) 3399 movw(dst, src); 3400 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); 3401 return; 3402 } 3403 3404 // Cannot assert, unverified entry point counts instructions (see .ad file) 3405 // vtableStubs also counts instructions in pd_code_size_limit. 3406 // Also do not verify_oop as this is called by verify_oop. 3407 if (dst == src) rbase = rheapbase; 3408 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3409 if (Universe::narrow_klass_shift() != 0) { 3410 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3411 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 3412 } else { 3413 add(dst, rbase, src); 3414 } 3415 if (dst == src) reinit_heapbase(); 3416 } 3417 3418 void MacroAssembler::decode_klass_not_null(Register r) { 3419 decode_klass_not_null(r, r); 3420 } 3421 3422 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 3423 assert (UseCompressedOops, "should only be used for compressed oops"); 3424 assert (Universe::heap() != NULL, "java heap should be initialized"); 3425 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3426 3427 int oop_index = oop_recorder()->find_index(obj); 3428 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3429 3430 InstructionMark im(this); 3431 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3432 code_section()->relocate(inst_mark(), rspec); 3433 movz(dst, 0xDEAD, 16); 3434 movk(dst, 0xBEEF); 3435 } 3436 3437 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 3438 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3439 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3440 int index = oop_recorder()->find_index(k); 3441 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); 3442 3443 InstructionMark im(this); 3444 RelocationHolder rspec = metadata_Relocation::spec(index); 3445 code_section()->relocate(inst_mark(), rspec); 3446 narrowKlass nk = Klass::encode_klass(k); 3447 movz(dst, (nk >> 16), 16); 3448 movk(dst, nk & 0xffff); 3449 } 3450 3451 void MacroAssembler::load_heap_oop(Register dst, Address src) 3452 { 3453 if (UseCompressedOops) { 3454 ldrw(dst, src); 3455 decode_heap_oop(dst); 3456 } else { 3457 ldr(dst, src); 3458 } 3459 } 3460 3461 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) 3462 { 3463 if (UseCompressedOops) { 3464 ldrw(dst, src); 3465 decode_heap_oop_not_null(dst); 3466 } else { 3467 ldr(dst, src); 3468 } 3469 } 3470 3471 void MacroAssembler::store_heap_oop(Address dst, Register src) { 3472 if (UseCompressedOops) { 3473 assert(!dst.uses(src), "not enough registers"); 3474 encode_heap_oop(src); 3475 strw(src, dst); 3476 } else 3477 str(src, dst); 3478 } 3479 3480 // Used for storing NULLs. 3481 void MacroAssembler::store_heap_oop_null(Address dst) { 3482 if (UseCompressedOops) { 3483 strw(zr, dst); 3484 } else 3485 str(zr, dst); 3486 } 3487 3488 #if INCLUDE_ALL_GCS 3489 void MacroAssembler::g1_write_barrier_pre(Register obj, 3490 Register pre_val, 3491 Register thread, 3492 Register tmp, 3493 bool tosca_live, 3494 bool expand_call) { 3495 // If expand_call is true then we expand the call_VM_leaf macro 3496 // directly to skip generating the check by 3497 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 3498 3499 assert(thread == rthread, "must be"); 3500 3501 Label done; 3502 Label runtime; 3503 3504 assert(pre_val != noreg, "check this code"); 3505 3506 if (obj != noreg) 3507 assert_different_registers(obj, pre_val, tmp); 3508 3509 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3510 SATBMarkQueue::byte_offset_of_active())); 3511 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3512 SATBMarkQueue::byte_offset_of_index())); 3513 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3514 SATBMarkQueue::byte_offset_of_buf())); 3515 3516 3517 // Is marking active? 3518 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3519 ldrw(tmp, in_progress); 3520 } else { 3521 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 3522 ldrb(tmp, in_progress); 3523 } 3524 cbzw(tmp, done); 3525 3526 // Do we need to load the previous value? 3527 if (obj != noreg) { 3528 load_heap_oop(pre_val, Address(obj, 0)); 3529 } 3530 3531 // Is the previous value null? 3532 cbz(pre_val, done); 3533 3534 // Can we store original value in the thread's buffer? 3535 // Is index == 0? 3536 // (The index field is typed as size_t.) 3537 3538 ldr(tmp, index); // tmp := *index_adr 3539 cbz(tmp, runtime); // tmp == 0? 3540 // If yes, goto runtime 3541 3542 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize 3543 str(tmp, index); // *index_adr := tmp 3544 ldr(rscratch1, buffer); 3545 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr 3546 3547 // Record the previous value 3548 str(pre_val, Address(tmp, 0)); 3549 b(done); 3550 3551 bind(runtime); 3552 // save the live input values 3553 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3554 3555 // Calling the runtime using the regular call_VM_leaf mechanism generates 3556 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 3557 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. 3558 // 3559 // If we care generating the pre-barrier without a frame (e.g. in the 3560 // intrinsified Reference.get() routine) then ebp might be pointing to 3561 // the caller frame and so this check will most likely fail at runtime. 3562 // 3563 // Expanding the call directly bypasses the generation of the check. 3564 // So when we do not have have a full interpreter frame on the stack 3565 // expand_call should be passed true. 3566 3567 if (expand_call) { 3568 assert(pre_val != c_rarg1, "smashed arg"); 3569 pass_arg1(this, thread); 3570 pass_arg0(this, pre_val); 3571 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 3572 } else { 3573 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 3574 } 3575 3576 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3577 3578 bind(done); 3579 } 3580 3581 void MacroAssembler::g1_write_barrier_post(Register store_addr, 3582 Register new_val, 3583 Register thread, 3584 Register tmp, 3585 Register tmp2) { 3586 assert(thread == rthread, "must be"); 3587 3588 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3589 DirtyCardQueue::byte_offset_of_index())); 3590 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3591 DirtyCardQueue::byte_offset_of_buf())); 3592 3593 BarrierSet* bs = Universe::heap()->barrier_set(); 3594 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 3595 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3596 3597 Label done; 3598 Label runtime; 3599 3600 // Does store cross heap regions? 3601 3602 eor(tmp, store_addr, new_val); 3603 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes); 3604 cbz(tmp, done); 3605 3606 // crosses regions, storing NULL? 3607 3608 cbz(new_val, done); 3609 3610 // storing region crossing non-NULL, is card already dirty? 3611 3612 ExternalAddress cardtable((address) ct->byte_map_base); 3613 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3614 const Register card_addr = tmp; 3615 3616 lsr(card_addr, store_addr, CardTableModRefBS::card_shift); 3617 3618 // get the address of the card 3619 load_byte_map_base(tmp2); 3620 add(card_addr, card_addr, tmp2); 3621 ldrb(tmp2, Address(card_addr)); 3622 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val()); 3623 br(Assembler::EQ, done); 3624 3625 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); 3626 3627 membar(Assembler::StoreLoad); 3628 3629 ldrb(tmp2, Address(card_addr)); 3630 cbzw(tmp2, done); 3631 3632 // storing a region crossing, non-NULL oop, card is clean. 3633 // dirty card and log. 3634 3635 strb(zr, Address(card_addr)); 3636 3637 ldr(rscratch1, queue_index); 3638 cbz(rscratch1, runtime); 3639 sub(rscratch1, rscratch1, wordSize); 3640 str(rscratch1, queue_index); 3641 3642 ldr(tmp2, buffer); 3643 str(card_addr, Address(tmp2, rscratch1)); 3644 b(done); 3645 3646 bind(runtime); 3647 // save the live input values 3648 push(store_addr->bit(true) | new_val->bit(true), sp); 3649 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 3650 pop(store_addr->bit(true) | new_val->bit(true), sp); 3651 3652 bind(done); 3653 } 3654 3655 #endif // INCLUDE_ALL_GCS 3656 3657 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 3658 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 3659 int index = oop_recorder()->allocate_metadata_index(obj); 3660 RelocationHolder rspec = metadata_Relocation::spec(index); 3661 return Address((address)obj, rspec); 3662 } 3663 3664 // Move an oop into a register. immediate is true if we want 3665 // immediate instrcutions, i.e. we are not going to patch this 3666 // instruction while the code is being executed by another thread. In 3667 // that case we can use move immediates rather than the constant pool. 3668 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 3669 int oop_index; 3670 if (obj == NULL) { 3671 oop_index = oop_recorder()->allocate_oop_index(obj); 3672 } else { 3673 oop_index = oop_recorder()->find_index(obj); 3674 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3675 } 3676 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3677 if (! immediate) { 3678 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 3679 ldr_constant(dst, Address(dummy, rspec)); 3680 } else 3681 mov(dst, Address((address)obj, rspec)); 3682 } 3683 3684 // Move a metadata address into a register. 3685 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 3686 int oop_index; 3687 if (obj == NULL) { 3688 oop_index = oop_recorder()->allocate_metadata_index(obj); 3689 } else { 3690 oop_index = oop_recorder()->find_index(obj); 3691 } 3692 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 3693 mov(dst, Address((address)obj, rspec)); 3694 } 3695 3696 Address MacroAssembler::constant_oop_address(jobject obj) { 3697 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3698 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 3699 int oop_index = oop_recorder()->find_index(obj); 3700 return Address((address)obj, oop_Relocation::spec(oop_index)); 3701 } 3702 3703 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3704 void MacroAssembler::tlab_allocate(Register obj, 3705 Register var_size_in_bytes, 3706 int con_size_in_bytes, 3707 Register t1, 3708 Register t2, 3709 Label& slow_case) { 3710 assert_different_registers(obj, t2); 3711 assert_different_registers(obj, var_size_in_bytes); 3712 Register end = t2; 3713 3714 // verify_tlab(); 3715 3716 ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); 3717 if (var_size_in_bytes == noreg) { 3718 lea(end, Address(obj, con_size_in_bytes)); 3719 } else { 3720 lea(end, Address(obj, var_size_in_bytes)); 3721 } 3722 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); 3723 cmp(end, rscratch1); 3724 br(Assembler::HI, slow_case); 3725 3726 // update the tlab top pointer 3727 str(end, Address(rthread, JavaThread::tlab_top_offset())); 3728 3729 // recover var_size_in_bytes if necessary 3730 if (var_size_in_bytes == end) { 3731 sub(var_size_in_bytes, var_size_in_bytes, obj); 3732 } 3733 // verify_tlab(); 3734 } 3735 3736 // Preserves r19, and r3. 3737 Register MacroAssembler::tlab_refill(Label& retry, 3738 Label& try_eden, 3739 Label& slow_case) { 3740 Register top = r0; 3741 Register t1 = r2; 3742 Register t2 = r4; 3743 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3); 3744 Label do_refill, discard_tlab; 3745 3746 if (!Universe::heap()->supports_inline_contig_alloc()) { 3747 // No allocation in the shared eden. 3748 b(slow_case); 3749 } 3750 3751 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3752 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3753 3754 // calculate amount of free space 3755 sub(t1, t1, top); 3756 lsr(t1, t1, LogHeapWordSize); 3757 3758 // Retain tlab and allocate object in shared space if 3759 // the amount free in the tlab is too large to discard. 3760 3761 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3762 cmp(t1, rscratch1); 3763 br(Assembler::LE, discard_tlab); 3764 3765 // Retain 3766 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3767 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 3768 add(rscratch1, rscratch1, t2); 3769 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3770 3771 if (TLABStats) { 3772 // increment number of slow_allocations 3773 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), 3774 1, rscratch1); 3775 } 3776 b(try_eden); 3777 3778 bind(discard_tlab); 3779 if (TLABStats) { 3780 // increment number of refills 3781 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, 3782 rscratch1); 3783 // accumulate wastage -- t1 is amount free in tlab 3784 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, 3785 rscratch1); 3786 } 3787 3788 // if tlab is currently allocated (top or end != null) then 3789 // fill [top, end + alignment_reserve) with array object 3790 cbz(top, do_refill); 3791 3792 // set up the mark word 3793 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 3794 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes())); 3795 // set the length to the remaining space 3796 sub(t1, t1, typeArrayOopDesc::header_size(T_INT)); 3797 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 3798 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); 3799 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes())); 3800 // set klass to intArrayKlass 3801 { 3802 unsigned long offset; 3803 // dubious reloc why not an oop reloc? 3804 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), 3805 offset); 3806 ldr(t1, Address(rscratch1, offset)); 3807 } 3808 // store klass last. concurrent gcs assumes klass length is valid if 3809 // klass field is not null. 3810 store_klass(top, t1); 3811 3812 mov(t1, top); 3813 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3814 sub(t1, t1, rscratch1); 3815 incr_allocated_bytes(rthread, t1, 0, rscratch1); 3816 3817 // refill the tlab with an eden allocation 3818 bind(do_refill); 3819 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3820 lsl(t1, t1, LogHeapWordSize); 3821 // allocate new tlab, address returned in top 3822 eden_allocate(top, t1, 0, t2, slow_case); 3823 3824 // Check that t1 was preserved in eden_allocate. 3825 #ifdef ASSERT 3826 if (UseTLAB) { 3827 Label ok; 3828 Register tsize = r4; 3829 assert_different_registers(tsize, rthread, t1); 3830 str(tsize, Address(pre(sp, -16))); 3831 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3832 lsl(tsize, tsize, LogHeapWordSize); 3833 cmp(t1, tsize); 3834 br(Assembler::EQ, ok); 3835 STOP("assert(t1 != tlab size)"); 3836 should_not_reach_here(); 3837 3838 bind(ok); 3839 ldr(tsize, Address(post(sp, 16))); 3840 } 3841 #endif 3842 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3843 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3844 add(top, top, t1); 3845 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 3846 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3847 verify_tlab(); 3848 b(retry); 3849 3850 return rthread; // for use by caller 3851 } 3852 3853 // Defines obj, preserves var_size_in_bytes 3854 void MacroAssembler::eden_allocate(Register obj, 3855 Register var_size_in_bytes, 3856 int con_size_in_bytes, 3857 Register t1, 3858 Label& slow_case) { 3859 assert_different_registers(obj, var_size_in_bytes, t1); 3860 if (!Universe::heap()->supports_inline_contig_alloc()) { 3861 b(slow_case); 3862 } else { 3863 Register end = t1; 3864 Register heap_end = rscratch2; 3865 Label retry; 3866 bind(retry); 3867 { 3868 unsigned long offset; 3869 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); 3870 ldr(heap_end, Address(rscratch1, offset)); 3871 } 3872 3873 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 3874 3875 // Get the current top of the heap 3876 { 3877 unsigned long offset; 3878 adrp(rscratch1, heap_top, offset); 3879 // Use add() here after ARDP, rather than lea(). 3880 // lea() does not generate anything if its offset is zero. 3881 // However, relocs expect to find either an ADD or a load/store 3882 // insn after an ADRP. add() always generates an ADD insn, even 3883 // for add(Rn, Rn, 0). 3884 add(rscratch1, rscratch1, offset); 3885 ldaxr(obj, rscratch1); 3886 } 3887 3888 // Adjust it my the size of our new object 3889 if (var_size_in_bytes == noreg) { 3890 lea(end, Address(obj, con_size_in_bytes)); 3891 } else { 3892 lea(end, Address(obj, var_size_in_bytes)); 3893 } 3894 3895 // if end < obj then we wrapped around high memory 3896 cmp(end, obj); 3897 br(Assembler::LO, slow_case); 3898 3899 cmp(end, heap_end); 3900 br(Assembler::HI, slow_case); 3901 3902 // If heap_top hasn't been changed by some other thread, update it. 3903 stlxr(rscratch2, end, rscratch1); 3904 cbnzw(rscratch2, retry); 3905 } 3906 } 3907 3908 void MacroAssembler::verify_tlab() { 3909 #ifdef ASSERT 3910 if (UseTLAB && VerifyOops) { 3911 Label next, ok; 3912 3913 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 3914 3915 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3916 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3917 cmp(rscratch2, rscratch1); 3918 br(Assembler::HS, next); 3919 STOP("assert(top >= start)"); 3920 should_not_reach_here(); 3921 3922 bind(next); 3923 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3924 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3925 cmp(rscratch2, rscratch1); 3926 br(Assembler::HS, ok); 3927 STOP("assert(top <= end)"); 3928 should_not_reach_here(); 3929 3930 bind(ok); 3931 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 3932 } 3933 #endif 3934 } 3935 3936 // Writes to stack successive pages until offset reached to check for 3937 // stack overflow + shadow pages. This clobbers tmp. 3938 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 3939 assert_different_registers(tmp, size, rscratch1); 3940 mov(tmp, sp); 3941 // Bang stack for total size given plus shadow page size. 3942 // Bang one page at a time because large size can bang beyond yellow and 3943 // red zones. 3944 Label loop; 3945 mov(rscratch1, os::vm_page_size()); 3946 bind(loop); 3947 lea(tmp, Address(tmp, -os::vm_page_size())); 3948 subsw(size, size, rscratch1); 3949 str(size, Address(tmp)); 3950 br(Assembler::GT, loop); 3951 3952 // Bang down shadow pages too. 3953 // At this point, (tmp-0) is the last address touched, so don't 3954 // touch it again. (It was touched as (tmp-pagesize) but then tmp 3955 // was post-decremented.) Skip this address by starting at i=1, and 3956 // touch a few more pages below. N.B. It is important to touch all 3957 // the way down to and including i=StackShadowPages. 3958 for (int i = 0; i< StackShadowPages-1; i++) { 3959 // this could be any sized move but this is can be a debugging crumb 3960 // so the bigger the better. 3961 lea(tmp, Address(tmp, -os::vm_page_size())); 3962 str(size, Address(tmp)); 3963 } 3964 } 3965 3966 3967 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { 3968 unsigned long off; 3969 adrp(r, Address(page, rtype), off); 3970 InstructionMark im(this); 3971 code_section()->relocate(inst_mark(), rtype); 3972 ldrw(zr, Address(r, off)); 3973 return inst_mark(); 3974 } 3975 3976 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 3977 InstructionMark im(this); 3978 code_section()->relocate(inst_mark(), rtype); 3979 ldrw(zr, Address(r, 0)); 3980 return inst_mark(); 3981 } 3982 3983 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { 3984 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 3985 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; 3986 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; 3987 unsigned long dest_page = (unsigned long)dest.target() >> 12; 3988 long offset_low = dest_page - low_page; 3989 long offset_high = dest_page - high_page; 3990 3991 assert(is_valid_AArch64_address(dest.target()), "bad address"); 3992 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 3993 3994 InstructionMark im(this); 3995 code_section()->relocate(inst_mark(), dest.rspec()); 3996 // 8143067: Ensure that the adrp can reach the dest from anywhere within 3997 // the code cache so that if it is relocated we know it will still reach 3998 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 3999 _adrp(reg1, dest.target()); 4000 } else { 4001 unsigned long pc_page = (unsigned long)pc() >> 12; 4002 long offset = dest_page - pc_page; 4003 offset = (offset & ((1<<20)-1)) << 12; 4004 _adrp(reg1, pc()+offset); 4005 movk(reg1, (unsigned long)dest.target() >> 32, 32); 4006 } 4007 byte_offset = (unsigned long)dest.target() & 0xfff; 4008 } 4009 4010 void MacroAssembler::load_byte_map_base(Register reg) { 4011 jbyte *byte_map_base = 4012 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base; 4013 4014 if (is_valid_AArch64_address((address)byte_map_base)) { 4015 // Strictly speaking the byte_map_base isn't an address at all, 4016 // and it might even be negative. 4017 unsigned long offset; 4018 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4019 assert(offset == 0, "misaligned card table base"); 4020 } else { 4021 mov(reg, (uint64_t)byte_map_base); 4022 } 4023 } 4024 4025 void MacroAssembler::build_frame(int framesize) { 4026 assert(framesize > 0, "framesize must be > 0"); 4027 if (framesize < ((1 << 9) + 2 * wordSize)) { 4028 sub(sp, sp, framesize); 4029 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4030 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4031 } else { 4032 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4033 if (PreserveFramePointer) mov(rfp, sp); 4034 if (framesize < ((1 << 12) + 2 * wordSize)) 4035 sub(sp, sp, framesize - 2 * wordSize); 4036 else { 4037 mov(rscratch1, framesize - 2 * wordSize); 4038 sub(sp, sp, rscratch1); 4039 } 4040 } 4041 } 4042 4043 void MacroAssembler::remove_frame(int framesize) { 4044 assert(framesize > 0, "framesize must be > 0"); 4045 if (framesize < ((1 << 9) + 2 * wordSize)) { 4046 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4047 add(sp, sp, framesize); 4048 } else { 4049 if (framesize < ((1 << 12) + 2 * wordSize)) 4050 add(sp, sp, framesize - 2 * wordSize); 4051 else { 4052 mov(rscratch1, framesize - 2 * wordSize); 4053 add(sp, sp, rscratch1); 4054 } 4055 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4056 } 4057 } 4058 4059 4060 // Search for str1 in str2 and return index or -1 4061 void MacroAssembler::string_indexof(Register str2, Register str1, 4062 Register cnt2, Register cnt1, 4063 Register tmp1, Register tmp2, 4064 Register tmp3, Register tmp4, 4065 int icnt1, Register result) { 4066 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; 4067 4068 Register ch1 = rscratch1; 4069 Register ch2 = rscratch2; 4070 Register cnt1tmp = tmp1; 4071 Register cnt2tmp = tmp2; 4072 Register cnt1_neg = cnt1; 4073 Register cnt2_neg = cnt2; 4074 Register result_tmp = tmp4; 4075 4076 // Note, inline_string_indexOf() generates checks: 4077 // if (substr.count > string.count) return -1; 4078 // if (substr.count == 0) return 0; 4079 4080 // We have two strings, a source string in str2, cnt2 and a pattern string 4081 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1. 4082 4083 // For larger pattern and source we use a simplified Boyer Moore algorithm. 4084 // With a small pattern and source we use linear scan. 4085 4086 if (icnt1 == -1) { 4087 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 4088 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use 4089 br(LO, LINEARSEARCH); // a byte array. 4090 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM 4091 br(HS, LINEARSEARCH); 4092 } 4093 4094 // The Boyer Moore alogorithm is based on the description here:- 4095 // 4096 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm 4097 // 4098 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule 4099 // and the 'Good Suffix' rule. 4100 // 4101 // These rules are essentially heuristics for how far we can shift the 4102 // pattern along the search string. 4103 // 4104 // The implementation here uses the 'Bad Character' rule only because of the 4105 // complexity of initialisation for the 'Good Suffix' rule. 4106 // 4107 // This is also known as the Boyer-Moore-Horspool algorithm:- 4108 // 4109 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm 4110 // 4111 // #define ASIZE 128 4112 // 4113 // int bm(unsigned char *x, int m, unsigned char *y, int n) { 4114 // int i, j; 4115 // unsigned c; 4116 // unsigned char bc[ASIZE]; 4117 // 4118 // /* Preprocessing */ 4119 // for (i = 0; i < ASIZE; ++i) 4120 // bc[i] = 0; 4121 // for (i = 0; i < m - 1; ) { 4122 // c = x[i]; 4123 // ++i; 4124 // if (c < ASIZE) bc[c] = i; 4125 // } 4126 // 4127 // /* Searching */ 4128 // j = 0; 4129 // while (j <= n - m) { 4130 // c = y[i+j]; 4131 // if (x[m-1] == c) 4132 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); 4133 // if (i < 0) return j; 4134 // if (c < ASIZE) 4135 // j = j - bc[y[j+m-1]] + m; 4136 // else 4137 // j += 1; // Advance by 1 only if char >= ASIZE 4138 // } 4139 // } 4140 4141 if (icnt1 == -1) { 4142 BIND(BM); 4143 4144 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; 4145 Label BMADV, BMMATCH, BMCHECKEND; 4146 4147 Register cnt1end = tmp2; 4148 Register str2end = cnt2; 4149 Register skipch = tmp2; 4150 4151 // Restrict ASIZE to 128 to reduce stack space/initialisation. 4152 // The presence of chars >= ASIZE in the target string does not affect 4153 // performance, but we must be careful not to initialise them in the stack 4154 // array. 4155 // The presence of chars >= ASIZE in the source string may adversely affect 4156 // performance since we can only advance by one when we encounter one. 4157 4158 stp(zr, zr, pre(sp, -128)); 4159 for (int i = 1; i < 8; i++) 4160 stp(zr, zr, Address(sp, i*16)); 4161 4162 mov(cnt1tmp, 0); 4163 sub(cnt1end, cnt1, 1); 4164 BIND(BCLOOP); 4165 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4166 cmp(ch1, 128); 4167 add(cnt1tmp, cnt1tmp, 1); 4168 br(HS, BCSKIP); 4169 strb(cnt1tmp, Address(sp, ch1)); 4170 BIND(BCSKIP); 4171 cmp(cnt1tmp, cnt1end); 4172 br(LT, BCLOOP); 4173 4174 mov(result_tmp, str2); 4175 4176 sub(cnt2, cnt2, cnt1); 4177 add(str2end, str2, cnt2, LSL, 1); 4178 BIND(BMLOOPSTR2); 4179 sub(cnt1tmp, cnt1, 1); 4180 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4181 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1))); 4182 cmp(ch1, skipch); 4183 br(NE, BMSKIP); 4184 subs(cnt1tmp, cnt1tmp, 1); 4185 br(LT, BMMATCH); 4186 BIND(BMLOOPSTR1); 4187 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4188 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1))); 4189 cmp(ch1, ch2); 4190 br(NE, BMSKIP); 4191 subs(cnt1tmp, cnt1tmp, 1); 4192 br(GE, BMLOOPSTR1); 4193 BIND(BMMATCH); 4194 sub(result_tmp, str2, result_tmp); 4195 lsr(result, result_tmp, 1); 4196 add(sp, sp, 128); 4197 b(DONE); 4198 BIND(BMADV); 4199 add(str2, str2, 2); 4200 b(BMCHECKEND); 4201 BIND(BMSKIP); 4202 cmp(skipch, 128); 4203 br(HS, BMADV); 4204 ldrb(ch2, Address(sp, skipch)); 4205 add(str2, str2, cnt1, LSL, 1); 4206 sub(str2, str2, ch2, LSL, 1); 4207 BIND(BMCHECKEND); 4208 cmp(str2, str2end); 4209 br(LE, BMLOOPSTR2); 4210 add(sp, sp, 128); 4211 b(NOMATCH); 4212 } 4213 4214 BIND(LINEARSEARCH); 4215 { 4216 Label DO1, DO2, DO3; 4217 4218 Register str2tmp = tmp2; 4219 Register first = tmp3; 4220 4221 if (icnt1 == -1) 4222 { 4223 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD; 4224 4225 cmp(cnt1, 4); 4226 br(LT, DOSHORT); 4227 4228 sub(cnt2, cnt2, cnt1); 4229 sub(cnt1, cnt1, 4); 4230 mov(result_tmp, cnt2); 4231 4232 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4233 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4234 sub(cnt1_neg, zr, cnt1, LSL, 1); 4235 sub(cnt2_neg, zr, cnt2, LSL, 1); 4236 ldr(first, Address(str1, cnt1_neg)); 4237 4238 BIND(FIRST_LOOP); 4239 ldr(ch2, Address(str2, cnt2_neg)); 4240 cmp(first, ch2); 4241 br(EQ, STR1_LOOP); 4242 BIND(STR2_NEXT); 4243 adds(cnt2_neg, cnt2_neg, 2); 4244 br(LE, FIRST_LOOP); 4245 b(NOMATCH); 4246 4247 BIND(STR1_LOOP); 4248 adds(cnt1tmp, cnt1_neg, 8); 4249 add(cnt2tmp, cnt2_neg, 8); 4250 br(GE, LAST_WORD); 4251 4252 BIND(STR1_NEXT); 4253 ldr(ch1, Address(str1, cnt1tmp)); 4254 ldr(ch2, Address(str2, cnt2tmp)); 4255 cmp(ch1, ch2); 4256 br(NE, STR2_NEXT); 4257 adds(cnt1tmp, cnt1tmp, 8); 4258 add(cnt2tmp, cnt2tmp, 8); 4259 br(LT, STR1_NEXT); 4260 4261 BIND(LAST_WORD); 4262 ldr(ch1, Address(str1)); 4263 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding 4264 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2 4265 cmp(ch1, ch2); 4266 br(NE, STR2_NEXT); 4267 b(MATCH); 4268 4269 BIND(DOSHORT); 4270 cmp(cnt1, 2); 4271 br(LT, DO1); 4272 br(GT, DO3); 4273 } 4274 4275 if (icnt1 == 4) { 4276 Label CH1_LOOP; 4277 4278 ldr(ch1, str1); 4279 sub(cnt2, cnt2, 4); 4280 mov(result_tmp, cnt2); 4281 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4282 sub(cnt2_neg, zr, cnt2, LSL, 1); 4283 4284 BIND(CH1_LOOP); 4285 ldr(ch2, Address(str2, cnt2_neg)); 4286 cmp(ch1, ch2); 4287 br(EQ, MATCH); 4288 adds(cnt2_neg, cnt2_neg, 2); 4289 br(LE, CH1_LOOP); 4290 b(NOMATCH); 4291 } 4292 4293 if (icnt1 == -1 || icnt1 == 2) { 4294 Label CH1_LOOP; 4295 4296 BIND(DO2); 4297 ldrw(ch1, str1); 4298 sub(cnt2, cnt2, 2); 4299 mov(result_tmp, cnt2); 4300 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4301 sub(cnt2_neg, zr, cnt2, LSL, 1); 4302 4303 BIND(CH1_LOOP); 4304 ldrw(ch2, Address(str2, cnt2_neg)); 4305 cmp(ch1, ch2); 4306 br(EQ, MATCH); 4307 adds(cnt2_neg, cnt2_neg, 2); 4308 br(LE, CH1_LOOP); 4309 b(NOMATCH); 4310 } 4311 4312 if (icnt1 == -1 || icnt1 == 3) { 4313 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; 4314 4315 BIND(DO3); 4316 ldrw(first, str1); 4317 ldrh(ch1, Address(str1, 4)); 4318 4319 sub(cnt2, cnt2, 3); 4320 mov(result_tmp, cnt2); 4321 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4322 sub(cnt2_neg, zr, cnt2, LSL, 1); 4323 4324 BIND(FIRST_LOOP); 4325 ldrw(ch2, Address(str2, cnt2_neg)); 4326 cmpw(first, ch2); 4327 br(EQ, STR1_LOOP); 4328 BIND(STR2_NEXT); 4329 adds(cnt2_neg, cnt2_neg, 2); 4330 br(LE, FIRST_LOOP); 4331 b(NOMATCH); 4332 4333 BIND(STR1_LOOP); 4334 add(cnt2tmp, cnt2_neg, 4); 4335 ldrh(ch2, Address(str2, cnt2tmp)); 4336 cmp(ch1, ch2); 4337 br(NE, STR2_NEXT); 4338 b(MATCH); 4339 } 4340 4341 if (icnt1 == -1 || icnt1 == 1) { 4342 Label CH1_LOOP, HAS_ZERO; 4343 Label DO1_SHORT, DO1_LOOP; 4344 4345 BIND(DO1); 4346 ldrh(ch1, str1); 4347 cmp(cnt2, 4); 4348 br(LT, DO1_SHORT); 4349 4350 orr(ch1, ch1, ch1, LSL, 16); 4351 orr(ch1, ch1, ch1, LSL, 32); 4352 4353 sub(cnt2, cnt2, 4); 4354 mov(result_tmp, cnt2); 4355 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4356 sub(cnt2_neg, zr, cnt2, LSL, 1); 4357 4358 mov(tmp3, 0x0001000100010001); 4359 BIND(CH1_LOOP); 4360 ldr(ch2, Address(str2, cnt2_neg)); 4361 eor(ch2, ch1, ch2); 4362 sub(tmp1, ch2, tmp3); 4363 orr(tmp2, ch2, 0x7fff7fff7fff7fff); 4364 bics(tmp1, tmp1, tmp2); 4365 br(NE, HAS_ZERO); 4366 adds(cnt2_neg, cnt2_neg, 8); 4367 br(LT, CH1_LOOP); 4368 4369 cmp(cnt2_neg, 8); 4370 mov(cnt2_neg, 0); 4371 br(LT, CH1_LOOP); 4372 b(NOMATCH); 4373 4374 BIND(HAS_ZERO); 4375 rev(tmp1, tmp1); 4376 clz(tmp1, tmp1); 4377 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); 4378 b(MATCH); 4379 4380 BIND(DO1_SHORT); 4381 mov(result_tmp, cnt2); 4382 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4383 sub(cnt2_neg, zr, cnt2, LSL, 1); 4384 BIND(DO1_LOOP); 4385 ldrh(ch2, Address(str2, cnt2_neg)); 4386 cmpw(ch1, ch2); 4387 br(EQ, MATCH); 4388 adds(cnt2_neg, cnt2_neg, 2); 4389 br(LT, DO1_LOOP); 4390 } 4391 } 4392 BIND(NOMATCH); 4393 mov(result, -1); 4394 b(DONE); 4395 BIND(MATCH); 4396 add(result, result_tmp, cnt2_neg, ASR, 1); 4397 BIND(DONE); 4398 } 4399 4400 // Compare strings. 4401 void MacroAssembler::string_compare(Register str1, Register str2, 4402 Register cnt1, Register cnt2, Register result, 4403 Register tmp1) { 4404 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, 4405 NEXT_WORD, DIFFERENCE; 4406 4407 BLOCK_COMMENT("string_compare {"); 4408 4409 // Compute the minimum of the string lengths and save the difference. 4410 subsw(tmp1, cnt1, cnt2); 4411 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min 4412 4413 // A very short string 4414 cmpw(cnt2, 4); 4415 br(Assembler::LT, SHORT_STRING); 4416 4417 // Check if the strings start at the same location. 4418 cmp(str1, str2); 4419 br(Assembler::EQ, LENGTH_DIFF); 4420 4421 // Compare longwords 4422 { 4423 subw(cnt2, cnt2, 4); // The last longword is a special case 4424 4425 // Move both string pointers to the last longword of their 4426 // strings, negate the remaining count, and convert it to bytes. 4427 lea(str1, Address(str1, cnt2, Address::uxtw(1))); 4428 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4429 sub(cnt2, zr, cnt2, LSL, 1); 4430 4431 // Loop, loading longwords and comparing them into rscratch2. 4432 bind(NEXT_WORD); 4433 ldr(result, Address(str1, cnt2)); 4434 ldr(cnt1, Address(str2, cnt2)); 4435 adds(cnt2, cnt2, wordSize); 4436 eor(rscratch2, result, cnt1); 4437 cbnz(rscratch2, DIFFERENCE); 4438 br(Assembler::LT, NEXT_WORD); 4439 4440 // Last longword. In the case where length == 4 we compare the 4441 // same longword twice, but that's still faster than another 4442 // conditional branch. 4443 4444 ldr(result, Address(str1)); 4445 ldr(cnt1, Address(str2)); 4446 eor(rscratch2, result, cnt1); 4447 cbz(rscratch2, LENGTH_DIFF); 4448 4449 // Find the first different characters in the longwords and 4450 // compute their difference. 4451 bind(DIFFERENCE); 4452 rev(rscratch2, rscratch2); 4453 clz(rscratch2, rscratch2); 4454 andr(rscratch2, rscratch2, -16); 4455 lsrv(result, result, rscratch2); 4456 uxthw(result, result); 4457 lsrv(cnt1, cnt1, rscratch2); 4458 uxthw(cnt1, cnt1); 4459 subw(result, result, cnt1); 4460 b(DONE); 4461 } 4462 4463 bind(SHORT_STRING); 4464 // Is the minimum length zero? 4465 cbz(cnt2, LENGTH_DIFF); 4466 4467 bind(SHORT_LOOP); 4468 load_unsigned_short(result, Address(post(str1, 2))); 4469 load_unsigned_short(cnt1, Address(post(str2, 2))); 4470 subw(result, result, cnt1); 4471 cbnz(result, DONE); 4472 sub(cnt2, cnt2, 1); 4473 cbnz(cnt2, SHORT_LOOP); 4474 4475 // Strings are equal up to min length. Return the length difference. 4476 bind(LENGTH_DIFF); 4477 mov(result, tmp1); 4478 4479 // That's it 4480 bind(DONE); 4481 4482 BLOCK_COMMENT("} string_compare"); 4483 } 4484 4485 4486 void MacroAssembler::string_equals(Register str1, Register str2, 4487 Register cnt, Register result, 4488 Register tmp1) { 4489 Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING, 4490 NEXT_WORD; 4491 4492 const Register tmp2 = rscratch1; 4493 assert_different_registers(str1, str2, cnt, result, tmp1, tmp2, rscratch2); 4494 4495 BLOCK_COMMENT("string_equals {"); 4496 4497 // Start by assuming that the strings are not equal. 4498 mov(result, zr); 4499 4500 // A very short string 4501 cmpw(cnt, 4); 4502 br(Assembler::LT, SHORT_STRING); 4503 4504 // Check if the strings start at the same location. 4505 cmp(str1, str2); 4506 br(Assembler::EQ, SAME_CHARS); 4507 4508 // Compare longwords 4509 { 4510 subw(cnt, cnt, 4); // The last longword is a special case 4511 4512 // Move both string pointers to the last longword of their 4513 // strings, negate the remaining count, and convert it to bytes. 4514 lea(str1, Address(str1, cnt, Address::uxtw(1))); 4515 lea(str2, Address(str2, cnt, Address::uxtw(1))); 4516 sub(cnt, zr, cnt, LSL, 1); 4517 4518 // Loop, loading longwords and comparing them into rscratch2. 4519 bind(NEXT_WORD); 4520 ldr(tmp1, Address(str1, cnt)); 4521 ldr(tmp2, Address(str2, cnt)); 4522 adds(cnt, cnt, wordSize); 4523 eor(rscratch2, tmp1, tmp2); 4524 cbnz(rscratch2, DONE); 4525 br(Assembler::LT, NEXT_WORD); 4526 4527 // Last longword. In the case where length == 4 we compare the 4528 // same longword twice, but that's still faster than another 4529 // conditional branch. 4530 4531 ldr(tmp1, Address(str1)); 4532 ldr(tmp2, Address(str2)); 4533 eor(rscratch2, tmp1, tmp2); 4534 cbz(rscratch2, SAME_CHARS); 4535 b(DONE); 4536 } 4537 4538 bind(SHORT_STRING); 4539 // Is the length zero? 4540 cbz(cnt, SAME_CHARS); 4541 4542 bind(SHORT_LOOP); 4543 load_unsigned_short(tmp1, Address(post(str1, 2))); 4544 load_unsigned_short(tmp2, Address(post(str2, 2))); 4545 subw(tmp1, tmp1, tmp2); 4546 cbnz(tmp1, DONE); 4547 sub(cnt, cnt, 1); 4548 cbnz(cnt, SHORT_LOOP); 4549 4550 // Strings are equal. 4551 bind(SAME_CHARS); 4552 mov(result, true); 4553 4554 // That's it 4555 bind(DONE); 4556 4557 BLOCK_COMMENT("} string_equals"); 4558 } 4559 4560 // Compare char[] arrays aligned to 4 bytes 4561 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, 4562 Register result, Register tmp1) 4563 { 4564 Register cnt1 = rscratch1; 4565 Register cnt2 = rscratch2; 4566 Register tmp2 = rscratch2; 4567 4568 Label SAME, DIFFER, NEXT, TAIL03, TAIL01; 4569 4570 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4571 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 4572 4573 BLOCK_COMMENT("char_arrays_equals {"); 4574 4575 // different until proven equal 4576 mov(result, false); 4577 4578 // same array? 4579 cmp(ary1, ary2); 4580 br(Assembler::EQ, SAME); 4581 4582 // ne if either null 4583 cbz(ary1, DIFFER); 4584 cbz(ary2, DIFFER); 4585 4586 // lengths ne? 4587 ldrw(cnt1, Address(ary1, length_offset)); 4588 ldrw(cnt2, Address(ary2, length_offset)); 4589 cmp(cnt1, cnt2); 4590 br(Assembler::NE, DIFFER); 4591 4592 lea(ary1, Address(ary1, base_offset)); 4593 lea(ary2, Address(ary2, base_offset)); 4594 4595 subs(cnt1, cnt1, 4); 4596 br(LT, TAIL03); 4597 4598 BIND(NEXT); 4599 ldr(tmp1, Address(post(ary1, 8))); 4600 ldr(tmp2, Address(post(ary2, 8))); 4601 subs(cnt1, cnt1, 4); 4602 eor(tmp1, tmp1, tmp2); 4603 cbnz(tmp1, DIFFER); 4604 br(GE, NEXT); 4605 4606 BIND(TAIL03); // 0-3 chars left, cnt1 = #chars left - 4 4607 tst(cnt1, 0b10); 4608 br(EQ, TAIL01); 4609 ldrw(tmp1, Address(post(ary1, 4))); 4610 ldrw(tmp2, Address(post(ary2, 4))); 4611 cmp(tmp1, tmp2); 4612 br(NE, DIFFER); 4613 BIND(TAIL01); // 0-1 chars left 4614 tst(cnt1, 0b01); 4615 br(EQ, SAME); 4616 ldrh(tmp1, ary1); 4617 ldrh(tmp2, ary2); 4618 cmp(tmp1, tmp2); 4619 br(NE, DIFFER); 4620 4621 BIND(SAME); 4622 mov(result, true); 4623 BIND(DIFFER); // result already set 4624 4625 BLOCK_COMMENT("} char_arrays_equals"); 4626 } 4627 4628 // encode char[] to byte[] in ISO_8859_1 4629 void MacroAssembler::encode_iso_array(Register src, Register dst, 4630 Register len, Register result, 4631 FloatRegister Vtmp1, FloatRegister Vtmp2, 4632 FloatRegister Vtmp3, FloatRegister Vtmp4) 4633 { 4634 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; 4635 Register tmp1 = rscratch1; 4636 4637 mov(result, len); // Save initial len 4638 4639 #ifndef BUILTIN_SIM 4640 subs(len, len, 32); 4641 br(LT, LOOP_8); 4642 4643 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions 4644 // to convert chars to bytes. These set the 'QC' bit in the FPSR if 4645 // any char could not fit in a byte, so clear the FPSR so we can test it. 4646 clear_fpsr(); 4647 4648 BIND(NEXT_32); 4649 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4650 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half 4651 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half 4652 uqxtn(Vtmp2, T8B, Vtmp3, T8H); 4653 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 4654 get_fpsr(tmp1); 4655 cbnzw(tmp1, LOOP_8); 4656 st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); 4657 subs(len, len, 32); 4658 add(src, src, 64); 4659 br(GE, NEXT_32); 4660 4661 BIND(LOOP_8); 4662 adds(len, len, 32-8); 4663 br(LT, LOOP_1); 4664 clear_fpsr(); // QC may be set from loop above, clear again 4665 BIND(NEXT_8); 4666 ld1(Vtmp1, T8H, src); 4667 uqxtn(Vtmp1, T8B, Vtmp1, T8H); 4668 get_fpsr(tmp1); 4669 cbnzw(tmp1, LOOP_1); 4670 st1(Vtmp1, T8B, post(dst, 8)); 4671 subs(len, len, 8); 4672 add(src, src, 16); 4673 br(GE, NEXT_8); 4674 4675 BIND(LOOP_1); 4676 adds(len, len, 8); 4677 br(LE, DONE); 4678 #else 4679 cbz(len, DONE); 4680 #endif 4681 BIND(NEXT_1); 4682 ldrh(tmp1, Address(post(src, 2))); 4683 tst(tmp1, 0xff00); 4684 br(NE, DONE); 4685 strb(tmp1, Address(post(dst, 1))); 4686 subs(len, len, 1); 4687 br(GT, NEXT_1); 4688 4689 BIND(DONE); 4690 sub(result, result, len); // Return index where we stopped 4691 } 4692 4693 // get_thread() can be called anywhere inside generated code so we 4694 // need to save whatever non-callee save context might get clobbered 4695 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 4696 // the call setup code. 4697 // 4698 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 4699 // 4700 void MacroAssembler::get_thread(Register dst) { 4701 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 4702 push(saved_regs, sp); 4703 4704 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 4705 blrt(lr, 1, 0, 1); 4706 if (dst != c_rarg0) { 4707 mov(dst, c_rarg0); 4708 } 4709 4710 pop(saved_regs, sp); 4711 }