1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.hpp" 30 31 // MacroAssembler extends Assembler by frequently used macros. 32 // 33 // Instructions for which a 'better' code sequence exists depending 34 // on arguments should also go in here. 35 36 class MacroAssembler: public Assembler { 37 friend class LIR_Assembler; 38 39 public: 40 using Assembler::mov; 41 using Assembler::movi; 42 43 protected: 44 45 // Support for VM calls 46 // 47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 48 // may customize this version by overriding it for its purposes (e.g., to save/restore 49 // additional registers when doing a VM call). 50 #ifdef CC_INTERP 51 // c++ interpreter never wants to use interp_masm version of call_VM 52 #define VIRTUAL 53 #else 54 #define VIRTUAL virtual 55 #endif 56 57 VIRTUAL void call_VM_leaf_base( 58 address entry_point, // the entry point 59 int number_of_arguments, // the number of arguments to pop after the call 60 Label *retaddr = NULL 61 ); 62 63 VIRTUAL void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label &retaddr) { 67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 68 } 69 70 // This is the base routine called by the different versions of call_VM. The interpreter 71 // may customize this version by overriding it for its purposes (e.g., to save/restore 72 // additional registers when doing a VM call). 73 // 74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 75 // returns the register which contains the thread upon return. If a thread register has been 76 // specified, the return value will correspond to that register. If no last_java_sp is specified 77 // (noreg) than rsp will be used instead. 78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 80 Register java_thread, // the thread if computed before ; use noreg otherwise 81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 82 address entry_point, // the entry point 83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 84 bool check_exceptions // whether to check for pending exceptions after return 85 ); 86 87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 88 // The implementation is only non-empty for the InterpreterMacroAssembler, 89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 90 virtual void check_and_handle_popframe(Register java_thread); 91 virtual void check_and_handle_earlyret(Register java_thread); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 // Maximum size of class area in Metaspace when compressed 96 uint64_t use_XOR_for_compressed_class_base; 97 98 public: 99 MacroAssembler(CodeBuffer* code) : Assembler(code) { 100 use_XOR_for_compressed_class_base 101 = (operand_valid_for_logical_immediate(false /*is32*/, 102 (uint64_t)Universe::narrow_klass_base()) 103 && ((uint64_t)Universe::narrow_klass_base() 104 > (1u << log2_intptr(CompressedClassSpaceSize)))); 105 } 106 107 // Biased locking support 108 // lock_reg and obj_reg must be loaded up with the appropriate values. 109 // swap_reg is killed. 110 // tmp_reg must be supplied and must not be rscratch1 or rscratch2 111 // Optional slow case is for implementations (interpreter and C1) which branch to 112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 113 // Returns offset of first potentially-faulting instruction for null 114 // check info (currently consumed only by C1). If 115 // swap_reg_contains_mark is true then returns -1 as it is assumed 116 // the calling code has already passed any potential faults. 117 int biased_locking_enter(Register lock_reg, Register obj_reg, 118 Register swap_reg, Register tmp_reg, 119 bool swap_reg_contains_mark, 120 Label& done, Label* slow_case = NULL, 121 BiasedLockingCounters* counters = NULL); 122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 123 124 125 // Helper functions for statistics gathering. 126 // Unconditional atomic increment. 127 void atomic_incw(Register counter_addr, Register tmp, Register tmp2); 128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) { 129 lea(tmp1, counter_addr); 130 atomic_incw(tmp1, tmp2, tmp3); 131 } 132 // Load Effective Address 133 void lea(Register r, const Address &a) { 134 InstructionMark im(this); 135 code_section()->relocate(inst_mark(), a.rspec()); 136 a.lea(this, r); 137 } 138 139 void addmw(Address a, Register incr, Register scratch) { 140 ldrw(scratch, a); 141 addw(scratch, scratch, incr); 142 strw(scratch, a); 143 } 144 145 // Add constant to memory word 146 void addmw(Address a, int imm, Register scratch) { 147 ldrw(scratch, a); 148 if (imm > 0) 149 addw(scratch, scratch, (unsigned)imm); 150 else 151 subw(scratch, scratch, (unsigned)-imm); 152 strw(scratch, a); 153 } 154 155 void bind(Label& L) { 156 Assembler::bind(L); 157 code()->clear_last_membar(); 158 } 159 160 void membar(Membar_mask_bits order_constraint); 161 162 // Frame creation and destruction shared between JITs. 163 void build_frame(int framesize); 164 void remove_frame(int framesize); 165 166 virtual void _call_Unimplemented(address call_site) { 167 mov(rscratch2, call_site); 168 haltsim(); 169 } 170 171 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 172 173 virtual void notify(int type); 174 175 // aliases defined in AARCH64 spec 176 177 template<class T> 178 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 179 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); } 180 181 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } 182 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } 183 184 void cset(Register Rd, Assembler::Condition cond) { 185 csinc(Rd, zr, zr, ~cond); 186 } 187 void csetw(Register Rd, Assembler::Condition cond) { 188 csincw(Rd, zr, zr, ~cond); 189 } 190 191 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 192 csneg(Rd, Rn, Rn, ~cond); 193 } 194 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 195 csnegw(Rd, Rn, Rn, ~cond); 196 } 197 198 inline void movw(Register Rd, Register Rn) { 199 if (Rd == sp || Rn == sp) { 200 addw(Rd, Rn, 0U); 201 } else { 202 orrw(Rd, zr, Rn); 203 } 204 } 205 inline void mov(Register Rd, Register Rn) { 206 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 207 if (Rd == Rn) { 208 } else if (Rd == sp || Rn == sp) { 209 add(Rd, Rn, 0U); 210 } else { 211 orr(Rd, zr, Rn); 212 } 213 } 214 215 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 216 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 217 218 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); } 219 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); } 220 221 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); } 222 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); } 223 224 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 225 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 226 } 227 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 228 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 229 } 230 231 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 232 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 233 } 234 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 235 bfm(Rd, Rn, lsb , (lsb + width - 1)); 236 } 237 238 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 239 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 240 } 241 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 242 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 243 } 244 245 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 246 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 247 } 248 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 249 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 250 } 251 252 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 253 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 254 } 255 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 256 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 257 } 258 259 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 260 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 261 } 262 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 263 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 264 } 265 266 inline void asrw(Register Rd, Register Rn, unsigned imm) { 267 sbfmw(Rd, Rn, imm, 31); 268 } 269 270 inline void asr(Register Rd, Register Rn, unsigned imm) { 271 sbfm(Rd, Rn, imm, 63); 272 } 273 274 inline void lslw(Register Rd, Register Rn, unsigned imm) { 275 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 276 } 277 278 inline void lsl(Register Rd, Register Rn, unsigned imm) { 279 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 280 } 281 282 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 283 ubfmw(Rd, Rn, imm, 31); 284 } 285 286 inline void lsr(Register Rd, Register Rn, unsigned imm) { 287 ubfm(Rd, Rn, imm, 63); 288 } 289 290 inline void rorw(Register Rd, Register Rn, unsigned imm) { 291 extrw(Rd, Rn, Rn, imm); 292 } 293 294 inline void ror(Register Rd, Register Rn, unsigned imm) { 295 extr(Rd, Rn, Rn, imm); 296 } 297 298 inline void sxtbw(Register Rd, Register Rn) { 299 sbfmw(Rd, Rn, 0, 7); 300 } 301 inline void sxthw(Register Rd, Register Rn) { 302 sbfmw(Rd, Rn, 0, 15); 303 } 304 inline void sxtb(Register Rd, Register Rn) { 305 sbfm(Rd, Rn, 0, 7); 306 } 307 inline void sxth(Register Rd, Register Rn) { 308 sbfm(Rd, Rn, 0, 15); 309 } 310 inline void sxtw(Register Rd, Register Rn) { 311 sbfm(Rd, Rn, 0, 31); 312 } 313 314 inline void uxtbw(Register Rd, Register Rn) { 315 ubfmw(Rd, Rn, 0, 7); 316 } 317 inline void uxthw(Register Rd, Register Rn) { 318 ubfmw(Rd, Rn, 0, 15); 319 } 320 inline void uxtb(Register Rd, Register Rn) { 321 ubfm(Rd, Rn, 0, 7); 322 } 323 inline void uxth(Register Rd, Register Rn) { 324 ubfm(Rd, Rn, 0, 15); 325 } 326 inline void uxtw(Register Rd, Register Rn) { 327 ubfm(Rd, Rn, 0, 31); 328 } 329 330 inline void cmnw(Register Rn, Register Rm) { 331 addsw(zr, Rn, Rm); 332 } 333 inline void cmn(Register Rn, Register Rm) { 334 adds(zr, Rn, Rm); 335 } 336 337 inline void cmpw(Register Rn, Register Rm) { 338 subsw(zr, Rn, Rm); 339 } 340 inline void cmp(Register Rn, Register Rm) { 341 subs(zr, Rn, Rm); 342 } 343 344 inline void negw(Register Rd, Register Rn) { 345 subw(Rd, zr, Rn); 346 } 347 348 inline void neg(Register Rd, Register Rn) { 349 sub(Rd, zr, Rn); 350 } 351 352 inline void negsw(Register Rd, Register Rn) { 353 subsw(Rd, zr, Rn); 354 } 355 356 inline void negs(Register Rd, Register Rn) { 357 subs(Rd, zr, Rn); 358 } 359 360 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 361 addsw(zr, Rn, Rm, kind, shift); 362 } 363 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 364 adds(zr, Rn, Rm, kind, shift); 365 } 366 367 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 368 subsw(zr, Rn, Rm, kind, shift); 369 } 370 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 371 subs(zr, Rn, Rm, kind, shift); 372 } 373 374 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 375 subw(Rd, zr, Rn, kind, shift); 376 } 377 378 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 379 sub(Rd, zr, Rn, kind, shift); 380 } 381 382 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 383 subsw(Rd, zr, Rn, kind, shift); 384 } 385 386 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 387 subs(Rd, zr, Rn, kind, shift); 388 } 389 390 inline void mnegw(Register Rd, Register Rn, Register Rm) { 391 msubw(Rd, Rn, Rm, zr); 392 } 393 inline void mneg(Register Rd, Register Rn, Register Rm) { 394 msub(Rd, Rn, Rm, zr); 395 } 396 397 inline void mulw(Register Rd, Register Rn, Register Rm) { 398 maddw(Rd, Rn, Rm, zr); 399 } 400 inline void mul(Register Rd, Register Rn, Register Rm) { 401 madd(Rd, Rn, Rm, zr); 402 } 403 404 inline void smnegl(Register Rd, Register Rn, Register Rm) { 405 smsubl(Rd, Rn, Rm, zr); 406 } 407 inline void smull(Register Rd, Register Rn, Register Rm) { 408 smaddl(Rd, Rn, Rm, zr); 409 } 410 411 inline void umnegl(Register Rd, Register Rn, Register Rm) { 412 umsubl(Rd, Rn, Rm, zr); 413 } 414 inline void umull(Register Rd, Register Rn, Register Rm) { 415 umaddl(Rd, Rn, Rm, zr); 416 } 417 418 #define WRAP(INSN) \ 419 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 420 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \ 421 nop(); \ 422 Assembler::INSN(Rd, Rn, Rm, Ra); \ 423 } 424 425 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 426 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 427 #undef WRAP 428 429 430 // macro assembly operations needed for aarch64 431 432 // first two private routines for loading 32 bit or 64 bit constants 433 private: 434 435 void mov_immediate64(Register dst, u_int64_t imm64); 436 void mov_immediate32(Register dst, u_int32_t imm32); 437 438 int push(unsigned int bitset, Register stack); 439 int pop(unsigned int bitset, Register stack); 440 441 void mov(Register dst, Address a); 442 443 public: 444 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 445 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 446 447 // now mov instructions for loading absolute addresses and 32 or 448 // 64 bit integers 449 450 inline void mov(Register dst, address addr) 451 { 452 mov_immediate64(dst, (u_int64_t)addr); 453 } 454 455 inline void mov(Register dst, u_int64_t imm64) 456 { 457 mov_immediate64(dst, imm64); 458 } 459 460 inline void movw(Register dst, u_int32_t imm32) 461 { 462 mov_immediate32(dst, imm32); 463 } 464 465 inline void mov(Register dst, long l) 466 { 467 mov(dst, (u_int64_t)l); 468 } 469 470 inline void mov(Register dst, int i) 471 { 472 mov(dst, (long)i); 473 } 474 475 void mov(Register dst, RegisterOrConstant src) { 476 if (src.is_register()) 477 mov(dst, src.as_register()); 478 else 479 mov(dst, src.as_constant()); 480 } 481 482 void movptr(Register r, uintptr_t imm64); 483 484 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32); 485 486 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 487 orr(Vd, T, Vn, Vn); 488 } 489 490 public: 491 492 // Generalized Test Bit And Branch, including a "far" variety which 493 // spans more than 32KiB. 494 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) { 495 assert(cond == EQ || cond == NE, "must be"); 496 497 if (far) 498 cond = ~cond; 499 500 void (Assembler::* branch)(Register Rt, int bitpos, Label &L); 501 if (cond == Assembler::EQ) 502 branch = &Assembler::tbz; 503 else 504 branch = &Assembler::tbnz; 505 506 if (far) { 507 Label L; 508 (this->*branch)(Rt, bitpos, L); 509 b(dest); 510 bind(L); 511 } else { 512 (this->*branch)(Rt, bitpos, dest); 513 } 514 } 515 516 // macro instructions for accessing and updating floating point 517 // status register 518 // 519 // FPSR : op1 == 011 520 // CRn == 0100 521 // CRm == 0100 522 // op2 == 001 523 524 inline void get_fpsr(Register reg) 525 { 526 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 527 } 528 529 inline void set_fpsr(Register reg) 530 { 531 msr(0b011, 0b0100, 0b0100, 0b001, reg); 532 } 533 534 inline void clear_fpsr() 535 { 536 msr(0b011, 0b0100, 0b0100, 0b001, zr); 537 } 538 539 // idiv variant which deals with MINLONG as dividend and -1 as divisor 540 int corrected_idivl(Register result, Register ra, Register rb, 541 bool want_remainder, Register tmp = rscratch1); 542 int corrected_idivq(Register result, Register ra, Register rb, 543 bool want_remainder, Register tmp = rscratch1); 544 545 // Support for NULL-checks 546 // 547 // Generates code that causes a NULL OS exception if the content of reg is NULL. 548 // If the accessed location is M[reg + offset] and the offset is known, provide the 549 // offset. No explicit code generation is needed if the offset is within a certain 550 // range (0 <= offset <= page_size). 551 552 virtual void null_check(Register reg, int offset = -1); 553 static bool needs_explicit_null_check(intptr_t offset); 554 555 static address target_addr_for_insn(address insn_addr, unsigned insn); 556 static address target_addr_for_insn(address insn_addr) { 557 unsigned insn = *(unsigned*)insn_addr; 558 return target_addr_for_insn(insn_addr, insn); 559 } 560 561 // Required platform-specific helpers for Label::patch_instructions. 562 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 563 static int pd_patch_instruction_size(address branch, address target); 564 static void pd_patch_instruction(address branch, address target) { 565 pd_patch_instruction_size(branch, target); 566 } 567 static address pd_call_destination(address branch) { 568 return target_addr_for_insn(branch); 569 } 570 #ifndef PRODUCT 571 static void pd_print_patched_instruction(address branch); 572 #endif 573 574 static int patch_oop(address insn_addr, address o); 575 576 address emit_trampoline_stub(int insts_call_instruction_offset, address target); 577 578 // The following 4 methods return the offset of the appropriate move instruction 579 580 // Support for fast byte/short loading with zero extension (depending on particular CPU) 581 int load_unsigned_byte(Register dst, Address src); 582 int load_unsigned_short(Register dst, Address src); 583 584 // Support for fast byte/short loading with sign extension (depending on particular CPU) 585 int load_signed_byte(Register dst, Address src); 586 int load_signed_short(Register dst, Address src); 587 588 int load_signed_byte32(Register dst, Address src); 589 int load_signed_short32(Register dst, Address src); 590 591 // Support for sign-extension (hi:lo = extend_sign(lo)) 592 void extend_sign(Register hi, Register lo); 593 594 // Load and store values by size and signed-ness 595 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 596 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 597 598 // Support for inc/dec with optimal instruction selection depending on value 599 600 // x86_64 aliases an unqualified register/address increment and 601 // decrement to call incrementq and decrementq but also supports 602 // explicitly sized calls to incrementq/decrementq or 603 // incrementl/decrementl 604 605 // for aarch64 the proper convention would be to use 606 // increment/decrement for 64 bit operatons and 607 // incrementw/decrementw for 32 bit operations. so when porting 608 // x86_64 code we can leave calls to increment/decrement as is, 609 // replace incrementq/decrementq with increment/decrement and 610 // replace incrementl/decrementl with incrementw/decrementw. 611 612 // n.b. increment/decrement calls with an Address destination will 613 // need to use a scratch register to load the value to be 614 // incremented. increment/decrement calls which add or subtract a 615 // constant value greater than 2^12 will need to use a 2nd scratch 616 // register to hold the constant. so, a register increment/decrement 617 // may trash rscratch2 and an address increment/decrement trash 618 // rscratch and rscratch2 619 620 void decrementw(Address dst, int value = 1); 621 void decrementw(Register reg, int value = 1); 622 623 void decrement(Register reg, int value = 1); 624 void decrement(Address dst, int value = 1); 625 626 void incrementw(Address dst, int value = 1); 627 void incrementw(Register reg, int value = 1); 628 629 void increment(Register reg, int value = 1); 630 void increment(Address dst, int value = 1); 631 632 633 // Alignment 634 void align(int modulus); 635 636 // Stack frame creation/removal 637 void enter() 638 { 639 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 640 mov(rfp, sp); 641 } 642 void leave() 643 { 644 mov(sp, rfp); 645 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 646 } 647 648 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 649 // The pointer will be loaded into the thread register. 650 void get_thread(Register thread); 651 652 653 // Support for VM calls 654 // 655 // It is imperative that all calls into the VM are handled via the call_VM macros. 656 // They make sure that the stack linkage is setup correctly. call_VM's correspond 657 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 658 659 660 void call_VM(Register oop_result, 661 address entry_point, 662 bool check_exceptions = true); 663 void call_VM(Register oop_result, 664 address entry_point, 665 Register arg_1, 666 bool check_exceptions = true); 667 void call_VM(Register oop_result, 668 address entry_point, 669 Register arg_1, Register arg_2, 670 bool check_exceptions = true); 671 void call_VM(Register oop_result, 672 address entry_point, 673 Register arg_1, Register arg_2, Register arg_3, 674 bool check_exceptions = true); 675 676 // Overloadings with last_Java_sp 677 void call_VM(Register oop_result, 678 Register last_java_sp, 679 address entry_point, 680 int number_of_arguments = 0, 681 bool check_exceptions = true); 682 void call_VM(Register oop_result, 683 Register last_java_sp, 684 address entry_point, 685 Register arg_1, bool 686 check_exceptions = true); 687 void call_VM(Register oop_result, 688 Register last_java_sp, 689 address entry_point, 690 Register arg_1, Register arg_2, 691 bool check_exceptions = true); 692 void call_VM(Register oop_result, 693 Register last_java_sp, 694 address entry_point, 695 Register arg_1, Register arg_2, Register arg_3, 696 bool check_exceptions = true); 697 698 void get_vm_result (Register oop_result, Register thread); 699 void get_vm_result_2(Register metadata_result, Register thread); 700 701 // These always tightly bind to MacroAssembler::call_VM_base 702 // bypassing the virtual implementation 703 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 704 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 705 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 706 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 707 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 708 709 void call_VM_leaf(address entry_point, 710 int number_of_arguments = 0); 711 void call_VM_leaf(address entry_point, 712 Register arg_1); 713 void call_VM_leaf(address entry_point, 714 Register arg_1, Register arg_2); 715 void call_VM_leaf(address entry_point, 716 Register arg_1, Register arg_2, Register arg_3); 717 718 // These always tightly bind to MacroAssembler::call_VM_leaf_base 719 // bypassing the virtual implementation 720 void super_call_VM_leaf(address entry_point); 721 void super_call_VM_leaf(address entry_point, Register arg_1); 722 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 723 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 724 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 725 726 // last Java Frame (fills frame anchor) 727 void set_last_Java_frame(Register last_java_sp, 728 Register last_java_fp, 729 address last_java_pc, 730 Register scratch); 731 732 void set_last_Java_frame(Register last_java_sp, 733 Register last_java_fp, 734 Label &last_java_pc, 735 Register scratch); 736 737 void set_last_Java_frame(Register last_java_sp, 738 Register last_java_fp, 739 Register last_java_pc, 740 Register scratch); 741 742 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc); 743 744 // thread in the default location (r15_thread on 64bit) 745 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 746 747 // Stores 748 void store_check(Register obj); // store check for obj - register is destroyed afterwards 749 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 750 751 #if INCLUDE_ALL_GCS 752 753 void g1_write_barrier_pre(Register obj, 754 Register pre_val, 755 Register thread, 756 Register tmp, 757 bool tosca_live, 758 bool expand_call); 759 760 void g1_write_barrier_post(Register store_addr, 761 Register new_val, 762 Register thread, 763 Register tmp, 764 Register tmp2); 765 766 #endif // INCLUDE_ALL_GCS 767 768 // oop manipulations 769 void load_klass(Register dst, Register src); 770 void store_klass(Register dst, Register src); 771 void cmp_klass(Register oop, Register trial_klass, Register tmp); 772 773 void load_heap_oop(Register dst, Address src); 774 775 void load_heap_oop_not_null(Register dst, Address src); 776 void store_heap_oop(Address dst, Register src); 777 778 // currently unimplemented 779 // Used for storing NULL. All other oop constants should be 780 // stored using routines that take a jobject. 781 void store_heap_oop_null(Address dst); 782 783 void load_prototype_header(Register dst, Register src); 784 785 void store_klass_gap(Register dst, Register src); 786 787 // This dummy is to prevent a call to store_heap_oop from 788 // converting a zero (like NULL) into a Register by giving 789 // the compiler two choices it can't resolve 790 791 void store_heap_oop(Address dst, void* dummy); 792 793 void encode_heap_oop(Register d, Register s); 794 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 795 void decode_heap_oop(Register d, Register s); 796 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 797 void encode_heap_oop_not_null(Register r); 798 void decode_heap_oop_not_null(Register r); 799 void encode_heap_oop_not_null(Register dst, Register src); 800 void decode_heap_oop_not_null(Register dst, Register src); 801 802 void set_narrow_oop(Register dst, jobject obj); 803 804 void encode_klass_not_null(Register r); 805 void decode_klass_not_null(Register r); 806 void encode_klass_not_null(Register dst, Register src); 807 void decode_klass_not_null(Register dst, Register src); 808 809 void set_narrow_klass(Register dst, Klass* k); 810 811 // if heap base register is used - reinit it with the correct value 812 void reinit_heapbase(); 813 814 DEBUG_ONLY(void verify_heapbase(const char* msg);) 815 816 void push_CPU_state(bool save_vectors = false); 817 void pop_CPU_state(bool restore_vectors = false) ; 818 819 // Round up to a power of two 820 void round_to(Register reg, int modulus); 821 822 // allocation 823 void eden_allocate( 824 Register obj, // result: pointer to object after successful allocation 825 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 826 int con_size_in_bytes, // object size in bytes if known at compile time 827 Register t1, // temp register 828 Label& slow_case // continuation point if fast allocation fails 829 ); 830 void tlab_allocate( 831 Register obj, // result: pointer to object after successful allocation 832 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 833 int con_size_in_bytes, // object size in bytes if known at compile time 834 Register t1, // temp register 835 Register t2, // temp register 836 Label& slow_case // continuation point if fast allocation fails 837 ); 838 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 839 void verify_tlab(); 840 841 void incr_allocated_bytes(Register thread, 842 Register var_size_in_bytes, int con_size_in_bytes, 843 Register t1 = noreg); 844 845 // interface method calling 846 void lookup_interface_method(Register recv_klass, 847 Register intf_klass, 848 RegisterOrConstant itable_index, 849 Register method_result, 850 Register scan_temp, 851 Label& no_such_interface); 852 853 // virtual method calling 854 // n.b. x86 allows RegisterOrConstant for vtable_index 855 void lookup_virtual_method(Register recv_klass, 856 RegisterOrConstant vtable_index, 857 Register method_result); 858 859 // Test sub_klass against super_klass, with fast and slow paths. 860 861 // The fast path produces a tri-state answer: yes / no / maybe-slow. 862 // One of the three labels can be NULL, meaning take the fall-through. 863 // If super_check_offset is -1, the value is loaded up from super_klass. 864 // No registers are killed, except temp_reg. 865 void check_klass_subtype_fast_path(Register sub_klass, 866 Register super_klass, 867 Register temp_reg, 868 Label* L_success, 869 Label* L_failure, 870 Label* L_slow_path, 871 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 872 873 // The rest of the type check; must be wired to a corresponding fast path. 874 // It does not repeat the fast path logic, so don't use it standalone. 875 // The temp_reg and temp2_reg can be noreg, if no temps are available. 876 // Updates the sub's secondary super cache as necessary. 877 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 878 void check_klass_subtype_slow_path(Register sub_klass, 879 Register super_klass, 880 Register temp_reg, 881 Register temp2_reg, 882 Label* L_success, 883 Label* L_failure, 884 bool set_cond_codes = false); 885 886 // Simplified, combined version, good for typical uses. 887 // Falls through on failure. 888 void check_klass_subtype(Register sub_klass, 889 Register super_klass, 890 Register temp_reg, 891 Label& L_success); 892 893 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 894 895 896 // Debugging 897 898 // only if +VerifyOops 899 void verify_oop(Register reg, const char* s = "broken oop"); 900 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 901 902 // TODO: verify method and klass metadata (compare against vptr?) 903 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 904 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 905 906 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 907 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 908 909 // only if +VerifyFPU 910 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 911 912 // prints msg, dumps registers and stops execution 913 void stop(const char* msg); 914 915 // prints msg and continues 916 void warn(const char* msg); 917 918 static void debug64(char* msg, int64_t pc, int64_t regs[]); 919 920 void untested() { stop("untested"); } 921 922 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 923 924 void should_not_reach_here() { stop("should not reach here"); } 925 926 // Stack overflow checking 927 void bang_stack_with_offset(int offset) { 928 // stack grows down, caller passes positive offset 929 assert(offset > 0, "must bang with negative offset"); 930 mov(rscratch2, -offset); 931 str(zr, Address(sp, rscratch2)); 932 } 933 934 // Writes to stack successive pages until offset reached to check for 935 // stack overflow + shadow pages. Also, clobbers tmp 936 void bang_stack_size(Register size, Register tmp); 937 938 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 939 Register tmp, 940 int offset); 941 942 // Support for serializing memory accesses between threads 943 void serialize_memory(Register thread, Register tmp); 944 945 // Arithmetics 946 947 void addptr(const Address &dst, int32_t src); 948 void cmpptr(Register src1, Address src2); 949 950 // Various forms of CAS 951 952 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 953 Label &suceed, Label *fail); 954 955 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 956 Label &suceed, Label *fail); 957 958 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 959 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 960 961 void atomic_xchg(Register prev, Register newv, Register addr); 962 void atomic_xchgw(Register prev, Register newv, Register addr); 963 964 void orptr(Address adr, RegisterOrConstant src) { 965 ldr(rscratch2, adr); 966 if (src.is_register()) 967 orr(rscratch2, rscratch2, src.as_register()); 968 else 969 orr(rscratch2, rscratch2, src.as_constant()); 970 str(rscratch2, adr); 971 } 972 973 // A generic CAS; success or failure is in the EQ flag. 974 template <typename T1, typename T2> 975 void cmpxchg(Register addr, Register expected, Register new_val, 976 T1 load_insn, 977 void (MacroAssembler::*cmp_insn)(Register, Register), 978 T2 store_insn, 979 Register tmp = rscratch1) { 980 Label retry_load, done; 981 bind(retry_load); 982 (this->*load_insn)(tmp, addr); 983 (this->*cmp_insn)(tmp, expected); 984 br(Assembler::NE, done); 985 (this->*store_insn)(tmp, new_val, addr); 986 cbnzw(tmp, retry_load); 987 bind(done); 988 } 989 990 // Calls 991 992 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL); 993 994 static bool far_branches() { 995 return ReservedCodeCacheSize > branch_range; 996 } 997 998 // Jumps that can reach anywhere in the code cache. 999 // Trashes tmp. 1000 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 1001 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 1002 1003 static int far_branch_size() { 1004 if (far_branches()) { 1005 return 3 * 4; // adrp, add, br 1006 } else { 1007 return 4; 1008 } 1009 } 1010 1011 // Emit the CompiledIC call idiom 1012 address ic_call(address entry, jint method_index = 0); 1013 1014 public: 1015 1016 // Data 1017 1018 void mov_metadata(Register dst, Metadata* obj); 1019 Address allocate_metadata_address(Metadata* obj); 1020 Address constant_oop_address(jobject obj); 1021 1022 void movoop(Register dst, jobject obj, bool immediate = false); 1023 1024 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1025 void kernel_crc32(Register crc, Register buf, Register len, 1026 Register table0, Register table1, Register table2, Register table3, 1027 Register tmp, Register tmp2, Register tmp3); 1028 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic. 1029 void kernel_crc32c(Register crc, Register buf, Register len, 1030 Register table0, Register table1, Register table2, Register table3, 1031 Register tmp, Register tmp2, Register tmp3); 1032 1033 #undef VIRTUAL 1034 1035 // Stack push and pop individual 64 bit registers 1036 void push(Register src); 1037 void pop(Register dst); 1038 1039 // push all registers onto the stack 1040 void pusha(); 1041 void popa(); 1042 1043 void repne_scan(Register addr, Register value, Register count, 1044 Register scratch); 1045 void repne_scanw(Register addr, Register value, Register count, 1046 Register scratch); 1047 1048 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1049 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1050 1051 // If a constant does not fit in an immediate field, generate some 1052 // number of MOV instructions and then perform the operation 1053 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1054 add_sub_imm_insn insn1, 1055 add_sub_reg_insn insn2); 1056 // Seperate vsn which sets the flags 1057 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1058 add_sub_imm_insn insn1, 1059 add_sub_reg_insn insn2); 1060 1061 #define WRAP(INSN) \ 1062 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1063 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1064 } \ 1065 \ 1066 void INSN(Register Rd, Register Rn, Register Rm, \ 1067 enum shift_kind kind, unsigned shift = 0) { \ 1068 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1069 } \ 1070 \ 1071 void INSN(Register Rd, Register Rn, Register Rm) { \ 1072 Assembler::INSN(Rd, Rn, Rm); \ 1073 } \ 1074 \ 1075 void INSN(Register Rd, Register Rn, Register Rm, \ 1076 ext::operation option, int amount = 0) { \ 1077 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1078 } 1079 1080 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) 1081 1082 #undef WRAP 1083 #define WRAP(INSN) \ 1084 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1085 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1086 } \ 1087 \ 1088 void INSN(Register Rd, Register Rn, Register Rm, \ 1089 enum shift_kind kind, unsigned shift = 0) { \ 1090 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1091 } \ 1092 \ 1093 void INSN(Register Rd, Register Rn, Register Rm) { \ 1094 Assembler::INSN(Rd, Rn, Rm); \ 1095 } \ 1096 \ 1097 void INSN(Register Rd, Register Rn, Register Rm, \ 1098 ext::operation option, int amount = 0) { \ 1099 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1100 } 1101 1102 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) 1103 1104 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1105 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1106 void sub(Register Rd, Register Rn, RegisterOrConstant decrement); 1107 void subw(Register Rd, Register Rn, RegisterOrConstant decrement); 1108 1109 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); 1110 1111 void tableswitch(Register index, jint lowbound, jint highbound, 1112 Label &jumptable, Label &jumptable_end, int stride = 1) { 1113 adr(rscratch1, jumptable); 1114 subsw(rscratch2, index, lowbound); 1115 subsw(zr, rscratch2, highbound - lowbound); 1116 br(Assembler::HS, jumptable_end); 1117 add(rscratch1, rscratch1, rscratch2, 1118 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1119 br(rscratch1); 1120 } 1121 1122 // Form an address from base + offset in Rd. Rd may or may not 1123 // actually be used: you must use the Address that is returned. It 1124 // is up to you to ensure that the shift provided matches the size 1125 // of your data. 1126 Address form_address(Register Rd, Register base, long byte_offset, int shift); 1127 1128 // Prolog generator routines to support switch between x86 code and 1129 // generated ARM code 1130 1131 // routine to generate an x86 prolog for a stub function which 1132 // bootstraps into the generated ARM code which directly follows the 1133 // stub 1134 // 1135 1136 public: 1137 // enum used for aarch64--x86 linkage to define return type of x86 function 1138 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; 1139 1140 #ifdef BUILTIN_SIM 1141 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); 1142 #else 1143 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } 1144 #endif 1145 1146 // special version of call_VM_leaf_base needed for aarch64 simulator 1147 // where we need to specify both the gp and fp arg counts and the 1148 // return type so that the linkage routine from aarch64 to x86 and 1149 // back knows which aarch64 registers to copy to x86 registers and 1150 // which x86 result register to copy back to an aarch64 register 1151 1152 void call_VM_leaf_base1( 1153 address entry_point, // the entry point 1154 int number_of_gp_arguments, // the number of gp reg arguments to pass 1155 int number_of_fp_arguments, // the number of fp reg arguments to pass 1156 ret_type type, // the return type for the call 1157 Label* retaddr = NULL 1158 ); 1159 1160 void ldr_constant(Register dest, const Address &const_addr) { 1161 if (NearCpool) { 1162 ldr(dest, const_addr); 1163 } else { 1164 unsigned long offset; 1165 adrp(dest, InternalAddress(const_addr.target()), offset); 1166 ldr(dest, Address(dest, offset)); 1167 } 1168 } 1169 1170 address read_polling_page(Register r, address page, relocInfo::relocType rtype); 1171 address read_polling_page(Register r, relocInfo::relocType rtype); 1172 1173 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1174 void update_byte_crc32(Register crc, Register val, Register table); 1175 void update_word_crc32(Register crc, Register v, Register tmp, 1176 Register table0, Register table1, Register table2, Register table3, 1177 bool upper = false); 1178 1179 void string_compare(Register str1, Register str2, 1180 Register cnt1, Register cnt2, Register result, 1181 Register tmp1); 1182 void string_equals(Register str1, Register str2, 1183 Register cnt, Register result, 1184 Register tmp1); 1185 void char_arrays_equals(Register ary1, Register ary2, 1186 Register result, Register tmp1); 1187 void encode_iso_array(Register src, Register dst, 1188 Register len, Register result, 1189 FloatRegister Vtmp1, FloatRegister Vtmp2, 1190 FloatRegister Vtmp3, FloatRegister Vtmp4); 1191 void string_indexof(Register str1, Register str2, 1192 Register cnt1, Register cnt2, 1193 Register tmp1, Register tmp2, 1194 Register tmp3, Register tmp4, 1195 int int_cnt1, Register result); 1196 private: 1197 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1198 Register src1, Register src2); 1199 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1200 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1201 } 1202 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1203 Register y, Register y_idx, Register z, 1204 Register carry, Register product, 1205 Register idx, Register kdx); 1206 void multiply_128_x_128_loop(Register y, Register z, 1207 Register carry, Register carry2, 1208 Register idx, Register jdx, 1209 Register yz_idx1, Register yz_idx2, 1210 Register tmp, Register tmp3, Register tmp4, 1211 Register tmp7, Register product_hi); 1212 public: 1213 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1214 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1215 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1216 // ISB may be needed because of a safepoint 1217 void maybe_isb() { isb(); } 1218 1219 private: 1220 // Return the effective address r + (r1 << ext) + offset. 1221 // Uses rscratch2. 1222 Address offsetted_address(Register r, Register r1, Address::extend ext, 1223 int offset, int size); 1224 1225 private: 1226 // Returns an address on the stack which is reachable with a ldr/str of size 1227 // Uses rscratch2 if the address is not directly reachable 1228 Address spill_address(int size, int offset, Register tmp=rscratch2); 1229 1230 public: 1231 void spill(Register Rx, bool is64, int offset) { 1232 if (is64) { 1233 str(Rx, spill_address(8, offset)); 1234 } else { 1235 strw(Rx, spill_address(4, offset)); 1236 } 1237 } 1238 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1239 str(Vx, T, spill_address(1 << (int)T, offset)); 1240 } 1241 void unspill(Register Rx, bool is64, int offset) { 1242 if (is64) { 1243 ldr(Rx, spill_address(8, offset)); 1244 } else { 1245 ldrw(Rx, spill_address(4, offset)); 1246 } 1247 } 1248 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1249 ldr(Vx, T, spill_address(1 << (int)T, offset)); 1250 } 1251 void spill_copy128(int src_offset, int dst_offset, 1252 Register tmp1=rscratch1, Register tmp2=rscratch2) { 1253 if (src_offset < 512 && (src_offset & 7) == 0 && 1254 dst_offset < 512 && (dst_offset & 7) == 0) { 1255 ldp(tmp1, tmp2, Address(sp, src_offset)); 1256 stp(tmp1, tmp2, Address(sp, dst_offset)); 1257 } else { 1258 unspill(tmp1, true, src_offset); 1259 spill(tmp1, true, dst_offset); 1260 unspill(tmp1, true, src_offset+8); 1261 spill(tmp1, true, dst_offset+8); 1262 } 1263 } 1264 }; 1265 1266 #ifdef ASSERT 1267 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1268 #endif 1269 1270 /** 1271 * class SkipIfEqual: 1272 * 1273 * Instantiating this class will result in assembly code being output that will 1274 * jump around any code emitted between the creation of the instance and it's 1275 * automatic destruction at the end of a scope block, depending on the value of 1276 * the flag passed to the constructor, which will be checked at run-time. 1277 */ 1278 class SkipIfEqual { 1279 private: 1280 MacroAssembler* _masm; 1281 Label _label; 1282 1283 public: 1284 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1285 ~SkipIfEqual(); 1286 }; 1287 1288 struct tableswitch { 1289 Register _reg; 1290 int _insn_index; jint _first_key; jint _last_key; 1291 Label _after; 1292 Label _branches; 1293 }; 1294 1295 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP