1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.hpp" 30 31 // MacroAssembler extends Assembler by frequently used macros. 32 // 33 // Instructions for which a 'better' code sequence exists depending 34 // on arguments should also go in here. 35 36 class MacroAssembler: public Assembler { 37 friend class LIR_Assembler; 38 39 public: 40 using Assembler::mov; 41 using Assembler::movi; 42 43 protected: 44 45 // Support for VM calls 46 // 47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 48 // may customize this version by overriding it for its purposes (e.g., to save/restore 49 // additional registers when doing a VM call). 50 #ifdef CC_INTERP 51 // c++ interpreter never wants to use interp_masm version of call_VM 52 #define VIRTUAL 53 #else 54 #define VIRTUAL virtual 55 #endif 56 57 VIRTUAL void call_VM_leaf_base( 58 address entry_point, // the entry point 59 int number_of_arguments, // the number of arguments to pop after the call 60 Label *retaddr = NULL 61 ); 62 63 VIRTUAL void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label &retaddr) { 67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 68 } 69 70 // This is the base routine called by the different versions of call_VM. The interpreter 71 // may customize this version by overriding it for its purposes (e.g., to save/restore 72 // additional registers when doing a VM call). 73 // 74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 75 // returns the register which contains the thread upon return. If a thread register has been 76 // specified, the return value will correspond to that register. If no last_java_sp is specified 77 // (noreg) than rsp will be used instead. 78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 80 Register java_thread, // the thread if computed before ; use noreg otherwise 81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 82 address entry_point, // the entry point 83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 84 bool check_exceptions // whether to check for pending exceptions after return 85 ); 86 87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 88 // The implementation is only non-empty for the InterpreterMacroAssembler, 89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 90 virtual void check_and_handle_popframe(Register java_thread); 91 virtual void check_and_handle_earlyret(Register java_thread); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 // Maximum size of class area in Metaspace when compressed 96 uint64_t use_XOR_for_compressed_class_base; 97 98 public: 99 MacroAssembler(CodeBuffer* code) : Assembler(code) { 100 use_XOR_for_compressed_class_base 101 = (operand_valid_for_logical_immediate(false /*is32*/, 102 (uint64_t)Universe::narrow_klass_base()) 103 && ((uint64_t)Universe::narrow_klass_base() 104 > (1u << log2_intptr(CompressedClassSpaceSize)))); 105 } 106 107 // Biased locking support 108 // lock_reg and obj_reg must be loaded up with the appropriate values. 109 // swap_reg is killed. 110 // tmp_reg must be supplied and must not be rscratch1 or rscratch2 111 // Optional slow case is for implementations (interpreter and C1) which branch to 112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 113 // Returns offset of first potentially-faulting instruction for null 114 // check info (currently consumed only by C1). If 115 // swap_reg_contains_mark is true then returns -1 as it is assumed 116 // the calling code has already passed any potential faults. 117 int biased_locking_enter(Register lock_reg, Register obj_reg, 118 Register swap_reg, Register tmp_reg, 119 bool swap_reg_contains_mark, 120 Label& done, Label* slow_case = NULL, 121 BiasedLockingCounters* counters = NULL); 122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 123 124 125 // Helper functions for statistics gathering. 126 // Unconditional atomic increment. 127 void atomic_incw(Register counter_addr, Register tmp, Register tmp2); 128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) { 129 lea(tmp1, counter_addr); 130 atomic_incw(tmp1, tmp2, tmp3); 131 } 132 // Load Effective Address 133 void lea(Register r, const Address &a) { 134 InstructionMark im(this); 135 code_section()->relocate(inst_mark(), a.rspec()); 136 a.lea(this, r); 137 } 138 139 void addmw(Address a, Register incr, Register scratch) { 140 ldrw(scratch, a); 141 addw(scratch, scratch, incr); 142 strw(scratch, a); 143 } 144 145 // Add constant to memory word 146 void addmw(Address a, int imm, Register scratch) { 147 ldrw(scratch, a); 148 if (imm > 0) 149 addw(scratch, scratch, (unsigned)imm); 150 else 151 subw(scratch, scratch, (unsigned)-imm); 152 strw(scratch, a); 153 } 154 155 void bind(Label& L) { 156 Assembler::bind(L); 157 code()->clear_last_membar(); 158 } 159 160 void membar(Membar_mask_bits order_constraint); 161 162 // Frame creation and destruction shared between JITs. 163 void build_frame(int framesize); 164 void remove_frame(int framesize); 165 166 virtual void _call_Unimplemented(address call_site) { 167 mov(rscratch2, call_site); 168 haltsim(); 169 } 170 171 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 172 173 virtual void notify(int type); 174 175 // aliases defined in AARCH64 spec 176 177 template<class T> 178 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 179 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); } 180 181 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } 182 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } 183 184 void cset(Register Rd, Assembler::Condition cond) { 185 csinc(Rd, zr, zr, ~cond); 186 } 187 void csetw(Register Rd, Assembler::Condition cond) { 188 csincw(Rd, zr, zr, ~cond); 189 } 190 191 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 192 csneg(Rd, Rn, Rn, ~cond); 193 } 194 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 195 csnegw(Rd, Rn, Rn, ~cond); 196 } 197 198 inline void movw(Register Rd, Register Rn) { 199 if (Rd == sp || Rn == sp) { 200 addw(Rd, Rn, 0U); 201 } else { 202 orrw(Rd, zr, Rn); 203 } 204 } 205 inline void mov(Register Rd, Register Rn) { 206 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 207 if (Rd == Rn) { 208 } else if (Rd == sp || Rn == sp) { 209 add(Rd, Rn, 0U); 210 } else { 211 orr(Rd, zr, Rn); 212 } 213 } 214 215 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 216 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 217 218 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); } 219 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); } 220 221 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); } 222 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); } 223 224 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 225 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 226 } 227 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 228 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 229 } 230 231 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 232 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 233 } 234 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 235 bfm(Rd, Rn, lsb , (lsb + width - 1)); 236 } 237 238 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 239 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 240 } 241 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 242 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 243 } 244 245 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 246 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 247 } 248 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 249 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 250 } 251 252 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 253 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 254 } 255 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 256 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 257 } 258 259 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 260 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 261 } 262 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 263 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 264 } 265 266 inline void asrw(Register Rd, Register Rn, unsigned imm) { 267 sbfmw(Rd, Rn, imm, 31); 268 } 269 270 inline void asr(Register Rd, Register Rn, unsigned imm) { 271 sbfm(Rd, Rn, imm, 63); 272 } 273 274 inline void lslw(Register Rd, Register Rn, unsigned imm) { 275 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 276 } 277 278 inline void lsl(Register Rd, Register Rn, unsigned imm) { 279 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 280 } 281 282 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 283 ubfmw(Rd, Rn, imm, 31); 284 } 285 286 inline void lsr(Register Rd, Register Rn, unsigned imm) { 287 ubfm(Rd, Rn, imm, 63); 288 } 289 290 inline void rorw(Register Rd, Register Rn, unsigned imm) { 291 extrw(Rd, Rn, Rn, imm); 292 } 293 294 inline void ror(Register Rd, Register Rn, unsigned imm) { 295 extr(Rd, Rn, Rn, imm); 296 } 297 298 inline void sxtbw(Register Rd, Register Rn) { 299 sbfmw(Rd, Rn, 0, 7); 300 } 301 inline void sxthw(Register Rd, Register Rn) { 302 sbfmw(Rd, Rn, 0, 15); 303 } 304 inline void sxtb(Register Rd, Register Rn) { 305 sbfm(Rd, Rn, 0, 7); 306 } 307 inline void sxth(Register Rd, Register Rn) { 308 sbfm(Rd, Rn, 0, 15); 309 } 310 inline void sxtw(Register Rd, Register Rn) { 311 sbfm(Rd, Rn, 0, 31); 312 } 313 314 inline void uxtbw(Register Rd, Register Rn) { 315 ubfmw(Rd, Rn, 0, 7); 316 } 317 inline void uxthw(Register Rd, Register Rn) { 318 ubfmw(Rd, Rn, 0, 15); 319 } 320 inline void uxtb(Register Rd, Register Rn) { 321 ubfm(Rd, Rn, 0, 7); 322 } 323 inline void uxth(Register Rd, Register Rn) { 324 ubfm(Rd, Rn, 0, 15); 325 } 326 inline void uxtw(Register Rd, Register Rn) { 327 ubfm(Rd, Rn, 0, 31); 328 } 329 330 inline void cmnw(Register Rn, Register Rm) { 331 addsw(zr, Rn, Rm); 332 } 333 inline void cmn(Register Rn, Register Rm) { 334 adds(zr, Rn, Rm); 335 } 336 337 inline void cmpw(Register Rn, Register Rm) { 338 subsw(zr, Rn, Rm); 339 } 340 inline void cmp(Register Rn, Register Rm) { 341 subs(zr, Rn, Rm); 342 } 343 344 inline void negw(Register Rd, Register Rn) { 345 subw(Rd, zr, Rn); 346 } 347 348 inline void neg(Register Rd, Register Rn) { 349 sub(Rd, zr, Rn); 350 } 351 352 inline void negsw(Register Rd, Register Rn) { 353 subsw(Rd, zr, Rn); 354 } 355 356 inline void negs(Register Rd, Register Rn) { 357 subs(Rd, zr, Rn); 358 } 359 360 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 361 addsw(zr, Rn, Rm, kind, shift); 362 } 363 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 364 adds(zr, Rn, Rm, kind, shift); 365 } 366 367 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 368 subsw(zr, Rn, Rm, kind, shift); 369 } 370 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 371 subs(zr, Rn, Rm, kind, shift); 372 } 373 374 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 375 subw(Rd, zr, Rn, kind, shift); 376 } 377 378 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 379 sub(Rd, zr, Rn, kind, shift); 380 } 381 382 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 383 subsw(Rd, zr, Rn, kind, shift); 384 } 385 386 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 387 subs(Rd, zr, Rn, kind, shift); 388 } 389 390 inline void mnegw(Register Rd, Register Rn, Register Rm) { 391 msubw(Rd, Rn, Rm, zr); 392 } 393 inline void mneg(Register Rd, Register Rn, Register Rm) { 394 msub(Rd, Rn, Rm, zr); 395 } 396 397 inline void mulw(Register Rd, Register Rn, Register Rm) { 398 maddw(Rd, Rn, Rm, zr); 399 } 400 inline void mul(Register Rd, Register Rn, Register Rm) { 401 madd(Rd, Rn, Rm, zr); 402 } 403 404 inline void smnegl(Register Rd, Register Rn, Register Rm) { 405 smsubl(Rd, Rn, Rm, zr); 406 } 407 inline void smull(Register Rd, Register Rn, Register Rm) { 408 smaddl(Rd, Rn, Rm, zr); 409 } 410 411 inline void umnegl(Register Rd, Register Rn, Register Rm) { 412 umsubl(Rd, Rn, Rm, zr); 413 } 414 inline void umull(Register Rd, Register Rn, Register Rm) { 415 umaddl(Rd, Rn, Rm, zr); 416 } 417 418 #define WRAP(INSN) \ 419 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 420 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \ 421 nop(); \ 422 Assembler::INSN(Rd, Rn, Rm, Ra); \ 423 } 424 425 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 426 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 427 #undef WRAP 428 429 430 // macro assembly operations needed for aarch64 431 432 // first two private routines for loading 32 bit or 64 bit constants 433 private: 434 435 void mov_immediate64(Register dst, u_int64_t imm64); 436 void mov_immediate32(Register dst, u_int32_t imm32); 437 438 int push(unsigned int bitset, Register stack); 439 int pop(unsigned int bitset, Register stack); 440 441 void mov(Register dst, Address a); 442 443 public: 444 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 445 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 446 447 // Push and pop everything that might be clobbered by a native 448 // runtime call except rscratch1 and rscratch2. (They are always 449 // scratch, so we don't have to protect them.) Only save the lower 450 // 64 bits of each vector register. 451 void push_call_clobbered_registers(); 452 void pop_call_clobbered_registers(); 453 454 // now mov instructions for loading absolute addresses and 32 or 455 // 64 bit integers 456 457 inline void mov(Register dst, address addr) 458 { 459 mov_immediate64(dst, (u_int64_t)addr); 460 } 461 462 inline void mov(Register dst, u_int64_t imm64) 463 { 464 mov_immediate64(dst, imm64); 465 } 466 467 inline void movw(Register dst, u_int32_t imm32) 468 { 469 mov_immediate32(dst, imm32); 470 } 471 472 inline void mov(Register dst, long l) 473 { 474 mov(dst, (u_int64_t)l); 475 } 476 477 inline void mov(Register dst, int i) 478 { 479 mov(dst, (long)i); 480 } 481 482 void mov(Register dst, RegisterOrConstant src) { 483 if (src.is_register()) 484 mov(dst, src.as_register()); 485 else 486 mov(dst, src.as_constant()); 487 } 488 489 void movptr(Register r, uintptr_t imm64); 490 491 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32); 492 493 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 494 orr(Vd, T, Vn, Vn); 495 } 496 497 public: 498 499 // Generalized Test Bit And Branch, including a "far" variety which 500 // spans more than 32KiB. 501 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) { 502 assert(cond == EQ || cond == NE, "must be"); 503 504 if (far) 505 cond = ~cond; 506 507 void (Assembler::* branch)(Register Rt, int bitpos, Label &L); 508 if (cond == Assembler::EQ) 509 branch = &Assembler::tbz; 510 else 511 branch = &Assembler::tbnz; 512 513 if (far) { 514 Label L; 515 (this->*branch)(Rt, bitpos, L); 516 b(dest); 517 bind(L); 518 } else { 519 (this->*branch)(Rt, bitpos, dest); 520 } 521 } 522 523 // macro instructions for accessing and updating floating point 524 // status register 525 // 526 // FPSR : op1 == 011 527 // CRn == 0100 528 // CRm == 0100 529 // op2 == 001 530 531 inline void get_fpsr(Register reg) 532 { 533 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 534 } 535 536 inline void set_fpsr(Register reg) 537 { 538 msr(0b011, 0b0100, 0b0100, 0b001, reg); 539 } 540 541 inline void clear_fpsr() 542 { 543 msr(0b011, 0b0100, 0b0100, 0b001, zr); 544 } 545 546 // idiv variant which deals with MINLONG as dividend and -1 as divisor 547 int corrected_idivl(Register result, Register ra, Register rb, 548 bool want_remainder, Register tmp = rscratch1); 549 int corrected_idivq(Register result, Register ra, Register rb, 550 bool want_remainder, Register tmp = rscratch1); 551 552 // Support for NULL-checks 553 // 554 // Generates code that causes a NULL OS exception if the content of reg is NULL. 555 // If the accessed location is M[reg + offset] and the offset is known, provide the 556 // offset. No explicit code generation is needed if the offset is within a certain 557 // range (0 <= offset <= page_size). 558 559 virtual void null_check(Register reg, int offset = -1); 560 static bool needs_explicit_null_check(intptr_t offset); 561 562 static address target_addr_for_insn(address insn_addr, unsigned insn); 563 static address target_addr_for_insn(address insn_addr) { 564 unsigned insn = *(unsigned*)insn_addr; 565 return target_addr_for_insn(insn_addr, insn); 566 } 567 568 // Required platform-specific helpers for Label::patch_instructions. 569 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 570 static int pd_patch_instruction_size(address branch, address target); 571 static void pd_patch_instruction(address branch, address target) { 572 pd_patch_instruction_size(branch, target); 573 } 574 static address pd_call_destination(address branch) { 575 return target_addr_for_insn(branch); 576 } 577 #ifndef PRODUCT 578 static void pd_print_patched_instruction(address branch); 579 #endif 580 581 static int patch_oop(address insn_addr, address o); 582 583 address emit_trampoline_stub(int insts_call_instruction_offset, address target); 584 585 // The following 4 methods return the offset of the appropriate move instruction 586 587 // Support for fast byte/short loading with zero extension (depending on particular CPU) 588 int load_unsigned_byte(Register dst, Address src); 589 int load_unsigned_short(Register dst, Address src); 590 591 // Support for fast byte/short loading with sign extension (depending on particular CPU) 592 int load_signed_byte(Register dst, Address src); 593 int load_signed_short(Register dst, Address src); 594 595 int load_signed_byte32(Register dst, Address src); 596 int load_signed_short32(Register dst, Address src); 597 598 // Support for sign-extension (hi:lo = extend_sign(lo)) 599 void extend_sign(Register hi, Register lo); 600 601 // Load and store values by size and signed-ness 602 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 603 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 604 605 // Support for inc/dec with optimal instruction selection depending on value 606 607 // x86_64 aliases an unqualified register/address increment and 608 // decrement to call incrementq and decrementq but also supports 609 // explicitly sized calls to incrementq/decrementq or 610 // incrementl/decrementl 611 612 // for aarch64 the proper convention would be to use 613 // increment/decrement for 64 bit operatons and 614 // incrementw/decrementw for 32 bit operations. so when porting 615 // x86_64 code we can leave calls to increment/decrement as is, 616 // replace incrementq/decrementq with increment/decrement and 617 // replace incrementl/decrementl with incrementw/decrementw. 618 619 // n.b. increment/decrement calls with an Address destination will 620 // need to use a scratch register to load the value to be 621 // incremented. increment/decrement calls which add or subtract a 622 // constant value greater than 2^12 will need to use a 2nd scratch 623 // register to hold the constant. so, a register increment/decrement 624 // may trash rscratch2 and an address increment/decrement trash 625 // rscratch and rscratch2 626 627 void decrementw(Address dst, int value = 1); 628 void decrementw(Register reg, int value = 1); 629 630 void decrement(Register reg, int value = 1); 631 void decrement(Address dst, int value = 1); 632 633 void incrementw(Address dst, int value = 1); 634 void incrementw(Register reg, int value = 1); 635 636 void increment(Register reg, int value = 1); 637 void increment(Address dst, int value = 1); 638 639 640 // Alignment 641 void align(int modulus); 642 643 // Stack frame creation/removal 644 void enter() 645 { 646 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 647 mov(rfp, sp); 648 } 649 void leave() 650 { 651 mov(sp, rfp); 652 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 653 } 654 655 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 656 // The pointer will be loaded into the thread register. 657 void get_thread(Register thread); 658 659 660 // Support for VM calls 661 // 662 // It is imperative that all calls into the VM are handled via the call_VM macros. 663 // They make sure that the stack linkage is setup correctly. call_VM's correspond 664 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 665 666 667 void call_VM(Register oop_result, 668 address entry_point, 669 bool check_exceptions = true); 670 void call_VM(Register oop_result, 671 address entry_point, 672 Register arg_1, 673 bool check_exceptions = true); 674 void call_VM(Register oop_result, 675 address entry_point, 676 Register arg_1, Register arg_2, 677 bool check_exceptions = true); 678 void call_VM(Register oop_result, 679 address entry_point, 680 Register arg_1, Register arg_2, Register arg_3, 681 bool check_exceptions = true); 682 683 // Overloadings with last_Java_sp 684 void call_VM(Register oop_result, 685 Register last_java_sp, 686 address entry_point, 687 int number_of_arguments = 0, 688 bool check_exceptions = true); 689 void call_VM(Register oop_result, 690 Register last_java_sp, 691 address entry_point, 692 Register arg_1, bool 693 check_exceptions = true); 694 void call_VM(Register oop_result, 695 Register last_java_sp, 696 address entry_point, 697 Register arg_1, Register arg_2, 698 bool check_exceptions = true); 699 void call_VM(Register oop_result, 700 Register last_java_sp, 701 address entry_point, 702 Register arg_1, Register arg_2, Register arg_3, 703 bool check_exceptions = true); 704 705 void get_vm_result (Register oop_result, Register thread); 706 void get_vm_result_2(Register metadata_result, Register thread); 707 708 // These always tightly bind to MacroAssembler::call_VM_base 709 // bypassing the virtual implementation 710 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 711 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 712 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 713 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 714 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 715 716 void call_VM_leaf(address entry_point, 717 int number_of_arguments = 0); 718 void call_VM_leaf(address entry_point, 719 Register arg_1); 720 void call_VM_leaf(address entry_point, 721 Register arg_1, Register arg_2); 722 void call_VM_leaf(address entry_point, 723 Register arg_1, Register arg_2, Register arg_3); 724 725 // These always tightly bind to MacroAssembler::call_VM_leaf_base 726 // bypassing the virtual implementation 727 void super_call_VM_leaf(address entry_point); 728 void super_call_VM_leaf(address entry_point, Register arg_1); 729 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 730 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 731 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 732 733 // last Java Frame (fills frame anchor) 734 void set_last_Java_frame(Register last_java_sp, 735 Register last_java_fp, 736 address last_java_pc, 737 Register scratch); 738 739 void set_last_Java_frame(Register last_java_sp, 740 Register last_java_fp, 741 Label &last_java_pc, 742 Register scratch); 743 744 void set_last_Java_frame(Register last_java_sp, 745 Register last_java_fp, 746 Register last_java_pc, 747 Register scratch); 748 749 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc); 750 751 // thread in the default location (r15_thread on 64bit) 752 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 753 754 // Stores 755 void store_check(Register obj); // store check for obj - register is destroyed afterwards 756 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 757 758 #if INCLUDE_ALL_GCS 759 760 void g1_write_barrier_pre(Register obj, 761 Register pre_val, 762 Register thread, 763 Register tmp, 764 bool tosca_live, 765 bool expand_call); 766 767 void g1_write_barrier_post(Register store_addr, 768 Register new_val, 769 Register thread, 770 Register tmp, 771 Register tmp2); 772 773 #endif // INCLUDE_ALL_GCS 774 775 // oop manipulations 776 void load_klass(Register dst, Register src); 777 void store_klass(Register dst, Register src); 778 void cmp_klass(Register oop, Register trial_klass, Register tmp); 779 780 void load_heap_oop(Register dst, Address src); 781 782 void load_heap_oop_not_null(Register dst, Address src); 783 void store_heap_oop(Address dst, Register src); 784 785 // currently unimplemented 786 // Used for storing NULL. All other oop constants should be 787 // stored using routines that take a jobject. 788 void store_heap_oop_null(Address dst); 789 790 void load_prototype_header(Register dst, Register src); 791 792 void store_klass_gap(Register dst, Register src); 793 794 // This dummy is to prevent a call to store_heap_oop from 795 // converting a zero (like NULL) into a Register by giving 796 // the compiler two choices it can't resolve 797 798 void store_heap_oop(Address dst, void* dummy); 799 800 void encode_heap_oop(Register d, Register s); 801 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 802 void decode_heap_oop(Register d, Register s); 803 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 804 void encode_heap_oop_not_null(Register r); 805 void decode_heap_oop_not_null(Register r); 806 void encode_heap_oop_not_null(Register dst, Register src); 807 void decode_heap_oop_not_null(Register dst, Register src); 808 809 void set_narrow_oop(Register dst, jobject obj); 810 811 void encode_klass_not_null(Register r); 812 void decode_klass_not_null(Register r); 813 void encode_klass_not_null(Register dst, Register src); 814 void decode_klass_not_null(Register dst, Register src); 815 816 void set_narrow_klass(Register dst, Klass* k); 817 818 // if heap base register is used - reinit it with the correct value 819 void reinit_heapbase(); 820 821 DEBUG_ONLY(void verify_heapbase(const char* msg);) 822 823 void push_CPU_state(bool save_vectors = false); 824 void pop_CPU_state(bool restore_vectors = false) ; 825 826 // Round up to a power of two 827 void round_to(Register reg, int modulus); 828 829 // allocation 830 void eden_allocate( 831 Register obj, // result: pointer to object after successful allocation 832 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 833 int con_size_in_bytes, // object size in bytes if known at compile time 834 Register t1, // temp register 835 Label& slow_case // continuation point if fast allocation fails 836 ); 837 void tlab_allocate( 838 Register obj, // result: pointer to object after successful allocation 839 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 840 int con_size_in_bytes, // object size in bytes if known at compile time 841 Register t1, // temp register 842 Register t2, // temp register 843 Label& slow_case // continuation point if fast allocation fails 844 ); 845 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 846 void verify_tlab(); 847 848 void incr_allocated_bytes(Register thread, 849 Register var_size_in_bytes, int con_size_in_bytes, 850 Register t1 = noreg); 851 852 // interface method calling 853 void lookup_interface_method(Register recv_klass, 854 Register intf_klass, 855 RegisterOrConstant itable_index, 856 Register method_result, 857 Register scan_temp, 858 Label& no_such_interface); 859 860 // virtual method calling 861 // n.b. x86 allows RegisterOrConstant for vtable_index 862 void lookup_virtual_method(Register recv_klass, 863 RegisterOrConstant vtable_index, 864 Register method_result); 865 866 // Test sub_klass against super_klass, with fast and slow paths. 867 868 // The fast path produces a tri-state answer: yes / no / maybe-slow. 869 // One of the three labels can be NULL, meaning take the fall-through. 870 // If super_check_offset is -1, the value is loaded up from super_klass. 871 // No registers are killed, except temp_reg. 872 void check_klass_subtype_fast_path(Register sub_klass, 873 Register super_klass, 874 Register temp_reg, 875 Label* L_success, 876 Label* L_failure, 877 Label* L_slow_path, 878 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 879 880 // The rest of the type check; must be wired to a corresponding fast path. 881 // It does not repeat the fast path logic, so don't use it standalone. 882 // The temp_reg and temp2_reg can be noreg, if no temps are available. 883 // Updates the sub's secondary super cache as necessary. 884 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 885 void check_klass_subtype_slow_path(Register sub_klass, 886 Register super_klass, 887 Register temp_reg, 888 Register temp2_reg, 889 Label* L_success, 890 Label* L_failure, 891 bool set_cond_codes = false); 892 893 // Simplified, combined version, good for typical uses. 894 // Falls through on failure. 895 void check_klass_subtype(Register sub_klass, 896 Register super_klass, 897 Register temp_reg, 898 Label& L_success); 899 900 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 901 902 903 // Debugging 904 905 // only if +VerifyOops 906 void verify_oop(Register reg, const char* s = "broken oop"); 907 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 908 909 // TODO: verify method and klass metadata (compare against vptr?) 910 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 911 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 912 913 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 914 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 915 916 // only if +VerifyFPU 917 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 918 919 // prints msg, dumps registers and stops execution 920 void stop(const char* msg); 921 922 // prints msg and continues 923 void warn(const char* msg); 924 925 static void debug64(char* msg, int64_t pc, int64_t regs[]); 926 927 void untested() { stop("untested"); } 928 929 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 930 931 void should_not_reach_here() { stop("should not reach here"); } 932 933 // Stack overflow checking 934 void bang_stack_with_offset(int offset) { 935 // stack grows down, caller passes positive offset 936 assert(offset > 0, "must bang with negative offset"); 937 mov(rscratch2, -offset); 938 str(zr, Address(sp, rscratch2)); 939 } 940 941 // Writes to stack successive pages until offset reached to check for 942 // stack overflow + shadow pages. Also, clobbers tmp 943 void bang_stack_size(Register size, Register tmp); 944 945 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 946 Register tmp, 947 int offset); 948 949 // Support for serializing memory accesses between threads 950 void serialize_memory(Register thread, Register tmp); 951 952 // Arithmetics 953 954 void addptr(const Address &dst, int32_t src); 955 void cmpptr(Register src1, Address src2); 956 957 // Various forms of CAS 958 959 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 960 Label &suceed, Label *fail); 961 962 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 963 Label &suceed, Label *fail); 964 965 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 966 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 967 968 void atomic_xchg(Register prev, Register newv, Register addr); 969 void atomic_xchgw(Register prev, Register newv, Register addr); 970 971 void orptr(Address adr, RegisterOrConstant src) { 972 ldr(rscratch2, adr); 973 if (src.is_register()) 974 orr(rscratch2, rscratch2, src.as_register()); 975 else 976 orr(rscratch2, rscratch2, src.as_constant()); 977 str(rscratch2, adr); 978 } 979 980 // A generic CAS; success or failure is in the EQ flag. 981 template <typename T1, typename T2> 982 void cmpxchg(Register addr, Register expected, Register new_val, 983 T1 load_insn, 984 void (MacroAssembler::*cmp_insn)(Register, Register), 985 T2 store_insn, 986 Register tmp = rscratch1) { 987 Label retry_load, done; 988 bind(retry_load); 989 (this->*load_insn)(tmp, addr); 990 (this->*cmp_insn)(tmp, expected); 991 br(Assembler::NE, done); 992 (this->*store_insn)(tmp, new_val, addr); 993 cbnzw(tmp, retry_load); 994 bind(done); 995 } 996 997 // Calls 998 999 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL); 1000 1001 static bool far_branches() { 1002 return ReservedCodeCacheSize > branch_range; 1003 } 1004 1005 // Jumps that can reach anywhere in the code cache. 1006 // Trashes tmp. 1007 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 1008 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1); 1009 1010 static int far_branch_size() { 1011 if (far_branches()) { 1012 return 3 * 4; // adrp, add, br 1013 } else { 1014 return 4; 1015 } 1016 } 1017 1018 // Emit the CompiledIC call idiom 1019 address ic_call(address entry, jint method_index = 0); 1020 1021 public: 1022 1023 // Data 1024 1025 void mov_metadata(Register dst, Metadata* obj); 1026 Address allocate_metadata_address(Metadata* obj); 1027 Address constant_oop_address(jobject obj); 1028 1029 void movoop(Register dst, jobject obj, bool immediate = false); 1030 1031 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1032 void kernel_crc32(Register crc, Register buf, Register len, 1033 Register table0, Register table1, Register table2, Register table3, 1034 Register tmp, Register tmp2, Register tmp3); 1035 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic. 1036 void kernel_crc32c(Register crc, Register buf, Register len, 1037 Register table0, Register table1, Register table2, Register table3, 1038 Register tmp, Register tmp2, Register tmp3); 1039 1040 #undef VIRTUAL 1041 1042 // Stack push and pop individual 64 bit registers 1043 void push(Register src); 1044 void pop(Register dst); 1045 1046 // push all registers onto the stack 1047 void pusha(); 1048 void popa(); 1049 1050 void repne_scan(Register addr, Register value, Register count, 1051 Register scratch); 1052 void repne_scanw(Register addr, Register value, Register count, 1053 Register scratch); 1054 1055 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1056 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1057 1058 // If a constant does not fit in an immediate field, generate some 1059 // number of MOV instructions and then perform the operation 1060 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1061 add_sub_imm_insn insn1, 1062 add_sub_reg_insn insn2); 1063 // Seperate vsn which sets the flags 1064 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1065 add_sub_imm_insn insn1, 1066 add_sub_reg_insn insn2); 1067 1068 #define WRAP(INSN) \ 1069 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1070 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1071 } \ 1072 \ 1073 void INSN(Register Rd, Register Rn, Register Rm, \ 1074 enum shift_kind kind, unsigned shift = 0) { \ 1075 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1076 } \ 1077 \ 1078 void INSN(Register Rd, Register Rn, Register Rm) { \ 1079 Assembler::INSN(Rd, Rn, Rm); \ 1080 } \ 1081 \ 1082 void INSN(Register Rd, Register Rn, Register Rm, \ 1083 ext::operation option, int amount = 0) { \ 1084 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1085 } 1086 1087 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) 1088 1089 #undef WRAP 1090 #define WRAP(INSN) \ 1091 void INSN(Register Rd, Register Rn, unsigned imm) { \ 1092 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ 1093 } \ 1094 \ 1095 void INSN(Register Rd, Register Rn, Register Rm, \ 1096 enum shift_kind kind, unsigned shift = 0) { \ 1097 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1098 } \ 1099 \ 1100 void INSN(Register Rd, Register Rn, Register Rm) { \ 1101 Assembler::INSN(Rd, Rn, Rm); \ 1102 } \ 1103 \ 1104 void INSN(Register Rd, Register Rn, Register Rm, \ 1105 ext::operation option, int amount = 0) { \ 1106 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1107 } 1108 1109 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) 1110 1111 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1112 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1113 void sub(Register Rd, Register Rn, RegisterOrConstant decrement); 1114 void subw(Register Rd, Register Rn, RegisterOrConstant decrement); 1115 1116 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); 1117 1118 void tableswitch(Register index, jint lowbound, jint highbound, 1119 Label &jumptable, Label &jumptable_end, int stride = 1) { 1120 adr(rscratch1, jumptable); 1121 subsw(rscratch2, index, lowbound); 1122 subsw(zr, rscratch2, highbound - lowbound); 1123 br(Assembler::HS, jumptable_end); 1124 add(rscratch1, rscratch1, rscratch2, 1125 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1126 br(rscratch1); 1127 } 1128 1129 // Form an address from base + offset in Rd. Rd may or may not 1130 // actually be used: you must use the Address that is returned. It 1131 // is up to you to ensure that the shift provided matches the size 1132 // of your data. 1133 Address form_address(Register Rd, Register base, long byte_offset, int shift); 1134 1135 // Return true iff an address is within the 48-bit AArch64 address 1136 // space. 1137 bool is_valid_AArch64_address(address a) { 1138 return ((uint64_t)a >> 48) == 0; 1139 } 1140 1141 // Load the base of the cardtable byte map into reg. 1142 void load_byte_map_base(Register reg); 1143 1144 // Prolog generator routines to support switch between x86 code and 1145 // generated ARM code 1146 1147 // routine to generate an x86 prolog for a stub function which 1148 // bootstraps into the generated ARM code which directly follows the 1149 // stub 1150 // 1151 1152 public: 1153 // enum used for aarch64--x86 linkage to define return type of x86 function 1154 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double}; 1155 1156 #ifdef BUILTIN_SIM 1157 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL); 1158 #else 1159 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { } 1160 #endif 1161 1162 // special version of call_VM_leaf_base needed for aarch64 simulator 1163 // where we need to specify both the gp and fp arg counts and the 1164 // return type so that the linkage routine from aarch64 to x86 and 1165 // back knows which aarch64 registers to copy to x86 registers and 1166 // which x86 result register to copy back to an aarch64 register 1167 1168 void call_VM_leaf_base1( 1169 address entry_point, // the entry point 1170 int number_of_gp_arguments, // the number of gp reg arguments to pass 1171 int number_of_fp_arguments, // the number of fp reg arguments to pass 1172 ret_type type, // the return type for the call 1173 Label* retaddr = NULL 1174 ); 1175 1176 void ldr_constant(Register dest, const Address &const_addr) { 1177 if (NearCpool) { 1178 ldr(dest, const_addr); 1179 } else { 1180 unsigned long offset; 1181 adrp(dest, InternalAddress(const_addr.target()), offset); 1182 ldr(dest, Address(dest, offset)); 1183 } 1184 } 1185 1186 address read_polling_page(Register r, address page, relocInfo::relocType rtype); 1187 address read_polling_page(Register r, relocInfo::relocType rtype); 1188 1189 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1190 void update_byte_crc32(Register crc, Register val, Register table); 1191 void update_word_crc32(Register crc, Register v, Register tmp, 1192 Register table0, Register table1, Register table2, Register table3, 1193 bool upper = false); 1194 1195 void string_compare(Register str1, Register str2, 1196 Register cnt1, Register cnt2, Register result, 1197 Register tmp1); 1198 void string_equals(Register str1, Register str2, 1199 Register cnt, Register result, 1200 Register tmp1); 1201 void char_arrays_equals(Register ary1, Register ary2, 1202 Register result, Register tmp1); 1203 void encode_iso_array(Register src, Register dst, 1204 Register len, Register result, 1205 FloatRegister Vtmp1, FloatRegister Vtmp2, 1206 FloatRegister Vtmp3, FloatRegister Vtmp4); 1207 void string_indexof(Register str1, Register str2, 1208 Register cnt1, Register cnt2, 1209 Register tmp1, Register tmp2, 1210 Register tmp3, Register tmp4, 1211 int int_cnt1, Register result); 1212 private: 1213 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1214 Register src1, Register src2); 1215 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1216 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1217 } 1218 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1219 Register y, Register y_idx, Register z, 1220 Register carry, Register product, 1221 Register idx, Register kdx); 1222 void multiply_128_x_128_loop(Register y, Register z, 1223 Register carry, Register carry2, 1224 Register idx, Register jdx, 1225 Register yz_idx1, Register yz_idx2, 1226 Register tmp, Register tmp3, Register tmp4, 1227 Register tmp7, Register product_hi); 1228 public: 1229 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1230 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1231 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1232 // ISB may be needed because of a safepoint 1233 void maybe_isb() { isb(); } 1234 1235 private: 1236 // Return the effective address r + (r1 << ext) + offset. 1237 // Uses rscratch2. 1238 Address offsetted_address(Register r, Register r1, Address::extend ext, 1239 int offset, int size); 1240 1241 private: 1242 // Returns an address on the stack which is reachable with a ldr/str of size 1243 // Uses rscratch2 if the address is not directly reachable 1244 Address spill_address(int size, int offset, Register tmp=rscratch2); 1245 1246 public: 1247 void spill(Register Rx, bool is64, int offset) { 1248 if (is64) { 1249 str(Rx, spill_address(8, offset)); 1250 } else { 1251 strw(Rx, spill_address(4, offset)); 1252 } 1253 } 1254 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1255 str(Vx, T, spill_address(1 << (int)T, offset)); 1256 } 1257 void unspill(Register Rx, bool is64, int offset) { 1258 if (is64) { 1259 ldr(Rx, spill_address(8, offset)); 1260 } else { 1261 ldrw(Rx, spill_address(4, offset)); 1262 } 1263 } 1264 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1265 ldr(Vx, T, spill_address(1 << (int)T, offset)); 1266 } 1267 void spill_copy128(int src_offset, int dst_offset, 1268 Register tmp1=rscratch1, Register tmp2=rscratch2) { 1269 if (src_offset < 512 && (src_offset & 7) == 0 && 1270 dst_offset < 512 && (dst_offset & 7) == 0) { 1271 ldp(tmp1, tmp2, Address(sp, src_offset)); 1272 stp(tmp1, tmp2, Address(sp, dst_offset)); 1273 } else { 1274 unspill(tmp1, true, src_offset); 1275 spill(tmp1, true, dst_offset); 1276 unspill(tmp1, true, src_offset+8); 1277 spill(tmp1, true, dst_offset+8); 1278 } 1279 } 1280 }; 1281 1282 #ifdef ASSERT 1283 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1284 #endif 1285 1286 /** 1287 * class SkipIfEqual: 1288 * 1289 * Instantiating this class will result in assembly code being output that will 1290 * jump around any code emitted between the creation of the instance and it's 1291 * automatic destruction at the end of a scope block, depending on the value of 1292 * the flag passed to the constructor, which will be checked at run-time. 1293 */ 1294 class SkipIfEqual { 1295 private: 1296 MacroAssembler* _masm; 1297 Label _label; 1298 1299 public: 1300 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1301 ~SkipIfEqual(); 1302 }; 1303 1304 struct tableswitch { 1305 Register _reg; 1306 int _insn_index; jint _first_key; jint _last_key; 1307 Label _after; 1308 Label _branches; 1309 }; 1310 1311 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP