427 #undef WRAP
428
429
430 // macro assembly operations needed for aarch64
431
432 // first two private routines for loading 32 bit or 64 bit constants
433 private:
434
435 void mov_immediate64(Register dst, u_int64_t imm64);
436 void mov_immediate32(Register dst, u_int32_t imm32);
437
438 int push(unsigned int bitset, Register stack);
439 int pop(unsigned int bitset, Register stack);
440
441 void mov(Register dst, Address a);
442
443 public:
444 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
445 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
446
447 // now mov instructions for loading absolute addresses and 32 or
448 // 64 bit integers
449
450 inline void mov(Register dst, address addr)
451 {
452 mov_immediate64(dst, (u_int64_t)addr);
453 }
454
455 inline void mov(Register dst, u_int64_t imm64)
456 {
457 mov_immediate64(dst, imm64);
458 }
459
460 inline void movw(Register dst, u_int32_t imm32)
461 {
462 mov_immediate32(dst, imm32);
463 }
464
465 inline void mov(Register dst, long l)
466 {
1107 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1108
1109 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1110
1111 void tableswitch(Register index, jint lowbound, jint highbound,
1112 Label &jumptable, Label &jumptable_end, int stride = 1) {
1113 adr(rscratch1, jumptable);
1114 subsw(rscratch2, index, lowbound);
1115 subsw(zr, rscratch2, highbound - lowbound);
1116 br(Assembler::HS, jumptable_end);
1117 add(rscratch1, rscratch1, rscratch2,
1118 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1119 br(rscratch1);
1120 }
1121
1122 // Form an address from base + offset in Rd. Rd may or may not
1123 // actually be used: you must use the Address that is returned. It
1124 // is up to you to ensure that the shift provided matches the size
1125 // of your data.
1126 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1127
1128 // Prolog generator routines to support switch between x86 code and
1129 // generated ARM code
1130
1131 // routine to generate an x86 prolog for a stub function which
1132 // bootstraps into the generated ARM code which directly follows the
1133 // stub
1134 //
1135
1136 public:
1137 // enum used for aarch64--x86 linkage to define return type of x86 function
1138 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1139
1140 #ifdef BUILTIN_SIM
1141 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1142 #else
1143 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1144 #endif
1145
1146 // special version of call_VM_leaf_base needed for aarch64 simulator
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427 #undef WRAP
428
429
430 // macro assembly operations needed for aarch64
431
432 // first two private routines for loading 32 bit or 64 bit constants
433 private:
434
435 void mov_immediate64(Register dst, u_int64_t imm64);
436 void mov_immediate32(Register dst, u_int32_t imm32);
437
438 int push(unsigned int bitset, Register stack);
439 int pop(unsigned int bitset, Register stack);
440
441 void mov(Register dst, Address a);
442
443 public:
444 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
445 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
446
447 // Push and pop everything that might be clobbered by a native
448 // runtime call except rscratch1 and rscratch2. (They are always
449 // scratch, so we don't have to protect them.) Only save the lower
450 // 64 bits of each vector register.
451 void push_call_clobbered_registers();
452 void pop_call_clobbered_registers();
453
454 // now mov instructions for loading absolute addresses and 32 or
455 // 64 bit integers
456
457 inline void mov(Register dst, address addr)
458 {
459 mov_immediate64(dst, (u_int64_t)addr);
460 }
461
462 inline void mov(Register dst, u_int64_t imm64)
463 {
464 mov_immediate64(dst, imm64);
465 }
466
467 inline void movw(Register dst, u_int32_t imm32)
468 {
469 mov_immediate32(dst, imm32);
470 }
471
472 inline void mov(Register dst, long l)
473 {
1114 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1115
1116 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1117
1118 void tableswitch(Register index, jint lowbound, jint highbound,
1119 Label &jumptable, Label &jumptable_end, int stride = 1) {
1120 adr(rscratch1, jumptable);
1121 subsw(rscratch2, index, lowbound);
1122 subsw(zr, rscratch2, highbound - lowbound);
1123 br(Assembler::HS, jumptable_end);
1124 add(rscratch1, rscratch1, rscratch2,
1125 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1126 br(rscratch1);
1127 }
1128
1129 // Form an address from base + offset in Rd. Rd may or may not
1130 // actually be used: you must use the Address that is returned. It
1131 // is up to you to ensure that the shift provided matches the size
1132 // of your data.
1133 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1134
1135 // Return true iff an address is within the 48-bit AArch64 address
1136 // space.
1137 bool is_valid_AArch64_address(address a) {
1138 return ((uint64_t)a >> 48) == 0;
1139 }
1140
1141 // Load the base of the cardtable byte map into reg.
1142 void load_byte_map_base(Register reg);
1143
1144 // Prolog generator routines to support switch between x86 code and
1145 // generated ARM code
1146
1147 // routine to generate an x86 prolog for a stub function which
1148 // bootstraps into the generated ARM code which directly follows the
1149 // stub
1150 //
1151
1152 public:
1153 // enum used for aarch64--x86 linkage to define return type of x86 function
1154 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1155
1156 #ifdef BUILTIN_SIM
1157 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1158 #else
1159 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1160 #endif
1161
1162 // special version of call_VM_leaf_base needed for aarch64 simulator
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