228 if (dest == (address) -1) {
229 dest = instruction_address();
230 }
231
232 move->set_data((uintptr_t) dest);
233 };
234
235 //-------------------------------------------------------------------
236
237 bool NativeInstruction::is_safepoint_poll() {
238 // a safepoint_poll is implemented in two steps as either
239 //
240 // adrp(reg, polling_page);
241 // ldr(zr, [reg, #offset]);
242 //
243 // or
244 //
245 // mov(reg, polling_page);
246 // ldr(zr, [reg, #offset]);
247 //
248 // however, we cannot rely on the polling page address load always
249 // directly preceding the read from the page. C1 does that but C2
250 // has to do the load and read as two independent instruction
251 // generation steps. that's because with a single macro sequence the
252 // generic C2 code can only add the oop map before the mov/adrp and
253 // the trap handler expects an oop map to be associated with the
254 // load. with the load scheuled as a prior step the oop map goes
255 // where it is needed.
256 //
257 // so all we can do here is check that marked instruction is a load
258 // word to zr
259 return is_ldrw_to_zr(address(this));
260 }
261
262 bool NativeInstruction::is_adrp_at(address instr) {
263 unsigned insn = *(unsigned*)instr;
264 return (Instruction_aarch64::extract(insn, 31, 24) & 0b10011111) == 0b10010000;
265 }
266
267 bool NativeInstruction::is_ldr_literal_at(address instr) {
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228 if (dest == (address) -1) {
229 dest = instruction_address();
230 }
231
232 move->set_data((uintptr_t) dest);
233 };
234
235 //-------------------------------------------------------------------
236
237 bool NativeInstruction::is_safepoint_poll() {
238 // a safepoint_poll is implemented in two steps as either
239 //
240 // adrp(reg, polling_page);
241 // ldr(zr, [reg, #offset]);
242 //
243 // or
244 //
245 // mov(reg, polling_page);
246 // ldr(zr, [reg, #offset]);
247 //
248 // or
249 //
250 // ldr(reg, [rthread, #offset]);
251 // ldr(zr, [reg, #offset]);
252 //
253 // however, we cannot rely on the polling page address load always
254 // directly preceding the read from the page. C1 does that but C2
255 // has to do the load and read as two independent instruction
256 // generation steps. that's because with a single macro sequence the
257 // generic C2 code can only add the oop map before the mov/adrp and
258 // the trap handler expects an oop map to be associated with the
259 // load. with the load scheuled as a prior step the oop map goes
260 // where it is needed.
261 //
262 // so all we can do here is check that marked instruction is a load
263 // word to zr
264 return is_ldrw_to_zr(address(this));
265 }
266
267 bool NativeInstruction::is_adrp_at(address instr) {
268 unsigned insn = *(unsigned*)instr;
269 return (Instruction_aarch64::extract(insn, 31, 24) & 0b10011111) == 0b10010000;
270 }
271
272 bool NativeInstruction::is_ldr_literal_at(address instr) {
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