1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "utilities/powerOfTwo.hpp"
32
33 // MacroAssembler extends Assembler by frequently used macros.
34 //
35 // Instructions for which a 'better' code sequence exists depending
36 // on arguments should also go in here.
37
38 class MacroAssembler: public Assembler {
39 friend class LIR_Assembler;
40
41 public:
42 using Assembler::mov;
43 using Assembler::movi;
44
45 protected:
46
47 // Support for VM calls
48 //
49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
50 // may customize this version by overriding it for its purposes (e.g., to save/restore
51 // additional registers when doing a VM call).
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments, // the number of arguments to pop after the call
55 Label *retaddr = NULL
56 );
57
58 virtual void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments, // the number of arguments to pop after the call
61 Label &retaddr) {
62 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
63 }
64
65 // This is the base routine called by the different versions of call_VM. The interpreter
66 // may customize this version by overriding it for its purposes (e.g., to save/restore
67 // additional registers when doing a VM call).
68 //
69 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
70 // returns the register which contains the thread upon return. If a thread register has been
71 // specified, the return value will correspond to that register. If no last_java_sp is specified
72 // (noreg) than rsp will be used instead.
73 virtual void call_VM_base( // returns the register containing the thread upon return
74 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
75 Register java_thread, // the thread if computed before ; use noreg otherwise
76 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
77 address entry_point, // the entry point
78 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
79 bool check_exceptions // whether to check for pending exceptions after return
80 );
81
82 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
83
84 enum KlassDecodeMode {
85 KlassDecodeNone,
86 KlassDecodeZero,
87 KlassDecodeXor,
88 KlassDecodeMovk
89 };
90
91 KlassDecodeMode klass_decode_mode();
92
93 private:
94 static KlassDecodeMode _klass_decode_mode;
95
96 public:
97 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
98
99 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
100 // The implementation is only non-empty for the InterpreterMacroAssembler,
101 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
102 virtual void check_and_handle_popframe(Register java_thread);
103 virtual void check_and_handle_earlyret(Register java_thread);
104
105 void safepoint_poll(Label& slow_path);
106 void safepoint_poll_acquire(Label& slow_path);
107
108 // Biased locking support
109 // lock_reg and obj_reg must be loaded up with the appropriate values.
110 // swap_reg is killed.
111 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
112 // Optional slow case is for implementations (interpreter and C1) which branch to
113 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
114 // Returns offset of first potentially-faulting instruction for null
115 // check info (currently consumed only by C1). If
116 // swap_reg_contains_mark is true then returns -1 as it is assumed
117 // the calling code has already passed any potential faults.
118 int biased_locking_enter(Register lock_reg, Register obj_reg,
119 Register swap_reg, Register tmp_reg,
120 bool swap_reg_contains_mark,
121 Label& done, Label* slow_case = NULL,
122 BiasedLockingCounters* counters = NULL);
123 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
124
125
126 // Helper functions for statistics gathering.
127 // Unconditional atomic increment.
128 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
129 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
130 lea(tmp1, counter_addr);
131 atomic_incw(tmp1, tmp2, tmp3);
132 }
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 code_section()->relocate(inst_mark(), a.rspec());
137 a.lea(this, r);
138 }
139
140 /* Sometimes we get misaligned loads and stores, usually from Unsafe
141 accesses, and these can exceed the offset range. */
142 Address legitimize_address(const Address &a, int size, Register scratch) {
143 if (a.getMode() == Address::base_plus_offset) {
144 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
145 block_comment("legitimize_address {");
146 lea(scratch, a);
147 block_comment("} legitimize_address");
148 return Address(scratch);
149 }
150 }
151 return a;
152 }
153
154 void addmw(Address a, Register incr, Register scratch) {
155 ldrw(scratch, a);
156 addw(scratch, scratch, incr);
157 strw(scratch, a);
158 }
159
160 // Add constant to memory word
161 void addmw(Address a, int imm, Register scratch) {
162 ldrw(scratch, a);
163 if (imm > 0)
164 addw(scratch, scratch, (unsigned)imm);
165 else
166 subw(scratch, scratch, (unsigned)-imm);
167 strw(scratch, a);
168 }
169
170 void bind(Label& L) {
171 Assembler::bind(L);
172 code()->clear_last_insn();
173 }
174
175 void membar(Membar_mask_bits order_constraint);
176
177 using Assembler::ldr;
178 using Assembler::str;
179 using Assembler::ldrw;
180 using Assembler::strw;
181
182 void ldr(Register Rx, const Address &adr);
183 void ldrw(Register Rw, const Address &adr);
184 void str(Register Rx, const Address &adr);
185 void strw(Register Rx, const Address &adr);
186
187 // Frame creation and destruction shared between JITs.
188 void build_frame(int framesize);
189 void remove_frame(int framesize);
190
191 virtual void _call_Unimplemented(address call_site) {
192 mov(rscratch2, call_site);
193 }
194
195 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
196
197 // aliases defined in AARCH64 spec
198
199 template<class T>
200 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
201
202 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
203 inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
204
205 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
206 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
207
208 void cset(Register Rd, Assembler::Condition cond) {
209 csinc(Rd, zr, zr, ~cond);
210 }
211 void csetw(Register Rd, Assembler::Condition cond) {
212 csincw(Rd, zr, zr, ~cond);
213 }
214
215 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
216 csneg(Rd, Rn, Rn, ~cond);
217 }
218 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
219 csnegw(Rd, Rn, Rn, ~cond);
220 }
221
222 inline void movw(Register Rd, Register Rn) {
223 if (Rd == sp || Rn == sp) {
224 addw(Rd, Rn, 0U);
225 } else {
226 orrw(Rd, zr, Rn);
227 }
228 }
229 inline void mov(Register Rd, Register Rn) {
230 assert(Rd != r31_sp && Rn != r31_sp, "should be");
231 if (Rd == Rn) {
232 } else if (Rd == sp || Rn == sp) {
233 add(Rd, Rn, 0U);
234 } else {
235 orr(Rd, zr, Rn);
236 }
237 }
238
239 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
240 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
241
242 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
243 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
244
245 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
246 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
247
248 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
250 }
251 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
253 }
254
255 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 bfmw(Rd, Rn, lsb, (lsb + width - 1));
257 }
258 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
259 bfm(Rd, Rn, lsb , (lsb + width - 1));
260 }
261
262 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
264 }
265 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
267 }
268
269 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
271 }
272 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 sbfm(Rd, Rn, lsb , (lsb + width - 1));
274 }
275
276 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
278 }
279 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
281 }
282
283 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
285 }
286 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 ubfm(Rd, Rn, lsb , (lsb + width - 1));
288 }
289
290 inline void asrw(Register Rd, Register Rn, unsigned imm) {
291 sbfmw(Rd, Rn, imm, 31);
292 }
293
294 inline void asr(Register Rd, Register Rn, unsigned imm) {
295 sbfm(Rd, Rn, imm, 63);
296 }
297
298 inline void lslw(Register Rd, Register Rn, unsigned imm) {
299 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
300 }
301
302 inline void lsl(Register Rd, Register Rn, unsigned imm) {
303 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
304 }
305
306 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
307 ubfmw(Rd, Rn, imm, 31);
308 }
309
310 inline void lsr(Register Rd, Register Rn, unsigned imm) {
311 ubfm(Rd, Rn, imm, 63);
312 }
313
314 inline void rorw(Register Rd, Register Rn, unsigned imm) {
315 extrw(Rd, Rn, Rn, imm);
316 }
317
318 inline void ror(Register Rd, Register Rn, unsigned imm) {
319 extr(Rd, Rn, Rn, imm);
320 }
321
322 inline void sxtbw(Register Rd, Register Rn) {
323 sbfmw(Rd, Rn, 0, 7);
324 }
325 inline void sxthw(Register Rd, Register Rn) {
326 sbfmw(Rd, Rn, 0, 15);
327 }
328 inline void sxtb(Register Rd, Register Rn) {
329 sbfm(Rd, Rn, 0, 7);
330 }
331 inline void sxth(Register Rd, Register Rn) {
332 sbfm(Rd, Rn, 0, 15);
333 }
334 inline void sxtw(Register Rd, Register Rn) {
335 sbfm(Rd, Rn, 0, 31);
336 }
337
338 inline void uxtbw(Register Rd, Register Rn) {
339 ubfmw(Rd, Rn, 0, 7);
340 }
341 inline void uxthw(Register Rd, Register Rn) {
342 ubfmw(Rd, Rn, 0, 15);
343 }
344 inline void uxtb(Register Rd, Register Rn) {
345 ubfm(Rd, Rn, 0, 7);
346 }
347 inline void uxth(Register Rd, Register Rn) {
348 ubfm(Rd, Rn, 0, 15);
349 }
350 inline void uxtw(Register Rd, Register Rn) {
351 ubfm(Rd, Rn, 0, 31);
352 }
353
354 inline void cmnw(Register Rn, Register Rm) {
355 addsw(zr, Rn, Rm);
356 }
357 inline void cmn(Register Rn, Register Rm) {
358 adds(zr, Rn, Rm);
359 }
360
361 inline void cmpw(Register Rn, Register Rm) {
362 subsw(zr, Rn, Rm);
363 }
364 inline void cmp(Register Rn, Register Rm) {
365 subs(zr, Rn, Rm);
366 }
367
368 inline void negw(Register Rd, Register Rn) {
369 subw(Rd, zr, Rn);
370 }
371
372 inline void neg(Register Rd, Register Rn) {
373 sub(Rd, zr, Rn);
374 }
375
376 inline void negsw(Register Rd, Register Rn) {
377 subsw(Rd, zr, Rn);
378 }
379
380 inline void negs(Register Rd, Register Rn) {
381 subs(Rd, zr, Rn);
382 }
383
384 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
385 addsw(zr, Rn, Rm, kind, shift);
386 }
387 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
388 adds(zr, Rn, Rm, kind, shift);
389 }
390
391 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
392 subsw(zr, Rn, Rm, kind, shift);
393 }
394 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
395 subs(zr, Rn, Rm, kind, shift);
396 }
397
398 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
399 subw(Rd, zr, Rn, kind, shift);
400 }
401
402 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
403 sub(Rd, zr, Rn, kind, shift);
404 }
405
406 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
407 subsw(Rd, zr, Rn, kind, shift);
408 }
409
410 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
411 subs(Rd, zr, Rn, kind, shift);
412 }
413
414 inline void mnegw(Register Rd, Register Rn, Register Rm) {
415 msubw(Rd, Rn, Rm, zr);
416 }
417 inline void mneg(Register Rd, Register Rn, Register Rm) {
418 msub(Rd, Rn, Rm, zr);
419 }
420
421 inline void mulw(Register Rd, Register Rn, Register Rm) {
422 maddw(Rd, Rn, Rm, zr);
423 }
424 inline void mul(Register Rd, Register Rn, Register Rm) {
425 madd(Rd, Rn, Rm, zr);
426 }
427
428 inline void smnegl(Register Rd, Register Rn, Register Rm) {
429 smsubl(Rd, Rn, Rm, zr);
430 }
431 inline void smull(Register Rd, Register Rn, Register Rm) {
432 smaddl(Rd, Rn, Rm, zr);
433 }
434
435 inline void umnegl(Register Rd, Register Rn, Register Rm) {
436 umsubl(Rd, Rn, Rm, zr);
437 }
438 inline void umull(Register Rd, Register Rn, Register Rm) {
439 umaddl(Rd, Rn, Rm, zr);
440 }
441
442 #define WRAP(INSN) \
443 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
444 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
445 nop(); \
446 Assembler::INSN(Rd, Rn, Rm, Ra); \
447 }
448
449 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
450 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
451 #undef WRAP
452
453
454 // macro assembly operations needed for aarch64
455
456 // first two private routines for loading 32 bit or 64 bit constants
457 private:
458
459 void mov_immediate64(Register dst, u_int64_t imm64);
460 void mov_immediate32(Register dst, u_int32_t imm32);
461
462 int push(unsigned int bitset, Register stack);
463 int pop(unsigned int bitset, Register stack);
464
465 int push_fp(unsigned int bitset, Register stack);
466 int pop_fp(unsigned int bitset, Register stack);
467
468 void mov(Register dst, Address a);
469
470 public:
471 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
472 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
473
474 void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
475 void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
476
477 // Push and pop everything that might be clobbered by a native
478 // runtime call except rscratch1 and rscratch2. (They are always
479 // scratch, so we don't have to protect them.) Only save the lower
480 // 64 bits of each vector register.
481 void push_call_clobbered_registers();
482 void pop_call_clobbered_registers();
483
484 // now mov instructions for loading absolute addresses and 32 or
485 // 64 bit integers
486
487 inline void mov(Register dst, address addr)
488 {
489 mov_immediate64(dst, (u_int64_t)addr);
490 }
491
492 inline void mov(Register dst, u_int64_t imm64)
493 {
494 mov_immediate64(dst, imm64);
495 }
496
497 inline void movw(Register dst, u_int32_t imm32)
498 {
499 mov_immediate32(dst, imm32);
500 }
501
502 inline void mov(Register dst, long l)
503 {
504 mov(dst, (u_int64_t)l);
505 }
506
507 inline void mov(Register dst, int i)
508 {
509 mov(dst, (long)i);
510 }
511
512 void mov(Register dst, RegisterOrConstant src) {
513 if (src.is_register())
514 mov(dst, src.as_register());
515 else
516 mov(dst, src.as_constant());
517 }
518
519 void movptr(Register r, uintptr_t imm64);
520
521 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
522
523 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
524 orr(Vd, T, Vn, Vn);
525 }
526
527 public:
528
529 // Generalized Test Bit And Branch, including a "far" variety which
530 // spans more than 32KiB.
531 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
532 assert(cond == EQ || cond == NE, "must be");
533
534 if (far)
535 cond = ~cond;
536
537 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
538 if (cond == Assembler::EQ)
539 branch = &Assembler::tbz;
540 else
541 branch = &Assembler::tbnz;
542
543 if (far) {
544 Label L;
545 (this->*branch)(Rt, bitpos, L);
546 b(dest);
547 bind(L);
548 } else {
549 (this->*branch)(Rt, bitpos, dest);
550 }
551 }
552
553 // macro instructions for accessing and updating floating point
554 // status register
555 //
556 // FPSR : op1 == 011
557 // CRn == 0100
558 // CRm == 0100
559 // op2 == 001
560
561 inline void get_fpsr(Register reg)
562 {
563 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
564 }
565
566 inline void set_fpsr(Register reg)
567 {
568 msr(0b011, 0b0100, 0b0100, 0b001, reg);
569 }
570
571 inline void clear_fpsr()
572 {
573 msr(0b011, 0b0100, 0b0100, 0b001, zr);
574 }
575
576 // DCZID_EL0: op1 == 011
577 // CRn == 0000
578 // CRm == 0000
579 // op2 == 111
580 inline void get_dczid_el0(Register reg)
581 {
582 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
583 }
584
585 // CTR_EL0: op1 == 011
586 // CRn == 0000
587 // CRm == 0000
588 // op2 == 001
589 inline void get_ctr_el0(Register reg)
590 {
591 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
592 }
593
594 // idiv variant which deals with MINLONG as dividend and -1 as divisor
595 int corrected_idivl(Register result, Register ra, Register rb,
596 bool want_remainder, Register tmp = rscratch1);
597 int corrected_idivq(Register result, Register ra, Register rb,
598 bool want_remainder, Register tmp = rscratch1);
599
600 // Support for NULL-checks
601 //
602 // Generates code that causes a NULL OS exception if the content of reg is NULL.
603 // If the accessed location is M[reg + offset] and the offset is known, provide the
604 // offset. No explicit code generation is needed if the offset is within a certain
605 // range (0 <= offset <= page_size).
606
607 virtual void null_check(Register reg, int offset = -1);
608 static bool needs_explicit_null_check(intptr_t offset);
609 static bool uses_implicit_null_check(void* address);
610
611 static address target_addr_for_insn(address insn_addr, unsigned insn);
612 static address target_addr_for_insn(address insn_addr) {
613 unsigned insn = *(unsigned*)insn_addr;
614 return target_addr_for_insn(insn_addr, insn);
615 }
616
617 // Required platform-specific helpers for Label::patch_instructions.
618 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
619 static int pd_patch_instruction_size(address branch, address target);
620 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
621 pd_patch_instruction_size(branch, target);
622 }
623 static address pd_call_destination(address branch) {
624 return target_addr_for_insn(branch);
625 }
626 #ifndef PRODUCT
627 static void pd_print_patched_instruction(address branch);
628 #endif
629
630 static int patch_oop(address insn_addr, address o);
631 static int patch_narrow_klass(address insn_addr, narrowKlass n);
632
633 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
634 void emit_static_call_stub();
635
636 // The following 4 methods return the offset of the appropriate move instruction
637
638 // Support for fast byte/short loading with zero extension (depending on particular CPU)
639 int load_unsigned_byte(Register dst, Address src);
640 int load_unsigned_short(Register dst, Address src);
641
642 // Support for fast byte/short loading with sign extension (depending on particular CPU)
643 int load_signed_byte(Register dst, Address src);
644 int load_signed_short(Register dst, Address src);
645
646 int load_signed_byte32(Register dst, Address src);
647 int load_signed_short32(Register dst, Address src);
648
649 // Support for sign-extension (hi:lo = extend_sign(lo))
650 void extend_sign(Register hi, Register lo);
651
652 // Load and store values by size and signed-ness
653 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
654 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
655
656 // Support for inc/dec with optimal instruction selection depending on value
657
658 // x86_64 aliases an unqualified register/address increment and
659 // decrement to call incrementq and decrementq but also supports
660 // explicitly sized calls to incrementq/decrementq or
661 // incrementl/decrementl
662
663 // for aarch64 the proper convention would be to use
664 // increment/decrement for 64 bit operatons and
665 // incrementw/decrementw for 32 bit operations. so when porting
666 // x86_64 code we can leave calls to increment/decrement as is,
667 // replace incrementq/decrementq with increment/decrement and
668 // replace incrementl/decrementl with incrementw/decrementw.
669
670 // n.b. increment/decrement calls with an Address destination will
671 // need to use a scratch register to load the value to be
672 // incremented. increment/decrement calls which add or subtract a
673 // constant value greater than 2^12 will need to use a 2nd scratch
674 // register to hold the constant. so, a register increment/decrement
675 // may trash rscratch2 and an address increment/decrement trash
676 // rscratch and rscratch2
677
678 void decrementw(Address dst, int value = 1);
679 void decrementw(Register reg, int value = 1);
680
681 void decrement(Register reg, int value = 1);
682 void decrement(Address dst, int value = 1);
683
684 void incrementw(Address dst, int value = 1);
685 void incrementw(Register reg, int value = 1);
686
687 void increment(Register reg, int value = 1);
688 void increment(Address dst, int value = 1);
689
690
691 // Alignment
692 void align(int modulus);
693
694 // Stack frame creation/removal
695 void enter()
696 {
697 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
698 mov(rfp, sp);
699 }
700 void leave()
701 {
702 mov(sp, rfp);
703 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
704 }
705
706 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
707 // The pointer will be loaded into the thread register.
708 void get_thread(Register thread);
709
710
711 // Support for VM calls
712 //
713 // It is imperative that all calls into the VM are handled via the call_VM macros.
714 // They make sure that the stack linkage is setup correctly. call_VM's correspond
715 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
716
717
718 void call_VM(Register oop_result,
719 address entry_point,
720 bool check_exceptions = true);
721 void call_VM(Register oop_result,
722 address entry_point,
723 Register arg_1,
724 bool check_exceptions = true);
725 void call_VM(Register oop_result,
726 address entry_point,
727 Register arg_1, Register arg_2,
728 bool check_exceptions = true);
729 void call_VM(Register oop_result,
730 address entry_point,
731 Register arg_1, Register arg_2, Register arg_3,
732 bool check_exceptions = true);
733
734 // Overloadings with last_Java_sp
735 void call_VM(Register oop_result,
736 Register last_java_sp,
737 address entry_point,
738 int number_of_arguments = 0,
739 bool check_exceptions = true);
740 void call_VM(Register oop_result,
741 Register last_java_sp,
742 address entry_point,
743 Register arg_1, bool
744 check_exceptions = true);
745 void call_VM(Register oop_result,
746 Register last_java_sp,
747 address entry_point,
748 Register arg_1, Register arg_2,
749 bool check_exceptions = true);
750 void call_VM(Register oop_result,
751 Register last_java_sp,
752 address entry_point,
753 Register arg_1, Register arg_2, Register arg_3,
754 bool check_exceptions = true);
755
756 void get_vm_result (Register oop_result, Register thread);
757 void get_vm_result_2(Register metadata_result, Register thread);
758
759 // These always tightly bind to MacroAssembler::call_VM_base
760 // bypassing the virtual implementation
761 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
762 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
763 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
764 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
765 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
766
767 void call_VM_leaf(address entry_point,
768 int number_of_arguments = 0);
769 void call_VM_leaf(address entry_point,
770 Register arg_1);
771 void call_VM_leaf(address entry_point,
772 Register arg_1, Register arg_2);
773 void call_VM_leaf(address entry_point,
774 Register arg_1, Register arg_2, Register arg_3);
775
776 // These always tightly bind to MacroAssembler::call_VM_leaf_base
777 // bypassing the virtual implementation
778 void super_call_VM_leaf(address entry_point);
779 void super_call_VM_leaf(address entry_point, Register arg_1);
780 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
781 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
782 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
783
784 // last Java Frame (fills frame anchor)
785 void set_last_Java_frame(Register last_java_sp,
786 Register last_java_fp,
787 address last_java_pc,
788 Register scratch);
789
790 void set_last_Java_frame(Register last_java_sp,
791 Register last_java_fp,
792 Label &last_java_pc,
793 Register scratch);
794
795 void set_last_Java_frame(Register last_java_sp,
796 Register last_java_fp,
797 Register last_java_pc,
798 Register scratch);
799
800 void reset_last_Java_frame(Register thread);
801
802 // thread in the default location (rthread)
803 void reset_last_Java_frame(bool clear_fp);
804
805 // Stores
806 void store_check(Register obj); // store check for obj - register is destroyed afterwards
807 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
808
809 void resolve_jobject(Register value, Register thread, Register tmp);
810
811 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
812 void c2bool(Register x);
813
814 void load_method_holder_cld(Register rresult, Register rmethod);
815 void load_method_holder(Register holder, Register method);
816
817 // oop manipulations
818 void load_klass(Register dst, Register src);
819 void store_klass(Register dst, Register src);
820 void cmp_klass(Register oop, Register trial_klass, Register tmp);
821
822 void resolve_weak_handle(Register result, Register tmp);
823 void resolve_oop_handle(Register result, Register tmp = r5);
824 void load_mirror(Register dst, Register method, Register tmp = r5);
825
826 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
827 Register tmp1, Register tmp_thread);
828
829 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
830 Register tmp1, Register tmp_thread);
831
832 // Resolves obj for access. Result is placed in the same register.
833 // All other registers are preserved.
834 void resolve(DecoratorSet decorators, Register obj);
835
836 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
837 Register thread_tmp = noreg, DecoratorSet decorators = 0);
838
839 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
840 Register thread_tmp = noreg, DecoratorSet decorators = 0);
841 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
842 Register tmp_thread = noreg, DecoratorSet decorators = 0);
843
844 // currently unimplemented
845 // Used for storing NULL. All other oop constants should be
846 // stored using routines that take a jobject.
847 void store_heap_oop_null(Address dst);
848
849 void load_prototype_header(Register dst, Register src);
850
851 void store_klass_gap(Register dst, Register src);
852
853 // This dummy is to prevent a call to store_heap_oop from
854 // converting a zero (like NULL) into a Register by giving
855 // the compiler two choices it can't resolve
856
857 void store_heap_oop(Address dst, void* dummy);
858
859 void encode_heap_oop(Register d, Register s);
860 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
861 void decode_heap_oop(Register d, Register s);
862 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
863 void encode_heap_oop_not_null(Register r);
864 void decode_heap_oop_not_null(Register r);
865 void encode_heap_oop_not_null(Register dst, Register src);
866 void decode_heap_oop_not_null(Register dst, Register src);
867
868 void set_narrow_oop(Register dst, jobject obj);
869
870 void encode_klass_not_null(Register r);
871 void decode_klass_not_null(Register r);
872 void encode_klass_not_null(Register dst, Register src);
873 void decode_klass_not_null(Register dst, Register src);
874
875 void set_narrow_klass(Register dst, Klass* k);
876
877 // if heap base register is used - reinit it with the correct value
878 void reinit_heapbase();
879
880 DEBUG_ONLY(void verify_heapbase(const char* msg);)
881
882 void push_CPU_state(bool save_vectors = false);
883 void pop_CPU_state(bool restore_vectors = false) ;
884
885 // Round up to a power of two
886 void round_to(Register reg, int modulus);
887
888 // allocation
889 void eden_allocate(
890 Register obj, // result: pointer to object after successful allocation
891 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
892 int con_size_in_bytes, // object size in bytes if known at compile time
893 Register t1, // temp register
894 Label& slow_case // continuation point if fast allocation fails
895 );
896 void tlab_allocate(
897 Register obj, // result: pointer to object after successful allocation
898 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
899 int con_size_in_bytes, // object size in bytes if known at compile time
900 Register t1, // temp register
901 Register t2, // temp register
902 Label& slow_case // continuation point if fast allocation fails
903 );
904 void zero_memory(Register addr, Register len, Register t1);
905 void verify_tlab();
906
907 // interface method calling
908 void lookup_interface_method(Register recv_klass,
909 Register intf_klass,
910 RegisterOrConstant itable_index,
911 Register method_result,
912 Register scan_temp,
913 Label& no_such_interface,
914 bool return_method = true);
915
916 // virtual method calling
917 // n.b. x86 allows RegisterOrConstant for vtable_index
918 void lookup_virtual_method(Register recv_klass,
919 RegisterOrConstant vtable_index,
920 Register method_result);
921
922 // Test sub_klass against super_klass, with fast and slow paths.
923
924 // The fast path produces a tri-state answer: yes / no / maybe-slow.
925 // One of the three labels can be NULL, meaning take the fall-through.
926 // If super_check_offset is -1, the value is loaded up from super_klass.
927 // No registers are killed, except temp_reg.
928 void check_klass_subtype_fast_path(Register sub_klass,
929 Register super_klass,
930 Register temp_reg,
931 Label* L_success,
932 Label* L_failure,
933 Label* L_slow_path,
934 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
935
936 // The rest of the type check; must be wired to a corresponding fast path.
937 // It does not repeat the fast path logic, so don't use it standalone.
938 // The temp_reg and temp2_reg can be noreg, if no temps are available.
939 // Updates the sub's secondary super cache as necessary.
940 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
941 void check_klass_subtype_slow_path(Register sub_klass,
942 Register super_klass,
943 Register temp_reg,
944 Register temp2_reg,
945 Label* L_success,
946 Label* L_failure,
947 bool set_cond_codes = false);
948
949 // Simplified, combined version, good for typical uses.
950 // Falls through on failure.
951 void check_klass_subtype(Register sub_klass,
952 Register super_klass,
953 Register temp_reg,
954 Label& L_success);
955
956 void clinit_barrier(Register klass,
957 Register thread,
958 Label* L_fast_path = NULL,
959 Label* L_slow_path = NULL);
960
961 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
962
963
964 // Debugging
965
966 // only if +VerifyOops
967 void verify_oop(Register reg, const char* s = "broken oop");
968 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
969
970 // TODO: verify method and klass metadata (compare against vptr?)
971 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
972 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
973
974 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
975 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
976
977 // only if +VerifyFPU
978 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
979
980 // prints msg, dumps registers and stops execution
981 void stop(const char* msg);
982
983 // prints msg and continues
984 void warn(const char* msg);
985
986 static void debug64(char* msg, int64_t pc, int64_t regs[]);
987
988 void untested() { stop("untested"); }
989
990 void unimplemented(const char* what = "");
991
992 void should_not_reach_here() { stop("should not reach here"); }
993
994 // Stack overflow checking
995 void bang_stack_with_offset(int offset) {
996 // stack grows down, caller passes positive offset
997 assert(offset > 0, "must bang with negative offset");
998 sub(rscratch2, sp, offset);
999 str(zr, Address(rscratch2));
1000 }
1001
1002 // Writes to stack successive pages until offset reached to check for
1003 // stack overflow + shadow pages. Also, clobbers tmp
1004 void bang_stack_size(Register size, Register tmp);
1005
1006 // Check for reserved stack access in method being exited (for JIT)
1007 void reserved_stack_check();
1008
1009 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1010 Register tmp,
1011 int offset);
1012
1013 // Arithmetics
1014
1015 void addptr(const Address &dst, int32_t src);
1016 void cmpptr(Register src1, Address src2);
1017
1018 void cmpoop(Register obj1, Register obj2);
1019
1020 // Various forms of CAS
1021
1022 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1023 Label &suceed, Label *fail);
1024 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1025 Label &suceed, Label *fail);
1026
1027 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1028 Label &suceed, Label *fail);
1029
1030 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1031 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1032 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1033 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1034
1035 void atomic_xchg(Register prev, Register newv, Register addr);
1036 void atomic_xchgw(Register prev, Register newv, Register addr);
1037 void atomic_xchgal(Register prev, Register newv, Register addr);
1038 void atomic_xchgalw(Register prev, Register newv, Register addr);
1039
1040 void orptr(Address adr, RegisterOrConstant src) {
1041 ldr(rscratch1, adr);
1042 if (src.is_register())
1043 orr(rscratch1, rscratch1, src.as_register());
1044 else
1045 orr(rscratch1, rscratch1, src.as_constant());
1046 str(rscratch1, adr);
1047 }
1048
1049 // A generic CAS; success or failure is in the EQ flag.
1050 // Clobbers rscratch1
1051 void cmpxchg(Register addr, Register expected, Register new_val,
1052 enum operand_size size,
1053 bool acquire, bool release, bool weak,
1054 Register result);
1055 private:
1056 void compare_eq(Register rn, Register rm, enum operand_size size);
1057
1058 public:
1059 // Calls
1060
1061 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1062
1063 static bool far_branches() {
1064 return ReservedCodeCacheSize > branch_range || UseAOT;
1065 }
1066
1067 // Jumps that can reach anywhere in the code cache.
1068 // Trashes tmp.
1069 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1070 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1071
1072 static int far_branch_size() {
1073 if (far_branches()) {
1074 return 3 * 4; // adrp, add, br
1075 } else {
1076 return 4;
1077 }
1078 }
1079
1080 // Emit the CompiledIC call idiom
1081 address ic_call(address entry, jint method_index = 0);
1082
1083 public:
1084
1085 // Data
1086
1087 void mov_metadata(Register dst, Metadata* obj);
1088 Address allocate_metadata_address(Metadata* obj);
1089 Address constant_oop_address(jobject obj);
1090
1091 void movoop(Register dst, jobject obj, bool immediate = false);
1092
1093 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1094 void kernel_crc32(Register crc, Register buf, Register len,
1095 Register table0, Register table1, Register table2, Register table3,
1096 Register tmp, Register tmp2, Register tmp3);
1097 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1098 void kernel_crc32c(Register crc, Register buf, Register len,
1099 Register table0, Register table1, Register table2, Register table3,
1100 Register tmp, Register tmp2, Register tmp3);
1101
1102 // Stack push and pop individual 64 bit registers
1103 void push(Register src);
1104 void pop(Register dst);
1105
1106 // push all registers onto the stack
1107 void pusha();
1108 void popa();
1109
1110 void repne_scan(Register addr, Register value, Register count,
1111 Register scratch);
1112 void repne_scanw(Register addr, Register value, Register count,
1113 Register scratch);
1114
1115 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1116 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1117
1118 // If a constant does not fit in an immediate field, generate some
1119 // number of MOV instructions and then perform the operation
1120 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1121 add_sub_imm_insn insn1,
1122 add_sub_reg_insn insn2);
1123 // Seperate vsn which sets the flags
1124 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1125 add_sub_imm_insn insn1,
1126 add_sub_reg_insn insn2);
1127
1128 #define WRAP(INSN) \
1129 void INSN(Register Rd, Register Rn, unsigned imm) { \
1130 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1131 } \
1132 \
1133 void INSN(Register Rd, Register Rn, Register Rm, \
1134 enum shift_kind kind, unsigned shift = 0) { \
1135 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1136 } \
1137 \
1138 void INSN(Register Rd, Register Rn, Register Rm) { \
1139 Assembler::INSN(Rd, Rn, Rm); \
1140 } \
1141 \
1142 void INSN(Register Rd, Register Rn, Register Rm, \
1143 ext::operation option, int amount = 0) { \
1144 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1145 }
1146
1147 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1148
1149 #undef WRAP
1150 #define WRAP(INSN) \
1151 void INSN(Register Rd, Register Rn, unsigned imm) { \
1152 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1153 } \
1154 \
1155 void INSN(Register Rd, Register Rn, Register Rm, \
1156 enum shift_kind kind, unsigned shift = 0) { \
1157 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1158 } \
1159 \
1160 void INSN(Register Rd, Register Rn, Register Rm) { \
1161 Assembler::INSN(Rd, Rn, Rm); \
1162 } \
1163 \
1164 void INSN(Register Rd, Register Rn, Register Rm, \
1165 ext::operation option, int amount = 0) { \
1166 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1167 }
1168
1169 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1170
1171 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1172 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1173 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1174 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1175
1176 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1177
1178 void tableswitch(Register index, jint lowbound, jint highbound,
1179 Label &jumptable, Label &jumptable_end, int stride = 1) {
1180 adr(rscratch1, jumptable);
1181 subsw(rscratch2, index, lowbound);
1182 subsw(zr, rscratch2, highbound - lowbound);
1183 br(Assembler::HS, jumptable_end);
1184 add(rscratch1, rscratch1, rscratch2,
1185 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1186 br(rscratch1);
1187 }
1188
1189 // Form an address from base + offset in Rd. Rd may or may not
1190 // actually be used: you must use the Address that is returned. It
1191 // is up to you to ensure that the shift provided matches the size
1192 // of your data.
1193 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1194
1195 // Return true iff an address is within the 48-bit AArch64 address
1196 // space.
1197 bool is_valid_AArch64_address(address a) {
1198 return ((uint64_t)a >> 48) == 0;
1199 }
1200
1201 // Load the base of the cardtable byte map into reg.
1202 void load_byte_map_base(Register reg);
1203
1204 // Prolog generator routines to support switch between x86 code and
1205 // generated ARM code
1206
1207 // routine to generate an x86 prolog for a stub function which
1208 // bootstraps into the generated ARM code which directly follows the
1209 // stub
1210 //
1211
1212 public:
1213
1214 void ldr_constant(Register dest, const Address &const_addr) {
1215 if (NearCpool) {
1216 ldr(dest, const_addr);
1217 } else {
1218 unsigned long offset;
1219 adrp(dest, InternalAddress(const_addr.target()), offset);
1220 ldr(dest, Address(dest, offset));
1221 }
1222 }
1223
1224 address read_polling_page(Register r, relocInfo::relocType rtype);
1225 void get_polling_page(Register dest, relocInfo::relocType rtype);
1226 address fetch_and_read_polling_page(Register r, relocInfo::relocType rtype);
1227
1228 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1229 void update_byte_crc32(Register crc, Register val, Register table);
1230 void update_word_crc32(Register crc, Register v, Register tmp,
1231 Register table0, Register table1, Register table2, Register table3,
1232 bool upper = false);
1233
1234 void has_negatives(Register ary1, Register len, Register result);
1235
1236 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1237 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1238
1239 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1240 int elem_size);
1241
1242 void fill_words(Register base, Register cnt, Register value);
1243 void zero_words(Register base, u_int64_t cnt);
1244 void zero_words(Register ptr, Register cnt);
1245 void zero_dcache_blocks(Register base, Register cnt);
1246
1247 static const int zero_words_block_size;
1248
1249 void byte_array_inflate(Register src, Register dst, Register len,
1250 FloatRegister vtmp1, FloatRegister vtmp2,
1251 FloatRegister vtmp3, Register tmp4);
1252
1253 void char_array_compress(Register src, Register dst, Register len,
1254 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1255 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1256 Register result);
1257
1258 void encode_iso_array(Register src, Register dst,
1259 Register len, Register result,
1260 FloatRegister Vtmp1, FloatRegister Vtmp2,
1261 FloatRegister Vtmp3, FloatRegister Vtmp4);
1262 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1263 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1264 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1265 FloatRegister tmpC4, Register tmp1, Register tmp2,
1266 Register tmp3, Register tmp4, Register tmp5);
1267 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1268 address pio2, address dsin_coef, address dcos_coef);
1269 private:
1270 // begin trigonometric functions support block
1271 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1272 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1273 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1274 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1275 // end trigonometric functions support block
1276 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1277 Register src1, Register src2);
1278 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1279 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1280 }
1281 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1282 Register y, Register y_idx, Register z,
1283 Register carry, Register product,
1284 Register idx, Register kdx);
1285 void multiply_128_x_128_loop(Register y, Register z,
1286 Register carry, Register carry2,
1287 Register idx, Register jdx,
1288 Register yz_idx1, Register yz_idx2,
1289 Register tmp, Register tmp3, Register tmp4,
1290 Register tmp7, Register product_hi);
1291 void kernel_crc32_using_crc32(Register crc, Register buf,
1292 Register len, Register tmp0, Register tmp1, Register tmp2,
1293 Register tmp3);
1294 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1295 Register len, Register tmp0, Register tmp1, Register tmp2,
1296 Register tmp3);
1297 public:
1298 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1299 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1300 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1301 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1302 // ISB may be needed because of a safepoint
1303 void maybe_isb() { isb(); }
1304
1305 private:
1306 // Return the effective address r + (r1 << ext) + offset.
1307 // Uses rscratch2.
1308 Address offsetted_address(Register r, Register r1, Address::extend ext,
1309 int offset, int size);
1310
1311 private:
1312 // Returns an address on the stack which is reachable with a ldr/str of size
1313 // Uses rscratch2 if the address is not directly reachable
1314 Address spill_address(int size, int offset, Register tmp=rscratch2);
1315
1316 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1317
1318 // Check whether two loads/stores can be merged into ldp/stp.
1319 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1320
1321 // Merge current load/store with previous load/store into ldp/stp.
1322 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1323
1324 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1325 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1326
1327 public:
1328 void spill(Register Rx, bool is64, int offset) {
1329 if (is64) {
1330 str(Rx, spill_address(8, offset));
1331 } else {
1332 strw(Rx, spill_address(4, offset));
1333 }
1334 }
1335 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1336 str(Vx, T, spill_address(1 << (int)T, offset));
1337 }
1338 void unspill(Register Rx, bool is64, int offset) {
1339 if (is64) {
1340 ldr(Rx, spill_address(8, offset));
1341 } else {
1342 ldrw(Rx, spill_address(4, offset));
1343 }
1344 }
1345 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1346 ldr(Vx, T, spill_address(1 << (int)T, offset));
1347 }
1348 void spill_copy128(int src_offset, int dst_offset,
1349 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1350 if (src_offset < 512 && (src_offset & 7) == 0 &&
1351 dst_offset < 512 && (dst_offset & 7) == 0) {
1352 ldp(tmp1, tmp2, Address(sp, src_offset));
1353 stp(tmp1, tmp2, Address(sp, dst_offset));
1354 } else {
1355 unspill(tmp1, true, src_offset);
1356 spill(tmp1, true, dst_offset);
1357 unspill(tmp1, true, src_offset+8);
1358 spill(tmp1, true, dst_offset+8);
1359 }
1360 }
1361
1362 void cache_wb(Address line);
1363 void cache_wbsync(bool is_pre);
1364 };
1365
1366 #ifdef ASSERT
1367 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1368 #endif
1369
1370 /**
1371 * class SkipIfEqual:
1372 *
1373 * Instantiating this class will result in assembly code being output that will
1374 * jump around any code emitted between the creation of the instance and it's
1375 * automatic destruction at the end of a scope block, depending on the value of
1376 * the flag passed to the constructor, which will be checked at run-time.
1377 */
1378 class SkipIfEqual {
1379 private:
1380 MacroAssembler* _masm;
1381 Label _label;
1382
1383 public:
1384 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1385 ~SkipIfEqual();
1386 };
1387
1388 struct tableswitch {
1389 Register _reg;
1390 int _insn_index; jint _first_key; jint _last_key;
1391 Label _after;
1392 Label _branches;
1393 };
1394
1395 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP