50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #ifdef ARM
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef ARM
151 assert(disp() == 0 || index()->is_illegal(), "can't have both");
152 // Note: offsets higher than 4096 must not be rejected here. They can
153 // be handled by the back-end or will be rejected if not.
154 #endif
155 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand");
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
159 "wrong type for addresses");
160 #else
161 assert(base()->is_single_cpu(), "wrong base operand");
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
164 "wrong type for addresses");
165 #endif
166 }
167 #endif
168
169
170 //---------------------------------------------------
171
172 char LIR_OprDesc::type_char(BasicType t) {
173 switch (t) {
174 case T_ARRAY:
175 t = T_OBJECT;
176 case T_BOOLEAN:
177 case T_CHAR:
1555
1556 out->print("[");
1557 if (is_pointer()) {
1558 pointer()->print_value_on(out);
1559 } else if (is_single_stack()) {
1560 out->print("stack:%d", single_stack_ix());
1561 } else if (is_double_stack()) {
1562 out->print("dbl_stack:%d",double_stack_ix());
1563 } else if (is_virtual()) {
1564 out->print("R%d", vreg_number());
1565 } else if (is_single_cpu()) {
1566 out->print("%s", as_register()->name());
1567 } else if (is_double_cpu()) {
1568 out->print("%s", as_register_hi()->name());
1569 out->print("%s", as_register_lo()->name());
1570 #if defined(X86)
1571 } else if (is_single_xmm()) {
1572 out->print("%s", as_xmm_float_reg()->name());
1573 } else if (is_double_xmm()) {
1574 out->print("%s", as_xmm_double_reg()->name());
1575 } else if (is_single_fpu()) {
1576 out->print("fpu%d", fpu_regnr());
1577 } else if (is_double_fpu()) {
1578 out->print("fpu%d", fpu_regnrLo());
1579 #elif defined(ARM)
1580 } else if (is_single_fpu()) {
1581 out->print("s%d", fpu_regnr());
1582 } else if (is_double_fpu()) {
1583 out->print("d%d", fpu_regnrLo() >> 1);
1584 #else
1585 } else if (is_single_fpu()) {
1586 out->print("%s", as_float_reg()->name());
1587 } else if (is_double_fpu()) {
1588 out->print("%s", as_double_reg()->name());
1589 #endif
1590
1591 } else if (is_illegal()) {
1592 out->print("-");
1593 } else {
1594 out->print("Unknown Operand");
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50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #if defined(ARM) || defined (AARCH64)
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef ARM
151 assert(disp() == 0 || index()->is_illegal(), "can't have both");
152 // Note: offsets higher than 4096 must not be rejected here. They can
153 // be handled by the back-end or will be rejected if not.
154 #endif
155 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand");
157 #ifndef AARCH64
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #else
160 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
161 #endif
162 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
163 "wrong type for addresses");
164 #else
165 assert(base()->is_single_cpu(), "wrong base operand");
166 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
167 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
168 "wrong type for addresses");
169 #endif
170 }
171 #endif
172
173
174 //---------------------------------------------------
175
176 char LIR_OprDesc::type_char(BasicType t) {
177 switch (t) {
178 case T_ARRAY:
179 t = T_OBJECT;
180 case T_BOOLEAN:
181 case T_CHAR:
1559
1560 out->print("[");
1561 if (is_pointer()) {
1562 pointer()->print_value_on(out);
1563 } else if (is_single_stack()) {
1564 out->print("stack:%d", single_stack_ix());
1565 } else if (is_double_stack()) {
1566 out->print("dbl_stack:%d",double_stack_ix());
1567 } else if (is_virtual()) {
1568 out->print("R%d", vreg_number());
1569 } else if (is_single_cpu()) {
1570 out->print("%s", as_register()->name());
1571 } else if (is_double_cpu()) {
1572 out->print("%s", as_register_hi()->name());
1573 out->print("%s", as_register_lo()->name());
1574 #if defined(X86)
1575 } else if (is_single_xmm()) {
1576 out->print("%s", as_xmm_float_reg()->name());
1577 } else if (is_double_xmm()) {
1578 out->print("%s", as_xmm_double_reg()->name());
1579 } else if (is_single_fpu()) {
1580 out->print("fpu%d", fpu_regnr());
1581 } else if (is_double_fpu()) {
1582 out->print("fpu%d", fpu_regnrLo());
1583 #elif defined(AARCH64)
1584 } else if (is_single_fpu()) {
1585 out->print("fpu%d", fpu_regnr());
1586 } else if (is_double_fpu()) {
1587 out->print("fpu%d", fpu_regnrLo());
1588 #elif defined(ARM)
1589 } else if (is_single_fpu()) {
1590 out->print("s%d", fpu_regnr());
1591 } else if (is_double_fpu()) {
1592 out->print("d%d", fpu_regnrLo() >> 1);
1593 #else
1594 } else if (is_single_fpu()) {
1595 out->print("%s", as_float_reg()->name());
1596 } else if (is_double_fpu()) {
1597 out->print("%s", as_double_reg()->name());
1598 #endif
1599
1600 } else if (is_illegal()) {
1601 out->print("-");
1602 } else {
1603 out->print("Unknown Operand");
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