1 /*
2 * Copyright (c) 2014, Red Hat Inc.
3 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights
4 * reserved. DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE
5 * HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include <stdio.h>
28 #include <sys/types.h>
29
30 #include "precompiled.hpp"
31 #include "asm/assembler.hpp"
32 #include "asm/assembler.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34
35 #ifndef PRODUCT
36 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
37 #endif
38
39 #include "compiler/disassembler.hpp"
40 #include "memory/resourceArea.hpp"
41 #include "runtime/interfaceSupport.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 // for the moment we reuse the logical/floating point immediate encode
45 // and decode functiosn provided by the simulator. when we move to
46 // real hardware we will need to pull taht code into here
47
48 #include "immediate_aarch64.hpp"
49
50 // #include "gc_interface/collectedHeap.inline.hpp"
51 // #include "interpreter/interpreter.hpp"
52 // #include "memory/cardTableModRefBS.hpp"
53 // #include "prims/methodHandles.hpp"
54 // #include "runtime/biasedLocking.hpp"
55 // #include "runtime/interfaceSupport.hpp"
56 // #include "runtime/objectMonitor.hpp"
57 // #include "runtime/os.hpp"
58 // #include "runtime/sharedRuntime.hpp"
59 // #include "runtime/stubRoutines.hpp"
60 // #if INCLUDE_ALL_GCS
61 // #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
62 // #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
63 // #include "gc_implementation/g1/heapRegion.hpp"
64 // #endif
65
66 extern "C" void entry(CodeBuffer *cb);
67
68 #define __ _masm.
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #endif
74
75 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
76
77 static float unpack(unsigned value);
78
79 void entry(CodeBuffer *cb) {
80
81 // {
82 // for (int i = 0; i < 256; i+=16)
83 // {
84 // printf("\"%20.20g\", ", unpack(i));
85 // printf("\"%20.20g\", ", unpack(i+1));
86 // }
87 // printf("\n");
88 // }
89
90 Assembler _masm(cb);
91 address entry = __ pc();
92
93 // Smoke test for assembler
94
95 #ifdef ASSERT
96 // BEGIN Generated code -- do not edit
97 // Generated by aarch64-asmtest.py
98 Label back, forth;
99 __ bind(back);
100
101 // ArithOp
102 __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28
103 __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13
104 __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2
105 __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41
106 __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19
107 __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14
108 __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13
109 __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9
110 __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19
111 __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17
112 __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51
113 __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15
114 __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23
115 __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4
116 __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22
117 __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29
118 __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37
119 __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29
120 __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47
121 __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46
122 __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20
123 __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24
124 __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6
125 __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24
126
127 // AddSubImmOp
128 __ addw(r7, r19, 340u); // add w7, w19, #340
129 __ addsw(r8, r0, 401u); // adds w8, w0, #401
130 __ subw(r29, r20, 163u); // sub w29, w20, #163
131 __ subsw(r8, r23, 759u); // subs w8, w23, #759
132 __ add(r1, r12, 523u); // add x1, x12, #523
133 __ adds(r2, r11, 426u); // adds x2, x11, #426
134 __ sub(r14, r29, 716u); // sub x14, x29, #716
135 __ subs(r11, r5, 582u); // subs x11, x5, #582
136
137 // LogicalImmOp
138 __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000
139 __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0
140 __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0
141 __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80
142 __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000
143 __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000
144 __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0
145 __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc
146
147 // AbsOp
148 __ b(__ pc()); // b .
149 __ b(back); // b back
150 __ b(forth); // b forth
151 __ bl(__ pc()); // bl .
152 __ bl(back); // bl back
153 __ bl(forth); // bl forth
154
155 // RegAndAbsOp
156 __ cbzw(r12, __ pc()); // cbz w12, .
157 __ cbzw(r12, back); // cbz w12, back
158 __ cbzw(r12, forth); // cbz w12, forth
159 __ cbnzw(r20, __ pc()); // cbnz w20, .
160 __ cbnzw(r20, back); // cbnz w20, back
161 __ cbnzw(r20, forth); // cbnz w20, forth
162 __ cbz(r12, __ pc()); // cbz x12, .
163 __ cbz(r12, back); // cbz x12, back
164 __ cbz(r12, forth); // cbz x12, forth
165 __ cbnz(r24, __ pc()); // cbnz x24, .
166 __ cbnz(r24, back); // cbnz x24, back
167 __ cbnz(r24, forth); // cbnz x24, forth
168 __ adr(r6, __ pc()); // adr x6, .
169 __ adr(r6, back); // adr x6, back
170 __ adr(r6, forth); // adr x6, forth
171 __ _adrp(r21, __ pc()); // adrp x21, .
172
173 // RegImmAbsOp
174 __ tbz(r1, 1, __ pc()); // tbz x1, #1, .
175 __ tbz(r1, 1, back); // tbz x1, #1, back
176 __ tbz(r1, 1, forth); // tbz x1, #1, forth
177 __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, .
178 __ tbnz(r8, 9, back); // tbnz x8, #9, back
179 __ tbnz(r8, 9, forth); // tbnz x8, #9, forth
180
181 // MoveWideImmOp
182 __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0
183 __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16
184 __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0
185 __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48
186 __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0
187 __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16
188
189 // BitfieldOp
190 __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22
191 __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19
192 __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15
193 __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16
194 __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25
195 __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8
196
197 // ExtractOp
198 __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24
199 __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31
200
201 // CondBranchOp
202 __ br(Assembler::EQ, __ pc()); // b.EQ .
203 __ br(Assembler::EQ, back); // b.EQ back
204 __ br(Assembler::EQ, forth); // b.EQ forth
205 __ br(Assembler::NE, __ pc()); // b.NE .
206 __ br(Assembler::NE, back); // b.NE back
207 __ br(Assembler::NE, forth); // b.NE forth
208 __ br(Assembler::HS, __ pc()); // b.HS .
209 __ br(Assembler::HS, back); // b.HS back
210 __ br(Assembler::HS, forth); // b.HS forth
211 __ br(Assembler::CS, __ pc()); // b.CS .
212 __ br(Assembler::CS, back); // b.CS back
213 __ br(Assembler::CS, forth); // b.CS forth
214 __ br(Assembler::LO, __ pc()); // b.LO .
215 __ br(Assembler::LO, back); // b.LO back
216 __ br(Assembler::LO, forth); // b.LO forth
217 __ br(Assembler::CC, __ pc()); // b.CC .
218 __ br(Assembler::CC, back); // b.CC back
219 __ br(Assembler::CC, forth); // b.CC forth
220 __ br(Assembler::MI, __ pc()); // b.MI .
221 __ br(Assembler::MI, back); // b.MI back
222 __ br(Assembler::MI, forth); // b.MI forth
223 __ br(Assembler::PL, __ pc()); // b.PL .
224 __ br(Assembler::PL, back); // b.PL back
225 __ br(Assembler::PL, forth); // b.PL forth
226 __ br(Assembler::VS, __ pc()); // b.VS .
227 __ br(Assembler::VS, back); // b.VS back
228 __ br(Assembler::VS, forth); // b.VS forth
229 __ br(Assembler::VC, __ pc()); // b.VC .
230 __ br(Assembler::VC, back); // b.VC back
231 __ br(Assembler::VC, forth); // b.VC forth
232 __ br(Assembler::HI, __ pc()); // b.HI .
233 __ br(Assembler::HI, back); // b.HI back
234 __ br(Assembler::HI, forth); // b.HI forth
235 __ br(Assembler::LS, __ pc()); // b.LS .
236 __ br(Assembler::LS, back); // b.LS back
237 __ br(Assembler::LS, forth); // b.LS forth
238 __ br(Assembler::GE, __ pc()); // b.GE .
239 __ br(Assembler::GE, back); // b.GE back
240 __ br(Assembler::GE, forth); // b.GE forth
241 __ br(Assembler::LT, __ pc()); // b.LT .
242 __ br(Assembler::LT, back); // b.LT back
243 __ br(Assembler::LT, forth); // b.LT forth
244 __ br(Assembler::GT, __ pc()); // b.GT .
245 __ br(Assembler::GT, back); // b.GT back
246 __ br(Assembler::GT, forth); // b.GT forth
247 __ br(Assembler::LE, __ pc()); // b.LE .
248 __ br(Assembler::LE, back); // b.LE back
249 __ br(Assembler::LE, forth); // b.LE forth
250 __ br(Assembler::AL, __ pc()); // b.AL .
251 __ br(Assembler::AL, back); // b.AL back
252 __ br(Assembler::AL, forth); // b.AL forth
253 __ br(Assembler::NV, __ pc()); // b.NV .
254 __ br(Assembler::NV, back); // b.NV back
255 __ br(Assembler::NV, forth); // b.NV forth
256
257 // ImmOp
258 __ svc(12729); // svc #12729
259 __ hvc(6788); // hvc #6788
260 __ smc(1535); // smc #1535
261 __ brk(16766); // brk #16766
262 __ hlt(9753); // hlt #9753
263
264 // Op
265 __ nop(); // nop
266 __ eret(); // eret
267 __ drps(); // drps
268 __ isb(); // isb
269
270 // SystemOp
271 __ dsb(Assembler::SY); // dsb SY
272 __ dmb(Assembler::ISHST); // dmb ISHST
273
274 // OneRegOp
275 __ br(r2); // br x2
276 __ blr(r5); // blr x5
277
278 // LoadStoreExclusiveOp
279 __ stxr(r20, r21, r2); // stxr w20, x21, [x2]
280 __ stlxr(r7, r29, r7); // stlxr w7, x29, [x7]
281 __ ldxr(r5, r16); // ldxr x5, [x16]
282 __ ldaxr(r27, r29); // ldaxr x27, [x29]
283 __ stlr(r0, r29); // stlr x0, [x29]
284 __ ldar(r21, r28); // ldar x21, [x28]
285
286 // LoadStoreExclusiveOp
287 __ stxrw(r24, r24, r7); // stxr w24, w24, [x7]
288 __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28]
289 __ ldxrw(r21, r6); // ldxr w21, [x6]
290 __ ldaxrw(r15, r30); // ldaxr w15, [x30]
291 __ stlrw(r19, r3); // stlr w19, [x3]
292 __ ldarw(r22, r2); // ldar w22, [x2]
293
294 // LoadStoreExclusiveOp
295 __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0]
296 __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28]
297 __ ldxrh(r29, r6); // ldxrh w29, [x6]
298 __ ldaxrh(r18, r7); // ldaxrh w18, [x7]
299 __ stlrh(r25, r28); // stlrh w25, [x28]
300 __ ldarh(r2, r19); // ldarh w2, [x19]
301
302 // LoadStoreExclusiveOp
303 __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1]
304 __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22]
305 __ ldxrb(r25, r2); // ldxrb w25, [x2]
306 __ ldaxrb(r24, r5); // ldaxrb w24, [x5]
307 __ stlrb(r16, r3); // stlrb w16, [x3]
308 __ ldarb(r22, r29); // ldarb w22, [x29]
309
310 // LoadStoreExclusiveOp
311 __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19]
312 __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14]
313 __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5]
314 __ stlxp(r6, r8, r14, r6); // stlxp w6, x8, x14, [x6]
315
316 // LoadStoreExclusiveOp
317 __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
318 __ ldaxpw(r14, r14, r15); // ldaxp w14, w14, [x15]
319 __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10]
320 __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18]
321
322 // base_plus_unscaled_offset
323 // LoadStoreOp
324 __ str(r30, Address(r11, 99)); // str x30, [x11, 99]
325 __ strw(r23, Address(r25, -77)); // str w23, [x25, -77]
326 __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3]
327 __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5]
328 __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57]
329 __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78]
330 __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3]
331 __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47]
332 __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12]
333 __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14]
334 __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10]
335 __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91]
336 __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17]
337 __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10]
338 __ strd(v30, Address(r18, -223)); // str d30, [x18, -223]
339 __ strs(v13, Address(r22, 21)); // str s13, [x22, 21]
340
341 // pre
342 // LoadStoreOp
343 __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]!
344 __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]!
345 __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]!
346 __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]!
347 __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]!
348 __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]!
349 __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]!
350 __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]!
351 __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]!
352 __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]!
353 __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]!
354 __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]!
355 __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]!
356 __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]!
357 __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]!
358 __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]!
359
360 // post
361 // LoadStoreOp
362 __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37
363 __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19
364 __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1
365 __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6
366 __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230
367 __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27
368 __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25
369 __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32
370 __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4
371 __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25
372 __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62
373 __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51
374 __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48
375 __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10
376 __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222
377 __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41
378
379 // base_plus_reg
380 // LoadStoreOp
381 __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0]
382 __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0]
383 __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0]
384 __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1]
385 __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0]
386 __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2]
387 __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0]
388 __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1]
389 __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0]
390 __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1]
391 __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1]
392 __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0]
393 __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3]
394 __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2]
395 __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0]
396 __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0]
397
398 // base_plus_scaled_offset
399 // LoadStoreOp
400 __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256]
401 __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588]
402 __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866]
403 __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734]
404 __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224]
405 __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396]
406 __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721]
407 __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656]
408 __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887]
409 __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080]
410 __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916]
411 __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828]
412 __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032]
413 __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452]
414 __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992]
415 __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688]
416
417 // pcrel
418 // LoadStoreOp
419 __ ldr(r10, forth); // ldr x10, forth
420 __ ldrw(r3, __ pc()); // ldr w3, .
421
422 // LoadStoreOp
423 __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9]
424
425 // LoadStoreOp
426 __ prfm(back); // prfm PLDL1KEEP, back
427
428 // LoadStoreOp
429 __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0]
430
431 // LoadStoreOp
432 __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080]
433
434 // AddSubCarryOp
435 __ adcw(r13, r9, r28); // adc w13, w9, w28
436 __ adcsw(r27, r19, r28); // adcs w27, w19, w28
437 __ sbcw(r19, r18, r6); // sbc w19, w18, w6
438 __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3
439 __ adc(r16, r14, r8); // adc x16, x14, x8
440 __ adcs(r0, r29, r8); // adcs x0, x29, x8
441 __ sbc(r8, r24, r20); // sbc x8, x24, x20
442 __ sbcs(r12, r28, r0); // sbcs x12, x28, x0
443
444 // AddSubExtendedOp
445 __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4
446 __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2
447 __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1
448 __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3
449 __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3
450 __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2
451 __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1
452 __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4
453
454 // ConditionalCompareOp
455 __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE
456 __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI
457 __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE
458 __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS
459
460 // ConditionalCompareImmedOp
461 __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC
462 __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL
463 __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS
464 __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE
465
466 // ConditionalSelectOp
467 __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT
468 __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS
469 __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI
470 __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS
471 __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS
472 __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC
473 __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE
474 __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS
475
476 // TwoRegOp
477 __ rbitw(r0, r16); // rbit w0, w16
478 __ rev16w(r17, r23); // rev16 w17, w23
479 __ revw(r17, r14); // rev w17, w14
480 __ clzw(r24, r30); // clz w24, w30
481 __ clsw(r24, r22); // cls w24, w22
482 __ rbit(r3, r17); // rbit x3, x17
483 __ rev16(r12, r13); // rev16 x12, x13
484 __ rev32(r9, r22); // rev32 x9, x22
485 __ rev(r0, r0); // rev x0, x0
486 __ clz(r5, r16); // clz x5, x16
487 __ cls(r25, r22); // cls x25, x22
488
489 // ThreeRegOp
490 __ udivw(r29, r4, r0); // udiv w29, w4, w0
491 __ sdivw(r0, r29, r29); // sdiv w0, w29, w29
492 __ lslvw(r5, r17, r21); // lslv w5, w17, w21
493 __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18
494 __ asrvw(r1, r27, r8); // asrv w1, w27, w8
495 __ rorvw(r18, r20, r13); // rorv w18, w20, w13
496 __ udiv(r8, r25, r12); // udiv x8, x25, x12
497 __ sdiv(r7, r5, r28); // sdiv x7, x5, x28
498 __ lslv(r5, r17, r27); // lslv x5, x17, x27
499 __ lsrv(r23, r26, r20); // lsrv x23, x26, x20
500 __ asrv(r28, r8, r28); // asrv x28, x8, x28
501 __ rorv(r3, r29, r4); // rorv x3, x29, x4
502
503 // FourRegMulOp
504 __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21
505 __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11
506 __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28
507 __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8
508 __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8
509 __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19
510 __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24
511 __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5
512
513 // ThreeRegFloatOp
514 __ fmuls(v8, v18, v13); // fmul s8, s18, s13
515 __ fdivs(v2, v14, v28); // fdiv s2, s14, s28
516 __ fadds(v15, v12, v28); // fadd s15, s12, s28
517 __ fsubs(v0, v12, v1); // fsub s0, s12, s1
518 __ fmuls(v15, v29, v4); // fmul s15, s29, s4
519 __ fmuld(v12, v1, v23); // fmul d12, d1, d23
520 __ fdivd(v27, v8, v18); // fdiv d27, d8, d18
521 __ faddd(v23, v20, v11); // fadd d23, d20, d11
522 __ fsubd(v8, v12, v18); // fsub d8, d12, d18
523 __ fmuld(v26, v24, v23); // fmul d26, d24, d23
524
525 // FourRegFloatOp
526 __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25
527 __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14
528 __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30
529 __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22
530 __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5
531 __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10
532 __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1
533 __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0
534
535 // TwoRegFloatOp
536 __ fmovs(v25, v9); // fmov s25, s9
537 __ fabss(v20, v4); // fabs s20, s4
538 __ fnegs(v3, v27); // fneg s3, s27
539 __ fsqrts(v1, v2); // fsqrt s1, s2
540 __ fcvts(v30, v0); // fcvt d30, s0
541 __ fmovd(v12, v4); // fmov d12, d4
542 __ fabsd(v1, v27); // fabs d1, d27
543 __ fnegd(v8, v22); // fneg d8, d22
544 __ fsqrtd(v11, v11); // fsqrt d11, d11
545 __ fcvtd(v22, v28); // fcvt s22, d28
546
547 // FloatConvertOp
548 __ fcvtzsw(r28, v22); // fcvtzs w28, s22
549 __ fcvtzs(r20, v27); // fcvtzs x20, s27
550 __ fcvtzdw(r14, v0); // fcvtzs w14, d0
551 __ fcvtzd(r26, v11); // fcvtzs x26, d11
552 __ scvtfws(v28, r22); // scvtf s28, w22
553 __ scvtfs(v16, r10); // scvtf s16, x10
554 __ scvtfwd(v8, r21); // scvtf d8, w21
555 __ scvtfd(v21, r28); // scvtf d21, x28
556 __ fmovs(r24, v24); // fmov w24, s24
557 __ fmovd(r8, v19); // fmov x8, d19
558 __ fmovs(v8, r12); // fmov s8, w12
559 __ fmovd(v6, r7); // fmov d6, x7
560
561 // TwoRegFloatOp
562 __ fcmps(v30, v16); // fcmp s30, s16
563 __ fcmpd(v25, v11); // fcmp d25, d11
564 __ fcmps(v11, 0.0); // fcmp s11, #0.0
565 __ fcmpd(v11, 0.0); // fcmp d11, #0.0
566
567 // LoadStorePairOp
568 __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128]
569 __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96]
570 __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64]
571 __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112]
572 __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16]
573
574 // LoadStorePairOp
575 __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]!
576 __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]!
577 __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]!
578 __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]!
579 __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]!
580
581 // LoadStorePairOp
582 __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128
583 __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192
584 __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144
585 __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96
586 __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32
587
588 // LoadStorePairOp
589 __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224]
590 __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144]
591 __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128]
592 __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176]
593
594 // FloatImmediateOp
595 __ fmovd(v0, 2.0); // fmov d0, #2.0
596 __ fmovd(v0, 2.125); // fmov d0, #2.125
597 __ fmovd(v0, 4.0); // fmov d0, #4.0
598 __ fmovd(v0, 4.25); // fmov d0, #4.25
599 __ fmovd(v0, 8.0); // fmov d0, #8.0
600 __ fmovd(v0, 8.5); // fmov d0, #8.5
601 __ fmovd(v0, 16.0); // fmov d0, #16.0
602 __ fmovd(v0, 17.0); // fmov d0, #17.0
603 __ fmovd(v0, 0.125); // fmov d0, #0.125
604 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
605 __ fmovd(v0, 0.25); // fmov d0, #0.25
606 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
607 __ fmovd(v0, 0.5); // fmov d0, #0.5
608 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
609 __ fmovd(v0, 1.0); // fmov d0, #1.0
610 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
611 __ fmovd(v0, -2.0); // fmov d0, #-2.0
612 __ fmovd(v0, -2.125); // fmov d0, #-2.125
613 __ fmovd(v0, -4.0); // fmov d0, #-4.0
614 __ fmovd(v0, -4.25); // fmov d0, #-4.25
615 __ fmovd(v0, -8.0); // fmov d0, #-8.0
616 __ fmovd(v0, -8.5); // fmov d0, #-8.5
617 __ fmovd(v0, -16.0); // fmov d0, #-16.0
618 __ fmovd(v0, -17.0); // fmov d0, #-17.0
619 __ fmovd(v0, -0.125); // fmov d0, #-0.125
620 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
621 __ fmovd(v0, -0.25); // fmov d0, #-0.25
622 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
623 __ fmovd(v0, -0.5); // fmov d0, #-0.5
624 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
625 __ fmovd(v0, -1.0); // fmov d0, #-1.0
626 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
627
628 __ bind(forth);
629
630 /*
631 aarch64ops.o: file format elf64-littleaarch64
632
633
634 Disassembly of section .text:
635
636 0000000000000000 <back>:
637 0: 8b0772d3 add x19, x22, x7, lsl #28
638 4: cb4a3570 sub x16, x11, x10, lsr #13
639 8: ab9c09bb adds x27, x13, x28, asr #2
640 c: eb9aa794 subs x20, x28, x26, asr #41
641 10: 0b934e68 add w8, w19, w19, asr #19
642 14: 4b0a3924 sub w4, w9, w10, lsl #14
643 18: 2b1e3568 adds w8, w11, w30, lsl #13
644 1c: 6b132720 subs w0, w25, w19, lsl #9
645 20: 8a154c14 and x20, x0, x21, lsl #19
646 24: aa1445d5 orr x21, x14, x20, lsl #17
647 28: ca01cf99 eor x25, x28, x1, lsl #51
648 2c: ea8b3f6a ands x10, x27, x11, asr #15
649 30: 0a8c5cb9 and w25, w5, w12, asr #23
650 34: 2a4a11d2 orr w18, w14, w10, lsr #4
651 38: 4a855aa4 eor w4, w21, w5, asr #22
652 3c: 6a857415 ands w21, w0, w5, asr #29
653 40: 8aa697da bic x26, x30, x6, asr #37
654 44: aa6d7423 orn x3, x1, x13, lsr #29
655 48: ca29bf80 eon x0, x28, x9, lsl #47
656 4c: ea3cb8bd bics x29, x5, x28, lsl #46
657 50: 0a675249 bic w9, w18, w7, lsr #20
658 54: 2ab961ba orn w26, w13, w25, asr #24
659 58: 4a331899 eon w25, w4, w19, lsl #6
660 5c: 6a646345 bics w5, w26, w4, lsr #24
661 60: 11055267 add w7, w19, #0x154
662 64: 31064408 adds w8, w0, #0x191
663 68: 51028e9d sub w29, w20, #0xa3
664 6c: 710bdee8 subs w8, w23, #0x2f7
665 70: 91082d81 add x1, x12, #0x20b
666 74: b106a962 adds x2, x11, #0x1aa
667 78: d10b33ae sub x14, x29, #0x2cc
668 7c: f10918ab subs x11, x5, #0x246
669 80: 121102d7 and w23, w22, #0x8000
670 84: 3204cd44 orr w4, w10, #0xf0f0f0f0
671 88: 5204cf00 eor w0, w24, #0xf0f0f0f0
672 8c: 72099fb3 ands w19, w29, #0x7f807f80
673 90: 92729545 and x5, x10, #0xfffffffffc000
674 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000
675 98: d27c34be eor x30, x5, #0x3fff0
676 9c: f27e4efa ands x26, x23, #0x3ffffc
677 a0: 14000000 b a0 <back+0xa0>
678 a4: 17ffffd7 b 0 <back>
679 a8: 1400017f b 6a4 <forth>
680 ac: 94000000 bl ac <back+0xac>
681 b0: 97ffffd4 bl 0 <back>
682 b4: 9400017c bl 6a4 <forth>
683 b8: 3400000c cbz w12, b8 <back+0xb8>
684 bc: 34fffa2c cbz w12, 0 <back>
685 c0: 34002f2c cbz w12, 6a4 <forth>
686 c4: 35000014 cbnz w20, c4 <back+0xc4>
687 c8: 35fff9d4 cbnz w20, 0 <back>
688 cc: 35002ed4 cbnz w20, 6a4 <forth>
689 d0: b400000c cbz x12, d0 <back+0xd0>
690 d4: b4fff96c cbz x12, 0 <back>
691 d8: b4002e6c cbz x12, 6a4 <forth>
692 dc: b5000018 cbnz x24, dc <back+0xdc>
693 e0: b5fff918 cbnz x24, 0 <back>
694 e4: b5002e18 cbnz x24, 6a4 <forth>
695 e8: 10000006 adr x6, e8 <back+0xe8>
696 ec: 10fff8a6 adr x6, 0 <back>
697 f0: 10002da6 adr x6, 6a4 <forth>
698 f4: 90000015 adrp x21, 0 <back>
699 f8: 36080001 tbz w1, #1, f8 <back+0xf8>
700 fc: 360ff821 tbz w1, #1, 0 <back>
701 100: 36082d21 tbz w1, #1, 6a4 <forth>
702 104: 37480008 tbnz w8, #9, 104 <back+0x104>
703 108: 374ff7c8 tbnz w8, #9, 0 <back>
704 10c: 37482cc8 tbnz w8, #9, 6a4 <forth>
705 110: 128b50ec movn w12, #0x5a87
706 114: 52a9ff8b movz w11, #0x4ffc, lsl #16
707 118: 7281d095 movk w21, #0xe84
708 11c: 92edfebd movn x29, #0x6ff5, lsl #48
709 120: d28361e3 movz x3, #0x1b0f
710 124: f2a4cc96 movk x22, #0x2664, lsl #16
711 128: 9346590c sbfx x12, x8, #6, #17
712 12c: 33194f33 bfi w19, w25, #7, #20
713 130: 531d3d89 ubfiz w9, w12, #3, #16
714 134: 9350433c sbfx x28, x25, #16, #1
715 138: b34464ac bfxil x12, x5, #4, #22
716 13c: d3462140 ubfx x0, x10, #6, #3
717 140: 139a61a4 extr w4, w13, w26, #24
718 144: 93d87fd7 extr x23, x30, x24, #31
719 148: 54000000 b.eq 148 <back+0x148>
720 14c: 54fff5a0 b.eq 0 <back>
721 150: 54002aa0 b.eq 6a4 <forth>
722 154: 54000001 b.ne 154 <back+0x154>
723 158: 54fff541 b.ne 0 <back>
724 15c: 54002a41 b.ne 6a4 <forth>
725 160: 54000002 b.cs 160 <back+0x160>
726 164: 54fff4e2 b.cs 0 <back>
727 168: 540029e2 b.cs 6a4 <forth>
728 16c: 54000002 b.cs 16c <back+0x16c>
729 170: 54fff482 b.cs 0 <back>
730 174: 54002982 b.cs 6a4 <forth>
731 178: 54000003 b.cc 178 <back+0x178>
732 17c: 54fff423 b.cc 0 <back>
733 180: 54002923 b.cc 6a4 <forth>
734 184: 54000003 b.cc 184 <back+0x184>
735 188: 54fff3c3 b.cc 0 <back>
736 18c: 540028c3 b.cc 6a4 <forth>
737 190: 54000004 b.mi 190 <back+0x190>
738 194: 54fff364 b.mi 0 <back>
739 198: 54002864 b.mi 6a4 <forth>
740 19c: 54000005 b.pl 19c <back+0x19c>
741 1a0: 54fff305 b.pl 0 <back>
742 1a4: 54002805 b.pl 6a4 <forth>
743 1a8: 54000006 b.vs 1a8 <back+0x1a8>
744 1ac: 54fff2a6 b.vs 0 <back>
745 1b0: 540027a6 b.vs 6a4 <forth>
746 1b4: 54000007 b.vc 1b4 <back+0x1b4>
747 1b8: 54fff247 b.vc 0 <back>
748 1bc: 54002747 b.vc 6a4 <forth>
749 1c0: 54000008 b.hi 1c0 <back+0x1c0>
750 1c4: 54fff1e8 b.hi 0 <back>
751 1c8: 540026e8 b.hi 6a4 <forth>
752 1cc: 54000009 b.ls 1cc <back+0x1cc>
753 1d0: 54fff189 b.ls 0 <back>
754 1d4: 54002689 b.ls 6a4 <forth>
755 1d8: 5400000a b.ge 1d8 <back+0x1d8>
756 1dc: 54fff12a b.ge 0 <back>
757 1e0: 5400262a b.ge 6a4 <forth>
758 1e4: 5400000b b.lt 1e4 <back+0x1e4>
759 1e8: 54fff0cb b.lt 0 <back>
760 1ec: 540025cb b.lt 6a4 <forth>
761 1f0: 5400000c b.gt 1f0 <back+0x1f0>
762 1f4: 54fff06c b.gt 0 <back>
763 1f8: 5400256c b.gt 6a4 <forth>
764 1fc: 5400000d b.le 1fc <back+0x1fc>
765 200: 54fff00d b.le 0 <back>
766 204: 5400250d b.le 6a4 <forth>
767 208: 5400000e b.al 208 <back+0x208>
768 20c: 54ffefae b.al 0 <back>
769 210: 540024ae b.al 6a4 <forth>
770 214: 5400000f b.nv 214 <back+0x214>
771 218: 54ffef4f b.nv 0 <back>
772 21c: 5400244f b.nv 6a4 <forth>
773 220: d4063721 svc #0x31b9
774 224: d4035082 hvc #0x1a84
775 228: d400bfe3 smc #0x5ff
776 22c: d4282fc0 brk #0x417e
777 230: d444c320 hlt #0x2619
778 234: d503201f nop
779 238: d69f03e0 eret
780 23c: d6bf03e0 drps
781 240: d5033fdf isb
782 244: d5033f9f dsb sy
783 248: d5033abf dmb ishst
784 24c: d61f0040 br x2
785 250: d63f00a0 blr x5
786 254: c8147c55 stxr w20, x21, [x2]
787 258: c807fcfd stlxr w7, x29, [x7]
788 25c: c85f7e05 ldxr x5, [x16]
789 260: c85fffbb ldaxr x27, [x29]
790 264: c89fffa0 stlr x0, [x29]
791 268: c8dfff95 ldar x21, [x28]
792 26c: 88187cf8 stxr w24, w24, [x7]
793 270: 8815ff9a stlxr w21, w26, [x28]
794 274: 885f7cd5 ldxr w21, [x6]
795 278: 885fffcf ldaxr w15, [x30]
796 27c: 889ffc73 stlr w19, [x3]
797 280: 88dffc56 ldar w22, [x2]
798 284: 48127c0f stxrh w18, w15, [x0]
799 288: 480bff85 stlxrh w11, w5, [x28]
800 28c: 485f7cdd ldxrh w29, [x6]
801 290: 485ffcf2 ldaxrh w18, [x7]
802 294: 489fff99 stlrh w25, [x28]
803 298: 48dffe62 ldarh w2, [x19]
804 29c: 080a7c3e stxrb w10, w30, [x1]
805 2a0: 0814fed5 stlxrb w20, w21, [x22]
806 2a4: 085f7c59 ldxrb w25, [x2]
807 2a8: 085ffcb8 ldaxrb w24, [x5]
808 2ac: 089ffc70 stlrb w16, [x3]
809 2b0: 08dfffb6 ldarb w22, [x29]
810 2b4: c87f0a68 ldxp x8, x2, [x19]
811 2b8: c87fcdc7 ldaxp x7, x19, [x14]
812 2bc: c82870bb stxp w8, x27, x28, [x5]
813 2c0: c826b8c8 stlxp w6, x8, x14, [x6]
814 2c4: 887f12d9 ldxp w25, w4, [x22]
815 2c8: 887fb9ee ldaxp w14, w14, [x15]
816 2cc: 8834215a stxp w20, w26, w8, [x10]
817 2d0: 8837ca52 stlxp w23, w18, w18, [x18]
818 2d4: f806317e str x30, [x11,#99]
819 2d8: b81b3337 str w23, [x25,#-77]
820 2dc: 39000dc2 strb w2, [x14,#3]
821 2e0: 78005149 strh w9, [x10,#5]
822 2e4: f84391f4 ldr x20, [x15,#57]
823 2e8: b85b220c ldr w12, [x16,#-78]
824 2ec: 385fd356 ldrb w22, [x26,#-3]
825 2f0: 785d127e ldrh w30, [x19,#-47]
826 2f4: 389f4149 ldrsb x9, [x10,#-12]
827 2f8: 79801e3c ldrsh x28, [x17,#14]
828 2fc: 79c014a3 ldrsh w3, [x5,#10]
829 300: b89a5231 ldrsw x17, [x17,#-91]
830 304: fc5ef282 ldr d2, [x20,#-17]
831 308: bc5f60f6 ldr s22, [x7,#-10]
832 30c: fc12125e str d30, [x18,#-223]
833 310: bc0152cd str s13, [x22,#21]
834 314: f8190e49 str x9, [x18,#-112]!
835 318: b800befd str w29, [x23,#11]!
836 31c: 381ffd92 strb w18, [x12,#-1]!
837 320: 781e9e90 strh w16, [x20,#-23]!
838 324: f8409fa3 ldr x3, [x29,#9]!
839 328: b8413c79 ldr w25, [x3,#19]!
840 32c: 385fffa1 ldrb w1, [x29,#-1]!
841 330: 785c7fa8 ldrh w8, [x29,#-57]!
842 334: 389f3dc5 ldrsb x5, [x14,#-13]!
843 338: 78801f6a ldrsh x10, [x27,#1]!
844 33c: 78c19d4b ldrsh w11, [x10,#25]!
845 340: b89a4ec4 ldrsw x4, [x22,#-92]!
846 344: fc408eeb ldr d11, [x23,#8]!
847 348: bc436e79 ldr s25, [x19,#54]!
848 34c: fc152ce1 str d1, [x7,#-174]!
849 350: bc036f28 str s8, [x25,#54]!
850 354: f8025565 str x5, [x11],#37
851 358: b80135f8 str w24, [x15],#19
852 35c: 381ff74f strb w15, [x26],#-1
853 360: 781fa652 strh w18, [x18],#-6
854 364: f851a447 ldr x7, [x2],#-230
855 368: b85e557b ldr w27, [x11],#-27
856 36c: 385e7472 ldrb w18, [x3],#-25
857 370: 785e070a ldrh w10, [x24],#-32
858 374: 38804556 ldrsb x22, [x10],#4
859 378: 78819591 ldrsh x17, [x12],#25
860 37c: 78dc24e8 ldrsh w8, [x7],#-62
861 380: b89cd6d7 ldrsw x23, [x22],#-51
862 384: fc430738 ldr d24, [x25],#48
863 388: bc5f6595 ldr s21, [x12],#-10
864 38c: fc1225b2 str d18, [x13],#-222
865 390: bc1d7430 str s16, [x1],#-41
866 394: f82fcac2 str x2, [x22,w15,sxtw]
867 398: b83d6a02 str w2, [x16,x29]
868 39c: 382e5a54 strb w20, [x18,w14,uxtw #0]
869 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1]
870 3a4: f86ecbae ldr x14, [x29,w14,sxtw]
871 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2]
872 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0]
873 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1]
874 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0]
875 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1]
876 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1]
877 3c0: b8ac6ab7 ldrsw x23, [x21,x12]
878 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3]
879 3c8: bc767943 ldr s3, [x10,x22,lsl #2]
880 3cc: fc3bc84e str d14, [x2,w27,sxtw]
881 3d0: bc3968d4 str s20, [x6,x25]
882 3d4: f91fc0fe str x30, [x7,#16256]
883 3d8: b91da50f str w15, [x8,#7588]
884 3dc: 391d280b strb w11, [x0,#1866]
885 3e0: 791d2e23 strh w3, [x17,#3734]
886 3e4: f95bc8e2 ldr x2, [x7,#14224]
887 3e8: b95ce525 ldr w5, [x9,#7396]
888 3ec: 395ae53c ldrb w28, [x9,#1721]
889 3f0: 795c9282 ldrh w2, [x20,#3656]
890 3f4: 399d7dd6 ldrsb x22, [x14,#1887]
891 3f8: 799fe008 ldrsh x8, [x0,#4080]
892 3fc: 79de9bc0 ldrsh w0, [x30,#3916]
893 400: b99aae78 ldrsw x24, [x19,#6828]
894 404: fd597598 ldr d24, [x12,#13032]
895 408: bd5d1d08 ldr s8, [x8,#7452]
896 40c: fd1f3dea str d10, [x15,#15992]
897 410: bd1a227a str s26, [x19,#6688]
898 414: 5800148a ldr x10, 6a4 <forth>
899 418: 18000003 ldr w3, 418 <back+0x418>
900 41c: f88092e0 prfm pldl1keep, [x23,#9]
901 420: d8ffdf00 prfm pldl1keep, 0 <back>
902 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw]
903 428: f99d7560 prfm pldl1keep, [x11,#15080]
904 42c: 1a1c012d adc w13, w9, w28
905 430: 3a1c027b adcs w27, w19, w28
906 434: 5a060253 sbc w19, w18, w6
907 438: 7a03028e sbcs w14, w20, w3
908 43c: 9a0801d0 adc x16, x14, x8
909 440: ba0803a0 adcs x0, x29, x8
910 444: da140308 sbc x8, x24, x20
911 448: fa00038c sbcs x12, x28, x0
912 44c: 0b3010d7 add w23, w6, w16, uxtb #4
913 450: 2b37ab39 adds w25, w25, w23, sxth #2
914 454: cb2466da sub x26, x22, x4, uxtx #1
915 458: 6b33efb1 subs w17, w29, w19, sxtx #3
916 45c: 8b350fcb add x11, x30, w21, uxtb #3
917 460: ab208a70 adds x16, x19, w0, sxtb #2
918 464: cb39e52b sub x11, x9, x25, sxtx #1
919 468: eb2c9291 subs x17, x20, w12, sxtb #4
920 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le
921 470: 7a4c81a2 ccmp w13, w12, #0x2, hi
922 474: ba42106c ccmn x3, x2, #0xc, ne
923 478: fa5560e3 ccmp x7, x21, #0x3, vs
924 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc
925 480: 7a515a26 ccmp w17, #0x11, #0x6, pl
926 484: ba4c2940 ccmn x10, #0xc, #0x0, cs
927 488: fa52aaae ccmp x21, #0x12, #0xe, ge
928 48c: 1a8cc1b5 csel w21, w13, w12, gt
929 490: 1a8f976a csinc w10, w27, w15, ls
930 494: 5a8981a0 csinv w0, w13, w9, hi
931 498: 5a9a6492 csneg w18, w4, w26, vs
932 49c: 9a8793ac csel x12, x29, x7, ls
933 4a0: 9a9474e6 csinc x6, x7, x20, vc
934 4a4: da83d2b6 csinv x22, x21, x3, le
935 4a8: da9b9593 csneg x19, x12, x27, ls
936 4ac: 5ac00200 rbit w0, w16
937 4b0: 5ac006f1 rev16 w17, w23
938 4b4: 5ac009d1 rev w17, w14
939 4b8: 5ac013d8 clz w24, w30
940 4bc: 5ac016d8 cls w24, w22
941 4c0: dac00223 rbit x3, x17
942 4c4: dac005ac rev16 x12, x13
943 4c8: dac00ac9 rev32 x9, x22
944 4cc: dac00c00 rev x0, x0
945 4d0: dac01205 clz x5, x16
946 4d4: dac016d9 cls x25, x22
947 4d8: 1ac0089d udiv w29, w4, w0
948 4dc: 1add0fa0 sdiv w0, w29, w29
949 4e0: 1ad52225 lsl w5, w17, w21
950 4e4: 1ad22529 lsr w9, w9, w18
951 4e8: 1ac82b61 asr w1, w27, w8
952 4ec: 1acd2e92 ror w18, w20, w13
953 4f0: 9acc0b28 udiv x8, x25, x12
954 4f4: 9adc0ca7 sdiv x7, x5, x28
955 4f8: 9adb2225 lsl x5, x17, x27
956 4fc: 9ad42757 lsr x23, x26, x20
957 500: 9adc291c asr x28, x8, x28
958 504: 9ac42fa3 ror x3, x29, x4
959 508: 1b1a55d1 madd w17, w14, w26, w21
960 50c: 1b0bafc1 msub w1, w30, w11, w11
961 510: 9b067221 madd x1, x17, x6, x28
962 514: 9b1ea0de msub x30, x6, x30, x8
963 518: 9b2e20d5 smaddl x21, w6, w14, x8
964 51c: 9b38cd4a smsubl x10, w10, w24, x19
965 520: 9bae6254 umaddl x20, w18, w14, x24
966 524: 9ba59452 umsubl x18, w2, w5, x5
967 528: 1e2d0a48 fmul s8, s18, s13
968 52c: 1e3c19c2 fdiv s2, s14, s28
969 530: 1e3c298f fadd s15, s12, s28
970 534: 1e213980 fsub s0, s12, s1
971 538: 1e240baf fmul s15, s29, s4
972 53c: 1e77082c fmul d12, d1, d23
973 540: 1e72191b fdiv d27, d8, d18
974 544: 1e6b2a97 fadd d23, d20, d11
975 548: 1e723988 fsub d8, d12, d18
976 54c: 1e770b1a fmul d26, d24, d23
977 550: 1f0d66f5 fmadd s21, s23, s13, s25
978 554: 1f01b956 fmsub s22, s10, s1, s14
979 558: 1f227a8e fnmadd s14, s20, s2, s30
980 55c: 1f365ba7 fnmadd s7, s29, s22, s22
981 560: 1f4f14ad fmadd d13, d5, d15, d5
982 564: 1f45a98e fmsub d14, d12, d5, d10
983 568: 1f60066a fnmadd d10, d19, d0, d1
984 56c: 1f620054 fnmadd d20, d2, d2, d0
985 570: 1e204139 fmov s25, s9
986 574: 1e20c094 fabs s20, s4
987 578: 1e214363 fneg s3, s27
988 57c: 1e21c041 fsqrt s1, s2
989 580: 1e22c01e fcvt d30, s0
990 584: 1e60408c fmov d12, d4
991 588: 1e60c361 fabs d1, d27
992 58c: 1e6142c8 fneg d8, d22
993 590: 1e61c16b fsqrt d11, d11
994 594: 1e624396 fcvt s22, d28
995 598: 1e3802dc fcvtzs w28, s22
996 59c: 9e380374 fcvtzs x20, s27
997 5a0: 1e78000e fcvtzs w14, d0
998 5a4: 9e78017a fcvtzs x26, d11
999 5a8: 1e2202dc scvtf s28, w22
1000 5ac: 9e220150 scvtf s16, x10
1001 5b0: 1e6202a8 scvtf d8, w21
1002 5b4: 9e620395 scvtf d21, x28
1003 5b8: 1e260318 fmov w24, s24
1004 5bc: 9e660268 fmov x8, d19
1005 5c0: 1e270188 fmov s8, w12
1006 5c4: 9e6700e6 fmov d6, x7
1007 5c8: 1e3023c0 fcmp s30, s16
1008 5cc: 1e6b2320 fcmp d25, d11
1009 5d0: 1e202168 fcmp s11, #0.0
1010 5d4: 1e602168 fcmp d11, #0.0
1011 5d8: 2910323d stp w29, w12, [x17,#128]
1012 5dc: 297449d6 ldp w22, w18, [x14,#-96]
1013 5e0: 6948402b ldpsw x11, x16, [x1,#64]
1014 5e4: a9072f40 stp x0, x11, [x26,#112]
1015 5e8: a9410747 ldp x7, x1, [x26,#16]
1016 5ec: 29801f0a stp w10, w7, [x24,#0]!
1017 5f0: 29e07307 ldp w7, w28, [x24,#-256]!
1018 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]!
1019 5f8: a9bf49d4 stp x20, x18, [x14,#-16]!
1020 5fc: a9c529a8 ldp x8, x10, [x13,#80]!
1021 600: 28b0605a stp w26, w24, [x2],#-128
1022 604: 28e866a2 ldp w2, w25, [x21],#-192
1023 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144
1024 60c: a886296c stp x12, x10, [x11],#96
1025 610: a8fe1a38 ldp x24, x6, [x17],#-32
1026 614: 282479c3 stnp w3, w30, [x14,#-224]
1027 618: 286e534f ldnp w15, w20, [x26,#-144]
1028 61c: a8386596 stnp x22, x25, [x12,#-128]
1029 620: a8755a3b ldnp x27, x22, [x17,#-176]
1030 624: 1e601000 fmov d0, #2.000000000000000000e+00
1031 628: 1e603000 fmov d0, #2.125000000000000000e+00
1032 62c: 1e621000 fmov d0, #4.000000000000000000e+00
1033 630: 1e623000 fmov d0, #4.250000000000000000e+00
1034 634: 1e641000 fmov d0, #8.000000000000000000e+00
1035 638: 1e643000 fmov d0, #8.500000000000000000e+00
1036 63c: 1e661000 fmov d0, #1.600000000000000000e+01
1037 640: 1e663000 fmov d0, #1.700000000000000000e+01
1038 644: 1e681000 fmov d0, #1.250000000000000000e-01
1039 648: 1e683000 fmov d0, #1.328125000000000000e-01
1040 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01
1041 650: 1e6a3000 fmov d0, #2.656250000000000000e-01
1042 654: 1e6c1000 fmov d0, #5.000000000000000000e-01
1043 658: 1e6c3000 fmov d0, #5.312500000000000000e-01
1044 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00
1045 660: 1e6e3000 fmov d0, #1.062500000000000000e+00
1046 664: 1e701000 fmov d0, #-2.000000000000000000e+00
1047 668: 1e703000 fmov d0, #-2.125000000000000000e+00
1048 66c: 1e721000 fmov d0, #-4.000000000000000000e+00
1049 670: 1e723000 fmov d0, #-4.250000000000000000e+00
1050 674: 1e741000 fmov d0, #-8.000000000000000000e+00
1051 678: 1e743000 fmov d0, #-8.500000000000000000e+00
1052 67c: 1e761000 fmov d0, #-1.600000000000000000e+01
1053 680: 1e763000 fmov d0, #-1.700000000000000000e+01
1054 684: 1e781000 fmov d0, #-1.250000000000000000e-01
1055 688: 1e783000 fmov d0, #-1.328125000000000000e-01
1056 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1057 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1058 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1059 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1060 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1061 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1062 */
1063
1064 static const unsigned int insns[] =
1065 {
1066 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794,
1067 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720,
1068 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a,
1069 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415,
1070 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd,
1071 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345,
1072 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8,
1073 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab,
1074 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3,
1075 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa,
1076 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000,
1077 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c,
1078 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4,
1079 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018,
1080 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6,
1081 0x10002da6, 0x90000015, 0x36080001, 0x360ff821,
1082 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8,
1083 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd,
1084 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33,
1085 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140,
1086 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0,
1087 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41,
1088 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002,
1089 0x54fff482, 0x54002982, 0x54000003, 0x54fff423,
1090 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3,
1091 0x54000004, 0x54fff364, 0x54002864, 0x54000005,
1092 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6,
1093 0x540027a6, 0x54000007, 0x54fff247, 0x54002747,
1094 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009,
1095 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a,
1096 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb,
1097 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d,
1098 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae,
1099 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f,
1100 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0,
1101 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1102 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040,
1103 0xd63f00a0, 0xc8147c55, 0xc807fcfd, 0xc85f7e05,
1104 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88187cf8,
1105 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73,
1106 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd,
1107 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e,
1108 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70,
1109 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb,
1110 0xc826b8c8, 0x887f12d9, 0x887fb9ee, 0x8834215a,
1111 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2,
1112 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356,
1113 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3,
1114 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e,
1115 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92,
1116 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1,
1117 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b,
1118 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1,
1119 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f,
1120 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472,
1121 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8,
1122 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2,
1123 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54,
1124 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989,
1125 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9,
1126 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e,
1127 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b,
1128 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c,
1129 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0,
1130 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea,
1131 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0,
1132 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d,
1133 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0,
1134 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7,
1135 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb,
1136 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3,
1137 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844,
1138 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5,
1139 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac,
1140 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200,
1141 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8,
1142 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00,
1143 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0,
1144 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92,
1145 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757,
1146 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1,
1147 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a,
1148 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2,
1149 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c,
1150 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a,
1151 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7,
1152 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054,
1153 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041,
1154 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8,
1155 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374,
1156 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150,
1157 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268,
1158 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320,
1159 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6,
1160 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a,
1161 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8,
1162 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c,
1163 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596,
1164 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000,
1165 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000,
1166 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000,
1167 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000,
1168 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000,
1169 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000,
1170 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000,
1171 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000,
1172 0x1e7e3000,
1173 };
1174 // END Generated code -- do not edit
1175
1176 {
1177 bool ok = true;
1178 unsigned int *insns1 = (unsigned int *)entry;
1179 for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) {
1180 if (insns[i] != insns1[i]) {
1181 ok = false;
1182 printf("Ours:\n");
1183 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
1184 printf("Theirs:\n");
1185 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
1186 printf("\n");
1187 }
1188 }
1189 assert(ok, "Assembler smoke test failed");
1190 }
1191
1192 #ifndef PRODUCT
1193
1194 address PC = __ pc();
1195 __ ld1(v0, __ T16B, Address(r16)); // No offset
1196 __ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index
1197 __ ld1(v0, __ T16B, Address(r16, r17)); //
1198
1199
1200 #endif // PRODUCT
1201 #endif // ASSERT
1202 }
1203
1204 #undef __
1205
1206 void Assembler::emit_data64(jlong data,
1207 relocInfo::relocType rtype,
1208 int format) {
1209 if (rtype == relocInfo::none) {
1210 emit_int64(data);
1211 } else {
1212 emit_data64(data, Relocation::spec_simple(rtype), format);
1213 }
1214 }
1215
1216 void Assembler::emit_data64(jlong data,
1217 RelocationHolder const& rspec,
1218 int format) {
1219
1220 assert(inst_mark() != NULL, "must be inside InstructionMark");
1221 // Do not use AbstractAssembler::relocate, which is not intended for
1222 // embedded words. Instead, relocate to the enclosing instruction.
1223 code_section()->relocate(inst_mark(), rspec, format);
1224 emit_int64(data);
1225 }
1226
1227 extern "C" {
1228 void das(uint64_t start, int len) {
1229 ResourceMark rm;
1230 len <<= 2;
1231 if (len < 0)
1232 Disassembler::decode((address)start + len, (address)start);
1233 else
1234 Disassembler::decode((address)start, (address)start + len);
1235 }
1236
1237 JNIEXPORT void das1(unsigned long insn) {
1238 das(insn, 1);
1239 }
1240 }
1241
1242 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1243
1244 #define __ as->
1245
1246 void Address::lea(MacroAssembler *as, Register r) const {
1247 Relocation* reloc = _rspec.reloc();
1248 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1249
1250 switch(_mode) {
1251 case base_plus_offset: {
1252 if (_offset == 0 && _base == r) // it's a nop
1253 break;
1254 if (_offset > 0)
1255 __ add(r, _base, _offset);
1256 else
1257 __ sub(r, _base, -_offset);
1258 break;
1259 }
1260 case base_plus_offset_reg: {
1261 __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1262 break;
1263 }
1264 case literal: {
1265 if (rtype == relocInfo::none)
1266 __ mov(r, target());
1267 else
1268 __ movptr(r, (uint64_t)target());
1269 break;
1270 }
1271 default:
1272 ShouldNotReachHere();
1273 }
1274 }
1275
1276 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1277 ShouldNotReachHere();
1278 }
1279
1280 #undef __
1281
1282 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1283
1284 void Assembler::adr(Register Rd, address adr) {
1285 long offset = adr - pc();
1286 int offset_lo = offset & 3;
1287 offset >>= 2;
1288 starti;
1289 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1290 rf(Rd, 0);
1291 }
1292
1293 void Assembler::_adrp(Register Rd, address adr) {
1294 uint64_t pc_page = (uint64_t)pc() >> 12;
1295 uint64_t adr_page = (uint64_t)adr >> 12;
1296 long offset = adr_page - pc_page;
1297 int offset_lo = offset & 3;
1298 offset >>= 2;
1299 starti;
1300 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1301 rf(Rd, 0);
1302 }
1303
1304 #undef starti
1305
1306 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1307 _is_lval = false;
1308 _target = target;
1309 switch (rtype) {
1310 case relocInfo::oop_type:
1311 case relocInfo::metadata_type:
1312 // Oops are a special case. Normally they would be their own section
1313 // but in cases like icBuffer they are literals in the code stream that
1314 // we don't have a section for. We use none so that we get a literal address
1315 // which is always patchable.
1316 break;
1317 case relocInfo::external_word_type:
1318 _rspec = external_word_Relocation::spec(target);
1319 break;
1320 case relocInfo::internal_word_type:
1321 _rspec = internal_word_Relocation::spec(target);
1322 break;
1323 case relocInfo::opt_virtual_call_type:
1324 _rspec = opt_virtual_call_Relocation::spec();
1325 break;
1326 case relocInfo::static_call_type:
1327 _rspec = static_call_Relocation::spec();
1328 break;
1329 case relocInfo::runtime_call_type:
1330 _rspec = runtime_call_Relocation::spec();
1331 break;
1332 case relocInfo::poll_type:
1333 case relocInfo::poll_return_type:
1334 _rspec = Relocation::spec_simple(rtype);
1335 break;
1336 case relocInfo::none:
1337 _rspec = RelocationHolder::none;
1338 break;
1339 default:
1340 ShouldNotReachHere();
1341 break;
1342 }
1343 }
1344
1345 void Assembler::b(const Address &dest) {
1346 code_section()->relocate(pc(), dest.rspec());
1347 b(dest.target());
1348 }
1349
1350 void Assembler::bl(const Address &dest) {
1351 code_section()->relocate(pc(), dest.rspec());
1352 bl(dest.target());
1353 }
1354
1355 void Assembler::adr(Register r, const Address &dest) {
1356 code_section()->relocate(pc(), dest.rspec());
1357 adr(r, dest.target());
1358 }
1359
1360 void Assembler::br(Condition cc, Label &L) {
1361 if (L.is_bound()) {
1362 br(cc, target(L));
1363 } else {
1364 L.add_patch_at(code(), locator());
1365 br(cc, pc());
1366 }
1367 }
1368
1369 void Assembler::wrap_label(Label &L,
1370 Assembler::uncond_branch_insn insn) {
1371 if (L.is_bound()) {
1372 (this->*insn)(target(L));
1373 } else {
1374 L.add_patch_at(code(), locator());
1375 (this->*insn)(pc());
1376 }
1377 }
1378
1379 void Assembler::wrap_label(Register r, Label &L,
1380 compare_and_branch_insn insn) {
1381 if (L.is_bound()) {
1382 (this->*insn)(r, target(L));
1383 } else {
1384 L.add_patch_at(code(), locator());
1385 (this->*insn)(r, pc());
1386 }
1387 }
1388
1389 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1390 test_and_branch_insn insn) {
1391 if (L.is_bound()) {
1392 (this->*insn)(r, bitpos, target(L));
1393 } else {
1394 L.add_patch_at(code(), locator());
1395 (this->*insn)(r, bitpos, pc());
1396 }
1397 }
1398
1399 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1400 if (L.is_bound()) {
1401 (this->*insn)(target(L), op);
1402 } else {
1403 L.add_patch_at(code(), locator());
1404 (this->*insn)(pc(), op);
1405 }
1406 }
1407
1408 // An "all-purpose" add/subtract immediate, per ARM documentation:
1409 // A "programmer-friendly" assembler may accept a negative immediate
1410 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1411 // requested ADD operation to a SUB, or vice versa, and then encode
1412 // the absolute value of the immediate as for uimm24.
1413 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1414 int negated_op) {
1415 bool sets_flags = op & 1; // this op sets flags
1416 union {
1417 unsigned u;
1418 int imm;
1419 };
1420 u = uimm;
1421 bool shift = false;
1422 bool neg = imm < 0;
1423 if (neg) {
1424 imm = -imm;
1425 op = negated_op;
1426 }
1427 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1428 if (imm >= (1 << 11)
1429 && ((imm >> 12) << 12 == imm)) {
1430 imm >>= 12;
1431 shift = true;
1432 }
1433 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1434
1435 // add/subtract immediate ops with the S bit set treat r31 as zr;
1436 // with S unset they use sp.
1437 if (sets_flags)
1438 zrf(Rd, 0);
1439 else
1440 srf(Rd, 0);
1441
1442 srf(Rn, 5);
1443 }
1444
1445 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1446 bool shift = false;
1447 unsigned long uimm = uabs(imm);
1448 if (uimm < (1 << 12))
1449 return true;
1450 if (uimm < (1 << 24)
1451 && ((uimm >> 12) << 12 == uimm)) {
1452 return true;
1453 }
1454 return false;
1455 }
1456
1457 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1458 return encode_logical_immediate(is32, imm) != 0xffffffff;
1459 }
1460
1461 static uint64_t doubleTo64Bits(jdouble d) {
1462 union {
1463 jdouble double_value;
1464 uint64_t double_bits;
1465 };
1466
1467 double_value = d;
1468 return double_bits;
1469 }
1470
1471 bool Assembler::operand_valid_for_float_immediate(double imm) {
1472 // If imm is all zero bits we can use ZR as the source of a
1473 // floating-point value.
1474 if (doubleTo64Bits(imm) == 0)
1475 return true;
1476
1477 // Otherwise try to encode imm then convert the encoded value back
1478 // and make sure it's the exact same bit pattern.
1479 unsigned result = encoding_for_fp_immediate(imm);
1480 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1481 }
1482
1483 int AbstractAssembler::code_fill_byte() {
1484 return 0;
1485 }
1486
1487 // n.b. this is implemented in subclass MacroAssembler
1488 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1489
1490
1491 // these are the functions provided by the simulator which are used to
1492 // encode and decode logical immediates and floating point immediates
1493 //
1494 // u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
1495 //
1496 // u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
1497 //
1498 // u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
1499 //
1500 // u_int32_t encoding_for_fp_immediate(float immediate);
1501 //
1502 // we currently import these from the simulator librray but the
1503 // definitions will need to be moved to here when we switch to real
1504 // hardware.
1505
1506 // and now the routines called by the assembler which encapsulate the
1507 // above encode and decode functions
1508
1509 uint32_t
1510 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1511 {
1512 if (is32) {
1513 /* Allow all zeros or all ones in top 32-bits, so that
1514 constant expressions like ~1 are permitted. */
1515 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1516 return 0xffffffff;
1517 /* Replicate the 32 lower bits to the 32 upper bits. */
1518 imm &= 0xffffffff;
1519 imm |= imm << 32;
1520 }
1521
1522 return encoding_for_logical_immediate(imm);
1523 }
1524
1525 unsigned Assembler::pack(double value) {
1526 float val = (float)value;
1527 unsigned result = encoding_for_fp_immediate(val);
1528 guarantee(unpack(result) == value,
1529 "Invalid floating-point immediate operand");
1530 return result;
1531 }
1532
1533 // Packed operands for Floating-point Move (immediate)
1534
1535 static float unpack(unsigned value) {
1536 union {
1537 unsigned ival;
1538 float val;
1539 };
1540 ival = fp_immediate_for_encoding(value, 0);
1541 return val;
1542 }