1 /*
2 * Copyright (c) 2014, Red Hat Inc.
3 * Copyright (c) 1997, 2012, Oracle and/or its affiliates.
4 * All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
29
30 #include "asm/assembler.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 using Assembler::mov;
41
42 protected:
43
44 // Support for VM calls
45 //
46 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
47 // may customize this version by overriding it for its purposes (e.g., to save/restore
48 // additional registers when doing a VM call).
49 #ifdef CC_INTERP
50 // c++ interpreter never wants to use interp_masm version of call_VM
51 #define VIRTUAL
52 #else
53 #define VIRTUAL virtual
54 #endif
55
56 VIRTUAL void call_VM_leaf_base(
57 address entry_point, // the entry point
58 int number_of_arguments, // the number of arguments to pop after the call
59 Label *retaddr = NULL
60 );
61
62 VIRTUAL void call_VM_leaf_base(
63 address entry_point, // the entry point
64 int number_of_arguments, // the number of arguments to pop after the call
65 Label &retaddr) {
66 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
67 }
68
69 // This is the base routine called by the different versions of call_VM. The interpreter
70 // may customize this version by overriding it for its purposes (e.g., to save/restore
71 // additional registers when doing a VM call).
72 //
73 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
74 // returns the register which contains the thread upon return. If a thread register has been
75 // specified, the return value will correspond to that register. If no last_java_sp is specified
76 // (noreg) than rsp will be used instead.
77 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
78 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
79 Register java_thread, // the thread if computed before ; use noreg otherwise
80 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
81 address entry_point, // the entry point
82 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
83 bool check_exceptions // whether to check for pending exceptions after return
84 );
85
86 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
87 // The implementation is only non-empty for the InterpreterMacroAssembler,
88 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
89 virtual void check_and_handle_popframe(Register java_thread);
90 virtual void check_and_handle_earlyret(Register java_thread);
91
92 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
93
94 // Maximum size of class area in Metaspace when compressed
95 uint64_t use_XOR_for_compressed_class_base;
96
97 public:
98 MacroAssembler(CodeBuffer* code) : Assembler(code) {
99 use_XOR_for_compressed_class_base
100 = (operand_valid_for_logical_immediate(false /*is32*/,
101 (uint64_t)Universe::narrow_klass_base())
102 && ((uint64_t)Universe::narrow_klass_base()
103 > (1u << log2_intptr(CompressedClassSpaceSize))));
104 }
105
106 // Biased locking support
107 // lock_reg and obj_reg must be loaded up with the appropriate values.
108 // swap_reg is killed.
109 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
110 // be killed; if not supplied, push/pop will be used internally to
111 // allocate a temporary (inefficient, avoid if possible).
112 // Optional slow case is for implementations (interpreter and C1) which branch to
113 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
114 // Returns offset of first potentially-faulting instruction for null
115 // check info (currently consumed only by C1). If
116 // swap_reg_contains_mark is true then returns -1 as it is assumed
117 // the calling code has already passed any potential faults.
118 int biased_locking_enter(Register lock_reg, Register obj_reg,
119 Register swap_reg, Register tmp_reg,
120 bool swap_reg_contains_mark,
121 Label& done, Label* slow_case = NULL,
122 BiasedLockingCounters* counters = NULL);
123 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
124
125
126 // Helper functions for statistics gathering.
127 // Unconditional atomic increment.
128 void atomic_incw(Register counter_addr, Register tmp);
129 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2) {
130 lea(tmp1, counter_addr);
131 atomic_incw(tmp1, tmp2);
132 }
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 code_section()->relocate(inst_mark(), a.rspec());
137 a.lea(this, r);
138 }
139
140 void addmw(Address a, Register incr, Register scratch) {
141 ldrw(scratch, a);
142 addw(scratch, scratch, incr);
143 strw(scratch, a);
144 }
145
146 // Add constant to memory word
147 void addmw(Address a, int imm, Register scratch) {
148 ldrw(scratch, a);
149 if (imm > 0)
150 addw(scratch, scratch, (unsigned)imm);
151 else
152 subw(scratch, scratch, (unsigned)-imm);
153 strw(scratch, a);
154 }
155
156 // Frame creation and destruction shared between JITs.
157 void build_frame(int framesize);
158 void remove_frame(int framesize);
159
160 virtual void _call_Unimplemented(address call_site) {
161 mov(rscratch2, call_site);
162 haltsim();
163 }
164
165 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
166
167 virtual void notify(int type);
168
169 // aliases defined in AARCH64 spec
170
171
172 template<class T>
173 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
174 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
175
176 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
177 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
178
179 void cset(Register Rd, Assembler::Condition cond) {
180 csinc(Rd, zr, zr, ~cond);
181 }
182 void csetw(Register Rd, Assembler::Condition cond) {
183 csincw(Rd, zr, zr, ~cond);
184 }
185
186 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
187 csneg(Rd, Rn, Rn, ~cond);
188 }
189 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
190 csnegw(Rd, Rn, Rn, ~cond);
191 }
192
193 inline void movw(Register Rd, Register Rn) {
194 if (Rd == sp || Rn == sp) {
195 addw(Rd, Rn, 0U);
196 } else {
197 orrw(Rd, zr, Rn);
198 }
199 }
200 inline void mov(Register Rd, Register Rn) {
201 assert(Rd != r31_sp && Rn != r31_sp, "should be");
202 if (Rd == Rn) {
203 } else if (Rd == sp || Rn == sp) {
204 add(Rd, Rn, 0U);
205 } else {
206 orr(Rd, zr, Rn);
207 }
208 }
209
210 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
211 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
212
213 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
214 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
215
216 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
217 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
218 }
219 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
220 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
221 }
222
223 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
224 bfmw(Rd, Rn, lsb, (lsb + width - 1));
225 }
226 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
227 bfm(Rd, Rn, lsb , (lsb + width - 1));
228 }
229
230 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
231 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
232 }
233 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
234 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
235 }
236
237 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
238 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
239 }
240 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
241 sbfm(Rd, Rn, lsb , (lsb + width - 1));
242 }
243
244 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
245 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
246 }
247 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
248 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
249 }
250
251 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
253 }
254 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
255 ubfm(Rd, Rn, lsb , (lsb + width - 1));
256 }
257
258 inline void asrw(Register Rd, Register Rn, unsigned imm) {
259 sbfmw(Rd, Rn, imm, 31);
260 }
261
262 inline void asr(Register Rd, Register Rn, unsigned imm) {
263 sbfm(Rd, Rn, imm, 63);
264 }
265
266 inline void lslw(Register Rd, Register Rn, unsigned imm) {
267 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
268 }
269
270 inline void lsl(Register Rd, Register Rn, unsigned imm) {
271 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
272 }
273
274 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
275 ubfmw(Rd, Rn, imm, 31);
276 }
277
278 inline void lsr(Register Rd, Register Rn, unsigned imm) {
279 ubfm(Rd, Rn, imm, 63);
280 }
281
282 inline void rorw(Register Rd, Register Rn, unsigned imm) {
283 extrw(Rd, Rn, Rn, imm);
284 }
285
286 inline void ror(Register Rd, Register Rn, unsigned imm) {
287 extr(Rd, Rn, Rn, imm);
288 }
289
290 inline void sxtbw(Register Rd, Register Rn) {
291 sbfmw(Rd, Rn, 0, 7);
292 }
293 inline void sxthw(Register Rd, Register Rn) {
294 sbfmw(Rd, Rn, 0, 15);
295 }
296 inline void sxtb(Register Rd, Register Rn) {
297 sbfm(Rd, Rn, 0, 7);
298 }
299 inline void sxth(Register Rd, Register Rn) {
300 sbfm(Rd, Rn, 0, 15);
301 }
302 inline void sxtw(Register Rd, Register Rn) {
303 sbfm(Rd, Rn, 0, 31);
304 }
305
306 inline void uxtbw(Register Rd, Register Rn) {
307 ubfmw(Rd, Rn, 0, 7);
308 }
309 inline void uxthw(Register Rd, Register Rn) {
310 ubfmw(Rd, Rn, 0, 15);
311 }
312 inline void uxtb(Register Rd, Register Rn) {
313 ubfm(Rd, Rn, 0, 7);
314 }
315 inline void uxth(Register Rd, Register Rn) {
316 ubfm(Rd, Rn, 0, 15);
317 }
318 inline void uxtw(Register Rd, Register Rn) {
319 ubfm(Rd, Rn, 0, 31);
320 }
321
322 inline void cmnw(Register Rn, Register Rm) {
323 addsw(zr, Rn, Rm);
324 }
325 inline void cmn(Register Rn, Register Rm) {
326 adds(zr, Rn, Rm);
327 }
328
329 inline void cmpw(Register Rn, Register Rm) {
330 subsw(zr, Rn, Rm);
331 }
332 inline void cmp(Register Rn, Register Rm) {
333 subs(zr, Rn, Rm);
334 }
335
336 inline void negw(Register Rd, Register Rn) {
337 subw(Rd, zr, Rn);
338 }
339
340 inline void neg(Register Rd, Register Rn) {
341 sub(Rd, zr, Rn);
342 }
343
344 inline void negsw(Register Rd, Register Rn) {
345 subsw(Rd, zr, Rn);
346 }
347
348 inline void negs(Register Rd, Register Rn) {
349 subs(Rd, zr, Rn);
350 }
351
352 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
353 addsw(zr, Rn, Rm, kind, shift);
354 }
355 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
356 adds(zr, Rn, Rm, kind, shift);
357 }
358
359 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
360 subsw(zr, Rn, Rm, kind, shift);
361 }
362 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
363 subs(zr, Rn, Rm, kind, shift);
364 }
365
366 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
367 subw(Rd, zr, Rn, kind, shift);
368 }
369
370 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
371 sub(Rd, zr, Rn, kind, shift);
372 }
373
374 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
375 subsw(Rd, zr, Rn, kind, shift);
376 }
377
378 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
379 subs(Rd, zr, Rn, kind, shift);
380 }
381
382 inline void mnegw(Register Rd, Register Rn, Register Rm) {
383 msubw(Rd, Rn, Rm, zr);
384 }
385 inline void mneg(Register Rd, Register Rn, Register Rm) {
386 msub(Rd, Rn, Rm, zr);
387 }
388
389 inline void mulw(Register Rd, Register Rn, Register Rm) {
390 maddw(Rd, Rn, Rm, zr);
391 }
392 inline void mul(Register Rd, Register Rn, Register Rm) {
393 madd(Rd, Rn, Rm, zr);
394 }
395
396 inline void smnegl(Register Rd, Register Rn, Register Rm) {
397 smsubl(Rd, Rn, Rm, zr);
398 }
399 inline void smull(Register Rd, Register Rn, Register Rm) {
400 smaddl(Rd, Rn, Rm, zr);
401 }
402
403 inline void umnegl(Register Rd, Register Rn, Register Rm) {
404 umsubl(Rd, Rn, Rm, zr);
405 }
406 inline void umull(Register Rd, Register Rn, Register Rm) {
407 umaddl(Rd, Rn, Rm, zr);
408 }
409
410 // macro assembly operations needed for aarch64
411
412 // first two private routines for loading 32 bit or 64 bit constants
413 private:
414
415 void mov_immediate64(Register dst, u_int64_t imm64);
416 void mov_immediate32(Register dst, u_int32_t imm32);
417
418 int push(unsigned int bitset, Register stack);
419 int pop(unsigned int bitset, Register stack);
420
421 void mov(Register dst, Address a);
422
423 public:
424 int push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
425 int pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
426
427 // now mov instructions for loading absolute addresses and 32 or
428 // 64 bit integers
429
430 inline void mov(Register dst, address addr)
431 {
432 mov_immediate64(dst, (u_int64_t)addr);
433 }
434
435 inline void mov(Register dst, u_int64_t imm64)
436 {
437 mov_immediate64(dst, imm64);
438 }
439
440 inline void movw(Register dst, u_int32_t imm32)
441 {
442 mov_immediate32(dst, imm32);
443 }
444
445 inline void mov(Register dst, long l)
446 {
447 mov(dst, (u_int64_t)l);
448 }
449
450 inline void mov(Register dst, int i)
451 {
452 mov(dst, (long)i);
453 }
454
455 void movptr(Register r, uintptr_t imm64);
456
457 // macro instructions for accessing and updating floating point
458 // status register
459 //
460 // FPSR : op1 == 011
461 // CRn == 0100
462 // CRm == 0100
463 // op2 == 001
464
465 inline void get_fpsr(Register reg)
466 {
467 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
468 }
469
470 inline void set_fpsr(Register reg)
471 {
472 msr(0b011, 0b0100, 0b0100, 0b001, reg);
473 }
474
475 inline void clear_fpsr()
476 {
477 msr(0b011, 0b0100, 0b0100, 0b001, zr);
478 }
479
480 // idiv variant which deals with MINLONG as dividend and -1 as divisor
481 int corrected_idivl(Register result, Register ra, Register rb,
482 bool want_remainder, Register tmp = rscratch1);
483 int corrected_idivq(Register result, Register ra, Register rb,
484 bool want_remainder, Register tmp = rscratch1);
485
486 // Support for NULL-checks
487 //
488 // Generates code that causes a NULL OS exception if the content of reg is NULL.
489 // If the accessed location is M[reg + offset] and the offset is known, provide the
490 // offset. No explicit code generation is needed if the offset is within a certain
491 // range (0 <= offset <= page_size).
492
493 virtual void null_check(Register reg, int offset = -1);
494 static bool needs_explicit_null_check(intptr_t offset);
495
496 static address target_addr_for_insn(address insn_addr, unsigned insn);
497
498 // Required platform-specific helpers for Label::patch_instructions.
499 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
500 static int pd_patch_instruction_size(address branch, address target);
501 static void pd_patch_instruction(address branch, address target) {
502 pd_patch_instruction_size(branch, target);
503 }
504 static address pd_call_destination(address branch) {
505 unsigned insn = *(unsigned*)branch;
506 return target_addr_for_insn(branch, insn);
507 }
508 #ifndef PRODUCT
509 static void pd_print_patched_instruction(address branch);
510 #endif
511
512 static int patch_oop(address insn_addr, address o);
513
514 // The following 4 methods return the offset of the appropriate move instruction
515
516 // Support for fast byte/short loading with zero extension (depending on particular CPU)
517 int load_unsigned_byte(Register dst, Address src);
518 int load_unsigned_short(Register dst, Address src);
519
520 // Support for fast byte/short loading with sign extension (depending on particular CPU)
521 int load_signed_byte(Register dst, Address src);
522 int load_signed_short(Register dst, Address src);
523
524 int load_signed_byte32(Register dst, Address src);
525 int load_signed_short32(Register dst, Address src);
526
527 // Support for sign-extension (hi:lo = extend_sign(lo))
528 void extend_sign(Register hi, Register lo);
529
530 // Load and store values by size and signed-ness
531 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
532 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
533
534 // Support for inc/dec with optimal instruction selection depending on value
535
536 // x86_64 aliases an unqualified register/address increment and
537 // decrement to call incrementq and decrementq but also supports
538 // explicitly sized calls to incrementq/decrementq or
539 // incrementl/decrementl
540
541 // for aarch64 the proper convention would be to use
542 // increment/decrement for 64 bit operatons and
543 // incrementw/decrementw for 32 bit operations. so when porting
544 // x86_64 code we can leave calls to increment/decrement as is,
545 // replace incrementq/decrementq with increment/decrement and
546 // replace incrementl/decrementl with incrementw/decrementw.
547
548 // n.b. increment/decrement calls with an Address destination will
549 // need to use a scratch register to load the value to be
550 // incremented. increment/decrement calls which add or subtract a
551 // constant value greater than 2^12 will need to use a 2nd scratch
552 // register to hold the constant. so, a register increment/decrement
553 // may trash rscratch2 and an address increment/decrement trash
554 // rscratch and rscratch2
555
556 void decrementw(Address dst, int value = 1);
557 void decrementw(Register reg, int value = 1);
558
559 void decrement(Register reg, int value = 1);
560 void decrement(Address dst, int value = 1);
561
562 void incrementw(Address dst, int value = 1);
563 void incrementw(Register reg, int value = 1);
564
565 void increment(Register reg, int value = 1);
566 void increment(Address dst, int value = 1);
567
568
569 // Alignment
570 void align(int modulus);
571
572 // Stack frame creation/removal
573 void enter()
574 {
575 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
576 mov(rfp, sp);
577 }
578 void leave()
579 {
580 mov(sp, rfp);
581 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
582 }
583
584 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
585 // The pointer will be loaded into the thread register.
586 void get_thread(Register thread);
587
588
589 // Support for VM calls
590 //
591 // It is imperative that all calls into the VM are handled via the call_VM macros.
592 // They make sure that the stack linkage is setup correctly. call_VM's correspond
593 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
594
595
596 void call_VM(Register oop_result,
597 address entry_point,
598 bool check_exceptions = true);
599 void call_VM(Register oop_result,
600 address entry_point,
601 Register arg_1,
602 bool check_exceptions = true);
603 void call_VM(Register oop_result,
604 address entry_point,
605 Register arg_1, Register arg_2,
606 bool check_exceptions = true);
607 void call_VM(Register oop_result,
608 address entry_point,
609 Register arg_1, Register arg_2, Register arg_3,
610 bool check_exceptions = true);
611
612 // Overloadings with last_Java_sp
613 void call_VM(Register oop_result,
614 Register last_java_sp,
615 address entry_point,
616 int number_of_arguments = 0,
617 bool check_exceptions = true);
618 void call_VM(Register oop_result,
619 Register last_java_sp,
620 address entry_point,
621 Register arg_1, bool
622 check_exceptions = true);
623 void call_VM(Register oop_result,
624 Register last_java_sp,
625 address entry_point,
626 Register arg_1, Register arg_2,
627 bool check_exceptions = true);
628 void call_VM(Register oop_result,
629 Register last_java_sp,
630 address entry_point,
631 Register arg_1, Register arg_2, Register arg_3,
632 bool check_exceptions = true);
633
634 void get_vm_result (Register oop_result, Register thread);
635 void get_vm_result_2(Register metadata_result, Register thread);
636
637 // These always tightly bind to MacroAssembler::call_VM_base
638 // bypassing the virtual implementation
639 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
640 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
641 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
642 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
643 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
644
645 void call_VM_leaf(address entry_point,
646 int number_of_arguments = 0);
647 void call_VM_leaf(address entry_point,
648 Register arg_1);
649 void call_VM_leaf(address entry_point,
650 Register arg_1, Register arg_2);
651 void call_VM_leaf(address entry_point,
652 Register arg_1, Register arg_2, Register arg_3);
653
654 // These always tightly bind to MacroAssembler::call_VM_leaf_base
655 // bypassing the virtual implementation
656 void super_call_VM_leaf(address entry_point);
657 void super_call_VM_leaf(address entry_point, Register arg_1);
658 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
659 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
660 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
661
662 // last Java Frame (fills frame anchor)
663 void set_last_Java_frame(Register last_java_sp,
664 Register last_java_fp,
665 address last_java_pc,
666 Register scratch);
667
668 void set_last_Java_frame(Register last_java_sp,
669 Register last_java_fp,
670 Label &last_java_pc,
671 Register scratch);
672
673 void set_last_Java_frame(Register last_java_sp,
674 Register last_java_fp,
675 Register last_java_pc,
676 Register scratch);
677
678 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
679
680 // thread in the default location (r15_thread on 64bit)
681 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
682
683 // Stores
684 void store_check(Register obj); // store check for obj - register is destroyed afterwards
685 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
686
687 #if INCLUDE_ALL_GCS
688
689 void g1_write_barrier_pre(Register obj,
690 Register pre_val,
691 Register thread,
692 Register tmp,
693 bool tosca_live,
694 bool expand_call);
695
696 void g1_write_barrier_post(Register store_addr,
697 Register new_val,
698 Register thread,
699 Register tmp,
700 Register tmp2);
701
702 #endif // INCLUDE_ALL_GCS
703
704 // split store_check(Register obj) to enhance instruction interleaving
705 void store_check_part_1(Register obj);
706 void store_check_part_2(Register obj);
707
708 // oop manipulations
709 void load_klass(Register dst, Register src);
710 void store_klass(Register dst, Register src);
711 void cmp_klass(Register oop, Register trial_klass, Register tmp);
712
713 void load_heap_oop(Register dst, Address src);
714
715 void load_heap_oop_not_null(Register dst, Address src);
716 void store_heap_oop(Address dst, Register src);
717
718 // currently unimplemented
719 // Used for storing NULL. All other oop constants should be
720 // stored using routines that take a jobject.
721 void store_heap_oop_null(Address dst);
722
723 void load_prototype_header(Register dst, Register src);
724
725 void store_klass_gap(Register dst, Register src);
726
727 // This dummy is to prevent a call to store_heap_oop from
728 // converting a zero (like NULL) into a Register by giving
729 // the compiler two choices it can't resolve
730
731 void store_heap_oop(Address dst, void* dummy);
732
733 void encode_heap_oop(Register d, Register s);
734 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
735 void decode_heap_oop(Register d, Register s);
736 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
737 void encode_heap_oop_not_null(Register r);
738 void decode_heap_oop_not_null(Register r);
739 void encode_heap_oop_not_null(Register dst, Register src);
740 void decode_heap_oop_not_null(Register dst, Register src);
741
742 void set_narrow_oop(Register dst, jobject obj);
743
744 void encode_klass_not_null(Register r);
745 void decode_klass_not_null(Register r);
746 void encode_klass_not_null(Register dst, Register src);
747 void decode_klass_not_null(Register dst, Register src);
748
749 void set_narrow_klass(Register dst, Klass* k);
750
751 // if heap base register is used - reinit it with the correct value
752 void reinit_heapbase();
753
754 DEBUG_ONLY(void verify_heapbase(const char* msg);)
755
756 void push_CPU_state();
757 void pop_CPU_state() ;
758
759 // Round up to a power of two
760 void round_to(Register reg, int modulus);
761
762 // allocation
763 void eden_allocate(
764 Register obj, // result: pointer to object after successful allocation
765 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
766 int con_size_in_bytes, // object size in bytes if known at compile time
767 Register t1, // temp register
768 Label& slow_case // continuation point if fast allocation fails
769 );
770 void tlab_allocate(
771 Register obj, // result: pointer to object after successful allocation
772 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
773 int con_size_in_bytes, // object size in bytes if known at compile time
774 Register t1, // temp register
775 Register t2, // temp register
776 Label& slow_case // continuation point if fast allocation fails
777 );
778 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
779 void verify_tlab();
780
781 void incr_allocated_bytes(Register thread,
782 Register var_size_in_bytes, int con_size_in_bytes,
783 Register t1 = noreg);
784
785 // interface method calling
786 void lookup_interface_method(Register recv_klass,
787 Register intf_klass,
788 RegisterOrConstant itable_index,
789 Register method_result,
790 Register scan_temp,
791 Label& no_such_interface);
792
793 // virtual method calling
794 // n.b. x86 allows RegisterOrConstant for vtable_index
795 void lookup_virtual_method(Register recv_klass,
796 RegisterOrConstant vtable_index,
797 Register method_result);
798
799 // Test sub_klass against super_klass, with fast and slow paths.
800
801 // The fast path produces a tri-state answer: yes / no / maybe-slow.
802 // One of the three labels can be NULL, meaning take the fall-through.
803 // If super_check_offset is -1, the value is loaded up from super_klass.
804 // No registers are killed, except temp_reg.
805 void check_klass_subtype_fast_path(Register sub_klass,
806 Register super_klass,
807 Register temp_reg,
808 Label* L_success,
809 Label* L_failure,
810 Label* L_slow_path,
811 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
812
813 // The rest of the type check; must be wired to a corresponding fast path.
814 // It does not repeat the fast path logic, so don't use it standalone.
815 // The temp_reg and temp2_reg can be noreg, if no temps are available.
816 // Updates the sub's secondary super cache as necessary.
817 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
818 void check_klass_subtype_slow_path(Register sub_klass,
819 Register super_klass,
820 Register temp_reg,
821 Register temp2_reg,
822 Label* L_success,
823 Label* L_failure,
824 bool set_cond_codes = false);
825
826 // Simplified, combined version, good for typical uses.
827 // Falls through on failure.
828 void check_klass_subtype(Register sub_klass,
829 Register super_klass,
830 Register temp_reg,
831 Label& L_success);
832
833 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
834
835
836 // Debugging
837
838 // only if +VerifyOops
839 void verify_oop(Register reg, const char* s = "broken oop");
840 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
841
842 // TODO: verify method and klass metadata (compare against vptr?)
843 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
844 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
845
846 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
847 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
848
849 // only if +VerifyFPU
850 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
851
852 // prints msg, dumps registers and stops execution
853 void stop(const char* msg);
854
855 // prints msg and continues
856 void warn(const char* msg);
857
858 static void debug64(char* msg, int64_t pc, int64_t regs[]);
859
860 void untested() { stop("untested"); }
861
862 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
863
864 void should_not_reach_here() { stop("should not reach here"); }
865
866 // Stack overflow checking
867 void bang_stack_with_offset(int offset) {
868 // stack grows down, caller passes positive offset
869 assert(offset > 0, "must bang with negative offset");
870 mov(rscratch2, -offset);
871 ldr(zr, Address(sp, rscratch2));
872 }
873
874 // Writes to stack successive pages until offset reached to check for
875 // stack overflow + shadow pages. Also, clobbers tmp
876 void bang_stack_size(Register size, Register tmp);
877
878 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
879 Register tmp,
880 int offset);
881
882 // Support for serializing memory accesses between threads
883 void serialize_memory(Register thread, Register tmp);
884
885 // Arithmetics
886
887 void addptr(Address dst, int32_t src) {
888 lea(rscratch2, dst);
889 ldr(rscratch1, Address(rscratch2));
890 add(rscratch1, rscratch1, src);
891 str(rscratch1, Address(rscratch2));
892 }
893
894 void cmpptr(Register src1, Address src2);
895
896 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
897 Label &suceed, Label *fail);
898
899 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
900 Label &suceed, Label *fail);
901
902 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
903 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
904
905 void atomic_xchg(Register prev, Register newv, Register addr);
906 void atomic_xchgw(Register prev, Register newv, Register addr);
907
908 void orptr(Address adr, RegisterOrConstant src) {
909 ldr(rscratch2, adr);
910 if (src.is_register())
911 orr(rscratch2, rscratch2, src.as_register());
912 else
913 orr(rscratch2, rscratch2, src.as_constant());
914 str(rscratch2, adr);
915 }
916
917 // Calls
918
919 // void call(Label& L, relocInfo::relocType rtype);
920
921 // NOTE: this call tranfers to the effective address of entry NOT
922 // the address contained by entry. This is because this is more natural
923 // for jumps/calls.
924 void call(Address entry);
925
926 // Emit the CompiledIC call idiom
927 void ic_call(address entry);
928
929 public:
930
931 // Data
932
933 void mov_metadata(Register dst, Metadata* obj);
934 Address allocate_metadata_address(Metadata* obj);
935 Address constant_oop_address(jobject obj);
936
937 void movoop(Register dst, jobject obj, bool immediate = false);
938
939 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
940 void kernel_crc32(Register crc, Register buf, Register len,
941 Register table0, Register table1, Register table2, Register table3,
942 Register tmp, Register tmp2, Register tmp3);
943
944 #undef VIRTUAL
945
946 // Stack push and pop individual 64 bit registers
947 void push(Register src);
948 void pop(Register dst);
949
950 // push all registers onto the stack
951 void pusha();
952 void popa();
953
954 void repne_scan(Register addr, Register value, Register count,
955 Register scratch);
956 void repne_scanw(Register addr, Register value, Register count,
957 Register scratch);
958
959 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
960 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
961
962 // If a constant does not fit in an immediate field, generate some
963 // number of MOV instructions and then perform the operation
964 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
965 add_sub_imm_insn insn1,
966 add_sub_reg_insn insn2);
967 // Seperate vsn which sets the flags
968 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
969 add_sub_imm_insn insn1,
970 add_sub_reg_insn insn2);
971
972 #define WRAP(INSN) \
973 void INSN(Register Rd, Register Rn, unsigned imm) { \
974 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
975 } \
976 \
977 void INSN(Register Rd, Register Rn, Register Rm, \
978 enum shift_kind kind, unsigned shift = 0) { \
979 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
980 } \
981 \
982 void INSN(Register Rd, Register Rn, Register Rm) { \
983 Assembler::INSN(Rd, Rn, Rm); \
984 } \
985 \
986 void INSN(Register Rd, Register Rn, Register Rm, \
987 ext::operation option, int amount = 0) { \
988 Assembler::INSN(Rd, Rn, Rm, option, amount); \
989 }
990
991 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
992
993 #undef WRAP
994 #define WRAP(INSN) \
995 void INSN(Register Rd, Register Rn, unsigned imm) { \
996 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
997 } \
998 \
999 void INSN(Register Rd, Register Rn, Register Rm, \
1000 enum shift_kind kind, unsigned shift = 0) { \
1001 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1002 } \
1003 \
1004 void INSN(Register Rd, Register Rn, Register Rm) { \
1005 Assembler::INSN(Rd, Rn, Rm); \
1006 } \
1007 \
1008 void INSN(Register Rd, Register Rn, Register Rm, \
1009 ext::operation option, int amount = 0) { \
1010 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1011 }
1012
1013 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1014
1015 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1016 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1017
1018 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1019
1020 void tableswitch(Register index, jint lowbound, jint highbound,
1021 Label &jumptable, Label &jumptable_end, int stride = 1) {
1022 adr(rscratch1, jumptable);
1023 subsw(rscratch2, index, lowbound);
1024 subsw(zr, rscratch2, highbound - lowbound);
1025 br(Assembler::HS, jumptable_end);
1026 add(rscratch1, rscratch1, rscratch2,
1027 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1028 br(rscratch1);
1029 }
1030
1031 // Form an address from base + offset in Rd. Rd may or may not
1032 // actually be used: you must use the Address that is returned. It
1033 // is up to you to ensure that the shift provided matches the size
1034 // of your data.
1035 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1036
1037 // Prolog generator routines to support switch between x86 code and
1038 // generated ARM code
1039
1040 // routine to generate an x86 prolog for a stub function which
1041 // bootstraps into the generated ARM code which directly follows the
1042 // stub
1043 //
1044
1045 public:
1046 // enum used for aarch64--x86 linkage to define return type of x86 function
1047 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1048
1049 #ifdef BUILTIN_SIM
1050 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1051 #else
1052 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1053 #endif
1054
1055 // special version of call_VM_leaf_base needed for aarch64 simulator
1056 // where we need to specify both the gp and fp arg counts and the
1057 // return type so that the linkage routine from aarch64 to x86 and
1058 // back knows which aarch64 registers to copy to x86 registers and
1059 // which x86 result register to copy back to an aarch64 register
1060
1061 void call_VM_leaf_base1(
1062 address entry_point, // the entry point
1063 int number_of_gp_arguments, // the number of gp reg arguments to pass
1064 int number_of_fp_arguments, // the number of fp reg arguments to pass
1065 ret_type type, // the return type for the call
1066 Label* retaddr = NULL
1067 );
1068
1069 void ldr_constant(Register dest, const Address &const_addr) {
1070 if (NearCpool) {
1071 ldr(dest, const_addr);
1072 } else {
1073 unsigned long offset;
1074 adrp(dest, InternalAddress(const_addr.target()), offset);
1075 ldr(dest, Address(dest, offset));
1076 }
1077 }
1078
1079 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1080 address read_polling_page(Register r, relocInfo::relocType rtype);
1081
1082 // Used by aarch64.ad to control code generation
1083 static bool use_acq_rel_for_volatile_fields();
1084
1085 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1086 void update_byte_crc32(Register crc, Register val, Register table);
1087 void update_word_crc32(Register crc, Register v, Register tmp,
1088 Register table0, Register table1, Register table2, Register table3,
1089 bool upper = false);
1090
1091 void string_compare(Register str1, Register str2,
1092 Register cnt1, Register cnt2, Register result,
1093 Register tmp1);
1094 void string_equals(Register str1, Register str2,
1095 Register cnt, Register result,
1096 Register tmp1);
1097 void char_arrays_equals(Register ary1, Register ary2,
1098 Register result, Register tmp1);
1099 void encode_iso_array(Register src, Register dst,
1100 Register len, Register result,
1101 FloatRegister Vtmp1, FloatRegister Vtmp2,
1102 FloatRegister Vtmp3, FloatRegister Vtmp4);
1103 void string_indexof(Register str1, Register str2,
1104 Register cnt1, Register cnt2,
1105 Register tmp1, Register tmp2,
1106 Register tmp3, Register tmp4,
1107 int int_cnt1, Register result);
1108
1109 // ISB may be needed because of a safepoint
1110 void maybe_isb() { isb(); }
1111 };
1112
1113 // Used by aarch64.ad to control code generation
1114 #define treat_as_volatile(MEM_NODE) \
1115 (MacroAssembler::use_acq_rel_for_volatile_fields() ? (MEM_NODE)->is_volatile() : false)
1116
1117 #ifdef ASSERT
1118 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1119 #endif
1120
1121 /**
1122 * class SkipIfEqual:
1123 *
1124 * Instantiating this class will result in assembly code being output that will
1125 * jump around any code emitted between the creation of the instance and it's
1126 * automatic destruction at the end of a scope block, depending on the value of
1127 * the flag passed to the constructor, which will be checked at run-time.
1128 */
1129 class SkipIfEqual {
1130 private:
1131 MacroAssembler* _masm;
1132 Label _label;
1133
1134 public:
1135 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1136 ~SkipIfEqual();
1137 };
1138
1139 struct tableswitch {
1140 Register _reg;
1141 int _insn_index; jint _first_key; jint _last_key;
1142 Label _after;
1143 Label _branches;
1144 };
1145
1146 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP