1 /*
2 * Copyright (c) 2014, Red Hat Inc.
3 * Copyright (c) 1997, 2011, Oracle and/or its affiliates.
4 * All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
28 #define CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
29
30 #include "asm/assembler.hpp"
31 #include "memory/allocation.hpp"
32 #include "runtime/icache.hpp"
33 #include "runtime/os.hpp"
34 #include "utilities/top.hpp"
35
36 // We have interfaces for the following instructions:
37 // - NativeInstruction
38 // - - NativeCall
39 // - - NativeMovConstReg
40 // - - NativeMovConstRegPatching
41 // - - NativeMovRegMem
42 // - - NativeMovRegMemPatching
43 // - - NativeJump
44 // - - NativeIllegalOpCode
45 // - - NativeGeneralJump
46 // - - NativeReturn
47 // - - NativeReturnX (return with argument)
48 // - - NativePushConst
49 // - - NativeTstRegMem
50
51 // The base class for different kinds of native instruction abstractions.
52 // Provides the primitive operations to manipulate code relative to this.
53
54 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
55 friend class Relocation;
56 public:
57 enum { instruction_size = 4 };
58 inline bool is_nop();
59 bool is_dtrace_trap();
60 inline bool is_illegal();
61 inline bool is_return();
62 bool is_jump();
63 inline bool is_jump_or_nop();
64 inline bool is_cond_jump();
65 bool is_safepoint_poll();
66 inline bool is_mov_literal64();
67 bool is_movz();
68 bool is_movk();
69
70 protected:
71 address addr_at(int offset) const { return address(this) + offset; }
72
73 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
74 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
75
76 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
77
78 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
79
80 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
81
82
83 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; }
84 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; }
85 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; }
86 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; }
87
88 public:
89
90 // unit test stuff
91 static void test() {} // override for testing
92
93 inline friend NativeInstruction* nativeInstruction_at(address address);
94
95 static bool is_adrp_at(address instr);
96 static bool is_ldr_literal_at(address instr);
97 static bool is_ldrw_to_zr(address instr);
98
99 static bool maybe_cpool_ref(address instr) {
100 return is_adrp_at(instr) || is_ldr_literal_at(instr);
101 }
102 };
103
104 inline NativeInstruction* nativeInstruction_at(address address) {
105 return (NativeInstruction*)address;
106 }
107
108 // The natural type of an AArch64 instruction is uint32_t
109 inline NativeInstruction* nativeInstruction_at(uint32_t *address) {
110 return (NativeInstruction*)address;
111 }
112
113 inline NativeCall* nativeCall_at(address address);
114 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
115 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
116
117 class NativeCall: public NativeInstruction {
118 public:
119 enum Aarch64_specific_constants {
120 instruction_size = 4,
121 instruction_offset = 0,
122 displacement_offset = 0,
123 return_address_offset = 4
124 };
125
126 enum { cache_line_size = BytesPerWord }; // conservative estimate!
127 address instruction_address() const { return addr_at(instruction_offset); }
128 address next_instruction_address() const { return addr_at(return_address_offset); }
129 int displacement() const { return (int_at(displacement_offset) << 6) >> 4; }
130 address displacement_address() const { return addr_at(displacement_offset); }
131 address return_address() const { return addr_at(return_address_offset); }
132 address destination() const;
133 void set_destination(address dest) {
134 int offset = dest - instruction_address();
135 unsigned int insn = 0b100101 << 26;
136 assert((offset & 3) == 0, "should be");
137 offset >>= 2;
138 offset &= (1 << 26) - 1; // mask off insn part
139 insn |= offset;
140 set_int_at(displacement_offset, insn);
141 ICache::invalidate_range(instruction_address(), instruction_size);
142 }
143
144 // Similar to replace_mt_safe, but just changes the destination. The
145 // important thing is that free-running threads are able to execute
146 // this call instruction at all times. If the call is an immediate BL
147 // instruction we can simply rely on atomicity of 32-bit writes to
148 // make sure other threads will see no intermediate states.
149
150 // We cannot rely on locks here, since the free-running threads must run at
151 // full speed.
152 //
153 // Used in the runtime linkage of calls; see class CompiledIC.
154 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
155 void set_destination_mt_safe(address dest) { set_destination(dest); }
156
157 void verify_alignment() { ; }
158 void verify();
159 void print();
160
161 // Creation
162 inline friend NativeCall* nativeCall_at(address address);
163 inline friend NativeCall* nativeCall_before(address return_address);
164
165 static bool is_call_at(address instr) {
166 const uint32_t insn = (*(uint32_t*)instr);
167 return (insn >> 26) == 0b100101;
168 }
169
170 static bool is_call_before(address return_address) {
171 return is_call_at(return_address - NativeCall::return_address_offset);
172 }
173
174 // MT-safe patching of a call instruction.
175 static void insert(address code_pos, address entry);
176
177 static void replace_mt_safe(address instr_addr, address code_buffer);
178 };
179
180 inline NativeCall* nativeCall_at(address address) {
181 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
182 #ifdef ASSERT
183 call->verify();
184 #endif
185 return call;
186 }
187
188 inline NativeCall* nativeCall_before(address return_address) {
189 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
190 #ifdef ASSERT
191 call->verify();
192 #endif
193 return call;
194 }
195
196 // An interface for accessing/manipulating native mov reg, imm instructions.
197 // (used to manipulate inlined 64-bit data calls, etc.)
198 class NativeMovConstReg: public NativeInstruction {
199 public:
200 enum Aarch64_specific_constants {
201 instruction_size = 3 * 4, // movz, movk, movk. See movptr().
202 instruction_offset = 0,
203 displacement_offset = 0,
204 };
205
206 address instruction_address() const { return addr_at(instruction_offset); }
207 address next_instruction_address() const {
208 if (nativeInstruction_at(instruction_address())->is_movz())
209 // Assume movz, movk, movk
210 return addr_at(instruction_size);
211 else if (is_adrp_at(instruction_address()))
212 return addr_at(2*4);
213 else if (is_ldr_literal_at(instruction_address()))
214 return(addr_at(4));
215 assert(false, "Unknown instruction in NativeMovConstReg");
216 }
217
218 intptr_t data() const;
219 void set_data(intptr_t x);
220
221 void flush() {
222 if (! maybe_cpool_ref(instruction_address())) {
223 ICache::invalidate_range(instruction_address(), instruction_size);
224 }
225 }
226
227 void verify();
228 void print();
229
230 // unit test stuff
231 static void test() {}
232
233 // Creation
234 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
235 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
236 };
237
238 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
239 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
240 #ifdef ASSERT
241 test->verify();
242 #endif
243 return test;
244 }
245
246 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
247 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
248 #ifdef ASSERT
249 test->verify();
250 #endif
251 return test;
252 }
253
254 class NativeMovConstRegPatching: public NativeMovConstReg {
255 private:
256 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
257 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
258 #ifdef ASSERT
259 test->verify();
260 #endif
261 return test;
262 }
263 };
264
265 // An interface for accessing/manipulating native moves of the form:
266 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
267 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
268 // mov[s/z]x[w/b/q] [reg + offset], reg
269 // fld_s [reg+offset]
270 // fld_d [reg+offset]
271 // fstp_s [reg + offset]
272 // fstp_d [reg + offset]
273 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
274 //
275 // Warning: These routines must be able to handle any instruction sequences
276 // that are generated as a result of the load/store byte,word,long
277 // macros. For example: The load_unsigned_byte instruction generates
278 // an xor reg,reg inst prior to generating the movb instruction. This
279 // class must skip the xor instruction.
280
281 class NativeMovRegMem: public NativeInstruction {
282 enum AArch64_specific_constants {
283 instruction_size = 4,
284 instruction_offset = 0,
285 data_offset = 0,
286 next_instruction_offset = 4
287 };
288
289 public:
290 // helper
291 int instruction_start() const;
292
293 address instruction_address() const;
294
295 address next_instruction_address() const;
296
297 int offset() const;
298
299 void set_offset(int x);
300
301 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
302
303 void verify();
304 void print ();
305
306 // unit test stuff
307 static void test() {}
308
309 private:
310 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
311 };
312
313 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
314 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
315 #ifdef ASSERT
316 test->verify();
317 #endif
318 return test;
319 }
320
321 class NativeMovRegMemPatching: public NativeMovRegMem {
322 private:
323 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0; }
324 };
325
326 // An interface for accessing/manipulating native leal instruction of form:
327 // leal reg, [reg + offset]
328
329 class NativeLoadAddress: public NativeMovRegMem {
330 static const bool has_rex = true;
331 static const int rex_size = 1;
332 public:
333
334 void verify();
335 void print ();
336
337 // unit test stuff
338 static void test() {}
339 };
340
341 class NativeJump: public NativeInstruction {
342 public:
343 enum AArch64_specific_constants {
344 instruction_size = 4,
345 instruction_offset = 0,
346 data_offset = 0,
347 next_instruction_offset = 4
348 };
349
350 address instruction_address() const { return addr_at(instruction_offset); }
351 address next_instruction_address() const { return addr_at(instruction_size); }
352 address jump_destination() const;
353 void set_jump_destination(address dest);
354
355 // Creation
356 inline friend NativeJump* nativeJump_at(address address);
357
358 void verify();
359
360 // Unit testing stuff
361 static void test() {}
362
363 // Insertion of native jump instruction
364 static void insert(address code_pos, address entry);
365 // MT-safe insertion of native jump at verified method entry
366 static void check_verified_entry_alignment(address entry, address verified_entry);
367 static void patch_verified_entry(address entry, address verified_entry, address dest);
368 };
369
370 inline NativeJump* nativeJump_at(address address) {
371 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
372 #ifdef ASSERT
373 jump->verify();
374 #endif
375 return jump;
376 }
377
378 class NativeGeneralJump: public NativeJump {
379 public:
380 enum AArch64_specific_constants {
381 instruction_size = 4,
382 instruction_offset = 0,
383 data_offset = 0,
384 next_instruction_offset = 4
385 };
386 static void insert_unconditional(address code_pos, address entry);
387 static void replace_mt_safe(address instr_addr, address code_buffer);
388 static void verify();
389 };
390
391 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
392 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
393 debug_only(jump->verify();)
394 return jump;
395 }
396
397 class NativePopReg : public NativeInstruction {
398 public:
399 // Insert a pop instruction
400 static void insert(address code_pos, Register reg);
401 };
402
403
404 class NativeIllegalInstruction: public NativeInstruction {
405 public:
406 // Insert illegal opcode as specific address
407 static void insert(address code_pos);
408 };
409
410 // return instruction that does not pop values of the stack
411 class NativeReturn: public NativeInstruction {
412 public:
413 };
414
415 // return instruction that does pop values of the stack
416 class NativeReturnX: public NativeInstruction {
417 public:
418 };
419
420 // Simple test vs memory
421 class NativeTstRegMem: public NativeInstruction {
422 public:
423 };
424
425 inline bool NativeInstruction::is_nop() {
426 uint32_t insn = *(uint32_t*)addr_at(0);
427 return insn == 0xd503201f;
428 }
429
430 inline bool NativeInstruction::is_jump() {
431 uint32_t insn = *(uint32_t*)addr_at(0);
432
433 if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
434 // Unconditional branch (immediate)
435 return true;
436 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
437 // Conditional branch (immediate)
438 return true;
439 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
440 // Compare & branch (immediate)
441 return true;
442 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
443 // Test & branch (immediate)
444 return true;
445 } else
446 return false;
447 }
448
449 inline bool NativeInstruction::is_jump_or_nop() {
450 return is_nop() || is_jump();
451 }
452
453 #endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP