1 /*
2 * Copyright (c) 2013, Red Hat Inc.
3 * Copyright (c) 1997, 2011, Oracle and/or its affiliates.
4 * All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
29
30 #include "asm/register.hpp"
31
32 // definitions of various symbolic names for machine registers
33
34 // First intercalls between C and Java which use 8 general registers
35 // and 8 floating registers
36
37 // we also have to copy between x86 and ARM registers but that's a
38 // secondary complication -- not all code employing C call convention
39 // executes as x86 code though -- we generate some of it
40
41 class Argument VALUE_OBJ_CLASS_SPEC {
42 public:
43 enum {
44 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
46
47 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
49 };
50 };
51
52 REGISTER_DECLARATION(Register, c_rarg0, r0);
53 REGISTER_DECLARATION(Register, c_rarg1, r1);
54 REGISTER_DECLARATION(Register, c_rarg2, r2);
55 REGISTER_DECLARATION(Register, c_rarg3, r3);
56 REGISTER_DECLARATION(Register, c_rarg4, r4);
57 REGISTER_DECLARATION(Register, c_rarg5, r5);
58 REGISTER_DECLARATION(Register, c_rarg6, r6);
59 REGISTER_DECLARATION(Register, c_rarg7, r7);
60
61 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
62 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
63 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
64 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
65 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
66 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
67 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
68 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
69
70 // Symbolically name the register arguments used by the Java calling convention.
71 // We have control over the convention for java so we can do what we please.
72 // What pleases us is to offset the java calling convention so that when
73 // we call a suitable jni method the arguments are lined up and we don't
74 // have to do much shuffling. A suitable jni method is non-static and a
75 // small number of arguments
76 //
77 // |--------------------------------------------------------------------|
78 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
79 // |--------------------------------------------------------------------|
80 // | r0 r1 r2 r3 r4 r5 r6 r7 |
81 // |--------------------------------------------------------------------|
82 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
83 // |--------------------------------------------------------------------|
84
85
86 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
87 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
88 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
89 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
90 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
91 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
92 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
93 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
94
95 // Java floating args are passed as per C
96
97 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
98 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
99 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
100 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
101 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
102 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
103 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
104 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
105
106 // registers used to hold VM data either temporarily within a method
107 // or across method calls
108
109 // volatile (caller-save) registers
110
111 // r8 is used for indirect result location return
112 // we use it and r9 as scratch registers
113 REGISTER_DECLARATION(Register, rscratch1, r8);
114 REGISTER_DECLARATION(Register, rscratch2, r9);
115
116 // current method -- must be in a call-clobbered register
117 REGISTER_DECLARATION(Register, rmethod, r12);
118
119 // non-volatile (callee-save) registers are r16-29
120 // of which the following are dedicated global state
121
122 // link register
123 REGISTER_DECLARATION(Register, lr, r30);
124 // frame pointer
125 REGISTER_DECLARATION(Register, rfp, r29);
126 // current thread
127 REGISTER_DECLARATION(Register, rthread, r28);
128 // base of heap
129 REGISTER_DECLARATION(Register, rheapbase, r27);
130 // constant pool cache
131 REGISTER_DECLARATION(Register, rcpool, r26);
132 // monitors allocated on stack
133 REGISTER_DECLARATION(Register, rmonitors, r25);
134 // locals on stack
135 REGISTER_DECLARATION(Register, rlocals, r24);
136 // bytecode pointer
137 REGISTER_DECLARATION(Register, rbcp, r22);
138 // Dispatch table base
139 REGISTER_DECLARATION(Register, rdispatch, r21);
140 // Java stack pointer
141 REGISTER_DECLARATION(Register, esp, r20);
142
143 // TODO : x86 uses rbp to save SP in method handle code
144 // we may need to do the same with fp
145 // JSR 292 fixed register usages:
146 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29);
147
148 #define assert_cond(ARG1) assert(ARG1, #ARG1)
149
150 namespace asm_util {
151 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
152 };
153
154 using namespace asm_util;
155
156
157 class Assembler;
158
159 class Instruction_aarch64 {
160 unsigned insn;
161 #ifdef ASSERT
162 unsigned bits;
163 #endif
164 Assembler *assem;
165
166 public:
167
168 Instruction_aarch64(class Assembler *as) {
169 #ifdef ASSERT
170 bits = 0;
171 #endif
172 insn = 0;
173 assem = as;
174 }
175
176 inline ~Instruction_aarch64();
177
178 unsigned &get_insn() { return insn; }
179 #ifdef ASSERT
180 unsigned &get_bits() { return bits; }
181 #endif
182
183 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
184 union {
185 unsigned u;
186 int n;
187 };
188
189 u = val << (31 - hi);
190 n = n >> (31 - hi + lo);
191 return n;
192 }
193
194 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
195 int nbits = msb - lsb + 1;
196 assert_cond(msb >= lsb);
197 uint32_t mask = (1U << nbits) - 1;
198 uint32_t result = val >> lsb;
199 result &= mask;
200 return result;
201 }
202
203 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
204 uint32_t uval = extract(val, msb, lsb);
205 return extend(uval, msb - lsb);
206 }
207
208 static void patch(address a, int msb, int lsb, unsigned long val) {
209 int nbits = msb - lsb + 1;
210 guarantee(val < (1U << nbits), "Field too big for insn");
211 assert_cond(msb >= lsb);
212 unsigned mask = (1U << nbits) - 1;
213 val <<= lsb;
214 mask <<= lsb;
215 unsigned target = *(unsigned *)a;
216 target &= ~mask;
217 target |= val;
218 *(unsigned *)a = target;
219 }
220
221 static void spatch(address a, int msb, int lsb, long val) {
222 int nbits = msb - lsb + 1;
223 long chk = val >> (nbits - 1);
224 guarantee (chk == -1 || chk == 0, "Field too big for insn");
225 unsigned uval = val;
226 unsigned mask = (1U << nbits) - 1;
227 uval &= mask;
228 uval <<= lsb;
229 mask <<= lsb;
230 unsigned target = *(unsigned *)a;
231 target &= ~mask;
232 target |= uval;
233 *(unsigned *)a = target;
234 }
235
236 void f(unsigned val, int msb, int lsb) {
237 int nbits = msb - lsb + 1;
238 guarantee(val < (1U << nbits), "Field too big for insn");
239 assert_cond(msb >= lsb);
240 unsigned mask = (1U << nbits) - 1;
241 val <<= lsb;
242 mask <<= lsb;
243 insn |= val;
244 assert_cond((bits & mask) == 0);
245 #ifdef ASSERT
246 bits |= mask;
247 #endif
248 }
249
250 void f(unsigned val, int bit) {
251 f(val, bit, bit);
252 }
253
254 void sf(long val, int msb, int lsb) {
255 int nbits = msb - lsb + 1;
256 long chk = val >> (nbits - 1);
257 guarantee (chk == -1 || chk == 0, "Field too big for insn");
258 unsigned uval = val;
259 unsigned mask = (1U << nbits) - 1;
260 uval &= mask;
261 f(uval, lsb + nbits - 1, lsb);
262 }
263
264 void rf(Register r, int lsb) {
265 f(r->encoding_nocheck(), lsb + 4, lsb);
266 }
267
268 // reg|ZR
269 void zrf(Register r, int lsb) {
270 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
271 }
272
273 // reg|SP
274 void srf(Register r, int lsb) {
275 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
276 }
277
278 void rf(FloatRegister r, int lsb) {
279 f(r->encoding_nocheck(), lsb + 4, lsb);
280 }
281
282 unsigned get(int msb = 31, int lsb = 0) {
283 int nbits = msb - lsb + 1;
284 unsigned mask = ((1U << nbits) - 1) << lsb;
285 assert_cond(bits & mask == mask);
286 return (insn & mask) >> lsb;
287 }
288
289 void fixed(unsigned value, unsigned mask) {
290 assert_cond ((mask & bits) == 0);
291 #ifdef ASSERT
292 bits |= mask;
293 #endif
294 insn |= value;
295 }
296 };
297
298 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
299
300 class PrePost {
301 int _offset;
302 Register _r;
303 public:
304 PrePost(Register reg, int o) : _r(reg), _offset(o) { }
305 int offset() { return _offset; }
306 Register reg() { return _r; }
307 };
308
309 class Pre : public PrePost {
310 public:
311 Pre(Register reg, int o) : PrePost(reg, o) { }
312 };
313 class Post : public PrePost {
314 public:
315 Post(Register reg, int o) : PrePost(reg, o) { }
316 };
317
318 namespace ext
319 {
320 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
321 };
322
323 // abs methods which cannot overflow and so are well-defined across
324 // the entire domain of integer types.
325 static inline unsigned int uabs(unsigned int n) {
326 union {
327 unsigned int result;
328 int value;
329 };
330 result = n;
331 if (value < 0) result = -result;
332 return result;
333 }
334 static inline unsigned long uabs(unsigned long n) {
335 union {
336 unsigned long result;
337 long value;
338 };
339 result = n;
340 if (value < 0) result = -result;
341 return result;
342 }
343 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
344 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
345
346 // Addressing modes
347 class Address VALUE_OBJ_CLASS_SPEC {
348 public:
349
350 enum mode { no_mode, base_plus_offset, pre, post, pcrel,
351 base_plus_offset_reg, literal };
352
353 // Shift and extend for base reg + reg offset addressing
354 class extend {
355 int _option, _shift;
356 ext::operation _op;
357 public:
358 extend() { }
359 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
360 int option() const{ return _option; }
361 int shift() const { return _shift; }
362 ext::operation op() const { return _op; }
363 };
364 class uxtw : public extend {
365 public:
366 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
367 };
368 class lsl : public extend {
369 public:
370 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
371 };
372 class sxtw : public extend {
373 public:
374 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
375 };
376 class sxtx : public extend {
377 public:
378 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
379 };
380
381 private:
382 Register _base;
383 Register _index;
384 long _offset;
385 enum mode _mode;
386 extend _ext;
387
388 RelocationHolder _rspec;
389
390 // Typically we use AddressLiterals we want to use their rval
391 // However in some situations we want the lval (effect address) of
392 // the item. We provide a special factory for making those lvals.
393 bool _is_lval;
394
395 // If the target is far we'll need to load the ea of this to a
396 // register to reach it. Otherwise if near we can do PC-relative
397 // addressing.
398 address _target;
399
400 public:
401 Address()
402 : _mode(no_mode) { }
403 Address(Register r)
404 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
405 Address(Register r, int o)
406 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
407 Address(Register r, long o)
408 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
409 Address(Register r, unsigned long o)
410 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
411 #ifdef ASSERT
412 Address(Register r, ByteSize disp)
413 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
414 _index(noreg), _target(0) { }
415 #endif
416 Address(Register r, Register r1, extend ext = lsl())
417 : _mode(base_plus_offset_reg), _base(r), _index(r1),
418 _ext(ext), _offset(0), _target(0) { }
419 Address(Pre p)
420 : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
421 Address(Post p)
422 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
423 Address(address target, RelocationHolder const& rspec)
424 : _mode(literal),
425 _rspec(rspec),
426 _is_lval(false),
427 _target(target) { }
428 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
429 Address(Register base, RegisterOrConstant index, extend ext = lsl())
430 : _base (base),
431 _ext(ext), _offset(0), _target(0) {
432 if (index.is_register()) {
433 _mode = base_plus_offset_reg;
434 _index = index.as_register();
435 } else {
436 guarantee(ext.option() == ext::uxtx, "should be");
437 assert(index.is_constant(), "should be");
438 _mode = base_plus_offset;
439 _offset = index.as_constant() << ext.shift();
440 }
441 }
442
443 Register base() const {
444 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
445 | _mode == post),
446 "wrong mode");
447 return _base;
448 }
449 long offset() const {
450 return _offset;
451 }
452 Register index() const {
453 return _index;
454 }
455 mode getMode() const {
456 return _mode;
457 }
458 bool uses(Register reg) const { return _base == reg || _index == reg; }
459 address target() const { return _target; }
460 const RelocationHolder& rspec() const { return _rspec; }
461
462 void encode(Instruction_aarch64 *i) const {
463 i->f(0b111, 29, 27);
464 i->srf(_base, 5);
465
466 switch(_mode) {
467 case base_plus_offset:
468 {
469 unsigned size = i->get(31, 30);
470 if (i->get(26, 26) && i->get(23, 23)) {
471 // SIMD Q Type - Size = 128 bits
472 assert(size == 0, "bad size");
473 size = 0b100;
474 }
475 unsigned mask = (1 << size) - 1;
476 if (_offset < 0 || _offset & mask)
477 {
478 i->f(0b00, 25, 24);
479 i->f(0, 21), i->f(0b00, 11, 10);
480 i->sf(_offset, 20, 12);
481 } else {
482 i->f(0b01, 25, 24);
483 i->f(_offset >> size, 21, 10);
484 }
485 }
486 break;
487
488 case base_plus_offset_reg:
489 {
490 i->f(0b00, 25, 24);
491 i->f(1, 21);
492 i->rf(_index, 16);
493 i->f(_ext.option(), 15, 13);
494 unsigned size = i->get(31, 30);
495 if (i->get(26, 26) && i->get(23, 23)) {
496 // SIMD Q Type - Size = 128 bits
497 assert(size == 0, "bad size");
498 size = 0b100;
499 }
500 if (size == 0) // It's a byte
501 i->f(_ext.shift() >= 0, 12);
502 else {
503 if (_ext.shift() > 0)
504 assert(_ext.shift() == (int)size, "bad shift");
505 i->f(_ext.shift() > 0, 12);
506 }
507 i->f(0b10, 11, 10);
508 }
509 break;
510
511 case pre:
512 i->f(0b00, 25, 24);
513 i->f(0, 21), i->f(0b11, 11, 10);
514 i->sf(_offset, 20, 12);
515 break;
516
517 case post:
518 i->f(0b00, 25, 24);
519 i->f(0, 21), i->f(0b01, 11, 10);
520 i->sf(_offset, 20, 12);
521 break;
522
523 default:
524 ShouldNotReachHere();
525 }
526 }
527
528 void encode_pair(Instruction_aarch64 *i) const {
529 switch(_mode) {
530 case base_plus_offset:
531 i->f(0b010, 25, 23);
532 break;
533 case pre:
534 i->f(0b011, 25, 23);
535 break;
536 case post:
537 i->f(0b001, 25, 23);
538 break;
539 default:
540 ShouldNotReachHere();
541 }
542
543 unsigned size; // Operand shift in 32-bit words
544
545 if (i->get(26, 26)) { // float
546 switch(i->get(31, 30)) {
547 case 0b10:
548 size = 2; break;
549 case 0b01:
550 size = 1; break;
551 case 0b00:
552 size = 0; break;
553 default:
554 ShouldNotReachHere();
555 }
556 } else {
557 size = i->get(31, 31);
558 }
559
560 size = 4 << size;
561 guarantee(_offset % size == 0, "bad offset");
562 i->sf(_offset / size, 21, 15);
563 i->srf(_base, 5);
564 }
565
566 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
567 // Only base + offset is allowed
568 i->f(0b000, 25, 23);
569 unsigned size = i->get(31, 31);
570 size = 4 << size;
571 guarantee(_offset % size == 0, "bad offset");
572 i->sf(_offset / size, 21, 15);
573 i->srf(_base, 5);
574 guarantee(_mode == Address::base_plus_offset,
575 "Bad addressing mode for non-temporal op");
576 }
577
578 void lea(MacroAssembler *, Register) const;
579
580 static bool offset_ok_for_immed(long offset, int shift = 0) {
581 unsigned mask = (1 << shift) - 1;
582 if (offset < 0 || offset & mask) {
583 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
584 } else {
585 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
586 }
587 }
588 };
589
590 // Convience classes
591 class RuntimeAddress: public Address {
592
593 public:
594
595 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
596
597 };
598
599 class OopAddress: public Address {
600
601 public:
602
603 OopAddress(address target) : Address(target, relocInfo::oop_type){}
604
605 };
606
607 class ExternalAddress: public Address {
608 private:
609 static relocInfo::relocType reloc_for_target(address target) {
610 // Sometimes ExternalAddress is used for values which aren't
611 // exactly addresses, like the card table base.
612 // external_word_type can't be used for values in the first page
613 // so just skip the reloc in that case.
614 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
615 }
616
617 public:
618
619 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
620
621 };
622
623 class InternalAddress: public Address {
624
625 public:
626
627 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
628 };
629
630 const int FPUStateSizeInWords = 32 * 2;
631 typedef enum {
632 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
633 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
634 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
635 } prfop;
636
637 class Assembler : public AbstractAssembler {
638
639 #ifndef PRODUCT
640 static const unsigned long asm_bp;
641
642 void emit_long(jint x) {
643 if ((unsigned long)pc() == asm_bp)
644 asm volatile ("nop");
645 AbstractAssembler::emit_int32(x);
646 }
647 #else
648 void emit_long(jint x) {
649 AbstractAssembler::emit_int32(x);
650 }
651 #endif
652
653 public:
654
655 enum { instruction_size = 4 };
656
657 Address adjust(Register base, int offset, bool preIncrement) {
658 if (preIncrement)
659 return Address(Pre(base, offset));
660 else
661 return Address(Post(base, offset));
662 }
663
664 Address pre(Register base, int offset) {
665 return adjust(base, offset, true);
666 }
667
668 Address post (Register base, int offset) {
669 return adjust(base, offset, false);
670 }
671
672 Instruction_aarch64* current;
673
674 void set_current(Instruction_aarch64* i) { current = i; }
675
676 void f(unsigned val, int msb, int lsb) {
677 current->f(val, msb, lsb);
678 }
679 void f(unsigned val, int msb) {
680 current->f(val, msb, msb);
681 }
682 void sf(long val, int msb, int lsb) {
683 current->sf(val, msb, lsb);
684 }
685 void rf(Register reg, int lsb) {
686 current->rf(reg, lsb);
687 }
688 void srf(Register reg, int lsb) {
689 current->srf(reg, lsb);
690 }
691 void zrf(Register reg, int lsb) {
692 current->zrf(reg, lsb);
693 }
694 void rf(FloatRegister reg, int lsb) {
695 current->rf(reg, lsb);
696 }
697 void fixed(unsigned value, unsigned mask) {
698 current->fixed(value, mask);
699 }
700
701 void emit() {
702 emit_long(current->get_insn());
703 assert_cond(current->get_bits() == 0xffffffff);
704 current = NULL;
705 }
706
707 typedef void (Assembler::* uncond_branch_insn)(address dest);
708 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
709 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
710 typedef void (Assembler::* prefetch_insn)(address target, prfop);
711
712 void wrap_label(Label &L, uncond_branch_insn insn);
713 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
714 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
715 void wrap_label(Label &L, prfop, prefetch_insn insn);
716
717 // PC-rel. addressing
718
719 void adr(Register Rd, address dest);
720 void _adrp(Register Rd, address dest);
721
722 void adr(Register Rd, const Address &dest);
723 void _adrp(Register Rd, const Address &dest);
724
725 void adr(Register Rd, Label &L) {
726 wrap_label(Rd, L, &Assembler::Assembler::adr);
727 }
728 void _adrp(Register Rd, Label &L) {
729 wrap_label(Rd, L, &Assembler::_adrp);
730 }
731
732 void adrp(Register Rd, const Address &dest, unsigned long &offset);
733
734 #undef INSN
735
736 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
737 int negated_op);
738
739 // Add/subtract (immediate)
740 #define INSN(NAME, decode, negated) \
741 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
742 starti; \
743 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
744 zrf(Rd, 0), srf(Rn, 5); \
745 } \
746 \
747 void NAME(Register Rd, Register Rn, unsigned imm) { \
748 starti; \
749 add_sub_immediate(Rd, Rn, imm, decode, negated); \
750 }
751
752 INSN(addsw, 0b001, 0b011);
753 INSN(subsw, 0b011, 0b001);
754 INSN(adds, 0b101, 0b111);
755 INSN(subs, 0b111, 0b101);
756
757 #undef INSN
758
759 #define INSN(NAME, decode, negated) \
760 void NAME(Register Rd, Register Rn, unsigned imm) { \
761 starti; \
762 add_sub_immediate(Rd, Rn, imm, decode, negated); \
763 }
764
765 INSN(addw, 0b000, 0b010);
766 INSN(subw, 0b010, 0b000);
767 INSN(add, 0b100, 0b110);
768 INSN(sub, 0b110, 0b100);
769
770 #undef INSN
771
772 // Logical (immediate)
773 #define INSN(NAME, decode, is32) \
774 void NAME(Register Rd, Register Rn, uint64_t imm) { \
775 starti; \
776 uint32_t val = encode_logical_immediate(is32, imm); \
777 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
778 srf(Rd, 0), zrf(Rn, 5); \
779 }
780
781 INSN(andw, 0b000, true);
782 INSN(orrw, 0b001, true);
783 INSN(eorw, 0b010, true);
784 INSN(andr, 0b100, false);
785 INSN(orr, 0b101, false);
786 INSN(eor, 0b110, false);
787
788 #undef INSN
789
790 #define INSN(NAME, decode, is32) \
791 void NAME(Register Rd, Register Rn, uint64_t imm) { \
792 starti; \
793 uint32_t val = encode_logical_immediate(is32, imm); \
794 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
795 zrf(Rd, 0), zrf(Rn, 5); \
796 }
797
798 INSN(ands, 0b111, false);
799 INSN(andsw, 0b011, true);
800
801 #undef INSN
802
803 // Move wide (immediate)
804 #define INSN(NAME, opcode) \
805 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
806 assert_cond((shift/16)*16 == shift); \
807 starti; \
808 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
809 f(imm, 20, 5); \
810 rf(Rd, 0); \
811 }
812
813 INSN(movnw, 0b000);
814 INSN(movzw, 0b010);
815 INSN(movkw, 0b011);
816 INSN(movn, 0b100);
817 INSN(movz, 0b110);
818 INSN(movk, 0b111);
819
820 #undef INSN
821
822 // Bitfield
823 #define INSN(NAME, opcode) \
824 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
825 starti; \
826 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
827 rf(Rn, 5), rf(Rd, 0); \
828 }
829
830 INSN(sbfmw, 0b0001001100);
831 INSN(bfmw, 0b0011001100);
832 INSN(ubfmw, 0b0101001100);
833 INSN(sbfm, 0b1001001101);
834 INSN(bfm, 0b1011001101);
835 INSN(ubfm, 0b1101001101);
836
837 #undef INSN
838
839 // Extract
840 #define INSN(NAME, opcode) \
841 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
842 starti; \
843 f(opcode, 31, 21), f(imms, 15, 10); \
844 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
845 }
846
847 INSN(extrw, 0b00010011100);
848 INSN(extr, 0b10010011110);
849
850 #undef INSN
851
852 // Unconditional branch (immediate)
853 #define INSN(NAME, opcode) \
854 void NAME(address dest) { \
855 starti; \
856 long offset = (dest - pc()) >> 2; \
857 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
858 } \
859 void NAME(Label &L) { \
860 wrap_label(L, &Assembler::NAME); \
861 } \
862 void NAME(const Address &dest);
863
864 INSN(b, 0);
865 INSN(bl, 1);
866
867 #undef INSN
868
869 // Compare & branch (immediate)
870 #define INSN(NAME, opcode) \
871 void NAME(Register Rt, address dest) { \
872 long offset = (dest - pc()) >> 2; \
873 starti; \
874 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
875 } \
876 void NAME(Register Rt, Label &L) { \
877 wrap_label(Rt, L, &Assembler::NAME); \
878 }
879
880 INSN(cbzw, 0b00110100);
881 INSN(cbnzw, 0b00110101);
882 INSN(cbz, 0b10110100);
883 INSN(cbnz, 0b10110101);
884
885 #undef INSN
886
887 // Test & branch (immediate)
888 #define INSN(NAME, opcode) \
889 void NAME(Register Rt, int bitpos, address dest) { \
890 long offset = (dest - pc()) >> 2; \
891 int b5 = bitpos >> 5; \
892 bitpos &= 0x1f; \
893 starti; \
894 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
895 rf(Rt, 0); \
896 } \
897 void NAME(Register Rt, int bitpos, Label &L) { \
898 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
899 }
900
901 INSN(tbz, 0b0110110);
902 INSN(tbnz, 0b0110111);
903
904 #undef INSN
905
906 // Conditional branch (immediate)
907 enum Condition
908 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
909
910 void br(Condition cond, address dest) {
911 long offset = (dest - pc()) >> 2;
912 starti;
913 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
914 }
915
916 #define INSN(NAME, cond) \
917 void NAME(address dest) { \
918 br(cond, dest); \
919 }
920
921 INSN(beq, EQ);
922 INSN(bne, NE);
923 INSN(bhs, HS);
924 INSN(bcs, CS);
925 INSN(blo, LO);
926 INSN(bcc, CC);
927 INSN(bmi, MI);
928 INSN(bpl, PL);
929 INSN(bvs, VS);
930 INSN(bvc, VC);
931 INSN(bhi, HI);
932 INSN(bls, LS);
933 INSN(bge, GE);
934 INSN(blt, LT);
935 INSN(bgt, GT);
936 INSN(ble, LE);
937 INSN(bal, AL);
938 INSN(bnv, NV);
939
940 void br(Condition cc, Label &L);
941
942 #undef INSN
943
944 // Exception generation
945 void generate_exception(int opc, int op2, int LL, unsigned imm) {
946 starti;
947 f(0b11010100, 31, 24);
948 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
949 }
950
951 #define INSN(NAME, opc, op2, LL) \
952 void NAME(unsigned imm) { \
953 generate_exception(opc, op2, LL, imm); \
954 }
955
956 INSN(svc, 0b000, 0, 0b01);
957 INSN(hvc, 0b000, 0, 0b10);
958 INSN(smc, 0b000, 0, 0b11);
959 INSN(brk, 0b001, 0, 0b00);
960 INSN(hlt, 0b010, 0, 0b00);
961 INSN(dpcs1, 0b101, 0, 0b01);
962 INSN(dpcs2, 0b101, 0, 0b10);
963 INSN(dpcs3, 0b101, 0, 0b11);
964
965 #undef INSN
966
967 // System
968 void system(int op0, int op1, int CRn, int CRm, int op2,
969 Register rt = (Register)0b11111)
970 {
971 starti;
972 f(0b11010101000, 31, 21);
973 f(op0, 20, 19);
974 f(op1, 18, 16);
975 f(CRn, 15, 12);
976 f(CRm, 11, 8);
977 f(op2, 7, 5);
978 rf(rt, 0);
979 }
980
981 void hint(int imm) {
982 system(0b00, 0b011, 0b0010, imm, 0b000);
983 }
984
985 void nop() {
986 hint(0);
987 }
988 // we only provide mrs and msr for the special purpose system
989 // registers where op1 (instr[20:19]) == 11 and, (currently) only
990 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
991
992 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
993 starti;
994 f(0b1101010100011, 31, 19);
995 f(op1, 18, 16);
996 f(CRn, 15, 12);
997 f(CRm, 11, 8);
998 f(op2, 7, 5);
999 // writing zr is ok
1000 zrf(rt, 0);
1001 }
1002
1003 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1004 starti;
1005 f(0b1101010100111, 31, 19);
1006 f(op1, 18, 16);
1007 f(CRn, 15, 12);
1008 f(CRm, 11, 8);
1009 f(op2, 7, 5);
1010 // reading to zr is a mistake
1011 rf(rt, 0);
1012 }
1013
1014 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1015 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1016
1017 void dsb(barrier imm) {
1018 system(0b00, 0b011, 0b00011, imm, 0b100);
1019 }
1020
1021 void dmb(barrier imm) {
1022 system(0b00, 0b011, 0b00011, imm, 0b101);
1023 }
1024
1025 void isb() {
1026 system(0b00, 0b011, 0b00011, SY, 0b110);
1027 }
1028
1029 void dc(Register Rt) {
1030 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt);
1031 }
1032
1033 void ic(Register Rt) {
1034 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
1035 }
1036
1037 // A more convenient access to dmb for our purposes
1038 enum Membar_mask_bits {
1039 // We can use ISH for a barrier because the ARM ARM says "This
1040 // architecture assumes that all Processing Elements that use the
1041 // same operating system or hypervisor are in the same Inner
1042 // Shareable shareability domain."
1043 StoreStore = ISHST,
1044 LoadStore = ISHLD,
1045 LoadLoad = ISHLD,
1046 StoreLoad = ISH,
1047 AnyAny = ISH
1048 };
1049
1050 void membar(Membar_mask_bits order_constraint) {
1051 dmb(Assembler::barrier(order_constraint));
1052 }
1053
1054 // Unconditional branch (register)
1055 void branch_reg(Register R, int opc) {
1056 starti;
1057 f(0b1101011, 31, 25);
1058 f(opc, 24, 21);
1059 f(0b11111000000, 20, 10);
1060 rf(R, 5);
1061 f(0b00000, 4, 0);
1062 }
1063
1064 #define INSN(NAME, opc) \
1065 void NAME(Register R) { \
1066 branch_reg(R, opc); \
1067 }
1068
1069 INSN(br, 0b0000);
1070 INSN(blr, 0b0001);
1071 INSN(ret, 0b0010);
1072
1073 void ret(void *p); // This forces a compile-time error for ret(0)
1074
1075 #undef INSN
1076
1077 #define INSN(NAME, opc) \
1078 void NAME() { \
1079 branch_reg((Register)0b11111, opc); \
1080 }
1081
1082 INSN(eret, 0b0100);
1083 INSN(drps, 0b0101);
1084
1085 #undef INSN
1086
1087 // Load/store exclusive
1088 enum operand_size { byte, halfword, word, xword };
1089
1090 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1091 Register Rn, enum operand_size sz, int op, int o0) {
1092 starti;
1093 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1094 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1095 }
1096
1097 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1098 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1099 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1100 }
1101
1102 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1103 void NAME(Register Rs, Register Rt, Register Rn) { \
1104 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \
1105 }
1106
1107 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1108 void NAME(Register Rt, Register Rn) { \
1109 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \
1110 Rn, sz, op, o0); \
1111 }
1112
1113 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1114 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1115 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \
1116 }
1117
1118 // bytes
1119 INSN3(stxrb, byte, 0b000, 0);
1120 INSN3(stlxrb, byte, 0b000, 1);
1121 INSN2(ldxrb, byte, 0b010, 0);
1122 INSN2(ldaxrb, byte, 0b010, 1);
1123 INSN2(stlrb, byte, 0b100, 1);
1124 INSN2(ldarb, byte, 0b110, 1);
1125
1126 // halfwords
1127 INSN3(stxrh, halfword, 0b000, 0);
1128 INSN3(stlxrh, halfword, 0b000, 1);
1129 INSN2(ldxrh, halfword, 0b010, 0);
1130 INSN2(ldaxrh, halfword, 0b010, 1);
1131 INSN2(stlrh, halfword, 0b100, 1);
1132 INSN2(ldarh, halfword, 0b110, 1);
1133
1134 // words
1135 INSN3(stxrw, word, 0b000, 0);
1136 INSN3(stlxrw, word, 0b000, 1);
1137 INSN4(stxpw, word, 0b001, 0);
1138 INSN4(stlxpw, word, 0b001, 1);
1139 INSN2(ldxrw, word, 0b010, 0);
1140 INSN2(ldaxrw, word, 0b010, 1);
1141 INSN_FOO(ldxpw, word, 0b011, 0);
1142 INSN_FOO(ldaxpw, word, 0b011, 1);
1143 INSN2(stlrw, word, 0b100, 1);
1144 INSN2(ldarw, word, 0b110, 1);
1145
1146 // xwords
1147 INSN3(stxr, xword, 0b000, 0);
1148 INSN3(stlxr, xword, 0b000, 1);
1149 INSN4(stxp, xword, 0b001, 0);
1150 INSN4(stlxp, xword, 0b001, 1);
1151 INSN2(ldxr, xword, 0b010, 0);
1152 INSN2(ldaxr, xword, 0b010, 1);
1153 INSN_FOO(ldxp, xword, 0b011, 0);
1154 INSN_FOO(ldaxp, xword, 0b011, 1);
1155 INSN2(stlr, xword, 0b100, 1);
1156 INSN2(ldar, xword, 0b110, 1);
1157
1158 #undef INSN2
1159 #undef INSN3
1160 #undef INSN4
1161 #undef INSN_FOO
1162
1163 // Load register (literal)
1164 #define INSN(NAME, opc, V) \
1165 void NAME(Register Rt, address dest) { \
1166 long offset = (dest - pc()) >> 2; \
1167 starti; \
1168 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1169 sf(offset, 23, 5); \
1170 rf(Rt, 0); \
1171 } \
1172 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1173 InstructionMark im(this); \
1174 guarantee(rtype == relocInfo::internal_word_type, \
1175 "only internal_word_type relocs make sense here"); \
1176 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1177 NAME(Rt, dest); \
1178 } \
1179 void NAME(Register Rt, Label &L) { \
1180 wrap_label(Rt, L, &Assembler::NAME); \
1181 }
1182
1183 INSN(ldrw, 0b00, 0);
1184 INSN(ldr, 0b01, 0);
1185 INSN(ldrsw, 0b10, 0);
1186
1187 #undef INSN
1188
1189 #define INSN(NAME, opc, V) \
1190 void NAME(FloatRegister Rt, address dest) { \
1191 long offset = (dest - pc()) >> 2; \
1192 starti; \
1193 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1194 sf(offset, 23, 5); \
1195 rf((Register)Rt, 0); \
1196 }
1197
1198 INSN(ldrs, 0b00, 1);
1199 INSN(ldrd, 0b01, 1);
1200 INSN(ldrq, 0x10, 1);
1201
1202 #undef INSN
1203
1204 #define INSN(NAME, opc, V) \
1205 void NAME(address dest, prfop op = PLDL1KEEP) { \
1206 long offset = (dest - pc()) >> 2; \
1207 starti; \
1208 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1209 sf(offset, 23, 5); \
1210 f(op, 4, 0); \
1211 } \
1212 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1213 wrap_label(L, op, &Assembler::NAME); \
1214 }
1215
1216 INSN(prfm, 0b11, 0);
1217
1218 #undef INSN
1219
1220 // Load/store
1221 void ld_st1(int opc, int p1, int V, int L,
1222 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1223 starti;
1224 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1225 zrf(Rt2, 10), zrf(Rt1, 0);
1226 if (no_allocate) {
1227 adr.encode_nontemporal_pair(current);
1228 } else {
1229 adr.encode_pair(current);
1230 }
1231 }
1232
1233 // Load/store register pair (offset)
1234 #define INSN(NAME, size, p1, V, L, no_allocate) \
1235 void NAME(Register Rt1, Register Rt2, Address adr) { \
1236 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1237 }
1238
1239 INSN(stpw, 0b00, 0b101, 0, 0, false);
1240 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1241 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1242 INSN(stp, 0b10, 0b101, 0, 0, false);
1243 INSN(ldp, 0b10, 0b101, 0, 1, false);
1244
1245 // Load/store no-allocate pair (offset)
1246 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1247 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1248 INSN(stnp, 0b10, 0b101, 0, 0, true);
1249 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1250
1251 #undef INSN
1252
1253 #define INSN(NAME, size, p1, V, L, no_allocate) \
1254 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1255 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1256 }
1257
1258 INSN(stps, 0b00, 0b101, 1, 0, false);
1259 INSN(ldps, 0b00, 0b101, 1, 1, false);
1260 INSN(stpd, 0b01, 0b101, 1, 0, false);
1261 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1262 INSN(stpq, 0b10, 0b101, 1, 0, false);
1263 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1264
1265 #undef INSN
1266
1267 // Load/store register (all modes)
1268 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1269 starti;
1270
1271 f(V, 26); // general reg?
1272 zrf(Rt, 0);
1273
1274 // Encoding for literal loads is done here (rather than pushed
1275 // down into Address::encode) because the encoding of this
1276 // instruction is too different from all of the other forms to
1277 // make it worth sharing.
1278 if (adr.getMode() == Address::literal) {
1279 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1280 assert(op == 0b01, "literal form can only be used with loads");
1281 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1282 long offset = (adr.target() - pc()) >> 2;
1283 sf(offset, 23, 5);
1284 code_section()->relocate(pc(), adr.rspec());
1285 return;
1286 }
1287
1288 f(size, 31, 30);
1289 f(op, 23, 22); // str
1290 adr.encode(current);
1291 }
1292
1293 #define INSN(NAME, size, op) \
1294 void NAME(Register Rt, const Address &adr) { \
1295 ld_st2(Rt, adr, size, op); \
1296 } \
1297
1298 INSN(str, 0b11, 0b00);
1299 INSN(strw, 0b10, 0b00);
1300 INSN(strb, 0b00, 0b00);
1301 INSN(strh, 0b01, 0b00);
1302
1303 INSN(ldr, 0b11, 0b01);
1304 INSN(ldrw, 0b10, 0b01);
1305 INSN(ldrb, 0b00, 0b01);
1306 INSN(ldrh, 0b01, 0b01);
1307
1308 INSN(ldrsb, 0b00, 0b10);
1309 INSN(ldrsbw, 0b00, 0b11);
1310 INSN(ldrsh, 0b01, 0b10);
1311 INSN(ldrshw, 0b01, 0b11);
1312 INSN(ldrsw, 0b10, 0b10);
1313
1314 #undef INSN
1315
1316 #define INSN(NAME, size, op) \
1317 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1318 ld_st2((Register)pfop, adr, size, op); \
1319 }
1320
1321 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1322 // writeback modes, but the assembler
1323 // doesn't enfore that.
1324
1325 #undef INSN
1326
1327 #define INSN(NAME, size, op) \
1328 void NAME(FloatRegister Rt, const Address &adr) { \
1329 ld_st2((Register)Rt, adr, size, op, 1); \
1330 }
1331
1332 INSN(strd, 0b11, 0b00);
1333 INSN(strs, 0b10, 0b00);
1334 INSN(ldrd, 0b11, 0b01);
1335 INSN(ldrs, 0b10, 0b01);
1336 INSN(strq, 0b00, 0b10);
1337 INSN(ldrq, 0x00, 0b11);
1338
1339 #undef INSN
1340
1341 enum shift_kind { LSL, LSR, ASR, ROR };
1342
1343 void op_shifted_reg(unsigned decode,
1344 enum shift_kind kind, unsigned shift,
1345 unsigned size, unsigned op) {
1346 f(size, 31);
1347 f(op, 30, 29);
1348 f(decode, 28, 24);
1349 f(shift, 15, 10);
1350 f(kind, 23, 22);
1351 }
1352
1353 // Logical (shifted register)
1354 #define INSN(NAME, size, op, N) \
1355 void NAME(Register Rd, Register Rn, Register Rm, \
1356 enum shift_kind kind = LSL, unsigned shift = 0) { \
1357 starti; \
1358 f(N, 21); \
1359 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1360 op_shifted_reg(0b01010, kind, shift, size, op); \
1361 }
1362
1363 INSN(andr, 1, 0b00, 0);
1364 INSN(orr, 1, 0b01, 0);
1365 INSN(eor, 1, 0b10, 0);
1366 INSN(ands, 1, 0b11, 0);
1367 INSN(andw, 0, 0b00, 0);
1368 INSN(orrw, 0, 0b01, 0);
1369 INSN(eorw, 0, 0b10, 0);
1370 INSN(andsw, 0, 0b11, 0);
1371
1372 INSN(bic, 1, 0b00, 1);
1373 INSN(orn, 1, 0b01, 1);
1374 INSN(eon, 1, 0b10, 1);
1375 INSN(bics, 1, 0b11, 1);
1376 INSN(bicw, 0, 0b00, 1);
1377 INSN(ornw, 0, 0b01, 1);
1378 INSN(eonw, 0, 0b10, 1);
1379 INSN(bicsw, 0, 0b11, 1);
1380
1381 #undef INSN
1382
1383 // Add/subtract (shifted register)
1384 #define INSN(NAME, size, op) \
1385 void NAME(Register Rd, Register Rn, Register Rm, \
1386 enum shift_kind kind, unsigned shift = 0) { \
1387 starti; \
1388 f(0, 21); \
1389 assert_cond(kind != ROR); \
1390 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1391 op_shifted_reg(0b01011, kind, shift, size, op); \
1392 }
1393
1394 INSN(add, 1, 0b000);
1395 INSN(sub, 1, 0b10);
1396 INSN(addw, 0, 0b000);
1397 INSN(subw, 0, 0b10);
1398
1399 INSN(adds, 1, 0b001);
1400 INSN(subs, 1, 0b11);
1401 INSN(addsw, 0, 0b001);
1402 INSN(subsw, 0, 0b11);
1403
1404 #undef INSN
1405
1406 // Add/subtract (extended register)
1407 #define INSN(NAME, op) \
1408 void NAME(Register Rd, Register Rn, Register Rm, \
1409 ext::operation option, int amount = 0) { \
1410 starti; \
1411 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1412 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1413 }
1414
1415 void add_sub_extended_reg(unsigned op, unsigned decode,
1416 Register Rd, Register Rn, Register Rm,
1417 unsigned opt, ext::operation option, unsigned imm) {
1418 guarantee(imm <= 4, "shift amount must be < 4");
1419 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1420 f(option, 15, 13), f(imm, 12, 10);
1421 }
1422
1423 INSN(addw, 0b000);
1424 INSN(subw, 0b010);
1425 INSN(add, 0b100);
1426 INSN(sub, 0b110);
1427
1428 #undef INSN
1429
1430 #define INSN(NAME, op) \
1431 void NAME(Register Rd, Register Rn, Register Rm, \
1432 ext::operation option, int amount = 0) { \
1433 starti; \
1434 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1435 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1436 }
1437
1438 INSN(addsw, 0b001);
1439 INSN(subsw, 0b011);
1440 INSN(adds, 0b101);
1441 INSN(subs, 0b111);
1442
1443 #undef INSN
1444
1445 // Aliases for short forms of add and sub
1446 #define INSN(NAME) \
1447 void NAME(Register Rd, Register Rn, Register Rm) { \
1448 if (Rd == sp || Rn == sp) \
1449 NAME(Rd, Rn, Rm, ext::uxtx); \
1450 else \
1451 NAME(Rd, Rn, Rm, LSL); \
1452 }
1453
1454 INSN(addw);
1455 INSN(subw);
1456 INSN(add);
1457 INSN(sub);
1458
1459 INSN(addsw);
1460 INSN(subsw);
1461 INSN(adds);
1462 INSN(subs);
1463
1464 #undef INSN
1465
1466 // Add/subtract (with carry)
1467 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1468 starti;
1469 f(op, 31, 29);
1470 f(0b11010000, 28, 21);
1471 f(0b000000, 15, 10);
1472 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1473 }
1474
1475 #define INSN(NAME, op) \
1476 void NAME(Register Rd, Register Rn, Register Rm) { \
1477 add_sub_carry(op, Rd, Rn, Rm); \
1478 }
1479
1480 INSN(adcw, 0b000);
1481 INSN(adcsw, 0b001);
1482 INSN(sbcw, 0b010);
1483 INSN(sbcsw, 0b011);
1484 INSN(adc, 0b100);
1485 INSN(adcs, 0b101);
1486 INSN(sbc,0b110);
1487 INSN(sbcs, 0b111);
1488
1489 #undef INSN
1490
1491 // Conditional compare (both kinds)
1492 void conditional_compare(unsigned op, int o2, int o3,
1493 Register Rn, unsigned imm5, unsigned nzcv,
1494 unsigned cond) {
1495 f(op, 31, 29);
1496 f(0b11010010, 28, 21);
1497 f(cond, 15, 12);
1498 f(o2, 10);
1499 f(o3, 4);
1500 f(nzcv, 3, 0);
1501 f(imm5, 20, 16), rf(Rn, 5);
1502 }
1503
1504 #define INSN(NAME, op) \
1505 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1506 starti; \
1507 f(0, 11); \
1508 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \
1509 } \
1510 \
1511 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1512 starti; \
1513 f(1, 11); \
1514 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \
1515 }
1516
1517 INSN(ccmnw, 0b001);
1518 INSN(ccmpw, 0b011);
1519 INSN(ccmn, 0b101);
1520 INSN(ccmp, 0b111);
1521
1522 #undef INSN
1523
1524 // Conditional select
1525 void conditional_select(unsigned op, unsigned op2,
1526 Register Rd, Register Rn, Register Rm,
1527 unsigned cond) {
1528 starti;
1529 f(op, 31, 29);
1530 f(0b11010100, 28, 21);
1531 f(cond, 15, 12);
1532 f(op2, 11, 10);
1533 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1534 }
1535
1536 #define INSN(NAME, op, op2) \
1537 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1538 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1539 }
1540
1541 INSN(cselw, 0b000, 0b00);
1542 INSN(csincw, 0b000, 0b01);
1543 INSN(csinvw, 0b010, 0b00);
1544 INSN(csnegw, 0b010, 0b01);
1545 INSN(csel, 0b100, 0b00);
1546 INSN(csinc, 0b100, 0b01);
1547 INSN(csinv, 0b110, 0b00);
1548 INSN(csneg, 0b110, 0b01);
1549
1550 #undef INSN
1551
1552 // Data processing
1553 void data_processing(unsigned op29, unsigned opcode,
1554 Register Rd, Register Rn) {
1555 f(op29, 31, 29), f(0b11010110, 28, 21);
1556 f(opcode, 15, 10);
1557 rf(Rn, 5), rf(Rd, 0);
1558 }
1559
1560 // (1 source)
1561 #define INSN(NAME, op29, opcode2, opcode) \
1562 void NAME(Register Rd, Register Rn) { \
1563 starti; \
1564 f(opcode2, 20, 16); \
1565 data_processing(op29, opcode, Rd, Rn); \
1566 }
1567
1568 INSN(rbitw, 0b010, 0b00000, 0b00000);
1569 INSN(rev16w, 0b010, 0b00000, 0b00001);
1570 INSN(revw, 0b010, 0b00000, 0b00010);
1571 INSN(clzw, 0b010, 0b00000, 0b00100);
1572 INSN(clsw, 0b010, 0b00000, 0b00101);
1573
1574 INSN(rbit, 0b110, 0b00000, 0b00000);
1575 INSN(rev16, 0b110, 0b00000, 0b00001);
1576 INSN(rev32, 0b110, 0b00000, 0b00010);
1577 INSN(rev, 0b110, 0b00000, 0b00011);
1578 INSN(clz, 0b110, 0b00000, 0b00100);
1579 INSN(cls, 0b110, 0b00000, 0b00101);
1580
1581 #undef INSN
1582
1583 // (2 sources)
1584 #define INSN(NAME, op29, opcode) \
1585 void NAME(Register Rd, Register Rn, Register Rm) { \
1586 starti; \
1587 rf(Rm, 16); \
1588 data_processing(op29, opcode, Rd, Rn); \
1589 }
1590
1591 INSN(udivw, 0b000, 0b000010);
1592 INSN(sdivw, 0b000, 0b000011);
1593 INSN(lslvw, 0b000, 0b001000);
1594 INSN(lsrvw, 0b000, 0b001001);
1595 INSN(asrvw, 0b000, 0b001010);
1596 INSN(rorvw, 0b000, 0b001011);
1597
1598 INSN(udiv, 0b100, 0b000010);
1599 INSN(sdiv, 0b100, 0b000011);
1600 INSN(lslv, 0b100, 0b001000);
1601 INSN(lsrv, 0b100, 0b001001);
1602 INSN(asrv, 0b100, 0b001010);
1603 INSN(rorv, 0b100, 0b001011);
1604
1605 #undef INSN
1606
1607 // (3 sources)
1608 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1609 Register Rd, Register Rn, Register Rm,
1610 Register Ra) {
1611 starti;
1612 f(op54, 31, 29), f(0b11011, 28, 24);
1613 f(op31, 23, 21), f(o0, 15);
1614 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1615 }
1616
1617 #define INSN(NAME, op54, op31, o0) \
1618 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1619 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1620 }
1621
1622 INSN(maddw, 0b000, 0b000, 0);
1623 INSN(msubw, 0b000, 0b000, 1);
1624 INSN(madd, 0b100, 0b000, 0);
1625 INSN(msub, 0b100, 0b000, 1);
1626 INSN(smaddl, 0b100, 0b001, 0);
1627 INSN(smsubl, 0b100, 0b001, 1);
1628 INSN(umaddl, 0b100, 0b101, 0);
1629 INSN(umsubl, 0b100, 0b101, 1);
1630
1631 #undef INSN
1632
1633 #define INSN(NAME, op54, op31, o0) \
1634 void NAME(Register Rd, Register Rn, Register Rm) { \
1635 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1636 }
1637
1638 INSN(smulh, 0b100, 0b010, 0);
1639 INSN(umulh, 0b100, 0b110, 0);
1640
1641 #undef INSN
1642
1643 // Floating-point data-processing (1 source)
1644 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1645 FloatRegister Vd, FloatRegister Vn) {
1646 starti;
1647 f(op31, 31, 29);
1648 f(0b11110, 28, 24);
1649 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1650 rf(Vn, 5), rf(Vd, 0);
1651 }
1652
1653 #define INSN(NAME, op31, type, opcode) \
1654 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1655 data_processing(op31, type, opcode, Vd, Vn); \
1656 }
1657
1658 private:
1659 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1660 public:
1661 INSN(fabss, 0b000, 0b00, 0b000001);
1662 INSN(fnegs, 0b000, 0b00, 0b000010);
1663 INSN(fsqrts, 0b000, 0b00, 0b000011);
1664 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1665
1666 private:
1667 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1668 public:
1669 INSN(fabsd, 0b000, 0b01, 0b000001);
1670 INSN(fnegd, 0b000, 0b01, 0b000010);
1671 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1672 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1673
1674 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1675 assert(Vd != Vn, "should be");
1676 i_fmovd(Vd, Vn);
1677 }
1678
1679 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1680 assert(Vd != Vn, "should be");
1681 i_fmovs(Vd, Vn);
1682 }
1683
1684 #undef INSN
1685
1686 // Floating-point data-processing (2 source)
1687 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1688 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1689 starti;
1690 f(op31, 31, 29);
1691 f(0b11110, 28, 24);
1692 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1693 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1694 }
1695
1696 #define INSN(NAME, op31, type, opcode) \
1697 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1698 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1699 }
1700
1701 INSN(fmuls, 0b000, 0b00, 0b0000);
1702 INSN(fdivs, 0b000, 0b00, 0b0001);
1703 INSN(fadds, 0b000, 0b00, 0b0010);
1704 INSN(fsubs, 0b000, 0b00, 0b0011);
1705 INSN(fnmuls, 0b000, 0b00, 0b1000);
1706
1707 INSN(fmuld, 0b000, 0b01, 0b0000);
1708 INSN(fdivd, 0b000, 0b01, 0b0001);
1709 INSN(faddd, 0b000, 0b01, 0b0010);
1710 INSN(fsubd, 0b000, 0b01, 0b0011);
1711 INSN(fnmuld, 0b000, 0b01, 0b1000);
1712
1713 #undef INSN
1714
1715 // Floating-point data-processing (3 source)
1716 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1717 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1718 FloatRegister Va) {
1719 starti;
1720 f(op31, 31, 29);
1721 f(0b11111, 28, 24);
1722 f(type, 23, 22), f(o1, 21), f(o0, 15);
1723 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1724 }
1725
1726 #define INSN(NAME, op31, type, o1, o0) \
1727 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1728 FloatRegister Va) { \
1729 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1730 }
1731
1732 INSN(fmadds, 0b000, 0b00, 0, 0);
1733 INSN(fmsubs, 0b000, 0b00, 0, 1);
1734 INSN(fnmadds, 0b000, 0b00, 1, 0);
1735 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1736
1737 INSN(fmaddd, 0b000, 0b01, 0, 0);
1738 INSN(fmsubd, 0b000, 0b01, 0, 1);
1739 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1740 INSN(fnmsub, 0b000, 0b01, 1, 1);
1741
1742 #undef INSN
1743
1744 // Floating-point conditional select
1745 void fp_conditional_select(unsigned op31, unsigned type,
1746 unsigned op1, unsigned op2,
1747 Condition cond, FloatRegister Vd,
1748 FloatRegister Vn, FloatRegister Vm) {
1749 starti;
1750 f(op31, 31, 29);
1751 f(0b11110, 28, 24);
1752 f(type, 23, 22);
1753 f(op1, 21, 21);
1754 f(op2, 11, 10);
1755 f(cond, 15, 12);
1756 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1757 }
1758
1759 #define INSN(NAME, op31, type, op1, op2) \
1760 void NAME(FloatRegister Vd, FloatRegister Vn, \
1761 FloatRegister Vm, Condition cond) { \
1762 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1763 }
1764
1765 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1766 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1767
1768 #undef INSN
1769
1770 // Floating-point<->integer conversions
1771 void float_int_convert(unsigned op31, unsigned type,
1772 unsigned rmode, unsigned opcode,
1773 Register Rd, Register Rn) {
1774 starti;
1775 f(op31, 31, 29);
1776 f(0b11110, 28, 24);
1777 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1778 f(opcode, 18, 16), f(0b000000, 15, 10);
1779 zrf(Rn, 5), zrf(Rd, 0);
1780 }
1781
1782 #define INSN(NAME, op31, type, rmode, opcode) \
1783 void NAME(Register Rd, FloatRegister Vn) { \
1784 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1785 }
1786
1787 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1788 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1789 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1790 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1791
1792 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1793 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1794
1795 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1796
1797 #undef INSN
1798
1799 #define INSN(NAME, op31, type, rmode, opcode) \
1800 void NAME(FloatRegister Vd, Register Rn) { \
1801 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1802 }
1803
1804 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1805 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1806
1807 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1808 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1809 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1810 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1811
1812 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1813
1814 #undef INSN
1815
1816 // Floating-point compare
1817 void float_compare(unsigned op31, unsigned type,
1818 unsigned op, unsigned op2,
1819 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1820 starti;
1821 f(op31, 31, 29);
1822 f(0b11110, 28, 24);
1823 f(type, 23, 22), f(1, 21);
1824 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1825 rf(Vn, 5), rf(Vm, 16);
1826 }
1827
1828
1829 #define INSN(NAME, op31, type, op, op2) \
1830 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1831 float_compare(op31, type, op, op2, Vn, Vm); \
1832 }
1833
1834 #define INSN1(NAME, op31, type, op, op2) \
1835 void NAME(FloatRegister Vn, double d) { \
1836 assert_cond(d == 0.0); \
1837 float_compare(op31, type, op, op2, Vn); \
1838 }
1839
1840 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1841 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1842 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1843 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1844
1845 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1846 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1847 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1848 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1849
1850 #undef INSN
1851 #undef INSN1
1852
1853 // Floating-point Move (immediate)
1854 private:
1855 unsigned pack(double value);
1856
1857 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
1858 starti;
1859 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
1860 f(pack(value), 20, 13), f(0b10000000, 12, 5);
1861 rf(Vn, 0);
1862 }
1863
1864 public:
1865
1866 void fmovs(FloatRegister Vn, double value) {
1867 if (value)
1868 fmov_imm(Vn, value, 0b00);
1869 else
1870 fmovs(Vn, zr);
1871 }
1872 void fmovd(FloatRegister Vn, double value) {
1873 if (value)
1874 fmov_imm(Vn, value, 0b01);
1875 else
1876 fmovd(Vn, zr);
1877 }
1878
1879 /* SIMD extensions
1880 *
1881 * We just use FloatRegister in the following. They are exactly the same
1882 * as SIMD registers.
1883 */
1884 public:
1885
1886 enum SIMD_Arrangement {
1887 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D
1888 };
1889
1890 enum SIMD_RegVariant {
1891 B, H, S, D, Q
1892 };
1893
1894 #define INSN(NAME, op) \
1895 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
1896 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
1897 } \
1898
1899 INSN(ldr, 1);
1900 INSN(str, 0);
1901
1902 #undef INSN
1903
1904 private:
1905
1906 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
1907 starti;
1908 f(0,31), f((int)T & 1, 30);
1909 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
1910 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1911 }
1912 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1913 int imm, int op1, int op2) {
1914 starti;
1915 f(0,31), f((int)T & 1, 30);
1916 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
1917 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1918 }
1919 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1920 Register Xm, int op1, int op2) {
1921 starti;
1922 f(0,31), f((int)T & 1, 30);
1923 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
1924 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1925 }
1926
1927 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
1928 switch (a.getMode()) {
1929 case Address::base_plus_offset:
1930 guarantee(a.offset() == 0, "no offset allowed here");
1931 ld_st(Vt, T, a.base(), op1, op2);
1932 break;
1933 case Address::post:
1934 ld_st(Vt, T, a.base(), a.offset(), op1, op2);
1935 break;
1936 case Address::base_plus_offset_reg:
1937 ld_st(Vt, T, a.base(), a.index(), op1, op2);
1938 break;
1939 default:
1940 ShouldNotReachHere();
1941 }
1942 }
1943
1944 public:
1945
1946 #define INSN1(NAME, op1, op2) \
1947 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
1948 ld_st(Vt, T, a, op1, op2); \
1949 }
1950
1951 #define INSN2(NAME, op1, op2) \
1952 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
1953 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
1954 ld_st(Vt, T, a, op1, op2); \
1955 }
1956
1957 #define INSN3(NAME, op1, op2) \
1958 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1959 SIMD_Arrangement T, const Address &a) { \
1960 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
1961 "Registers must be ordered"); \
1962 ld_st(Vt, T, a, op1, op2); \
1963 }
1964
1965 #define INSN4(NAME, op1, op2) \
1966 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1967 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
1968 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
1969 Vt3->successor() == Vt4, "Registers must be ordered"); \
1970 ld_st(Vt, T, a, op1, op2); \
1971 }
1972
1973 INSN1(ld1, 0b001100010, 0b0111);
1974 INSN2(ld1, 0b001100010, 0b1010);
1975 INSN3(ld1, 0b001100010, 0b0110);
1976 INSN4(ld1, 0b001100010, 0b0010);
1977
1978 INSN2(ld2, 0b001100010, 0b1000);
1979 INSN3(ld3, 0b001100010, 0b0100);
1980 INSN4(ld4, 0b001100010, 0b0000);
1981
1982 INSN1(st1, 0b001100000, 0b0111);
1983 INSN2(st1, 0b001100000, 0b1010);
1984 INSN3(st1, 0b001100000, 0b0110);
1985 INSN4(st1, 0b001100000, 0b0010);
1986
1987 INSN2(st2, 0b001100000, 0b1000);
1988 INSN3(st3, 0b001100000, 0b0100);
1989 INSN4(st4, 0b001100000, 0b0000);
1990
1991 INSN1(ld1r, 0b001101010, 0b1100);
1992 INSN2(ld2r, 0b001101011, 0b1100);
1993 INSN3(ld3r, 0b001101010, 0b1110);
1994 INSN4(ld4r, 0b001101011, 0b1110);
1995
1996 #undef INSN1
1997 #undef INSN2
1998 #undef INSN3
1999 #undef INSN4
2000
2001 #define INSN(NAME, opc) \
2002 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2003 starti; \
2004 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2005 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2006 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2007 }
2008
2009 INSN(eor, 0b101110001);
2010 INSN(orr, 0b001110101);
2011 INSN(andr, 0b001110001);
2012 INSN(bic, 0b001110011);
2013 INSN(bif, 0b101110111);
2014 INSN(bit, 0b101110101);
2015 INSN(bsl, 0b101110011);
2016 INSN(orn, 0b001110111);
2017
2018 #undef INSN
2019
2020 #define INSN(NAME, opc, opc2) \
2021 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2022 starti; \
2023 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2024 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2025 rf(Vn, 5), rf(Vd, 0); \
2026 }
2027
2028 INSN(addv, 0, 0b100001);
2029 INSN(subv, 1, 0b100001);
2030 INSN(mulv, 0, 0b100111);
2031 INSN(sshl, 0, 0b010001);
2032 INSN(ushl, 1, 0b010001);
2033
2034 #undef INSN
2035
2036 #define INSN(NAME, opc, opc2) \
2037 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2038 starti; \
2039 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2040 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2041 rf(Vn, 5), rf(Vd, 0); \
2042 }
2043
2044 INSN(absr, 0, 0b100000101110);
2045 INSN(negr, 1, 0b100000101110);
2046 INSN(notr, 1, 0b100000010110);
2047 INSN(addv, 0, 0b110001101110);
2048 INSN(cls, 0, 0b100000010010);
2049 INSN(clz, 1, 0b100000010010);
2050 INSN(cnt, 0, 0b100000010110);
2051
2052 #undef INSN
2053
2054 #define INSN(NAME, op0, cmode0) \
2055 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2056 unsigned cmode = cmode0; \
2057 unsigned op = op0; \
2058 starti; \
2059 assert(lsl == 0 || \
2060 ((T == T4H || T == T8H) && lsl == 8) || \
2061 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2062 cmode |= lsl >> 2; \
2063 if (T == T4H || T == T8H) cmode |= 0b1000; \
2064 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2065 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2066 cmode = 0b1110; \
2067 if (T == T1D || T == T2D) op = 1; \
2068 } \
2069 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2070 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2071 rf(Vd, 0); \
2072 }
2073
2074 INSN(movi, 0, 0);
2075 INSN(orri, 0, 1);
2076 INSN(mvni, 1, 0);
2077 INSN(bici, 1, 1);
2078
2079 #undef INSN
2080
2081 #define INSN(NAME, op1, op2, op3) \
2082 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2083 starti; \
2084 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2085 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2086 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2087 }
2088
2089 INSN(fadd, 0, 0, 0b110101);
2090 INSN(fdiv, 1, 0, 0b111111);
2091 INSN(fmul, 1, 0, 0b110111);
2092 INSN(fsub, 0, 1, 0b110101);
2093
2094 #undef INSN
2095
2096 #define INSN(NAME, opc) \
2097 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2098 starti; \
2099 assert(T == T4S, "arrangement must be T4S"); \
2100 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2101 }
2102
2103 INSN(sha1c, 0b000000);
2104 INSN(sha1m, 0b001000);
2105 INSN(sha1p, 0b000100);
2106 INSN(sha1su0, 0b001100);
2107 INSN(sha256h2, 0b010100);
2108 INSN(sha256h, 0b010000);
2109 INSN(sha256su1, 0b011000);
2110
2111 #undef INSN
2112
2113 #define INSN(NAME, opc) \
2114 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2115 starti; \
2116 assert(T == T4S, "arrangement must be T4S"); \
2117 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2118 }
2119
2120 INSN(sha1h, 0b000010);
2121 INSN(sha1su1, 0b000110);
2122 INSN(sha256su0, 0b001010);
2123
2124 #undef INSN
2125
2126 #define INSN(NAME, opc) \
2127 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2128 starti; \
2129 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2130 }
2131
2132 INSN(aese, 0b0100111000101000010010);
2133 INSN(aesd, 0b0100111000101000010110);
2134 INSN(aesmc, 0b0100111000101000011010);
2135 INSN(aesimc, 0b0100111000101000011110);
2136
2137 #undef INSN
2138
2139 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2140 starti;
2141 assert(T != Q, "invalid register variant");
2142 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2143 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2144 }
2145
2146 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2147 starti;
2148 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2149 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2150 rf(Vn, 5), rf(Rd, 0);
2151 }
2152
2153 #define INSN(NAME, opc, opc2) \
2154 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2155 starti; \
2156 /* The encodings for the immh:immb fields (bits 22:16) are \
2157 * 0001 xxx 8B/16B, shift = xxx \
2158 * 001x xxx 4H/8H, shift = xxxx \
2159 * 01xx xxx 2S/4S, shift = xxxxx \
2160 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \
2161 */ \
2162 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2163 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2164 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2165 }
2166
2167 INSN(shl, 0, 0b010101);
2168 INSN(sshr, 0, 0b000001);
2169 INSN(ushr, 1, 0b000001);
2170
2171 #undef INSN
2172
2173 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2174 starti;
2175 /* The encodings for the immh:immb fields (bits 22:16) are
2176 * 0001 xxx 8H, 8B/16b shift = xxx
2177 * 001x xxx 4S, 4H/8H shift = xxxx
2178 * 01xx xxx 2D, 2S/4S shift = xxxxx
2179 * 1xxx xxx RESERVED
2180 */
2181 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2182 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2183 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2184 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2185 }
2186 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2187 ushll(Vd, Ta, Vn, Tb, shift);
2188 }
2189
2190 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
2191 starti;
2192 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
2193 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
2194 }
2195 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
2196 uzp1(Vd, Vn, Vm, T, 1);
2197 }
2198
2199 // Move from general purpose register
2200 // mov Vd.T[index], Rn
2201 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2202 starti;
2203 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2204 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2205 }
2206
2207 // Move to general purpose register
2208 // mov Rd, Vn.T[index]
2209 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2210 starti;
2211 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2212 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2213 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2214 }
2215
2216 // We do not handle the 1Q arrangement.
2217 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2218 starti;
2219 assert(Ta == T8H && (Tb == T8B || Tb == T16B), "Invalid Size specifier");
2220 f(0, 31), f(Tb & 1, 30), f(0b001110001, 29, 21), rf(Vm, 16), f(0b111000, 15, 10);
2221 rf(Vn, 5), rf(Vd, 0);
2222 }
2223 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2224 pmull(Vd, Ta, Vn, Vm, Tb);
2225 }
2226
2227 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2228 starti;
2229 int size_b = (int)Tb >> 1;
2230 int size_a = (int)Ta >> 1;
2231 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2232 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2233 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2234 }
2235
2236 void rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn)
2237 {
2238 starti;
2239 assert(T <= T8H, "must be one of T8B, T16B, T4H, T8H");
2240 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24);
2241 f(T <= T16B ? 0b00 : 0b01, 23, 22), f(0b100000000010, 21, 10);
2242 rf(Vn, 5), rf(Vd, 0);
2243 }
2244
2245 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2246 {
2247 starti;
2248 assert(T != T1D, "reserved encoding");
2249 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2250 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2251 }
2252
2253 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2254 {
2255 starti;
2256 assert(T != T1D, "reserved encoding");
2257 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2258 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2259 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2260 }
2261
2262 // CRC32 instructions
2263 #define INSN(NAME, sf, sz) \
2264 void NAME(Register Rd, Register Rn, Register Rm) { \
2265 starti; \
2266 f(sf, 31), f(0b0011010110, 30, 21), f(0b0100, 15, 12), f(sz, 11, 10); \
2267 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2268 }
2269
2270 INSN(crc32b, 0, 0b00);
2271 INSN(crc32h, 0, 0b01);
2272 INSN(crc32w, 0, 0b10);
2273 INSN(crc32x, 1, 0b11);
2274
2275 #undef INSN
2276
2277
2278 /* Simulator extensions to the ISA
2279
2280 haltsim
2281
2282 takes no arguments, causes the sim to enter a debug break and then
2283 return from the simulator run() call with STATUS_HALT? The linking
2284 code will call fatal() when it sees STATUS_HALT.
2285
2286 blrt Xn, Wm
2287 blrt Xn, #gpargs, #fpargs, #type
2288 Xn holds the 64 bit x86 branch_address
2289 call format is encoded either as immediate data in the call
2290 or in register Wm. In the latter case
2291 Wm[13..6] = #gpargs,
2292 Wm[5..2] = #fpargs,
2293 Wm[1,0] = #type
2294
2295 calls the x86 code address 'branch_address' supplied in Xn passing
2296 arguments taken from the general and floating point registers according
2297 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2298 or v0 according to the the return type #type' where
2299
2300 address branch_address;
2301 uimm4 gpargs;
2302 uimm4 fpargs;
2303 enum ReturnType type;
2304
2305 enum ReturnType
2306 {
2307 void_ret = 0,
2308 int_ret = 1,
2309 long_ret = 1,
2310 obj_ret = 1, // i.e. same as long
2311 float_ret = 2,
2312 double_ret = 3
2313 }
2314
2315 notify
2316
2317 notifies the simulator of a transfer of control. instr[14:0]
2318 identifies the type of change of control.
2319
2320 0 ==> initial entry to a method.
2321
2322 1 ==> return into a method from a submethod call.
2323
2324 2 ==> exit out of Java method code.
2325
2326 3 ==> start execution for a new bytecode.
2327
2328 in cases 1 and 2 the simulator is expected to use a JVM callback to
2329 identify the name of the specific method being executed. in case 4
2330 the simulator is expected to use a JVM callback to identify the
2331 bytecode index.
2332
2333 Instruction encodings
2334 ---------------------
2335
2336 These are encoded in the space with instr[28:25] = 00 which is
2337 unallocated. Encodings are
2338
2339 10987654321098765432109876543210
2340 PSEUDO_HALT = 0x11100000000000000000000000000000
2341 PSEUDO_BLRT = 0x11000000000000000_______________
2342 PSEUDO_BLRTR = 0x1100000000000000100000__________
2343 PSEUDO_NOTIFY = 0x10100000000000000_______________
2344
2345 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2346
2347 for BLRT
2348 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2349 instr[6,5] = #type, instr[4,0] = Rn
2350 for BLRTR
2351 instr[9,5] = Rm, instr[4,0] = Rn
2352 for NOTIFY
2353 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2354 */
2355
2356 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2357
2358 virtual void notify(int type) {
2359 if (UseBuiltinSim) {
2360 starti;
2361 // 109
2362 f(0b101, 31, 29);
2363 // 87654321098765
2364 f(0b00000000000000, 28, 15);
2365 f(type, 14, 0);
2366 }
2367 }
2368
2369 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2370 if (UseBuiltinSim) {
2371 starti;
2372 f(0b110, 31 ,29);
2373 f(0b00, 28, 25);
2374 // 4321098765
2375 f(0b0000000000, 24, 15);
2376 f(gpargs, 14, 11);
2377 f(fpargs, 10, 7);
2378 f(type, 6, 5);
2379 rf(Rn, 0);
2380 } else {
2381 blr(Rn);
2382 }
2383 }
2384
2385 void blrt(Register Rn, Register Rm) {
2386 if (UseBuiltinSim) {
2387 starti;
2388 f(0b110, 31 ,29);
2389 f(0b00, 28, 25);
2390 // 4321098765
2391 f(0b0000000001, 24, 15);
2392 // 43210
2393 f(0b00000, 14, 10);
2394 rf(Rm, 5);
2395 rf(Rn, 0);
2396 } else {
2397 blr(Rn);
2398 }
2399 }
2400
2401 void haltsim() {
2402 starti;
2403 f(0b111, 31 ,29);
2404 f(0b00, 28, 27);
2405 // 654321098765432109876543210
2406 f(0b000000000000000000000000000, 26, 0);
2407 }
2408
2409 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2410 }
2411
2412 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2413 Register tmp,
2414 int offset) {
2415 }
2416
2417 // Stack overflow checking
2418 virtual void bang_stack_with_offset(int offset);
2419
2420 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2421 static bool operand_valid_for_add_sub_immediate(long imm);
2422 static bool operand_valid_for_float_immediate(double imm);
2423
2424 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2425 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2426 };
2427
2428 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2429 Assembler::Membar_mask_bits b) {
2430 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2431 }
2432
2433 Instruction_aarch64::~Instruction_aarch64() {
2434 assem->emit();
2435 }
2436
2437 #undef starti
2438
2439 // Invert a condition
2440 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2441 return Assembler::Condition(int(cond) ^ 1);
2442 }
2443
2444 class BiasedLockingCounters;
2445
2446 extern "C" void das(uint64_t start, int len);
2447
2448 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP