src/cpu/aarch64/vm/assembler_aarch64.hpp

@@ -1089,11 +1089,11 @@
 
   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
     Register Rn, enum operand_size sz, int op, int o0) {
     starti;
     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
-    rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
+    rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), srf(Rt1, 0);
   }
 
 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \