1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2014 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/os.hpp" 33 #include "runtime/stubCodeGenerator.hpp" 34 #include "utilities/defaultStream.hpp" 35 #include "vm_version_ppc.hpp" 36 37 # include <sys/sysinfo.h> 38 39 int VM_Version::_features = VM_Version::unknown_m; 40 int VM_Version::_measured_cache_line_size = 128; // default value 41 const char* VM_Version::_features_str = ""; 42 bool VM_Version::_is_determine_features_test_running = false; 43 44 45 #define MSG(flag) \ 46 if (flag && !FLAG_IS_DEFAULT(flag)) \ 47 jio_fprintf(defaultStream::error_stream(), \ 48 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 49 " -XX:+" #flag " will be disabled!\n"); 50 51 void VM_Version::initialize() { 52 53 // Test which instructions are supported and measure cache line size. 54 determine_features(); 55 56 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 57 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 58 if (VM_Version::has_popcntw()) { 59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 60 } else if (VM_Version::has_cmpb()) { 61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 62 } else if (VM_Version::has_popcntb()) { 63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 64 } else { 65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 66 } 67 } 68 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 || 69 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7, 70 "PowerArchitecturePPC64 should be 0, 5, 6 or 7"); 71 72 if (!UseSIGTRAP) { 73 MSG(TrapBasedICMissChecks); 74 MSG(TrapBasedNotEntrantChecks); 75 MSG(TrapBasedNullChecks); 76 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 77 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 78 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 79 } 80 81 #ifdef COMPILER2 82 if (!UseSIGTRAP) { 83 MSG(TrapBasedRangeChecks); 84 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 85 } 86 87 // On Power6 test for section size. 88 if (PowerArchitecturePPC64 == 6) { 89 determine_section_size(); 90 // TODO: PPC port } else { 91 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 92 } 93 94 MaxVectorSize = 8; 95 #endif 96 97 // Create and print feature-string. 98 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 99 jio_snprintf(buf, sizeof(buf), 100 "ppc64%s%s%s%s%s%s%s%s", 101 (has_fsqrt() ? " fsqrt" : ""), 102 (has_isel() ? " isel" : ""), 103 (has_lxarxeh() ? " lxarxeh" : ""), 104 (has_cmpb() ? " cmpb" : ""), 105 //(has_mftgpr()? " mftgpr" : ""), 106 (has_popcntb() ? " popcntb" : ""), 107 (has_popcntw() ? " popcntw" : ""), 108 (has_fcfids() ? " fcfids" : ""), 109 (has_vand() ? " vand" : "") 110 // Make sure number of %s matches num_features! 111 ); 112 _features_str = os::strdup(buf); 113 NOT_PRODUCT(if (Verbose) print_features();); 114 115 // PPC64 supports 8-byte compare-exchange operations (see 116 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 117 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 118 _supports_cx8 = true; 119 120 UseSSE = 0; // Only on x86 and x64 121 122 intx cache_line_size = _measured_cache_line_size; 123 124 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 125 126 if (AllocatePrefetchStyle == 4) { 127 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 128 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 129 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 130 } else { 131 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 132 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 133 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 134 } 135 136 assert(AllocatePrefetchLines > 0, "invalid value"); 137 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 138 AllocatePrefetchLines = 1; // Conservative value. 139 } 140 141 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 142 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 143 } 144 145 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 146 147 if (UseCRC32Intrinsics) { 148 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 149 warning("CRC32 intrinsics are not available on this CPU"); 150 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 151 } 152 153 // The AES intrinsic stubs require AES instruction support. 154 if (UseAES) { 155 warning("AES instructions are not available on this CPU"); 156 FLAG_SET_DEFAULT(UseAES, false); 157 } 158 if (UseAESIntrinsics) { 159 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 160 warning("AES intrinsics are not available on this CPU"); 161 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 162 } 163 164 if (UseSHA) { 165 warning("SHA instructions are not available on this CPU"); 166 FLAG_SET_DEFAULT(UseSHA, false); 167 } 168 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 169 warning("SHA intrinsics are not available on this CPU"); 170 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 171 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 172 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 173 } 174 175 } 176 177 void VM_Version::print_features() { 178 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size()); 179 } 180 181 #ifdef COMPILER2 182 // Determine section size on power6: If section size is 8 instructions, 183 // there should be a difference between the two testloops of ~15 %. If 184 // no difference is detected the section is assumed to be 32 instructions. 185 void VM_Version::determine_section_size() { 186 187 int unroll = 80; 188 189 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 190 191 // Allocate space for the code. 192 ResourceMark rm; 193 CodeBuffer cb("detect_section_size", code_size, 0); 194 MacroAssembler* a = new MacroAssembler(&cb); 195 196 uint32_t *code = (uint32_t *)a->pc(); 197 // Emit code. 198 void (*test1)() = (void(*)())(void *)a->function_entry(); 199 200 Label l1; 201 202 a->li(R4, 1); 203 a->sldi(R4, R4, 28); 204 a->b(l1); 205 a->align(CodeEntryAlignment); 206 207 a->bind(l1); 208 209 for (int i = 0; i < unroll; i++) { 210 // Schleife 1 211 // ------- sector 0 ------------ 212 // ;; 0 213 a->nop(); // 1 214 a->fpnop0(); // 2 215 a->fpnop1(); // 3 216 a->addi(R4,R4, -1); // 4 217 218 // ;; 1 219 a->nop(); // 5 220 a->fmr(F6, F6); // 6 221 a->fmr(F7, F7); // 7 222 a->endgroup(); // 8 223 // ------- sector 8 ------------ 224 225 // ;; 2 226 a->nop(); // 9 227 a->nop(); // 10 228 a->fmr(F8, F8); // 11 229 a->fmr(F9, F9); // 12 230 231 // ;; 3 232 a->nop(); // 13 233 a->fmr(F10, F10); // 14 234 a->fmr(F11, F11); // 15 235 a->endgroup(); // 16 236 // -------- sector 16 ------------- 237 238 // ;; 4 239 a->nop(); // 17 240 a->nop(); // 18 241 a->fmr(F15, F15); // 19 242 a->fmr(F16, F16); // 20 243 244 // ;; 5 245 a->nop(); // 21 246 a->fmr(F17, F17); // 22 247 a->fmr(F18, F18); // 23 248 a->endgroup(); // 24 249 // ------- sector 24 ------------ 250 251 // ;; 6 252 a->nop(); // 25 253 a->nop(); // 26 254 a->fmr(F19, F19); // 27 255 a->fmr(F20, F20); // 28 256 257 // ;; 7 258 a->nop(); // 29 259 a->fmr(F21, F21); // 30 260 a->fmr(F22, F22); // 31 261 a->brnop0(); // 32 262 263 // ------- sector 32 ------------ 264 } 265 266 // ;; 8 267 a->cmpdi(CCR0, R4, unroll); // 33 268 a->bge(CCR0, l1); // 34 269 a->blr(); 270 271 // Emit code. 272 void (*test2)() = (void(*)())(void *)a->function_entry(); 273 // uint32_t *code = (uint32_t *)a->pc(); 274 275 Label l2; 276 277 a->li(R4, 1); 278 a->sldi(R4, R4, 28); 279 a->b(l2); 280 a->align(CodeEntryAlignment); 281 282 a->bind(l2); 283 284 for (int i = 0; i < unroll; i++) { 285 // Schleife 2 286 // ------- sector 0 ------------ 287 // ;; 0 288 a->brnop0(); // 1 289 a->nop(); // 2 290 //a->cmpdi(CCR0, R4, unroll); 291 a->fpnop0(); // 3 292 a->fpnop1(); // 4 293 a->addi(R4,R4, -1); // 5 294 295 // ;; 1 296 297 a->nop(); // 6 298 a->fmr(F6, F6); // 7 299 a->fmr(F7, F7); // 8 300 // ------- sector 8 --------------- 301 302 // ;; 2 303 a->endgroup(); // 9 304 305 // ;; 3 306 a->nop(); // 10 307 a->nop(); // 11 308 a->fmr(F8, F8); // 12 309 310 // ;; 4 311 a->fmr(F9, F9); // 13 312 a->nop(); // 14 313 a->fmr(F10, F10); // 15 314 315 // ;; 5 316 a->fmr(F11, F11); // 16 317 // -------- sector 16 ------------- 318 319 // ;; 6 320 a->endgroup(); // 17 321 322 // ;; 7 323 a->nop(); // 18 324 a->nop(); // 19 325 a->fmr(F15, F15); // 20 326 327 // ;; 8 328 a->fmr(F16, F16); // 21 329 a->nop(); // 22 330 a->fmr(F17, F17); // 23 331 332 // ;; 9 333 a->fmr(F18, F18); // 24 334 // -------- sector 24 ------------- 335 336 // ;; 10 337 a->endgroup(); // 25 338 339 // ;; 11 340 a->nop(); // 26 341 a->nop(); // 27 342 a->fmr(F19, F19); // 28 343 344 // ;; 12 345 a->fmr(F20, F20); // 29 346 a->nop(); // 30 347 a->fmr(F21, F21); // 31 348 349 // ;; 13 350 a->fmr(F22, F22); // 32 351 } 352 353 // -------- sector 32 ------------- 354 // ;; 14 355 a->cmpdi(CCR0, R4, unroll); // 33 356 a->bge(CCR0, l2); // 34 357 358 a->blr(); 359 uint32_t *code_end = (uint32_t *)a->pc(); 360 a->flush(); 361 362 double loop1_seconds,loop2_seconds, rel_diff; 363 uint64_t start1, stop1; 364 365 start1 = os::current_thread_cpu_time(false); 366 (*test1)(); 367 stop1 = os::current_thread_cpu_time(false); 368 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 369 370 371 start1 = os::current_thread_cpu_time(false); 372 (*test2)(); 373 stop1 = os::current_thread_cpu_time(false); 374 375 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 376 377 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 378 379 if (PrintAssembly) { 380 ttyLocker ttyl; 381 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 382 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 383 tty->print_cr("Time loop1 :%f", loop1_seconds); 384 tty->print_cr("Time loop2 :%f", loop2_seconds); 385 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 386 387 if (rel_diff > 12.0) { 388 tty->print_cr("Section Size 8 Instructions"); 389 } else{ 390 tty->print_cr("Section Size 32 Instructions or Power5"); 391 } 392 } 393 394 #if 0 // TODO: PPC port 395 // Set sector size (if not set explicitly). 396 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 397 if (rel_diff > 12.0) { 398 PdScheduling::power6SectorSize = 0x20; 399 } else { 400 PdScheduling::power6SectorSize = 0x80; 401 } 402 } else if (Power6SectorSize128PPC64) { 403 PdScheduling::power6SectorSize = 0x80; 404 } else { 405 PdScheduling::power6SectorSize = 0x20; 406 } 407 #endif 408 if (UsePower6SchedulerPPC64) Unimplemented(); 409 } 410 #endif // COMPILER2 411 412 void VM_Version::determine_features() { 413 #if defined(ABI_ELFv2) 414 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect. 415 #else 416 // 7 InstWords for each call (function descriptor + blr instruction). 417 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 418 #endif 419 int features = 0; 420 421 // create test area 422 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 423 char test_area[BUFFER_SIZE]; 424 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 425 426 // Allocate space for the code. 427 ResourceMark rm; 428 CodeBuffer cb("detect_cpu_features", code_size, 0); 429 MacroAssembler* a = new MacroAssembler(&cb); 430 431 // Must be set to true so we can generate the test code. 432 _features = VM_Version::all_features_m; 433 434 // Emit code. 435 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 436 uint32_t *code = (uint32_t *)a->pc(); 437 // Don't use R0 in ldarx. 438 // Keep R3_ARG1 unmodified, it contains &field (see below). 439 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 440 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 441 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 442 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 443 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 444 a->cmpb(R7, R5, R6); // code[4] -> bcmp 445 //a->mftgpr(R7, F3); // code[5] -> mftgpr 446 a->popcntb(R7, R5); // code[6] -> popcntb 447 a->popcntw(R7, R5); // code[7] -> popcntw 448 a->fcfids(F3, F4); // code[8] -> fcfids 449 a->vand(VR0, VR0, VR0); // code[9] -> vand 450 a->blr(); 451 452 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 453 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 454 a->dcbz(R3_ARG1); // R3_ARG1 = addr 455 a->blr(); 456 457 uint32_t *code_end = (uint32_t *)a->pc(); 458 a->flush(); 459 _features = VM_Version::unknown_m; 460 461 // Print the detection code. 462 if (PrintAssembly) { 463 ttyLocker ttyl; 464 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 465 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 466 } 467 468 // Measure cache line size. 469 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 470 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 471 int count = 0; // count zeroed bytes 472 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 473 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 474 _measured_cache_line_size = count; 475 476 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 477 VM_Version::_is_determine_features_test_running = true; 478 (*test)((address)mid_of_test_area, (uint64_t)0); 479 VM_Version::_is_determine_features_test_running = false; 480 481 // determine which instructions are legal. 482 int feature_cntr = 0; 483 if (code[feature_cntr++]) features |= fsqrt_m; 484 if (code[feature_cntr++]) features |= fsqrts_m; 485 if (code[feature_cntr++]) features |= isel_m; 486 if (code[feature_cntr++]) features |= lxarxeh_m; 487 if (code[feature_cntr++]) features |= cmpb_m; 488 //if(code[feature_cntr++])features |= mftgpr_m; 489 if (code[feature_cntr++]) features |= popcntb_m; 490 if (code[feature_cntr++]) features |= popcntw_m; 491 if (code[feature_cntr++]) features |= fcfids_m; 492 if (code[feature_cntr++]) features |= vand_m; 493 494 // Print the detection code. 495 if (PrintAssembly) { 496 ttyLocker ttyl; 497 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 498 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 499 } 500 501 _features = features; 502 } 503 504 505 static int saved_features = 0; 506 507 void VM_Version::allow_all() { 508 saved_features = _features; 509 _features = all_features_m; 510 } 511 512 void VM_Version::revert() { 513 _features = saved_features; 514 }