339 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
340 }
341
342 if (has_sha512()) {
343 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
344 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
345 }
346 } else if (UseSHA512Intrinsics) {
347 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
348 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
349 }
350 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
351 FLAG_SET_DEFAULT(UseSHA, false);
352 }
353 }
354
355 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
356 (cache_line_size > ContendedPaddingWidth))
357 ContendedPaddingWidth = cache_line_size;
358
359 #ifndef PRODUCT
360 if (PrintMiscellaneous && Verbose) {
361 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
362 tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
363 tty->print("Allocation");
364 if (AllocatePrefetchStyle <= 0) {
365 tty->print_cr(": no prefetching");
366 } else {
367 tty->print(" prefetching: ");
368 if (AllocatePrefetchInstr == 0) {
369 tty->print("PREFETCH");
370 } else if (AllocatePrefetchInstr == 1) {
371 tty->print("BIS");
372 }
373 if (AllocatePrefetchLines > 1) {
374 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
375 } else {
376 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
377 }
378 }
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339 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
340 }
341
342 if (has_sha512()) {
343 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
344 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
345 }
346 } else if (UseSHA512Intrinsics) {
347 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
348 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
349 }
350 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
351 FLAG_SET_DEFAULT(UseSHA, false);
352 }
353 }
354
355 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
356 (cache_line_size > ContendedPaddingWidth))
357 ContendedPaddingWidth = cache_line_size;
358
359 // This machine does not allow unaligned memory accesses
360 if (! FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
361 warning("Unaligned memory access is not available on this CPU");
362 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
363 }
364
365 #ifndef PRODUCT
366 if (PrintMiscellaneous && Verbose) {
367 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
368 tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
369 tty->print("Allocation");
370 if (AllocatePrefetchStyle <= 0) {
371 tty->print_cr(": no prefetching");
372 } else {
373 tty->print(" prefetching: ");
374 if (AllocatePrefetchInstr == 0) {
375 tty->print("PREFETCH");
376 } else if (AllocatePrefetchInstr == 1) {
377 tty->print("BIS");
378 }
379 if (AllocatePrefetchLines > 1) {
380 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
381 } else {
382 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
383 }
384 }
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