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src/cpu/sparc/vm/assembler_sparc.hpp

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   1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


 112     flushw_op3   = 0x2b,
 113     movcc_op3    = 0x2c,
 114     sdivx_op3    = 0x2d,
 115     popc_op3     = 0x2e,
 116     movr_op3     = 0x2f,
 117 
 118     sir_op3      = 0x30,
 119     wrreg_op3    = 0x30,
 120     saved_op3    = 0x31,
 121 
 122     fpop1_op3    = 0x34,
 123     fpop2_op3    = 0x35,
 124     impdep1_op3  = 0x36,
 125     aes3_op3     = 0x36,
 126     sha_op3      = 0x36,
 127     alignaddr_op3  = 0x36,
 128     faligndata_op3 = 0x36,
 129     flog3_op3    = 0x36,
 130     edge_op3     = 0x36,
 131     fsrc_op3     = 0x36,

 132     impdep2_op3  = 0x37,
 133     stpartialf_op3 = 0x37,
 134     jmpl_op3     = 0x38,
 135     rett_op3     = 0x39,
 136     trap_op3     = 0x3a,
 137     flush_op3    = 0x3b,
 138     save_op3     = 0x3c,
 139     restore_op3  = 0x3d,
 140     done_op3     = 0x3e,
 141     retry_op3    = 0x3e,
 142 
 143     lduw_op3     = 0x00,
 144     ldub_op3     = 0x01,
 145     lduh_op3     = 0x02,
 146     ldd_op3      = 0x03,
 147     stw_op3      = 0x04,
 148     stb_op3      = 0x05,
 149     sth_op3      = 0x06,
 150     std_op3      = 0x07,
 151     ldsw_op3     = 0x08,


 203     fdivs_opf          = 0x4d,
 204     fdivd_opf          = 0x4e,
 205 
 206     fcmps_opf          = 0x51,
 207     fcmpd_opf          = 0x52,
 208 
 209     fstox_opf          = 0x81,
 210     fdtox_opf          = 0x82,
 211     fxtos_opf          = 0x84,
 212     fxtod_opf          = 0x88,
 213     fitos_opf          = 0xc4,
 214     fdtos_opf          = 0xc6,
 215     fitod_opf          = 0xc8,
 216     fstod_opf          = 0xc9,
 217     fstoi_opf          = 0xd1,
 218     fdtoi_opf          = 0xd2,
 219 
 220     mdtox_opf          = 0x110,
 221     mstouw_opf         = 0x111,
 222     mstosw_opf         = 0x113,


 223     mxtod_opf          = 0x118,
 224     mwtos_opf          = 0x119,
 225 
 226     aes_kexpand0_opf   = 0x130,
 227     aes_kexpand2_opf   = 0x131,
 228 
 229     sha1_opf           = 0x141,
 230     sha256_opf         = 0x142,
 231     sha512_opf         = 0x143
 232   };
 233 
 234   enum op5s {
 235     aes_eround01_op5     = 0x00,
 236     aes_eround23_op5     = 0x01,
 237     aes_dround01_op5     = 0x02,
 238     aes_dround23_op5     = 0x03,
 239     aes_eround01_l_op5   = 0x04,
 240     aes_eround23_l_op5   = 0x05,
 241     aes_dround01_l_op5   = 0x06,
 242     aes_dround23_l_op5   = 0x07,


1194   void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1195 
1196   void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1197 
1198   void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1199 
1200   void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1201 
1202   //  VIS2 instructions
1203 
1204   void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1205 
1206   // VIS3 instructions
1207 
1208   void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1209   void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1210   void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1211 
1212   void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1213   void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }



1214 
1215   // Crypto SHA instructions
1216 
1217   void sha1()   { sha1_only();    emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1218   void sha256() { sha256_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1219   void sha512() { sha512_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1220 
1221   // Creation
1222   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1223 #ifdef CHECK_DELAY
1224     delay_state = no_delay;
1225 #endif
1226   }
1227 };
1228 
1229 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
   1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


 112     flushw_op3   = 0x2b,
 113     movcc_op3    = 0x2c,
 114     sdivx_op3    = 0x2d,
 115     popc_op3     = 0x2e,
 116     movr_op3     = 0x2f,
 117 
 118     sir_op3      = 0x30,
 119     wrreg_op3    = 0x30,
 120     saved_op3    = 0x31,
 121 
 122     fpop1_op3    = 0x34,
 123     fpop2_op3    = 0x35,
 124     impdep1_op3  = 0x36,
 125     aes3_op3     = 0x36,
 126     sha_op3      = 0x36,
 127     alignaddr_op3  = 0x36,
 128     faligndata_op3 = 0x36,
 129     flog3_op3    = 0x36,
 130     edge_op3     = 0x36,
 131     fsrc_op3     = 0x36,
 132     xmulx_op3    = 0x36,
 133     impdep2_op3  = 0x37,
 134     stpartialf_op3 = 0x37,
 135     jmpl_op3     = 0x38,
 136     rett_op3     = 0x39,
 137     trap_op3     = 0x3a,
 138     flush_op3    = 0x3b,
 139     save_op3     = 0x3c,
 140     restore_op3  = 0x3d,
 141     done_op3     = 0x3e,
 142     retry_op3    = 0x3e,
 143 
 144     lduw_op3     = 0x00,
 145     ldub_op3     = 0x01,
 146     lduh_op3     = 0x02,
 147     ldd_op3      = 0x03,
 148     stw_op3      = 0x04,
 149     stb_op3      = 0x05,
 150     sth_op3      = 0x06,
 151     std_op3      = 0x07,
 152     ldsw_op3     = 0x08,


 204     fdivs_opf          = 0x4d,
 205     fdivd_opf          = 0x4e,
 206 
 207     fcmps_opf          = 0x51,
 208     fcmpd_opf          = 0x52,
 209 
 210     fstox_opf          = 0x81,
 211     fdtox_opf          = 0x82,
 212     fxtos_opf          = 0x84,
 213     fxtod_opf          = 0x88,
 214     fitos_opf          = 0xc4,
 215     fdtos_opf          = 0xc6,
 216     fitod_opf          = 0xc8,
 217     fstod_opf          = 0xc9,
 218     fstoi_opf          = 0xd1,
 219     fdtoi_opf          = 0xd2,
 220 
 221     mdtox_opf          = 0x110,
 222     mstouw_opf         = 0x111,
 223     mstosw_opf         = 0x113,
 224     xmulx_opf          = 0x115,
 225     xmulxhi_opf        = 0x116,
 226     mxtod_opf          = 0x118,
 227     mwtos_opf          = 0x119,
 228 
 229     aes_kexpand0_opf   = 0x130,
 230     aes_kexpand2_opf   = 0x131,
 231 
 232     sha1_opf           = 0x141,
 233     sha256_opf         = 0x142,
 234     sha512_opf         = 0x143
 235   };
 236 
 237   enum op5s {
 238     aes_eround01_op5     = 0x00,
 239     aes_eround23_op5     = 0x01,
 240     aes_dround01_op5     = 0x02,
 241     aes_dround23_op5     = 0x03,
 242     aes_eround01_l_op5   = 0x04,
 243     aes_eround23_l_op5   = 0x05,
 244     aes_dround01_l_op5   = 0x06,
 245     aes_dround23_l_op5   = 0x07,


1197   void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1198 
1199   void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1200 
1201   void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1202 
1203   void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1204 
1205   //  VIS2 instructions
1206 
1207   void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1208 
1209   // VIS3 instructions
1210 
1211   void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1212   void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1213   void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1214 
1215   void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1216   void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1217 
1218   void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1219   void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1220 
1221   // Crypto SHA instructions
1222 
1223   void sha1()   { sha1_only();    emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1224   void sha256() { sha256_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1225   void sha512() { sha512_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1226 
1227   // Creation
1228   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1229 #ifdef CHECK_DELAY
1230     delay_state = no_delay;
1231 #endif
1232   }
1233 };
1234 
1235 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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