1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)0xBD);
1118 emit_int8((unsigned char)(0xC0 | encode));
1119 }
1120
1121 void Assembler::bswapl(Register reg) { // bswap
1122 int encode = prefix_and_encode(reg->encoding());
1123 emit_int8(0x0F);
1124 emit_int8((unsigned char)(0xC8 | encode));
1125 }
1126
1127 void Assembler::blsil(Register dst, Register src) {
1128 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1129 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1130 emit_int8((unsigned char)0xF3);
1131 emit_int8((unsigned char)(0xC0 | encode));
1132 }
1133
1134 void Assembler::blsil(Register dst, Address src) {
1135 InstructionMark im(this);
1136 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1137 vex_prefix_0F38(rbx, dst, src);
1138 emit_int8((unsigned char)0xF3);
1139 emit_operand(rbx, src);
1140 }
1141
1142 void Assembler::blsmskl(Register dst, Register src) {
1143 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1144 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1145 emit_int8((unsigned char)0xF3);
1146 emit_int8((unsigned char)(0xC0 | encode));
1147 }
1148
1149 void Assembler::blsmskl(Register dst, Address src) {
1150 InstructionMark im(this);
1151 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1152 vex_prefix_0F38(rdx, dst, src);
1153 emit_int8((unsigned char)0xF3);
1154 emit_operand(rdx, src);
1155 }
1156
1157 void Assembler::blsrl(Register dst, Register src) {
1158 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1159 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1160 emit_int8((unsigned char)0xF3);
1161 emit_int8((unsigned char)(0xC0 | encode));
1162 }
1163
1164 void Assembler::blsrl(Register dst, Address src) {
1165 InstructionMark im(this);
1166 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1167 vex_prefix_0F38(rcx, dst, src);
1168 emit_int8((unsigned char)0xF3);
1169 emit_operand(rcx, src);
1170 }
1171
1172 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1173 // suspect disp32 is always good
1174 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1175
1176 if (L.is_bound()) {
1177 const int long_size = 5;
1178 int offs = (int)( target(L) - pc() );
1179 assert(offs <= 0, "assembler error");
1180 InstructionMark im(this);
1181 // 1110 1000 #32-bit disp
1182 emit_int8((unsigned char)0xE8);
1183 emit_data(offs - long_size, rtype, operand);
1184 } else {
1185 InstructionMark im(this);
1186 // 1110 1000 #32-bit disp
1187 L.add_patch_at(code(), locator());
1188
1189 emit_int8((unsigned char)0xE8);
1190 emit_data(int(0), rtype, operand);
1191 }
1192 }
1193
1194 void Assembler::call(Register dst) {
1195 int encode = prefix_and_encode(dst->encoding());
1196 emit_int8((unsigned char)0xFF);
1197 emit_int8((unsigned char)(0xD0 | encode));
1198 }
1199
1200
1201 void Assembler::call(Address adr) {
1202 InstructionMark im(this);
1203 prefix(adr);
1204 emit_int8((unsigned char)0xFF);
1205 emit_operand(rdx, adr);
1206 }
1207
1208 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1209 assert(entry != NULL, "call most probably wrong");
1210 InstructionMark im(this);
1211 emit_int8((unsigned char)0xE8);
1212 intptr_t disp = entry - (pc() + sizeof(int32_t));
1213 assert(is_simm32(disp), "must be 32bit offset (call2)");
1214 // Technically, should use call32_operand, but this format is
1215 // implied by the fact that we're emitting a call instruction.
1216
1217 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1218 emit_data((int) disp, rspec, operand);
1219 }
1220
1221 void Assembler::cdql() {
1222 emit_int8((unsigned char)0x99);
1223 }
1224
1225 void Assembler::cld() {
1226 emit_int8((unsigned char)0xFC);
1227 }
1228
1229 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1230 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1231 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1232 emit_int8(0x0F);
1233 emit_int8(0x40 | cc);
1234 emit_int8((unsigned char)(0xC0 | encode));
1235 }
1236
1237
1238 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1239 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1240 prefix(src, dst);
1241 emit_int8(0x0F);
1242 emit_int8(0x40 | cc);
1243 emit_operand(dst, src);
1244 }
1245
1246 void Assembler::cmpb(Address dst, int imm8) {
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_int8((unsigned char)0x80);
1250 emit_operand(rdi, dst, 1);
1251 emit_int8(imm8);
1252 }
1253
1254 void Assembler::cmpl(Address dst, int32_t imm32) {
1255 InstructionMark im(this);
1256 prefix(dst);
1257 emit_int8((unsigned char)0x81);
1258 emit_operand(rdi, dst, 4);
1259 emit_int32(imm32);
1260 }
1261
1262 void Assembler::cmpl(Register dst, int32_t imm32) {
1263 prefix(dst);
1264 emit_arith(0x81, 0xF8, dst, imm32);
1265 }
1266
1267 void Assembler::cmpl(Register dst, Register src) {
1268 (void) prefix_and_encode(dst->encoding(), src->encoding());
1269 emit_arith(0x3B, 0xC0, dst, src);
1270 }
1271
1272
1273 void Assembler::cmpl(Register dst, Address src) {
1274 InstructionMark im(this);
1275 prefix(src, dst);
1276 emit_int8((unsigned char)0x3B);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::cmpw(Address dst, int imm16) {
1281 InstructionMark im(this);
1282 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1283 emit_int8(0x66);
1284 emit_int8((unsigned char)0x81);
1285 emit_operand(rdi, dst, 2);
1286 emit_int16(imm16);
1287 }
1288
1289 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1290 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1291 // The ZF is set if the compared values were equal, and cleared otherwise.
1292 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1293 InstructionMark im(this);
1294 prefix(adr, reg);
1295 emit_int8(0x0F);
1296 emit_int8((unsigned char)0xB1);
1297 emit_operand(reg, adr);
1298 }
1299
1300 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1301 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1302 // The ZF is set if the compared values were equal, and cleared otherwise.
1303 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1304 InstructionMark im(this);
1305 prefix(adr, reg, true);
1306 emit_int8(0x0F);
1307 emit_int8((unsigned char)0xB0);
1308 emit_operand(reg, adr);
1309 }
1310
1311 void Assembler::comisd(XMMRegister dst, Address src) {
1312 // NOTE: dbx seems to decode this as comiss even though the
1313 // 0x66 is there. Strangly ucomisd comes out correct
1314 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1315 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1316 }
1317
1318 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1320 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1321 }
1322
1323 void Assembler::comiss(XMMRegister dst, Address src) {
1324 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1325 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1326 }
1327
1328 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1329 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1330 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1331 }
1332
1333 void Assembler::cpuid() {
1334 emit_int8(0x0F);
1335 emit_int8((unsigned char)0xA2);
1336 }
1337
1338 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1340 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1341 }
1342
1343 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1345 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1346 }
1347
1348 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1350 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1351 }
1352
1353 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1355 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1356 }
1357
1358 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1360 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1361 emit_int8(0x2A);
1362 emit_int8((unsigned char)(0xC0 | encode));
1363 }
1364
1365 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1367 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1368 }
1369
1370 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1371 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1372 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1373 emit_int8(0x2A);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1378 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1379 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1380 }
1381
1382 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1384 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1385 }
1386
1387 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1389 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1390 }
1391
1392
1393 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1394 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1395 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1396 emit_int8(0x2C);
1397 emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399
1400 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1401 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1402 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1403 emit_int8(0x2C);
1404 emit_int8((unsigned char)(0xC0 | encode));
1405 }
1406
1407 void Assembler::decl(Address dst) {
1408 // Don't use it directly. Use MacroAssembler::decrement() instead.
1409 InstructionMark im(this);
1410 prefix(dst);
1411 emit_int8((unsigned char)0xFF);
1412 emit_operand(rcx, dst);
1413 }
1414
1415 void Assembler::divsd(XMMRegister dst, Address src) {
1416 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1417 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1418 }
1419
1420 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1422 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1423 }
1424
1425 void Assembler::divss(XMMRegister dst, Address src) {
1426 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1427 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1428 }
1429
1430 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1431 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1432 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1433 }
1434
1435 void Assembler::emms() {
1436 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1437 emit_int8(0x0F);
1438 emit_int8(0x77);
1439 }
1440
1441 void Assembler::hlt() {
1442 emit_int8((unsigned char)0xF4);
1443 }
1444
1445 void Assembler::idivl(Register src) {
1446 int encode = prefix_and_encode(src->encoding());
1447 emit_int8((unsigned char)0xF7);
1448 emit_int8((unsigned char)(0xF8 | encode));
1449 }
1450
1451 void Assembler::divl(Register src) { // Unsigned
1452 int encode = prefix_and_encode(src->encoding());
1453 emit_int8((unsigned char)0xF7);
1454 emit_int8((unsigned char)(0xF0 | encode));
1455 }
1456
1457 void Assembler::imull(Register dst, Register src) {
1458 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1459 emit_int8(0x0F);
1460 emit_int8((unsigned char)0xAF);
1461 emit_int8((unsigned char)(0xC0 | encode));
1462 }
1463
1464
1465 void Assembler::imull(Register dst, Register src, int value) {
1466 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1467 if (is8bit(value)) {
1468 emit_int8(0x6B);
1469 emit_int8((unsigned char)(0xC0 | encode));
1470 emit_int8(value & 0xFF);
1471 } else {
1472 emit_int8(0x69);
1473 emit_int8((unsigned char)(0xC0 | encode));
1474 emit_int32(value);
1475 }
1476 }
1477
1478 void Assembler::imull(Register dst, Address src) {
1479 InstructionMark im(this);
1480 prefix(src, dst);
1481 emit_int8(0x0F);
1482 emit_int8((unsigned char) 0xAF);
1483 emit_operand(dst, src);
1484 }
1485
1486
1487 void Assembler::incl(Address dst) {
1488 // Don't use it directly. Use MacroAssembler::increment() instead.
1489 InstructionMark im(this);
1490 prefix(dst);
1491 emit_int8((unsigned char)0xFF);
1492 emit_operand(rax, dst);
1493 }
1494
1495 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1496 InstructionMark im(this);
1497 assert((0 <= cc) && (cc < 16), "illegal cc");
1498 if (L.is_bound()) {
1499 address dst = target(L);
1500 assert(dst != NULL, "jcc most probably wrong");
1501
1502 const int short_size = 2;
1503 const int long_size = 6;
1504 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1505 if (maybe_short && is8bit(offs - short_size)) {
1506 // 0111 tttn #8-bit disp
1507 emit_int8(0x70 | cc);
1508 emit_int8((offs - short_size) & 0xFF);
1509 } else {
1510 // 0000 1111 1000 tttn #32-bit disp
1511 assert(is_simm32(offs - long_size),
1512 "must be 32bit offset (call4)");
1513 emit_int8(0x0F);
1514 emit_int8((unsigned char)(0x80 | cc));
1515 emit_int32(offs - long_size);
1516 }
1517 } else {
1518 // Note: could eliminate cond. jumps to this jump if condition
1519 // is the same however, seems to be rather unlikely case.
1520 // Note: use jccb() if label to be bound is very close to get
1521 // an 8-bit displacement
1522 L.add_patch_at(code(), locator());
1523 emit_int8(0x0F);
1524 emit_int8((unsigned char)(0x80 | cc));
1525 emit_int32(0);
1526 }
1527 }
1528
1529 void Assembler::jccb(Condition cc, Label& L) {
1530 if (L.is_bound()) {
1531 const int short_size = 2;
1532 address entry = target(L);
1533 #ifdef ASSERT
1534 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1535 intptr_t delta = short_branch_delta();
1536 if (delta != 0) {
1537 dist += (dist < 0 ? (-delta) :delta);
1538 }
1539 assert(is8bit(dist), "Dispacement too large for a short jmp");
1540 #endif
1541 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1542 // 0111 tttn #8-bit disp
1543 emit_int8(0x70 | cc);
1544 emit_int8((offs - short_size) & 0xFF);
1545 } else {
1546 InstructionMark im(this);
1547 L.add_patch_at(code(), locator());
1548 emit_int8(0x70 | cc);
1549 emit_int8(0);
1550 }
1551 }
1552
1553 void Assembler::jmp(Address adr) {
1554 InstructionMark im(this);
1555 prefix(adr);
1556 emit_int8((unsigned char)0xFF);
1557 emit_operand(rsp, adr);
1558 }
1559
1560 void Assembler::jmp(Label& L, bool maybe_short) {
1561 if (L.is_bound()) {
1562 address entry = target(L);
1563 assert(entry != NULL, "jmp most probably wrong");
1564 InstructionMark im(this);
1565 const int short_size = 2;
1566 const int long_size = 5;
1567 intptr_t offs = entry - pc();
1568 if (maybe_short && is8bit(offs - short_size)) {
1569 emit_int8((unsigned char)0xEB);
1570 emit_int8((offs - short_size) & 0xFF);
1571 } else {
1572 emit_int8((unsigned char)0xE9);
1573 emit_int32(offs - long_size);
1574 }
1575 } else {
1576 // By default, forward jumps are always 32-bit displacements, since
1577 // we can't yet know where the label will be bound. If you're sure that
1578 // the forward jump will not run beyond 256 bytes, use jmpb to
1579 // force an 8-bit displacement.
1580 InstructionMark im(this);
1581 L.add_patch_at(code(), locator());
1582 emit_int8((unsigned char)0xE9);
1583 emit_int32(0);
1584 }
1585 }
1586
1587 void Assembler::jmp(Register entry) {
1588 int encode = prefix_and_encode(entry->encoding());
1589 emit_int8((unsigned char)0xFF);
1590 emit_int8((unsigned char)(0xE0 | encode));
1591 }
1592
1593 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1594 InstructionMark im(this);
1595 emit_int8((unsigned char)0xE9);
1596 assert(dest != NULL, "must have a target");
1597 intptr_t disp = dest - (pc() + sizeof(int32_t));
1598 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1599 emit_data(disp, rspec.reloc(), call32_operand);
1600 }
1601
1602 void Assembler::jmpb(Label& L) {
1603 if (L.is_bound()) {
1604 const int short_size = 2;
1605 address entry = target(L);
1606 assert(entry != NULL, "jmp most probably wrong");
1607 #ifdef ASSERT
1608 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1609 intptr_t delta = short_branch_delta();
1610 if (delta != 0) {
1611 dist += (dist < 0 ? (-delta) :delta);
1612 }
1613 assert(is8bit(dist), "Dispacement too large for a short jmp");
1614 #endif
1615 intptr_t offs = entry - pc();
1616 emit_int8((unsigned char)0xEB);
1617 emit_int8((offs - short_size) & 0xFF);
1618 } else {
1619 InstructionMark im(this);
1620 L.add_patch_at(code(), locator());
1621 emit_int8((unsigned char)0xEB);
1622 emit_int8(0);
1623 }
1624 }
1625
1626 void Assembler::ldmxcsr( Address src) {
1627 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1628 InstructionMark im(this);
1629 prefix(src);
1630 emit_int8(0x0F);
1631 emit_int8((unsigned char)0xAE);
1632 emit_operand(as_Register(2), src);
1633 }
1634
1635 void Assembler::leal(Register dst, Address src) {
1636 InstructionMark im(this);
1637 #ifdef _LP64
1638 emit_int8(0x67); // addr32
1639 prefix(src, dst);
1640 #endif // LP64
1641 emit_int8((unsigned char)0x8D);
1642 emit_operand(dst, src);
1643 }
1644
1645 void Assembler::lfence() {
1646 emit_int8(0x0F);
1647 emit_int8((unsigned char)0xAE);
1648 emit_int8((unsigned char)0xE8);
1649 }
1650
1651 void Assembler::lock() {
1652 emit_int8((unsigned char)0xF0);
1653 }
1654
1655 void Assembler::lzcntl(Register dst, Register src) {
1656 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1657 emit_int8((unsigned char)0xF3);
1658 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1659 emit_int8(0x0F);
1660 emit_int8((unsigned char)0xBD);
1661 emit_int8((unsigned char)(0xC0 | encode));
1662 }
1663
1664 // Emit mfence instruction
1665 void Assembler::mfence() {
1666 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1667 emit_int8(0x0F);
1668 emit_int8((unsigned char)0xAE);
1669 emit_int8((unsigned char)0xF0);
1670 }
1671
1672 void Assembler::mov(Register dst, Register src) {
1673 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1674 }
1675
1676 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1677 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1678 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1679 }
1680
1681 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1683 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1684 }
1685
1686 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1687 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1688 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1689 emit_int8(0x16);
1690 emit_int8((unsigned char)(0xC0 | encode));
1691 }
1692
1693 void Assembler::movb(Register dst, Address src) {
1694 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1695 InstructionMark im(this);
1696 prefix(src, dst, true);
1697 emit_int8((unsigned char)0x8A);
1698 emit_operand(dst, src);
1699 }
1700
1701
1702 void Assembler::movb(Address dst, int imm8) {
1703 InstructionMark im(this);
1704 prefix(dst);
1705 emit_int8((unsigned char)0xC6);
1706 emit_operand(rax, dst, 1);
1707 emit_int8(imm8);
1708 }
1709
1710
1711 void Assembler::movb(Address dst, Register src) {
1712 assert(src->has_byte_register(), "must have byte register");
1713 InstructionMark im(this);
1714 prefix(dst, src, true);
1715 emit_int8((unsigned char)0x88);
1716 emit_operand(src, dst);
1717 }
1718
1719 void Assembler::movdl(XMMRegister dst, Register src) {
1720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1721 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1722 emit_int8(0x6E);
1723 emit_int8((unsigned char)(0xC0 | encode));
1724 }
1725
1726 void Assembler::movdl(Register dst, XMMRegister src) {
1727 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1728 // swap src/dst to get correct prefix
1729 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1730 emit_int8(0x7E);
1731 emit_int8((unsigned char)(0xC0 | encode));
1732 }
1733
1734 void Assembler::movdl(XMMRegister dst, Address src) {
1735 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1736 InstructionMark im(this);
1737 simd_prefix(dst, src, VEX_SIMD_66);
1738 emit_int8(0x6E);
1739 emit_operand(dst, src);
1740 }
1741
1742 void Assembler::movdl(Address dst, XMMRegister src) {
1743 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1744 InstructionMark im(this);
1745 simd_prefix(dst, src, VEX_SIMD_66);
1746 emit_int8(0x7E);
1747 emit_operand(src, dst);
1748 }
1749
1750 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1752 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1753 }
1754
1755 void Assembler::movdqa(XMMRegister dst, Address src) {
1756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1757 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1758 }
1759
1760 void Assembler::movdqu(XMMRegister dst, Address src) {
1761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1762 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1763 }
1764
1765 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1768 }
1769
1770 void Assembler::movdqu(Address dst, XMMRegister src) {
1771 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1772 InstructionMark im(this);
1773 simd_prefix(dst, src, VEX_SIMD_F3);
1774 emit_int8(0x7F);
1775 emit_operand(src, dst);
1776 }
1777
1778 // Move Unaligned 256bit Vector
1779 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1780 assert(UseAVX > 0, "");
1781 bool vector256 = true;
1782 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1783 emit_int8(0x6F);
1784 emit_int8((unsigned char)(0xC0 | encode));
1785 }
1786
1787 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1788 assert(UseAVX > 0, "");
1789 InstructionMark im(this);
1790 bool vector256 = true;
1791 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1792 emit_int8(0x6F);
1793 emit_operand(dst, src);
1794 }
1795
1796 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1797 assert(UseAVX > 0, "");
1798 InstructionMark im(this);
1799 bool vector256 = true;
1800 // swap src<->dst for encoding
1801 assert(src != xnoreg, "sanity");
1802 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1803 emit_int8(0x7F);
1804 emit_operand(src, dst);
1805 }
1806
1807 // Uses zero extension on 64bit
1808
1809 void Assembler::movl(Register dst, int32_t imm32) {
1810 int encode = prefix_and_encode(dst->encoding());
1811 emit_int8((unsigned char)(0xB8 | encode));
1812 emit_int32(imm32);
1813 }
1814
1815 void Assembler::movl(Register dst, Register src) {
1816 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1817 emit_int8((unsigned char)0x8B);
1818 emit_int8((unsigned char)(0xC0 | encode));
1819 }
1820
1821 void Assembler::movl(Register dst, Address src) {
1822 InstructionMark im(this);
1823 prefix(src, dst);
1824 emit_int8((unsigned char)0x8B);
1825 emit_operand(dst, src);
1826 }
1827
1828 void Assembler::movl(Address dst, int32_t imm32) {
1829 InstructionMark im(this);
1830 prefix(dst);
1831 emit_int8((unsigned char)0xC7);
1832 emit_operand(rax, dst, 4);
1833 emit_int32(imm32);
1834 }
1835
1836 void Assembler::movl(Address dst, Register src) {
1837 InstructionMark im(this);
1838 prefix(dst, src);
1839 emit_int8((unsigned char)0x89);
1840 emit_operand(src, dst);
1841 }
1842
1843 // New cpus require to use movsd and movss to avoid partial register stall
1844 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1845 // The selection is done in MacroAssembler::movdbl() and movflt().
1846 void Assembler::movlpd(XMMRegister dst, Address src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1849 }
1850
1851 void Assembler::movq( MMXRegister dst, Address src ) {
1852 assert( VM_Version::supports_mmx(), "" );
1853 emit_int8(0x0F);
1854 emit_int8(0x6F);
1855 emit_operand(dst, src);
1856 }
1857
1858 void Assembler::movq( Address dst, MMXRegister src ) {
1859 assert( VM_Version::supports_mmx(), "" );
1860 emit_int8(0x0F);
1861 emit_int8(0x7F);
1862 // workaround gcc (3.2.1-7a) bug
1863 // In that version of gcc with only an emit_operand(MMX, Address)
1864 // gcc will tail jump and try and reverse the parameters completely
1865 // obliterating dst in the process. By having a version available
1866 // that doesn't need to swap the args at the tail jump the bug is
1867 // avoided.
1868 emit_operand(dst, src);
1869 }
1870
1871 void Assembler::movq(XMMRegister dst, Address src) {
1872 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1873 InstructionMark im(this);
1874 simd_prefix(dst, src, VEX_SIMD_F3);
1875 emit_int8(0x7E);
1876 emit_operand(dst, src);
1877 }
1878
1879 void Assembler::movq(Address dst, XMMRegister src) {
1880 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1881 InstructionMark im(this);
1882 simd_prefix(dst, src, VEX_SIMD_66);
1883 emit_int8((unsigned char)0xD6);
1884 emit_operand(src, dst);
1885 }
1886
1887 void Assembler::movsbl(Register dst, Address src) { // movsxb
1888 InstructionMark im(this);
1889 prefix(src, dst);
1890 emit_int8(0x0F);
1891 emit_int8((unsigned char)0xBE);
1892 emit_operand(dst, src);
1893 }
1894
1895 void Assembler::movsbl(Register dst, Register src) { // movsxb
1896 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1897 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1898 emit_int8(0x0F);
1899 emit_int8((unsigned char)0xBE);
1900 emit_int8((unsigned char)(0xC0 | encode));
1901 }
1902
1903 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1904 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1905 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1906 }
1907
1908 void Assembler::movsd(XMMRegister dst, Address src) {
1909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1910 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1911 }
1912
1913 void Assembler::movsd(Address dst, XMMRegister src) {
1914 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1915 InstructionMark im(this);
1916 simd_prefix(dst, src, VEX_SIMD_F2);
1917 emit_int8(0x11);
1918 emit_operand(src, dst);
1919 }
1920
1921 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1922 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1923 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1924 }
1925
1926 void Assembler::movss(XMMRegister dst, Address src) {
1927 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1928 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1929 }
1930
1931 void Assembler::movss(Address dst, XMMRegister src) {
1932 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1933 InstructionMark im(this);
1934 simd_prefix(dst, src, VEX_SIMD_F3);
1935 emit_int8(0x11);
1936 emit_operand(src, dst);
1937 }
1938
1939 void Assembler::movswl(Register dst, Address src) { // movsxw
1940 InstructionMark im(this);
1941 prefix(src, dst);
1942 emit_int8(0x0F);
1943 emit_int8((unsigned char)0xBF);
1944 emit_operand(dst, src);
1945 }
1946
1947 void Assembler::movswl(Register dst, Register src) { // movsxw
1948 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1949 emit_int8(0x0F);
1950 emit_int8((unsigned char)0xBF);
1951 emit_int8((unsigned char)(0xC0 | encode));
1952 }
1953
1954 void Assembler::movw(Address dst, int imm16) {
1955 InstructionMark im(this);
1956
1957 emit_int8(0x66); // switch to 16-bit mode
1958 prefix(dst);
1959 emit_int8((unsigned char)0xC7);
1960 emit_operand(rax, dst, 2);
1961 emit_int16(imm16);
1962 }
1963
1964 void Assembler::movw(Register dst, Address src) {
1965 InstructionMark im(this);
1966 emit_int8(0x66);
1967 prefix(src, dst);
1968 emit_int8((unsigned char)0x8B);
1969 emit_operand(dst, src);
1970 }
1971
1972 void Assembler::movw(Address dst, Register src) {
1973 InstructionMark im(this);
1974 emit_int8(0x66);
1975 prefix(dst, src);
1976 emit_int8((unsigned char)0x89);
1977 emit_operand(src, dst);
1978 }
1979
1980 void Assembler::movzbl(Register dst, Address src) { // movzxb
1981 InstructionMark im(this);
1982 prefix(src, dst);
1983 emit_int8(0x0F);
1984 emit_int8((unsigned char)0xB6);
1985 emit_operand(dst, src);
1986 }
1987
1988 void Assembler::movzbl(Register dst, Register src) { // movzxb
1989 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1990 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1991 emit_int8(0x0F);
1992 emit_int8((unsigned char)0xB6);
1993 emit_int8(0xC0 | encode);
1994 }
1995
1996 void Assembler::movzwl(Register dst, Address src) { // movzxw
1997 InstructionMark im(this);
1998 prefix(src, dst);
1999 emit_int8(0x0F);
2000 emit_int8((unsigned char)0xB7);
2001 emit_operand(dst, src);
2002 }
2003
2004 void Assembler::movzwl(Register dst, Register src) { // movzxw
2005 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2006 emit_int8(0x0F);
2007 emit_int8((unsigned char)0xB7);
2008 emit_int8(0xC0 | encode);
2009 }
2010
2011 void Assembler::mull(Address src) {
2012 InstructionMark im(this);
2013 prefix(src);
2014 emit_int8((unsigned char)0xF7);
2015 emit_operand(rsp, src);
2016 }
2017
2018 void Assembler::mull(Register src) {
2019 int encode = prefix_and_encode(src->encoding());
2020 emit_int8((unsigned char)0xF7);
2021 emit_int8((unsigned char)(0xE0 | encode));
2022 }
2023
2024 void Assembler::mulsd(XMMRegister dst, Address src) {
2025 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2026 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2027 }
2028
2029 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2030 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2031 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2032 }
2033
2034 void Assembler::mulss(XMMRegister dst, Address src) {
2035 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2036 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2037 }
2038
2039 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2040 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2041 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2042 }
2043
2044 void Assembler::negl(Register dst) {
2045 int encode = prefix_and_encode(dst->encoding());
2046 emit_int8((unsigned char)0xF7);
2047 emit_int8((unsigned char)(0xD8 | encode));
2048 }
2049
2050 void Assembler::nop(int i) {
2051 #ifdef ASSERT
2052 assert(i > 0, " ");
2053 // The fancy nops aren't currently recognized by debuggers making it a
2054 // pain to disassemble code while debugging. If asserts are on clearly
2055 // speed is not an issue so simply use the single byte traditional nop
2056 // to do alignment.
2057
2058 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2059 return;
2060
2061 #endif // ASSERT
2062
2063 if (UseAddressNop && VM_Version::is_intel()) {
2064 //
2065 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2066 // 1: 0x90
2067 // 2: 0x66 0x90
2068 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2069 // 4: 0x0F 0x1F 0x40 0x00
2070 // 5: 0x0F 0x1F 0x44 0x00 0x00
2071 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2072 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2073 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2074 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2075 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2076 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2077
2078 // The rest coding is Intel specific - don't use consecutive address nops
2079
2080 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2081 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2082 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2083 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2084
2085 while(i >= 15) {
2086 // For Intel don't generate consecutive addess nops (mix with regular nops)
2087 i -= 15;
2088 emit_int8(0x66); // size prefix
2089 emit_int8(0x66); // size prefix
2090 emit_int8(0x66); // size prefix
2091 addr_nop_8();
2092 emit_int8(0x66); // size prefix
2093 emit_int8(0x66); // size prefix
2094 emit_int8(0x66); // size prefix
2095 emit_int8((unsigned char)0x90);
2096 // nop
2097 }
2098 switch (i) {
2099 case 14:
2100 emit_int8(0x66); // size prefix
2101 case 13:
2102 emit_int8(0x66); // size prefix
2103 case 12:
2104 addr_nop_8();
2105 emit_int8(0x66); // size prefix
2106 emit_int8(0x66); // size prefix
2107 emit_int8(0x66); // size prefix
2108 emit_int8((unsigned char)0x90);
2109 // nop
2110 break;
2111 case 11:
2112 emit_int8(0x66); // size prefix
2113 case 10:
2114 emit_int8(0x66); // size prefix
2115 case 9:
2116 emit_int8(0x66); // size prefix
2117 case 8:
2118 addr_nop_8();
2119 break;
2120 case 7:
2121 addr_nop_7();
2122 break;
2123 case 6:
2124 emit_int8(0x66); // size prefix
2125 case 5:
2126 addr_nop_5();
2127 break;
2128 case 4:
2129 addr_nop_4();
2130 break;
2131 case 3:
2132 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2133 emit_int8(0x66); // size prefix
2134 case 2:
2135 emit_int8(0x66); // size prefix
2136 case 1:
2137 emit_int8((unsigned char)0x90);
2138 // nop
2139 break;
2140 default:
2141 assert(i == 0, " ");
2142 }
2143 return;
2144 }
2145 if (UseAddressNop && VM_Version::is_amd()) {
2146 //
2147 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2148 // 1: 0x90
2149 // 2: 0x66 0x90
2150 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2151 // 4: 0x0F 0x1F 0x40 0x00
2152 // 5: 0x0F 0x1F 0x44 0x00 0x00
2153 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2154 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2156 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2157 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2158 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2159
2160 // The rest coding is AMD specific - use consecutive address nops
2161
2162 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2163 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2164 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2165 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2166 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2167 // Size prefixes (0x66) are added for larger sizes
2168
2169 while(i >= 22) {
2170 i -= 11;
2171 emit_int8(0x66); // size prefix
2172 emit_int8(0x66); // size prefix
2173 emit_int8(0x66); // size prefix
2174 addr_nop_8();
2175 }
2176 // Generate first nop for size between 21-12
2177 switch (i) {
2178 case 21:
2179 i -= 1;
2180 emit_int8(0x66); // size prefix
2181 case 20:
2182 case 19:
2183 i -= 1;
2184 emit_int8(0x66); // size prefix
2185 case 18:
2186 case 17:
2187 i -= 1;
2188 emit_int8(0x66); // size prefix
2189 case 16:
2190 case 15:
2191 i -= 8;
2192 addr_nop_8();
2193 break;
2194 case 14:
2195 case 13:
2196 i -= 7;
2197 addr_nop_7();
2198 break;
2199 case 12:
2200 i -= 6;
2201 emit_int8(0x66); // size prefix
2202 addr_nop_5();
2203 break;
2204 default:
2205 assert(i < 12, " ");
2206 }
2207
2208 // Generate second nop for size between 11-1
2209 switch (i) {
2210 case 11:
2211 emit_int8(0x66); // size prefix
2212 case 10:
2213 emit_int8(0x66); // size prefix
2214 case 9:
2215 emit_int8(0x66); // size prefix
2216 case 8:
2217 addr_nop_8();
2218 break;
2219 case 7:
2220 addr_nop_7();
2221 break;
2222 case 6:
2223 emit_int8(0x66); // size prefix
2224 case 5:
2225 addr_nop_5();
2226 break;
2227 case 4:
2228 addr_nop_4();
2229 break;
2230 case 3:
2231 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2232 emit_int8(0x66); // size prefix
2233 case 2:
2234 emit_int8(0x66); // size prefix
2235 case 1:
2236 emit_int8((unsigned char)0x90);
2237 // nop
2238 break;
2239 default:
2240 assert(i == 0, " ");
2241 }
2242 return;
2243 }
2244
2245 // Using nops with size prefixes "0x66 0x90".
2246 // From AMD Optimization Guide:
2247 // 1: 0x90
2248 // 2: 0x66 0x90
2249 // 3: 0x66 0x66 0x90
2250 // 4: 0x66 0x66 0x66 0x90
2251 // 5: 0x66 0x66 0x90 0x66 0x90
2252 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2253 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2254 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2255 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2256 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2257 //
2258 while(i > 12) {
2259 i -= 4;
2260 emit_int8(0x66); // size prefix
2261 emit_int8(0x66);
2262 emit_int8(0x66);
2263 emit_int8((unsigned char)0x90);
2264 // nop
2265 }
2266 // 1 - 12 nops
2267 if(i > 8) {
2268 if(i > 9) {
2269 i -= 1;
2270 emit_int8(0x66);
2271 }
2272 i -= 3;
2273 emit_int8(0x66);
2274 emit_int8(0x66);
2275 emit_int8((unsigned char)0x90);
2276 }
2277 // 1 - 8 nops
2278 if(i > 4) {
2279 if(i > 6) {
2280 i -= 1;
2281 emit_int8(0x66);
2282 }
2283 i -= 3;
2284 emit_int8(0x66);
2285 emit_int8(0x66);
2286 emit_int8((unsigned char)0x90);
2287 }
2288 switch (i) {
2289 case 4:
2290 emit_int8(0x66);
2291 case 3:
2292 emit_int8(0x66);
2293 case 2:
2294 emit_int8(0x66);
2295 case 1:
2296 emit_int8((unsigned char)0x90);
2297 break;
2298 default:
2299 assert(i == 0, " ");
2300 }
2301 }
2302
2303 void Assembler::notl(Register dst) {
2304 int encode = prefix_and_encode(dst->encoding());
2305 emit_int8((unsigned char)0xF7);
2306 emit_int8((unsigned char)(0xD0 | encode));
2307 }
2308
2309 void Assembler::orl(Address dst, int32_t imm32) {
2310 InstructionMark im(this);
2311 prefix(dst);
2312 emit_arith_operand(0x81, rcx, dst, imm32);
2313 }
2314
2315 void Assembler::orl(Register dst, int32_t imm32) {
2316 prefix(dst);
2317 emit_arith(0x81, 0xC8, dst, imm32);
2318 }
2319
2320 void Assembler::orl(Register dst, Address src) {
2321 InstructionMark im(this);
2322 prefix(src, dst);
2323 emit_int8(0x0B);
2324 emit_operand(dst, src);
2325 }
2326
2327 void Assembler::orl(Register dst, Register src) {
2328 (void) prefix_and_encode(dst->encoding(), src->encoding());
2329 emit_arith(0x0B, 0xC0, dst, src);
2330 }
2331
2332 void Assembler::packuswb(XMMRegister dst, Address src) {
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2335 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2336 }
2337
2338 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2340 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2341 }
2342
2343 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2344 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2345 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2346 }
2347
2348 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2349 assert(VM_Version::supports_avx2(), "");
2350 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2351 emit_int8(0x00);
2352 emit_int8(0xC0 | encode);
2353 emit_int8(imm8);
2354 }
2355
2356 void Assembler::pause() {
2357 emit_int8((unsigned char)0xF3);
2358 emit_int8((unsigned char)0x90);
2359 }
2360
2361 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2362 assert(VM_Version::supports_sse4_2(), "");
2363 InstructionMark im(this);
2364 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2365 emit_int8(0x61);
2366 emit_operand(dst, src);
2367 emit_int8(imm8);
2368 }
2369
2370 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2371 assert(VM_Version::supports_sse4_2(), "");
2372 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2373 emit_int8(0x61);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 emit_int8(imm8);
2376 }
2377
2378 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2379 assert(VM_Version::supports_sse4_1(), "");
2380 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2381 emit_int8(0x16);
2382 emit_int8((unsigned char)(0xC0 | encode));
2383 emit_int8(imm8);
2384 }
2385
2386 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2387 assert(VM_Version::supports_sse4_1(), "");
2388 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2389 emit_int8(0x16);
2390 emit_int8((unsigned char)(0xC0 | encode));
2391 emit_int8(imm8);
2392 }
2393
2394 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2395 assert(VM_Version::supports_sse4_1(), "");
2396 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2397 emit_int8(0x22);
2398 emit_int8((unsigned char)(0xC0 | encode));
2399 emit_int8(imm8);
2400 }
2401
2402 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2403 assert(VM_Version::supports_sse4_1(), "");
2404 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2405 emit_int8(0x22);
2406 emit_int8((unsigned char)(0xC0 | encode));
2407 emit_int8(imm8);
2408 }
2409
2410 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2411 assert(VM_Version::supports_sse4_1(), "");
2412 InstructionMark im(this);
2413 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2414 emit_int8(0x30);
2415 emit_operand(dst, src);
2416 }
2417
2418 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2419 assert(VM_Version::supports_sse4_1(), "");
2420 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2421 emit_int8(0x30);
2422 emit_int8((unsigned char)(0xC0 | encode));
2423 }
2424
2425 // generic
2426 void Assembler::pop(Register dst) {
2427 int encode = prefix_and_encode(dst->encoding());
2428 emit_int8(0x58 | encode);
2429 }
2430
2431 void Assembler::popcntl(Register dst, Address src) {
2432 assert(VM_Version::supports_popcnt(), "must support");
2433 InstructionMark im(this);
2434 emit_int8((unsigned char)0xF3);
2435 prefix(src, dst);
2436 emit_int8(0x0F);
2437 emit_int8((unsigned char)0xB8);
2438 emit_operand(dst, src);
2439 }
2440
2441 void Assembler::popcntl(Register dst, Register src) {
2442 assert(VM_Version::supports_popcnt(), "must support");
2443 emit_int8((unsigned char)0xF3);
2444 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2445 emit_int8(0x0F);
2446 emit_int8((unsigned char)0xB8);
2447 emit_int8((unsigned char)(0xC0 | encode));
2448 }
2449
2450 void Assembler::popf() {
2451 emit_int8((unsigned char)0x9D);
2452 }
2453
2454 #ifndef _LP64 // no 32bit push/pop on amd64
2455 void Assembler::popl(Address dst) {
2456 // NOTE: this will adjust stack by 8byte on 64bits
2457 InstructionMark im(this);
2458 prefix(dst);
2459 emit_int8((unsigned char)0x8F);
2460 emit_operand(rax, dst);
2461 }
2462 #endif
2463
2464 void Assembler::prefetch_prefix(Address src) {
2465 prefix(src);
2466 emit_int8(0x0F);
2467 }
2468
2469 void Assembler::prefetchnta(Address src) {
2470 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2471 InstructionMark im(this);
2472 prefetch_prefix(src);
2473 emit_int8(0x18);
2474 emit_operand(rax, src); // 0, src
2475 }
2476
2477 void Assembler::prefetchr(Address src) {
2478 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2479 InstructionMark im(this);
2480 prefetch_prefix(src);
2481 emit_int8(0x0D);
2482 emit_operand(rax, src); // 0, src
2483 }
2484
2485 void Assembler::prefetcht0(Address src) {
2486 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2487 InstructionMark im(this);
2488 prefetch_prefix(src);
2489 emit_int8(0x18);
2490 emit_operand(rcx, src); // 1, src
2491 }
2492
2493 void Assembler::prefetcht1(Address src) {
2494 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2495 InstructionMark im(this);
2496 prefetch_prefix(src);
2497 emit_int8(0x18);
2498 emit_operand(rdx, src); // 2, src
2499 }
2500
2501 void Assembler::prefetcht2(Address src) {
2502 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2503 InstructionMark im(this);
2504 prefetch_prefix(src);
2505 emit_int8(0x18);
2506 emit_operand(rbx, src); // 3, src
2507 }
2508
2509 void Assembler::prefetchw(Address src) {
2510 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2511 InstructionMark im(this);
2512 prefetch_prefix(src);
2513 emit_int8(0x0D);
2514 emit_operand(rcx, src); // 1, src
2515 }
2516
2517 void Assembler::prefix(Prefix p) {
2518 emit_int8(p);
2519 }
2520
2521 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2522 assert(VM_Version::supports_ssse3(), "");
2523 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2524 emit_int8(0x00);
2525 emit_int8((unsigned char)(0xC0 | encode));
2526 }
2527
2528 void Assembler::pshufb(XMMRegister dst, Address src) {
2529 assert(VM_Version::supports_ssse3(), "");
2530 InstructionMark im(this);
2531 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2532 emit_int8(0x00);
2533 emit_operand(dst, src);
2534 }
2535
2536 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2537 assert(isByte(mode), "invalid value");
2538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2539 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2540 emit_int8(mode & 0xFF);
2541
2542 }
2543
2544 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2545 assert(isByte(mode), "invalid value");
2546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2547 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2548 InstructionMark im(this);
2549 simd_prefix(dst, src, VEX_SIMD_66);
2550 emit_int8(0x70);
2551 emit_operand(dst, src);
2552 emit_int8(mode & 0xFF);
2553 }
2554
2555 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2556 assert(isByte(mode), "invalid value");
2557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2558 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2559 emit_int8(mode & 0xFF);
2560 }
2561
2562 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2563 assert(isByte(mode), "invalid value");
2564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2565 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2566 InstructionMark im(this);
2567 simd_prefix(dst, src, VEX_SIMD_F2);
2568 emit_int8(0x70);
2569 emit_operand(dst, src);
2570 emit_int8(mode & 0xFF);
2571 }
2572
2573 void Assembler::psrldq(XMMRegister dst, int shift) {
2574 // Shift 128 bit value in xmm register by number of bytes.
2575 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2576 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2577 emit_int8(0x73);
2578 emit_int8((unsigned char)(0xC0 | encode));
2579 emit_int8(shift);
2580 }
2581
2582 void Assembler::pslldq(XMMRegister dst, int shift) {
2583 // Shift left 128 bit value in xmm register by number of bytes.
2584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2585 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66);
2586 emit_int8(0x73);
2587 emit_int8((unsigned char)(0xC0 | encode));
2588 emit_int8(shift);
2589 }
2590
2591 void Assembler::ptest(XMMRegister dst, Address src) {
2592 assert(VM_Version::supports_sse4_1(), "");
2593 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2594 InstructionMark im(this);
2595 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2596 emit_int8(0x17);
2597 emit_operand(dst, src);
2598 }
2599
2600 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2601 assert(VM_Version::supports_sse4_1(), "");
2602 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2603 emit_int8(0x17);
2604 emit_int8((unsigned char)(0xC0 | encode));
2605 }
2606
2607 void Assembler::vptest(XMMRegister dst, Address src) {
2608 assert(VM_Version::supports_avx(), "");
2609 InstructionMark im(this);
2610 bool vector256 = true;
2611 assert(dst != xnoreg, "sanity");
2612 int dst_enc = dst->encoding();
2613 // swap src<->dst for encoding
2614 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2615 emit_int8(0x17);
2616 emit_operand(dst, src);
2617 }
2618
2619 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2620 assert(VM_Version::supports_avx(), "");
2621 bool vector256 = true;
2622 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2623 emit_int8(0x17);
2624 emit_int8((unsigned char)(0xC0 | encode));
2625 }
2626
2627 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2629 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2630 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2631 }
2632
2633 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2635 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2636 }
2637
2638 void Assembler::punpckldq(XMMRegister dst, Address src) {
2639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2640 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2641 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2642 }
2643
2644 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2646 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2647 }
2648
2649 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2651 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2652 }
2653
2654 void Assembler::push(int32_t imm32) {
2655 // in 64bits we push 64bits onto the stack but only
2656 // take a 32bit immediate
2657 emit_int8(0x68);
2658 emit_int32(imm32);
2659 }
2660
2661 void Assembler::push(Register src) {
2662 int encode = prefix_and_encode(src->encoding());
2663
2664 emit_int8(0x50 | encode);
2665 }
2666
2667 void Assembler::pushf() {
2668 emit_int8((unsigned char)0x9C);
2669 }
2670
2671 #ifndef _LP64 // no 32bit push/pop on amd64
2672 void Assembler::pushl(Address src) {
2673 // Note this will push 64bit on 64bit
2674 InstructionMark im(this);
2675 prefix(src);
2676 emit_int8((unsigned char)0xFF);
2677 emit_operand(rsi, src);
2678 }
2679 #endif
2680
2681 void Assembler::rcll(Register dst, int imm8) {
2682 assert(isShiftCount(imm8), "illegal shift count");
2683 int encode = prefix_and_encode(dst->encoding());
2684 if (imm8 == 1) {
2685 emit_int8((unsigned char)0xD1);
2686 emit_int8((unsigned char)(0xD0 | encode));
2687 } else {
2688 emit_int8((unsigned char)0xC1);
2689 emit_int8((unsigned char)0xD0 | encode);
2690 emit_int8(imm8);
2691 }
2692 }
2693
2694 void Assembler::rdtsc() {
2695 emit_int8((unsigned char)0x0F);
2696 emit_int8((unsigned char)0x31);
2697 }
2698
2699 // copies data from [esi] to [edi] using rcx pointer sized words
2700 // generic
2701 void Assembler::rep_mov() {
2702 emit_int8((unsigned char)0xF3);
2703 // MOVSQ
2704 LP64_ONLY(prefix(REX_W));
2705 emit_int8((unsigned char)0xA5);
2706 }
2707
2708 // sets rcx bytes with rax, value at [edi]
2709 void Assembler::rep_stosb() {
2710 emit_int8((unsigned char)0xF3); // REP
2711 LP64_ONLY(prefix(REX_W));
2712 emit_int8((unsigned char)0xAA); // STOSB
2713 }
2714
2715 // sets rcx pointer sized words with rax, value at [edi]
2716 // generic
2717 void Assembler::rep_stos() {
2718 emit_int8((unsigned char)0xF3); // REP
2719 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2720 emit_int8((unsigned char)0xAB);
2721 }
2722
2723 // scans rcx pointer sized words at [edi] for occurance of rax,
2724 // generic
2725 void Assembler::repne_scan() { // repne_scan
2726 emit_int8((unsigned char)0xF2);
2727 // SCASQ
2728 LP64_ONLY(prefix(REX_W));
2729 emit_int8((unsigned char)0xAF);
2730 }
2731
2732 #ifdef _LP64
2733 // scans rcx 4 byte words at [edi] for occurance of rax,
2734 // generic
2735 void Assembler::repne_scanl() { // repne_scan
2736 emit_int8((unsigned char)0xF2);
2737 // SCASL
2738 emit_int8((unsigned char)0xAF);
2739 }
2740 #endif
2741
2742 void Assembler::ret(int imm16) {
2743 if (imm16 == 0) {
2744 emit_int8((unsigned char)0xC3);
2745 } else {
2746 emit_int8((unsigned char)0xC2);
2747 emit_int16(imm16);
2748 }
2749 }
2750
2751 void Assembler::sahf() {
2752 #ifdef _LP64
2753 // Not supported in 64bit mode
2754 ShouldNotReachHere();
2755 #endif
2756 emit_int8((unsigned char)0x9E);
2757 }
2758
2759 void Assembler::sarl(Register dst, int imm8) {
2760 int encode = prefix_and_encode(dst->encoding());
2761 assert(isShiftCount(imm8), "illegal shift count");
2762 if (imm8 == 1) {
2763 emit_int8((unsigned char)0xD1);
2764 emit_int8((unsigned char)(0xF8 | encode));
2765 } else {
2766 emit_int8((unsigned char)0xC1);
2767 emit_int8((unsigned char)(0xF8 | encode));
2768 emit_int8(imm8);
2769 }
2770 }
2771
2772 void Assembler::sarl(Register dst) {
2773 int encode = prefix_and_encode(dst->encoding());
2774 emit_int8((unsigned char)0xD3);
2775 emit_int8((unsigned char)(0xF8 | encode));
2776 }
2777
2778 void Assembler::sbbl(Address dst, int32_t imm32) {
2779 InstructionMark im(this);
2780 prefix(dst);
2781 emit_arith_operand(0x81, rbx, dst, imm32);
2782 }
2783
2784 void Assembler::sbbl(Register dst, int32_t imm32) {
2785 prefix(dst);
2786 emit_arith(0x81, 0xD8, dst, imm32);
2787 }
2788
2789
2790 void Assembler::sbbl(Register dst, Address src) {
2791 InstructionMark im(this);
2792 prefix(src, dst);
2793 emit_int8(0x1B);
2794 emit_operand(dst, src);
2795 }
2796
2797 void Assembler::sbbl(Register dst, Register src) {
2798 (void) prefix_and_encode(dst->encoding(), src->encoding());
2799 emit_arith(0x1B, 0xC0, dst, src);
2800 }
2801
2802 void Assembler::setb(Condition cc, Register dst) {
2803 assert(0 <= cc && cc < 16, "illegal cc");
2804 int encode = prefix_and_encode(dst->encoding(), true);
2805 emit_int8(0x0F);
2806 emit_int8((unsigned char)0x90 | cc);
2807 emit_int8((unsigned char)(0xC0 | encode));
2808 }
2809
2810 void Assembler::shll(Register dst, int imm8) {
2811 assert(isShiftCount(imm8), "illegal shift count");
2812 int encode = prefix_and_encode(dst->encoding());
2813 if (imm8 == 1 ) {
2814 emit_int8((unsigned char)0xD1);
2815 emit_int8((unsigned char)(0xE0 | encode));
2816 } else {
2817 emit_int8((unsigned char)0xC1);
2818 emit_int8((unsigned char)(0xE0 | encode));
2819 emit_int8(imm8);
2820 }
2821 }
2822
2823 void Assembler::shll(Register dst) {
2824 int encode = prefix_and_encode(dst->encoding());
2825 emit_int8((unsigned char)0xD3);
2826 emit_int8((unsigned char)(0xE0 | encode));
2827 }
2828
2829 void Assembler::shrl(Register dst, int imm8) {
2830 assert(isShiftCount(imm8), "illegal shift count");
2831 int encode = prefix_and_encode(dst->encoding());
2832 emit_int8((unsigned char)0xC1);
2833 emit_int8((unsigned char)(0xE8 | encode));
2834 emit_int8(imm8);
2835 }
2836
2837 void Assembler::shrl(Register dst) {
2838 int encode = prefix_and_encode(dst->encoding());
2839 emit_int8((unsigned char)0xD3);
2840 emit_int8((unsigned char)(0xE8 | encode));
2841 }
2842
2843 // copies a single word from [esi] to [edi]
2844 void Assembler::smovl() {
2845 emit_int8((unsigned char)0xA5);
2846 }
2847
2848 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2850 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2851 }
2852
2853 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2855 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2856 }
2857
2858 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2859 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2860 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2861 }
2862
2863 void Assembler::std() {
2864 emit_int8((unsigned char)0xFD);
2865 }
2866
2867 void Assembler::sqrtss(XMMRegister dst, Address src) {
2868 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2869 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2870 }
2871
2872 void Assembler::stmxcsr( Address dst) {
2873 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2874 InstructionMark im(this);
2875 prefix(dst);
2876 emit_int8(0x0F);
2877 emit_int8((unsigned char)0xAE);
2878 emit_operand(as_Register(3), dst);
2879 }
2880
2881 void Assembler::subl(Address dst, int32_t imm32) {
2882 InstructionMark im(this);
2883 prefix(dst);
2884 emit_arith_operand(0x81, rbp, dst, imm32);
2885 }
2886
2887 void Assembler::subl(Address dst, Register src) {
2888 InstructionMark im(this);
2889 prefix(dst, src);
2890 emit_int8(0x29);
2891 emit_operand(src, dst);
2892 }
2893
2894 void Assembler::subl(Register dst, int32_t imm32) {
2895 prefix(dst);
2896 emit_arith(0x81, 0xE8, dst, imm32);
2897 }
2898
2899 // Force generation of a 4 byte immediate value even if it fits into 8bit
2900 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2901 prefix(dst);
2902 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2903 }
2904
2905 void Assembler::subl(Register dst, Address src) {
2906 InstructionMark im(this);
2907 prefix(src, dst);
2908 emit_int8(0x2B);
2909 emit_operand(dst, src);
2910 }
2911
2912 void Assembler::subl(Register dst, Register src) {
2913 (void) prefix_and_encode(dst->encoding(), src->encoding());
2914 emit_arith(0x2B, 0xC0, dst, src);
2915 }
2916
2917 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2919 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2920 }
2921
2922 void Assembler::subsd(XMMRegister dst, Address src) {
2923 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2924 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2925 }
2926
2927 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2928 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2929 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2930 }
2931
2932 void Assembler::subss(XMMRegister dst, Address src) {
2933 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2934 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2935 }
2936
2937 void Assembler::testb(Register dst, int imm8) {
2938 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2939 (void) prefix_and_encode(dst->encoding(), true);
2940 emit_arith_b(0xF6, 0xC0, dst, imm8);
2941 }
2942
2943 void Assembler::testl(Register dst, int32_t imm32) {
2944 // not using emit_arith because test
2945 // doesn't support sign-extension of
2946 // 8bit operands
2947 int encode = dst->encoding();
2948 if (encode == 0) {
2949 emit_int8((unsigned char)0xA9);
2950 } else {
2951 encode = prefix_and_encode(encode);
2952 emit_int8((unsigned char)0xF7);
2953 emit_int8((unsigned char)(0xC0 | encode));
2954 }
2955 emit_int32(imm32);
2956 }
2957
2958 void Assembler::testl(Register dst, Register src) {
2959 (void) prefix_and_encode(dst->encoding(), src->encoding());
2960 emit_arith(0x85, 0xC0, dst, src);
2961 }
2962
2963 void Assembler::testl(Register dst, Address src) {
2964 InstructionMark im(this);
2965 prefix(src, dst);
2966 emit_int8((unsigned char)0x85);
2967 emit_operand(dst, src);
2968 }
2969
2970 void Assembler::tzcntl(Register dst, Register src) {
2971 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2972 emit_int8((unsigned char)0xF3);
2973 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2974 emit_int8(0x0F);
2975 emit_int8((unsigned char)0xBC);
2976 emit_int8((unsigned char)0xC0 | encode);
2977 }
2978
2979 void Assembler::tzcntq(Register dst, Register src) {
2980 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2981 emit_int8((unsigned char)0xF3);
2982 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2983 emit_int8(0x0F);
2984 emit_int8((unsigned char)0xBC);
2985 emit_int8((unsigned char)(0xC0 | encode));
2986 }
2987
2988 void Assembler::ucomisd(XMMRegister dst, Address src) {
2989 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2990 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2991 }
2992
2993 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2995 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2996 }
2997
2998 void Assembler::ucomiss(XMMRegister dst, Address src) {
2999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3000 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
3001 }
3002
3003 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3005 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
3006 }
3007
3008 void Assembler::xabort(int8_t imm8) {
3009 emit_int8((unsigned char)0xC6);
3010 emit_int8((unsigned char)0xF8);
3011 emit_int8((unsigned char)(imm8 & 0xFF));
3012 }
3013
3014 void Assembler::xaddl(Address dst, Register src) {
3015 InstructionMark im(this);
3016 prefix(dst, src);
3017 emit_int8(0x0F);
3018 emit_int8((unsigned char)0xC1);
3019 emit_operand(src, dst);
3020 }
3021
3022 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3023 InstructionMark im(this);
3024 relocate(rtype);
3025 if (abort.is_bound()) {
3026 address entry = target(abort);
3027 assert(entry != NULL, "abort entry NULL");
3028 intptr_t offset = entry - pc();
3029 emit_int8((unsigned char)0xC7);
3030 emit_int8((unsigned char)0xF8);
3031 emit_int32(offset - 6); // 2 opcode + 4 address
3032 } else {
3033 abort.add_patch_at(code(), locator());
3034 emit_int8((unsigned char)0xC7);
3035 emit_int8((unsigned char)0xF8);
3036 emit_int32(0);
3037 }
3038 }
3039
3040 void Assembler::xchgl(Register dst, Address src) { // xchg
3041 InstructionMark im(this);
3042 prefix(src, dst);
3043 emit_int8((unsigned char)0x87);
3044 emit_operand(dst, src);
3045 }
3046
3047 void Assembler::xchgl(Register dst, Register src) {
3048 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3049 emit_int8((unsigned char)0x87);
3050 emit_int8((unsigned char)(0xC0 | encode));
3051 }
3052
3053 void Assembler::xend() {
3054 emit_int8((unsigned char)0x0F);
3055 emit_int8((unsigned char)0x01);
3056 emit_int8((unsigned char)0xD5);
3057 }
3058
3059 void Assembler::xgetbv() {
3060 emit_int8(0x0F);
3061 emit_int8(0x01);
3062 emit_int8((unsigned char)0xD0);
3063 }
3064
3065 void Assembler::xorl(Register dst, int32_t imm32) {
3066 prefix(dst);
3067 emit_arith(0x81, 0xF0, dst, imm32);
3068 }
3069
3070 void Assembler::xorl(Register dst, Address src) {
3071 InstructionMark im(this);
3072 prefix(src, dst);
3073 emit_int8(0x33);
3074 emit_operand(dst, src);
3075 }
3076
3077 void Assembler::xorl(Register dst, Register src) {
3078 (void) prefix_and_encode(dst->encoding(), src->encoding());
3079 emit_arith(0x33, 0xC0, dst, src);
3080 }
3081
3082
3083 // AVX 3-operands scalar float-point arithmetic instructions
3084
3085 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3086 assert(VM_Version::supports_avx(), "");
3087 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3088 }
3089
3090 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3091 assert(VM_Version::supports_avx(), "");
3092 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3093 }
3094
3095 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3096 assert(VM_Version::supports_avx(), "");
3097 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3098 }
3099
3100 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3101 assert(VM_Version::supports_avx(), "");
3102 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3103 }
3104
3105 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3106 assert(VM_Version::supports_avx(), "");
3107 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3108 }
3109
3110 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3111 assert(VM_Version::supports_avx(), "");
3112 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3113 }
3114
3115 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3116 assert(VM_Version::supports_avx(), "");
3117 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3118 }
3119
3120 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3121 assert(VM_Version::supports_avx(), "");
3122 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3123 }
3124
3125 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3126 assert(VM_Version::supports_avx(), "");
3127 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3128 }
3129
3130 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3131 assert(VM_Version::supports_avx(), "");
3132 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3133 }
3134
3135 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3136 assert(VM_Version::supports_avx(), "");
3137 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3138 }
3139
3140 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3141 assert(VM_Version::supports_avx(), "");
3142 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3143 }
3144
3145 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3146 assert(VM_Version::supports_avx(), "");
3147 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3148 }
3149
3150 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3151 assert(VM_Version::supports_avx(), "");
3152 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3153 }
3154
3155 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3156 assert(VM_Version::supports_avx(), "");
3157 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3158 }
3159
3160 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3161 assert(VM_Version::supports_avx(), "");
3162 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3163 }
3164
3165 //====================VECTOR ARITHMETIC=====================================
3166
3167 // Float-point vector arithmetic
3168
3169 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3170 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3171 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3172 }
3173
3174 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3175 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3176 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3177 }
3178
3179 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3180 assert(VM_Version::supports_avx(), "");
3181 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3182 }
3183
3184 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3185 assert(VM_Version::supports_avx(), "");
3186 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3187 }
3188
3189 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3190 assert(VM_Version::supports_avx(), "");
3191 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3192 }
3193
3194 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3195 assert(VM_Version::supports_avx(), "");
3196 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3197 }
3198
3199 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3201 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3202 }
3203
3204 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3205 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3206 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3207 }
3208
3209 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3210 assert(VM_Version::supports_avx(), "");
3211 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3212 }
3213
3214 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3215 assert(VM_Version::supports_avx(), "");
3216 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3217 }
3218
3219 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3220 assert(VM_Version::supports_avx(), "");
3221 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3222 }
3223
3224 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3225 assert(VM_Version::supports_avx(), "");
3226 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3227 }
3228
3229 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3231 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3232 }
3233
3234 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3236 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3237 }
3238
3239 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3240 assert(VM_Version::supports_avx(), "");
3241 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3242 }
3243
3244 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3245 assert(VM_Version::supports_avx(), "");
3246 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3247 }
3248
3249 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3250 assert(VM_Version::supports_avx(), "");
3251 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3252 }
3253
3254 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3255 assert(VM_Version::supports_avx(), "");
3256 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3257 }
3258
3259 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3261 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3262 }
3263
3264 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3265 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3266 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3267 }
3268
3269 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3270 assert(VM_Version::supports_avx(), "");
3271 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3272 }
3273
3274 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3275 assert(VM_Version::supports_avx(), "");
3276 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3277 }
3278
3279 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3280 assert(VM_Version::supports_avx(), "");
3281 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3282 }
3283
3284 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3285 assert(VM_Version::supports_avx(), "");
3286 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3287 }
3288
3289 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3291 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3292 }
3293
3294 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3295 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3296 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3297 }
3298
3299 void Assembler::andps(XMMRegister dst, Address src) {
3300 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3301 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3302 }
3303
3304 void Assembler::andpd(XMMRegister dst, Address src) {
3305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3306 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3307 }
3308
3309 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3310 assert(VM_Version::supports_avx(), "");
3311 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3312 }
3313
3314 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3315 assert(VM_Version::supports_avx(), "");
3316 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3317 }
3318
3319 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3320 assert(VM_Version::supports_avx(), "");
3321 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3322 }
3323
3324 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3325 assert(VM_Version::supports_avx(), "");
3326 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3327 }
3328
3329 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3330 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3331 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3332 }
3333
3334 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3335 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3336 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3337 }
3338
3339 void Assembler::xorpd(XMMRegister dst, Address src) {
3340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3341 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3342 }
3343
3344 void Assembler::xorps(XMMRegister dst, Address src) {
3345 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3346 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3347 }
3348
3349 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3350 assert(VM_Version::supports_avx(), "");
3351 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3352 }
3353
3354 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3355 assert(VM_Version::supports_avx(), "");
3356 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3357 }
3358
3359 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3360 assert(VM_Version::supports_avx(), "");
3361 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3362 }
3363
3364 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3365 assert(VM_Version::supports_avx(), "");
3366 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3367 }
3368
3369
3370 // Integer vector arithmetic
3371 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3373 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3374 }
3375
3376 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3378 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3379 }
3380
3381 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3383 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3384 }
3385
3386 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3388 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3389 }
3390
3391 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3392 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3393 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3394 }
3395
3396 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3397 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3398 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3399 }
3400
3401 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3402 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3403 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3404 }
3405
3406 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3407 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3408 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3409 }
3410
3411 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3412 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3413 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3414 }
3415
3416 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3417 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3418 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3419 }
3420
3421 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3422 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3423 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3424 }
3425
3426 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3427 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3428 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3429 }
3430
3431 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3433 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3434 }
3435
3436 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3438 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3439 }
3440
3441 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3443 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3444 }
3445
3446 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3448 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3449 }
3450
3451 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3452 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3453 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3454 }
3455
3456 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3457 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3458 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3459 }
3460
3461 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3462 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3463 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3464 }
3465
3466 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3467 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3468 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3469 }
3470
3471 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3472 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3473 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3474 }
3475
3476 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3477 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3478 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3479 }
3480
3481 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3482 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3483 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3484 }
3485
3486 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3487 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3488 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3489 }
3490
3491 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3492 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3493 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3494 }
3495
3496 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3497 assert(VM_Version::supports_sse4_1(), "");
3498 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3499 emit_int8(0x40);
3500 emit_int8((unsigned char)(0xC0 | encode));
3501 }
3502
3503 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3504 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3505 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3506 }
3507
3508 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3509 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3510 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3511 emit_int8(0x40);
3512 emit_int8((unsigned char)(0xC0 | encode));
3513 }
3514
3515 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3516 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3517 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3518 }
3519
3520 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3521 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3522 InstructionMark im(this);
3523 int dst_enc = dst->encoding();
3524 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3525 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3526 emit_int8(0x40);
3527 emit_operand(dst, src);
3528 }
3529
3530 // Shift packed integers left by specified number of bits.
3531 void Assembler::psllw(XMMRegister dst, int shift) {
3532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3533 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3534 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3535 emit_int8(0x71);
3536 emit_int8((unsigned char)(0xC0 | encode));
3537 emit_int8(shift & 0xFF);
3538 }
3539
3540 void Assembler::pslld(XMMRegister dst, int shift) {
3541 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3542 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3543 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3544 emit_int8(0x72);
3545 emit_int8((unsigned char)(0xC0 | encode));
3546 emit_int8(shift & 0xFF);
3547 }
3548
3549 void Assembler::psllq(XMMRegister dst, int shift) {
3550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3551 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3552 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3553 emit_int8(0x73);
3554 emit_int8((unsigned char)(0xC0 | encode));
3555 emit_int8(shift & 0xFF);
3556 }
3557
3558 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3559 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3560 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3561 }
3562
3563 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3565 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3566 }
3567
3568 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3569 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3570 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3571 }
3572
3573 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3574 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3575 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3576 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3577 emit_int8(shift & 0xFF);
3578 }
3579
3580 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3581 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3582 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3583 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3584 emit_int8(shift & 0xFF);
3585 }
3586
3587 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3588 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3589 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3590 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3591 emit_int8(shift & 0xFF);
3592 }
3593
3594 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3595 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3596 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3597 }
3598
3599 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3600 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3601 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3602 }
3603
3604 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3605 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3606 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3607 }
3608
3609 // Shift packed integers logically right by specified number of bits.
3610 void Assembler::psrlw(XMMRegister dst, int shift) {
3611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3612 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3613 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3614 emit_int8(0x71);
3615 emit_int8((unsigned char)(0xC0 | encode));
3616 emit_int8(shift & 0xFF);
3617 }
3618
3619 void Assembler::psrld(XMMRegister dst, int shift) {
3620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3621 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3622 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3623 emit_int8(0x72);
3624 emit_int8((unsigned char)(0xC0 | encode));
3625 emit_int8(shift & 0xFF);
3626 }
3627
3628 void Assembler::psrlq(XMMRegister dst, int shift) {
3629 // Do not confuse it with psrldq SSE2 instruction which
3630 // shifts 128 bit value in xmm register by number of bytes.
3631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3632 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3633 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3634 emit_int8(0x73);
3635 emit_int8((unsigned char)(0xC0 | encode));
3636 emit_int8(shift & 0xFF);
3637 }
3638
3639 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3641 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3642 }
3643
3644 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3646 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3647 }
3648
3649 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3651 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3652 }
3653
3654 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3655 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3656 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3657 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3658 emit_int8(shift & 0xFF);
3659 }
3660
3661 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3662 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3663 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3664 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3665 emit_int8(shift & 0xFF);
3666 }
3667
3668 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3669 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3670 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3671 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3672 emit_int8(shift & 0xFF);
3673 }
3674
3675 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3676 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3677 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3678 }
3679
3680 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3681 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3682 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3683 }
3684
3685 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3686 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3687 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3688 }
3689
3690 // Shift packed integers arithmetically right by specified number of bits.
3691 void Assembler::psraw(XMMRegister dst, int shift) {
3692 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3693 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3694 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3695 emit_int8(0x71);
3696 emit_int8((unsigned char)(0xC0 | encode));
3697 emit_int8(shift & 0xFF);
3698 }
3699
3700 void Assembler::psrad(XMMRegister dst, int shift) {
3701 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3702 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3703 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3704 emit_int8(0x72);
3705 emit_int8((unsigned char)(0xC0 | encode));
3706 emit_int8(shift & 0xFF);
3707 }
3708
3709 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3711 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3712 }
3713
3714 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3716 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3717 }
3718
3719 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3720 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3721 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3722 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3723 emit_int8(shift & 0xFF);
3724 }
3725
3726 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3727 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3728 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3729 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3730 emit_int8(shift & 0xFF);
3731 }
3732
3733 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3734 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3735 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3736 }
3737
3738 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3739 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3740 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3741 }
3742
3743
3744 // AND packed integers
3745 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3747 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3748 }
3749
3750 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3751 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3752 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3753 }
3754
3755 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3756 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3757 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3758 }
3759
3760 void Assembler::por(XMMRegister dst, XMMRegister src) {
3761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3762 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3763 }
3764
3765 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3766 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3767 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3768 }
3769
3770 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3771 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3772 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3773 }
3774
3775 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3777 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3778 }
3779
3780 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3781 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3782 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3783 }
3784
3785 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3786 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3787 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3788 }
3789
3790
3791 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3792 assert(VM_Version::supports_avx(), "");
3793 bool vector256 = true;
3794 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3795 emit_int8(0x18);
3796 emit_int8((unsigned char)(0xC0 | encode));
3797 // 0x00 - insert into lower 128 bits
3798 // 0x01 - insert into upper 128 bits
3799 emit_int8(0x01);
3800 }
3801
3802 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3803 assert(VM_Version::supports_avx(), "");
3804 InstructionMark im(this);
3805 bool vector256 = true;
3806 assert(dst != xnoreg, "sanity");
3807 int dst_enc = dst->encoding();
3808 // swap src<->dst for encoding
3809 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3810 emit_int8(0x18);
3811 emit_operand(dst, src);
3812 // 0x01 - insert into upper 128 bits
3813 emit_int8(0x01);
3814 }
3815
3816 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3817 assert(VM_Version::supports_avx(), "");
3818 InstructionMark im(this);
3819 bool vector256 = true;
3820 assert(src != xnoreg, "sanity");
3821 int src_enc = src->encoding();
3822 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3823 emit_int8(0x19);
3824 emit_operand(src, dst);
3825 // 0x01 - extract from upper 128 bits
3826 emit_int8(0x01);
3827 }
3828
3829 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3830 assert(VM_Version::supports_avx2(), "");
3831 bool vector256 = true;
3832 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3833 emit_int8(0x38);
3834 emit_int8((unsigned char)(0xC0 | encode));
3835 // 0x00 - insert into lower 128 bits
3836 // 0x01 - insert into upper 128 bits
3837 emit_int8(0x01);
3838 }
3839
3840 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3841 assert(VM_Version::supports_avx2(), "");
3842 InstructionMark im(this);
3843 bool vector256 = true;
3844 assert(dst != xnoreg, "sanity");
3845 int dst_enc = dst->encoding();
3846 // swap src<->dst for encoding
3847 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3848 emit_int8(0x38);
3849 emit_operand(dst, src);
3850 // 0x01 - insert into upper 128 bits
3851 emit_int8(0x01);
3852 }
3853
3854 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3855 assert(VM_Version::supports_avx2(), "");
3856 InstructionMark im(this);
3857 bool vector256 = true;
3858 assert(src != xnoreg, "sanity");
3859 int src_enc = src->encoding();
3860 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3861 emit_int8(0x39);
3862 emit_operand(src, dst);
3863 // 0x01 - extract from upper 128 bits
3864 emit_int8(0x01);
3865 }
3866
3867 // duplicate 4-bytes integer data from src into 8 locations in dest
3868 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3869 assert(VM_Version::supports_avx2(), "");
3870 bool vector256 = true;
3871 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3872 emit_int8(0x58);
3873 emit_int8((unsigned char)(0xC0 | encode));
3874 }
3875
3876 // Carry-Less Multiplication Quadword
3877 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
3878 assert(VM_Version::supports_clmul(), "");
3879 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
3880 emit_int8(0x44);
3881 emit_int8((unsigned char)(0xC0 | encode));
3882 emit_int8((unsigned char)mask);
3883 }
3884
3885 // Carry-Less Multiplication Quadword
3886 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3887 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3888 bool vector256 = false;
3889 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3890 emit_int8(0x44);
3891 emit_int8((unsigned char)(0xC0 | encode));
3892 emit_int8((unsigned char)mask);
3893 }
3894
3895 void Assembler::vzeroupper() {
3896 assert(VM_Version::supports_avx(), "");
3897 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3898 emit_int8(0x77);
3899 }
3900
3901
3902 #ifndef _LP64
3903 // 32bit only pieces of the assembler
3904
3905 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3906 // NO PREFIX AS NEVER 64BIT
3907 InstructionMark im(this);
3908 emit_int8((unsigned char)0x81);
3909 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3910 emit_data(imm32, rspec, 0);
3911 }
3912
3913 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3914 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3915 InstructionMark im(this);
3916 emit_int8((unsigned char)0x81);
3917 emit_operand(rdi, src1);
3918 emit_data(imm32, rspec, 0);
3919 }
3920
3921 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3922 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3923 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3924 void Assembler::cmpxchg8(Address adr) {
3925 InstructionMark im(this);
3926 emit_int8(0x0F);
3927 emit_int8((unsigned char)0xC7);
3928 emit_operand(rcx, adr);
3929 }
3930
3931 void Assembler::decl(Register dst) {
3932 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3933 emit_int8(0x48 | dst->encoding());
3934 }
3935
3936 #endif // _LP64
3937
3938 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3939
3940 void Assembler::fabs() {
3941 emit_int8((unsigned char)0xD9);
3942 emit_int8((unsigned char)0xE1);
3943 }
3944
3945 void Assembler::fadd(int i) {
3946 emit_farith(0xD8, 0xC0, i);
3947 }
3948
3949 void Assembler::fadd_d(Address src) {
3950 InstructionMark im(this);
3951 emit_int8((unsigned char)0xDC);
3952 emit_operand32(rax, src);
3953 }
3954
3955 void Assembler::fadd_s(Address src) {
3956 InstructionMark im(this);
3957 emit_int8((unsigned char)0xD8);
3958 emit_operand32(rax, src);
3959 }
3960
3961 void Assembler::fadda(int i) {
3962 emit_farith(0xDC, 0xC0, i);
3963 }
3964
3965 void Assembler::faddp(int i) {
3966 emit_farith(0xDE, 0xC0, i);
3967 }
3968
3969 void Assembler::fchs() {
3970 emit_int8((unsigned char)0xD9);
3971 emit_int8((unsigned char)0xE0);
3972 }
3973
3974 void Assembler::fcom(int i) {
3975 emit_farith(0xD8, 0xD0, i);
3976 }
3977
3978 void Assembler::fcomp(int i) {
3979 emit_farith(0xD8, 0xD8, i);
3980 }
3981
3982 void Assembler::fcomp_d(Address src) {
3983 InstructionMark im(this);
3984 emit_int8((unsigned char)0xDC);
3985 emit_operand32(rbx, src);
3986 }
3987
3988 void Assembler::fcomp_s(Address src) {
3989 InstructionMark im(this);
3990 emit_int8((unsigned char)0xD8);
3991 emit_operand32(rbx, src);
3992 }
3993
3994 void Assembler::fcompp() {
3995 emit_int8((unsigned char)0xDE);
3996 emit_int8((unsigned char)0xD9);
3997 }
3998
3999 void Assembler::fcos() {
4000 emit_int8((unsigned char)0xD9);
4001 emit_int8((unsigned char)0xFF);
4002 }
4003
4004 void Assembler::fdecstp() {
4005 emit_int8((unsigned char)0xD9);
4006 emit_int8((unsigned char)0xF6);
4007 }
4008
4009 void Assembler::fdiv(int i) {
4010 emit_farith(0xD8, 0xF0, i);
4011 }
4012
4013 void Assembler::fdiv_d(Address src) {
4014 InstructionMark im(this);
4015 emit_int8((unsigned char)0xDC);
4016 emit_operand32(rsi, src);
4017 }
4018
4019 void Assembler::fdiv_s(Address src) {
4020 InstructionMark im(this);
4021 emit_int8((unsigned char)0xD8);
4022 emit_operand32(rsi, src);
4023 }
4024
4025 void Assembler::fdiva(int i) {
4026 emit_farith(0xDC, 0xF8, i);
4027 }
4028
4029 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
4030 // is erroneous for some of the floating-point instructions below.
4031
4032 void Assembler::fdivp(int i) {
4033 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
4034 }
4035
4036 void Assembler::fdivr(int i) {
4037 emit_farith(0xD8, 0xF8, i);
4038 }
4039
4040 void Assembler::fdivr_d(Address src) {
4041 InstructionMark im(this);
4042 emit_int8((unsigned char)0xDC);
4043 emit_operand32(rdi, src);
4044 }
4045
4046 void Assembler::fdivr_s(Address src) {
4047 InstructionMark im(this);
4048 emit_int8((unsigned char)0xD8);
4049 emit_operand32(rdi, src);
4050 }
4051
4052 void Assembler::fdivra(int i) {
4053 emit_farith(0xDC, 0xF0, i);
4054 }
4055
4056 void Assembler::fdivrp(int i) {
4057 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
4058 }
4059
4060 void Assembler::ffree(int i) {
4061 emit_farith(0xDD, 0xC0, i);
4062 }
4063
4064 void Assembler::fild_d(Address adr) {
4065 InstructionMark im(this);
4066 emit_int8((unsigned char)0xDF);
4067 emit_operand32(rbp, adr);
4068 }
4069
4070 void Assembler::fild_s(Address adr) {
4071 InstructionMark im(this);
4072 emit_int8((unsigned char)0xDB);
4073 emit_operand32(rax, adr);
4074 }
4075
4076 void Assembler::fincstp() {
4077 emit_int8((unsigned char)0xD9);
4078 emit_int8((unsigned char)0xF7);
4079 }
4080
4081 void Assembler::finit() {
4082 emit_int8((unsigned char)0x9B);
4083 emit_int8((unsigned char)0xDB);
4084 emit_int8((unsigned char)0xE3);
4085 }
4086
4087 void Assembler::fist_s(Address adr) {
4088 InstructionMark im(this);
4089 emit_int8((unsigned char)0xDB);
4090 emit_operand32(rdx, adr);
4091 }
4092
4093 void Assembler::fistp_d(Address adr) {
4094 InstructionMark im(this);
4095 emit_int8((unsigned char)0xDF);
4096 emit_operand32(rdi, adr);
4097 }
4098
4099 void Assembler::fistp_s(Address adr) {
4100 InstructionMark im(this);
4101 emit_int8((unsigned char)0xDB);
4102 emit_operand32(rbx, adr);
4103 }
4104
4105 void Assembler::fld1() {
4106 emit_int8((unsigned char)0xD9);
4107 emit_int8((unsigned char)0xE8);
4108 }
4109
4110 void Assembler::fld_d(Address adr) {
4111 InstructionMark im(this);
4112 emit_int8((unsigned char)0xDD);
4113 emit_operand32(rax, adr);
4114 }
4115
4116 void Assembler::fld_s(Address adr) {
4117 InstructionMark im(this);
4118 emit_int8((unsigned char)0xD9);
4119 emit_operand32(rax, adr);
4120 }
4121
4122
4123 void Assembler::fld_s(int index) {
4124 emit_farith(0xD9, 0xC0, index);
4125 }
4126
4127 void Assembler::fld_x(Address adr) {
4128 InstructionMark im(this);
4129 emit_int8((unsigned char)0xDB);
4130 emit_operand32(rbp, adr);
4131 }
4132
4133 void Assembler::fldcw(Address src) {
4134 InstructionMark im(this);
4135 emit_int8((unsigned char)0xD9);
4136 emit_operand32(rbp, src);
4137 }
4138
4139 void Assembler::fldenv(Address src) {
4140 InstructionMark im(this);
4141 emit_int8((unsigned char)0xD9);
4142 emit_operand32(rsp, src);
4143 }
4144
4145 void Assembler::fldlg2() {
4146 emit_int8((unsigned char)0xD9);
4147 emit_int8((unsigned char)0xEC);
4148 }
4149
4150 void Assembler::fldln2() {
4151 emit_int8((unsigned char)0xD9);
4152 emit_int8((unsigned char)0xED);
4153 }
4154
4155 void Assembler::fldz() {
4156 emit_int8((unsigned char)0xD9);
4157 emit_int8((unsigned char)0xEE);
4158 }
4159
4160 void Assembler::flog() {
4161 fldln2();
4162 fxch();
4163 fyl2x();
4164 }
4165
4166 void Assembler::flog10() {
4167 fldlg2();
4168 fxch();
4169 fyl2x();
4170 }
4171
4172 void Assembler::fmul(int i) {
4173 emit_farith(0xD8, 0xC8, i);
4174 }
4175
4176 void Assembler::fmul_d(Address src) {
4177 InstructionMark im(this);
4178 emit_int8((unsigned char)0xDC);
4179 emit_operand32(rcx, src);
4180 }
4181
4182 void Assembler::fmul_s(Address src) {
4183 InstructionMark im(this);
4184 emit_int8((unsigned char)0xD8);
4185 emit_operand32(rcx, src);
4186 }
4187
4188 void Assembler::fmula(int i) {
4189 emit_farith(0xDC, 0xC8, i);
4190 }
4191
4192 void Assembler::fmulp(int i) {
4193 emit_farith(0xDE, 0xC8, i);
4194 }
4195
4196 void Assembler::fnsave(Address dst) {
4197 InstructionMark im(this);
4198 emit_int8((unsigned char)0xDD);
4199 emit_operand32(rsi, dst);
4200 }
4201
4202 void Assembler::fnstcw(Address src) {
4203 InstructionMark im(this);
4204 emit_int8((unsigned char)0x9B);
4205 emit_int8((unsigned char)0xD9);
4206 emit_operand32(rdi, src);
4207 }
4208
4209 void Assembler::fnstsw_ax() {
4210 emit_int8((unsigned char)0xDF);
4211 emit_int8((unsigned char)0xE0);
4212 }
4213
4214 void Assembler::fprem() {
4215 emit_int8((unsigned char)0xD9);
4216 emit_int8((unsigned char)0xF8);
4217 }
4218
4219 void Assembler::fprem1() {
4220 emit_int8((unsigned char)0xD9);
4221 emit_int8((unsigned char)0xF5);
4222 }
4223
4224 void Assembler::frstor(Address src) {
4225 InstructionMark im(this);
4226 emit_int8((unsigned char)0xDD);
4227 emit_operand32(rsp, src);
4228 }
4229
4230 void Assembler::fsin() {
4231 emit_int8((unsigned char)0xD9);
4232 emit_int8((unsigned char)0xFE);
4233 }
4234
4235 void Assembler::fsqrt() {
4236 emit_int8((unsigned char)0xD9);
4237 emit_int8((unsigned char)0xFA);
4238 }
4239
4240 void Assembler::fst_d(Address adr) {
4241 InstructionMark im(this);
4242 emit_int8((unsigned char)0xDD);
4243 emit_operand32(rdx, adr);
4244 }
4245
4246 void Assembler::fst_s(Address adr) {
4247 InstructionMark im(this);
4248 emit_int8((unsigned char)0xD9);
4249 emit_operand32(rdx, adr);
4250 }
4251
4252 void Assembler::fstp_d(Address adr) {
4253 InstructionMark im(this);
4254 emit_int8((unsigned char)0xDD);
4255 emit_operand32(rbx, adr);
4256 }
4257
4258 void Assembler::fstp_d(int index) {
4259 emit_farith(0xDD, 0xD8, index);
4260 }
4261
4262 void Assembler::fstp_s(Address adr) {
4263 InstructionMark im(this);
4264 emit_int8((unsigned char)0xD9);
4265 emit_operand32(rbx, adr);
4266 }
4267
4268 void Assembler::fstp_x(Address adr) {
4269 InstructionMark im(this);
4270 emit_int8((unsigned char)0xDB);
4271 emit_operand32(rdi, adr);
4272 }
4273
4274 void Assembler::fsub(int i) {
4275 emit_farith(0xD8, 0xE0, i);
4276 }
4277
4278 void Assembler::fsub_d(Address src) {
4279 InstructionMark im(this);
4280 emit_int8((unsigned char)0xDC);
4281 emit_operand32(rsp, src);
4282 }
4283
4284 void Assembler::fsub_s(Address src) {
4285 InstructionMark im(this);
4286 emit_int8((unsigned char)0xD8);
4287 emit_operand32(rsp, src);
4288 }
4289
4290 void Assembler::fsuba(int i) {
4291 emit_farith(0xDC, 0xE8, i);
4292 }
4293
4294 void Assembler::fsubp(int i) {
4295 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4296 }
4297
4298 void Assembler::fsubr(int i) {
4299 emit_farith(0xD8, 0xE8, i);
4300 }
4301
4302 void Assembler::fsubr_d(Address src) {
4303 InstructionMark im(this);
4304 emit_int8((unsigned char)0xDC);
4305 emit_operand32(rbp, src);
4306 }
4307
4308 void Assembler::fsubr_s(Address src) {
4309 InstructionMark im(this);
4310 emit_int8((unsigned char)0xD8);
4311 emit_operand32(rbp, src);
4312 }
4313
4314 void Assembler::fsubra(int i) {
4315 emit_farith(0xDC, 0xE0, i);
4316 }
4317
4318 void Assembler::fsubrp(int i) {
4319 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4320 }
4321
4322 void Assembler::ftan() {
4323 emit_int8((unsigned char)0xD9);
4324 emit_int8((unsigned char)0xF2);
4325 emit_int8((unsigned char)0xDD);
4326 emit_int8((unsigned char)0xD8);
4327 }
4328
4329 void Assembler::ftst() {
4330 emit_int8((unsigned char)0xD9);
4331 emit_int8((unsigned char)0xE4);
4332 }
4333
4334 void Assembler::fucomi(int i) {
4335 // make sure the instruction is supported (introduced for P6, together with cmov)
4336 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4337 emit_farith(0xDB, 0xE8, i);
4338 }
4339
4340 void Assembler::fucomip(int i) {
4341 // make sure the instruction is supported (introduced for P6, together with cmov)
4342 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4343 emit_farith(0xDF, 0xE8, i);
4344 }
4345
4346 void Assembler::fwait() {
4347 emit_int8((unsigned char)0x9B);
4348 }
4349
4350 void Assembler::fxch(int i) {
4351 emit_farith(0xD9, 0xC8, i);
4352 }
4353
4354 void Assembler::fyl2x() {
4355 emit_int8((unsigned char)0xD9);
4356 emit_int8((unsigned char)0xF1);
4357 }
4358
4359 void Assembler::frndint() {
4360 emit_int8((unsigned char)0xD9);
4361 emit_int8((unsigned char)0xFC);
4362 }
4363
4364 void Assembler::f2xm1() {
4365 emit_int8((unsigned char)0xD9);
4366 emit_int8((unsigned char)0xF0);
4367 }
4368
4369 void Assembler::fldl2e() {
4370 emit_int8((unsigned char)0xD9);
4371 emit_int8((unsigned char)0xEA);
4372 }
4373
4374 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4375 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4376 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4377 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4378
4379 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4380 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4381 if (pre > 0) {
4382 emit_int8(simd_pre[pre]);
4383 }
4384 if (rex_w) {
4385 prefixq(adr, xreg);
4386 } else {
4387 prefix(adr, xreg);
4388 }
4389 if (opc > 0) {
4390 emit_int8(0x0F);
4391 int opc2 = simd_opc[opc];
4392 if (opc2 > 0) {
4393 emit_int8(opc2);
4394 }
4395 }
4396 }
4397
4398 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4399 if (pre > 0) {
4400 emit_int8(simd_pre[pre]);
4401 }
4402 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4403 prefix_and_encode(dst_enc, src_enc);
4404 if (opc > 0) {
4405 emit_int8(0x0F);
4406 int opc2 = simd_opc[opc];
4407 if (opc2 > 0) {
4408 emit_int8(opc2);
4409 }
4410 }
4411 return encode;
4412 }
4413
4414
4415 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4416 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4417 prefix(VEX_3bytes);
4418
4419 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4420 byte1 = (~byte1) & 0xE0;
4421 byte1 |= opc;
4422 emit_int8(byte1);
4423
4424 int byte2 = ((~nds_enc) & 0xf) << 3;
4425 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4426 emit_int8(byte2);
4427 } else {
4428 prefix(VEX_2bytes);
4429
4430 int byte1 = vex_r ? VEX_R : 0;
4431 byte1 = (~byte1) & 0x80;
4432 byte1 |= ((~nds_enc) & 0xf) << 3;
4433 byte1 |= (vector256 ? 4 : 0) | pre;
4434 emit_int8(byte1);
4435 }
4436 }
4437
4438 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4439 bool vex_r = (xreg_enc >= 8);
4440 bool vex_b = adr.base_needs_rex();
4441 bool vex_x = adr.index_needs_rex();
4442 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4443 }
4444
4445 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4446 bool vex_r = (dst_enc >= 8);
4447 bool vex_b = (src_enc >= 8);
4448 bool vex_x = false;
4449 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4450 return (((dst_enc & 7) << 3) | (src_enc & 7));
4451 }
4452
4453
4454 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4455 if (UseAVX > 0) {
4456 int xreg_enc = xreg->encoding();
4457 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4458 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4459 } else {
4460 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4461 rex_prefix(adr, xreg, pre, opc, rex_w);
4462 }
4463 }
4464
4465 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4466 int dst_enc = dst->encoding();
4467 int src_enc = src->encoding();
4468 if (UseAVX > 0) {
4469 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4470 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4471 } else {
4472 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4473 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4474 }
4475 }
4476
4477 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4478 InstructionMark im(this);
4479 simd_prefix(dst, dst, src, pre);
4480 emit_int8(opcode);
4481 emit_operand(dst, src);
4482 }
4483
4484 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4485 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4486 emit_int8(opcode);
4487 emit_int8((unsigned char)(0xC0 | encode));
4488 }
4489
4490 // Versions with no second source register (non-destructive source).
4491 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4492 InstructionMark im(this);
4493 simd_prefix(dst, xnoreg, src, pre);
4494 emit_int8(opcode);
4495 emit_operand(dst, src);
4496 }
4497
4498 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4499 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4500 emit_int8(opcode);
4501 emit_int8((unsigned char)(0xC0 | encode));
4502 }
4503
4504 // 3-operands AVX instructions
4505 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4506 Address src, VexSimdPrefix pre, bool vector256) {
4507 InstructionMark im(this);
4508 vex_prefix(dst, nds, src, pre, vector256);
4509 emit_int8(opcode);
4510 emit_operand(dst, src);
4511 }
4512
4513 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4514 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4515 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4516 emit_int8(opcode);
4517 emit_int8((unsigned char)(0xC0 | encode));
4518 }
4519
4520 #ifndef _LP64
4521
4522 void Assembler::incl(Register dst) {
4523 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4524 emit_int8(0x40 | dst->encoding());
4525 }
4526
4527 void Assembler::lea(Register dst, Address src) {
4528 leal(dst, src);
4529 }
4530
4531 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4532 InstructionMark im(this);
4533 emit_int8((unsigned char)0xC7);
4534 emit_operand(rax, dst);
4535 emit_data((int)imm32, rspec, 0);
4536 }
4537
4538 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4539 InstructionMark im(this);
4540 int encode = prefix_and_encode(dst->encoding());
4541 emit_int8((unsigned char)(0xB8 | encode));
4542 emit_data((int)imm32, rspec, 0);
4543 }
4544
4545 void Assembler::popa() { // 32bit
4546 emit_int8(0x61);
4547 }
4548
4549 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4550 InstructionMark im(this);
4551 emit_int8(0x68);
4552 emit_data(imm32, rspec, 0);
4553 }
4554
4555 void Assembler::pusha() { // 32bit
4556 emit_int8(0x60);
4557 }
4558
4559 void Assembler::set_byte_if_not_zero(Register dst) {
4560 emit_int8(0x0F);
4561 emit_int8((unsigned char)0x95);
4562 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4563 }
4564
4565 void Assembler::shldl(Register dst, Register src) {
4566 emit_int8(0x0F);
4567 emit_int8((unsigned char)0xA5);
4568 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4569 }
4570
4571 void Assembler::shrdl(Register dst, Register src) {
4572 emit_int8(0x0F);
4573 emit_int8((unsigned char)0xAD);
4574 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4575 }
4576
4577 #else // LP64
4578
4579 void Assembler::set_byte_if_not_zero(Register dst) {
4580 int enc = prefix_and_encode(dst->encoding(), true);
4581 emit_int8(0x0F);
4582 emit_int8((unsigned char)0x95);
4583 emit_int8((unsigned char)(0xE0 | enc));
4584 }
4585
4586 // 64bit only pieces of the assembler
4587 // This should only be used by 64bit instructions that can use rip-relative
4588 // it cannot be used by instructions that want an immediate value.
4589
4590 bool Assembler::reachable(AddressLiteral adr) {
4591 int64_t disp;
4592 // None will force a 64bit literal to the code stream. Likely a placeholder
4593 // for something that will be patched later and we need to certain it will
4594 // always be reachable.
4595 if (adr.reloc() == relocInfo::none) {
4596 return false;
4597 }
4598 if (adr.reloc() == relocInfo::internal_word_type) {
4599 // This should be rip relative and easily reachable.
4600 return true;
4601 }
4602 if (adr.reloc() == relocInfo::virtual_call_type ||
4603 adr.reloc() == relocInfo::opt_virtual_call_type ||
4604 adr.reloc() == relocInfo::static_call_type ||
4605 adr.reloc() == relocInfo::static_stub_type ) {
4606 // This should be rip relative within the code cache and easily
4607 // reachable until we get huge code caches. (At which point
4608 // ic code is going to have issues).
4609 return true;
4610 }
4611 if (adr.reloc() != relocInfo::external_word_type &&
4612 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4613 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4614 adr.reloc() != relocInfo::runtime_call_type ) {
4615 return false;
4616 }
4617
4618 // Stress the correction code
4619 if (ForceUnreachable) {
4620 // Must be runtimecall reloc, see if it is in the codecache
4621 // Flipping stuff in the codecache to be unreachable causes issues
4622 // with things like inline caches where the additional instructions
4623 // are not handled.
4624 if (CodeCache::find_blob(adr._target) == NULL) {
4625 return false;
4626 }
4627 }
4628 // For external_word_type/runtime_call_type if it is reachable from where we
4629 // are now (possibly a temp buffer) and where we might end up
4630 // anywhere in the codeCache then we are always reachable.
4631 // This would have to change if we ever save/restore shared code
4632 // to be more pessimistic.
4633 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4634 if (!is_simm32(disp)) return false;
4635 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4636 if (!is_simm32(disp)) return false;
4637
4638 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4639
4640 // Because rip relative is a disp + address_of_next_instruction and we
4641 // don't know the value of address_of_next_instruction we apply a fudge factor
4642 // to make sure we will be ok no matter the size of the instruction we get placed into.
4643 // We don't have to fudge the checks above here because they are already worst case.
4644
4645 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4646 // + 4 because better safe than sorry.
4647 const int fudge = 12 + 4;
4648 if (disp < 0) {
4649 disp -= fudge;
4650 } else {
4651 disp += fudge;
4652 }
4653 return is_simm32(disp);
4654 }
4655
4656 // Check if the polling page is not reachable from the code cache using rip-relative
4657 // addressing.
4658 bool Assembler::is_polling_page_far() {
4659 intptr_t addr = (intptr_t)os::get_polling_page();
4660 return ForceUnreachable ||
4661 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4662 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4663 }
4664
4665 void Assembler::emit_data64(jlong data,
4666 relocInfo::relocType rtype,
4667 int format) {
4668 if (rtype == relocInfo::none) {
4669 emit_int64(data);
4670 } else {
4671 emit_data64(data, Relocation::spec_simple(rtype), format);
4672 }
4673 }
4674
4675 void Assembler::emit_data64(jlong data,
4676 RelocationHolder const& rspec,
4677 int format) {
4678 assert(imm_operand == 0, "default format must be immediate in this file");
4679 assert(imm_operand == format, "must be immediate");
4680 assert(inst_mark() != NULL, "must be inside InstructionMark");
4681 // Do not use AbstractAssembler::relocate, which is not intended for
4682 // embedded words. Instead, relocate to the enclosing instruction.
4683 code_section()->relocate(inst_mark(), rspec, format);
4684 #ifdef ASSERT
4685 check_relocation(rspec, format);
4686 #endif
4687 emit_int64(data);
4688 }
4689
4690 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4691 if (reg_enc >= 8) {
4692 prefix(REX_B);
4693 reg_enc -= 8;
4694 } else if (byteinst && reg_enc >= 4) {
4695 prefix(REX);
4696 }
4697 return reg_enc;
4698 }
4699
4700 int Assembler::prefixq_and_encode(int reg_enc) {
4701 if (reg_enc < 8) {
4702 prefix(REX_W);
4703 } else {
4704 prefix(REX_WB);
4705 reg_enc -= 8;
4706 }
4707 return reg_enc;
4708 }
4709
4710 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4711 if (dst_enc < 8) {
4712 if (src_enc >= 8) {
4713 prefix(REX_B);
4714 src_enc -= 8;
4715 } else if (byteinst && src_enc >= 4) {
4716 prefix(REX);
4717 }
4718 } else {
4719 if (src_enc < 8) {
4720 prefix(REX_R);
4721 } else {
4722 prefix(REX_RB);
4723 src_enc -= 8;
4724 }
4725 dst_enc -= 8;
4726 }
4727 return dst_enc << 3 | src_enc;
4728 }
4729
4730 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4731 if (dst_enc < 8) {
4732 if (src_enc < 8) {
4733 prefix(REX_W);
4734 } else {
4735 prefix(REX_WB);
4736 src_enc -= 8;
4737 }
4738 } else {
4739 if (src_enc < 8) {
4740 prefix(REX_WR);
4741 } else {
4742 prefix(REX_WRB);
4743 src_enc -= 8;
4744 }
4745 dst_enc -= 8;
4746 }
4747 return dst_enc << 3 | src_enc;
4748 }
4749
4750 void Assembler::prefix(Register reg) {
4751 if (reg->encoding() >= 8) {
4752 prefix(REX_B);
4753 }
4754 }
4755
4756 void Assembler::prefix(Address adr) {
4757 if (adr.base_needs_rex()) {
4758 if (adr.index_needs_rex()) {
4759 prefix(REX_XB);
4760 } else {
4761 prefix(REX_B);
4762 }
4763 } else {
4764 if (adr.index_needs_rex()) {
4765 prefix(REX_X);
4766 }
4767 }
4768 }
4769
4770 void Assembler::prefixq(Address adr) {
4771 if (adr.base_needs_rex()) {
4772 if (adr.index_needs_rex()) {
4773 prefix(REX_WXB);
4774 } else {
4775 prefix(REX_WB);
4776 }
4777 } else {
4778 if (adr.index_needs_rex()) {
4779 prefix(REX_WX);
4780 } else {
4781 prefix(REX_W);
4782 }
4783 }
4784 }
4785
4786
4787 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4788 if (reg->encoding() < 8) {
4789 if (adr.base_needs_rex()) {
4790 if (adr.index_needs_rex()) {
4791 prefix(REX_XB);
4792 } else {
4793 prefix(REX_B);
4794 }
4795 } else {
4796 if (adr.index_needs_rex()) {
4797 prefix(REX_X);
4798 } else if (byteinst && reg->encoding() >= 4 ) {
4799 prefix(REX);
4800 }
4801 }
4802 } else {
4803 if (adr.base_needs_rex()) {
4804 if (adr.index_needs_rex()) {
4805 prefix(REX_RXB);
4806 } else {
4807 prefix(REX_RB);
4808 }
4809 } else {
4810 if (adr.index_needs_rex()) {
4811 prefix(REX_RX);
4812 } else {
4813 prefix(REX_R);
4814 }
4815 }
4816 }
4817 }
4818
4819 void Assembler::prefixq(Address adr, Register src) {
4820 if (src->encoding() < 8) {
4821 if (adr.base_needs_rex()) {
4822 if (adr.index_needs_rex()) {
4823 prefix(REX_WXB);
4824 } else {
4825 prefix(REX_WB);
4826 }
4827 } else {
4828 if (adr.index_needs_rex()) {
4829 prefix(REX_WX);
4830 } else {
4831 prefix(REX_W);
4832 }
4833 }
4834 } else {
4835 if (adr.base_needs_rex()) {
4836 if (adr.index_needs_rex()) {
4837 prefix(REX_WRXB);
4838 } else {
4839 prefix(REX_WRB);
4840 }
4841 } else {
4842 if (adr.index_needs_rex()) {
4843 prefix(REX_WRX);
4844 } else {
4845 prefix(REX_WR);
4846 }
4847 }
4848 }
4849 }
4850
4851 void Assembler::prefix(Address adr, XMMRegister reg) {
4852 if (reg->encoding() < 8) {
4853 if (adr.base_needs_rex()) {
4854 if (adr.index_needs_rex()) {
4855 prefix(REX_XB);
4856 } else {
4857 prefix(REX_B);
4858 }
4859 } else {
4860 if (adr.index_needs_rex()) {
4861 prefix(REX_X);
4862 }
4863 }
4864 } else {
4865 if (adr.base_needs_rex()) {
4866 if (adr.index_needs_rex()) {
4867 prefix(REX_RXB);
4868 } else {
4869 prefix(REX_RB);
4870 }
4871 } else {
4872 if (adr.index_needs_rex()) {
4873 prefix(REX_RX);
4874 } else {
4875 prefix(REX_R);
4876 }
4877 }
4878 }
4879 }
4880
4881 void Assembler::prefixq(Address adr, XMMRegister src) {
4882 if (src->encoding() < 8) {
4883 if (adr.base_needs_rex()) {
4884 if (adr.index_needs_rex()) {
4885 prefix(REX_WXB);
4886 } else {
4887 prefix(REX_WB);
4888 }
4889 } else {
4890 if (adr.index_needs_rex()) {
4891 prefix(REX_WX);
4892 } else {
4893 prefix(REX_W);
4894 }
4895 }
4896 } else {
4897 if (adr.base_needs_rex()) {
4898 if (adr.index_needs_rex()) {
4899 prefix(REX_WRXB);
4900 } else {
4901 prefix(REX_WRB);
4902 }
4903 } else {
4904 if (adr.index_needs_rex()) {
4905 prefix(REX_WRX);
4906 } else {
4907 prefix(REX_WR);
4908 }
4909 }
4910 }
4911 }
4912
4913 void Assembler::adcq(Register dst, int32_t imm32) {
4914 (void) prefixq_and_encode(dst->encoding());
4915 emit_arith(0x81, 0xD0, dst, imm32);
4916 }
4917
4918 void Assembler::adcq(Register dst, Address src) {
4919 InstructionMark im(this);
4920 prefixq(src, dst);
4921 emit_int8(0x13);
4922 emit_operand(dst, src);
4923 }
4924
4925 void Assembler::adcq(Register dst, Register src) {
4926 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4927 emit_arith(0x13, 0xC0, dst, src);
4928 }
4929
4930 void Assembler::addq(Address dst, int32_t imm32) {
4931 InstructionMark im(this);
4932 prefixq(dst);
4933 emit_arith_operand(0x81, rax, dst,imm32);
4934 }
4935
4936 void Assembler::addq(Address dst, Register src) {
4937 InstructionMark im(this);
4938 prefixq(dst, src);
4939 emit_int8(0x01);
4940 emit_operand(src, dst);
4941 }
4942
4943 void Assembler::addq(Register dst, int32_t imm32) {
4944 (void) prefixq_and_encode(dst->encoding());
4945 emit_arith(0x81, 0xC0, dst, imm32);
4946 }
4947
4948 void Assembler::addq(Register dst, Address src) {
4949 InstructionMark im(this);
4950 prefixq(src, dst);
4951 emit_int8(0x03);
4952 emit_operand(dst, src);
4953 }
4954
4955 void Assembler::addq(Register dst, Register src) {
4956 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4957 emit_arith(0x03, 0xC0, dst, src);
4958 }
4959
4960 void Assembler::adcxq(Register dst, Register src) {
4961 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4962 emit_int8((unsigned char)0x66);
4963 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4964 emit_int8(0x0F);
4965 emit_int8(0x38);
4966 emit_int8((unsigned char)0xF6);
4967 emit_int8((unsigned char)(0xC0 | encode));
4968 }
4969
4970 void Assembler::adoxq(Register dst, Register src) {
4971 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4972 emit_int8((unsigned char)0xF3);
4973 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4974 emit_int8(0x0F);
4975 emit_int8(0x38);
4976 emit_int8((unsigned char)0xF6);
4977 emit_int8((unsigned char)(0xC0 | encode));
4978 }
4979
4980 void Assembler::andq(Address dst, int32_t imm32) {
4981 InstructionMark im(this);
4982 prefixq(dst);
4983 emit_int8((unsigned char)0x81);
4984 emit_operand(rsp, dst, 4);
4985 emit_int32(imm32);
4986 }
4987
4988 void Assembler::andq(Register dst, int32_t imm32) {
4989 (void) prefixq_and_encode(dst->encoding());
4990 emit_arith(0x81, 0xE0, dst, imm32);
4991 }
4992
4993 void Assembler::andq(Register dst, Address src) {
4994 InstructionMark im(this);
4995 prefixq(src, dst);
4996 emit_int8(0x23);
4997 emit_operand(dst, src);
4998 }
4999
5000 void Assembler::andq(Register dst, Register src) {
5001 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5002 emit_arith(0x23, 0xC0, dst, src);
5003 }
5004
5005 void Assembler::andnq(Register dst, Register src1, Register src2) {
5006 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5007 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
5008 emit_int8((unsigned char)0xF2);
5009 emit_int8((unsigned char)(0xC0 | encode));
5010 }
5011
5012 void Assembler::andnq(Register dst, Register src1, Address src2) {
5013 InstructionMark im(this);
5014 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5015 vex_prefix_0F38_q(dst, src1, src2);
5016 emit_int8((unsigned char)0xF2);
5017 emit_operand(dst, src2);
5018 }
5019
5020 void Assembler::bsfq(Register dst, Register src) {
5021 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5022 emit_int8(0x0F);
5023 emit_int8((unsigned char)0xBC);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 void Assembler::bsrq(Register dst, Register src) {
5028 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5029 emit_int8(0x0F);
5030 emit_int8((unsigned char)0xBD);
5031 emit_int8((unsigned char)(0xC0 | encode));
5032 }
5033
5034 void Assembler::bswapq(Register reg) {
5035 int encode = prefixq_and_encode(reg->encoding());
5036 emit_int8(0x0F);
5037 emit_int8((unsigned char)(0xC8 | encode));
5038 }
5039
5040 void Assembler::blsiq(Register dst, Register src) {
5041 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5042 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
5043 emit_int8((unsigned char)0xF3);
5044 emit_int8((unsigned char)(0xC0 | encode));
5045 }
5046
5047 void Assembler::blsiq(Register dst, Address src) {
5048 InstructionMark im(this);
5049 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5050 vex_prefix_0F38_q(rbx, dst, src);
5051 emit_int8((unsigned char)0xF3);
5052 emit_operand(rbx, src);
5053 }
5054
5055 void Assembler::blsmskq(Register dst, Register src) {
5056 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5057 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
5058 emit_int8((unsigned char)0xF3);
5059 emit_int8((unsigned char)(0xC0 | encode));
5060 }
5061
5062 void Assembler::blsmskq(Register dst, Address src) {
5063 InstructionMark im(this);
5064 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5065 vex_prefix_0F38_q(rdx, dst, src);
5066 emit_int8((unsigned char)0xF3);
5067 emit_operand(rdx, src);
5068 }
5069
5070 void Assembler::blsrq(Register dst, Register src) {
5071 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5072 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
5073 emit_int8((unsigned char)0xF3);
5074 emit_int8((unsigned char)(0xC0 | encode));
5075 }
5076
5077 void Assembler::blsrq(Register dst, Address src) {
5078 InstructionMark im(this);
5079 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5080 vex_prefix_0F38_q(rcx, dst, src);
5081 emit_int8((unsigned char)0xF3);
5082 emit_operand(rcx, src);
5083 }
5084
5085 void Assembler::cdqq() {
5086 prefix(REX_W);
5087 emit_int8((unsigned char)0x99);
5088 }
5089
5090 void Assembler::clflush(Address adr) {
5091 prefix(adr);
5092 emit_int8(0x0F);
5093 emit_int8((unsigned char)0xAE);
5094 emit_operand(rdi, adr);
5095 }
5096
5097 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5098 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5099 emit_int8(0x0F);
5100 emit_int8(0x40 | cc);
5101 emit_int8((unsigned char)(0xC0 | encode));
5102 }
5103
5104 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5105 InstructionMark im(this);
5106 prefixq(src, dst);
5107 emit_int8(0x0F);
5108 emit_int8(0x40 | cc);
5109 emit_operand(dst, src);
5110 }
5111
5112 void Assembler::cmpq(Address dst, int32_t imm32) {
5113 InstructionMark im(this);
5114 prefixq(dst);
5115 emit_int8((unsigned char)0x81);
5116 emit_operand(rdi, dst, 4);
5117 emit_int32(imm32);
5118 }
5119
5120 void Assembler::cmpq(Register dst, int32_t imm32) {
5121 (void) prefixq_and_encode(dst->encoding());
5122 emit_arith(0x81, 0xF8, dst, imm32);
5123 }
5124
5125 void Assembler::cmpq(Address dst, Register src) {
5126 InstructionMark im(this);
5127 prefixq(dst, src);
5128 emit_int8(0x3B);
5129 emit_operand(src, dst);
5130 }
5131
5132 void Assembler::cmpq(Register dst, Register src) {
5133 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5134 emit_arith(0x3B, 0xC0, dst, src);
5135 }
5136
5137 void Assembler::cmpq(Register dst, Address src) {
5138 InstructionMark im(this);
5139 prefixq(src, dst);
5140 emit_int8(0x3B);
5141 emit_operand(dst, src);
5142 }
5143
5144 void Assembler::cmpxchgq(Register reg, Address adr) {
5145 InstructionMark im(this);
5146 prefixq(adr, reg);
5147 emit_int8(0x0F);
5148 emit_int8((unsigned char)0xB1);
5149 emit_operand(reg, adr);
5150 }
5151
5152 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5154 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5155 emit_int8(0x2A);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5158
5159 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5160 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5161 InstructionMark im(this);
5162 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5163 emit_int8(0x2A);
5164 emit_operand(dst, src);
5165 }
5166
5167 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5168 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5169 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5170 emit_int8(0x2A);
5171 emit_int8((unsigned char)(0xC0 | encode));
5172 }
5173
5174 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5175 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5176 InstructionMark im(this);
5177 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5178 emit_int8(0x2A);
5179 emit_operand(dst, src);
5180 }
5181
5182 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5184 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5185 emit_int8(0x2C);
5186 emit_int8((unsigned char)(0xC0 | encode));
5187 }
5188
5189 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5190 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5191 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5192 emit_int8(0x2C);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5195
5196 void Assembler::decl(Register dst) {
5197 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5198 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5199 int encode = prefix_and_encode(dst->encoding());
5200 emit_int8((unsigned char)0xFF);
5201 emit_int8((unsigned char)(0xC8 | encode));
5202 }
5203
5204 void Assembler::decq(Register dst) {
5205 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5206 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5207 int encode = prefixq_and_encode(dst->encoding());
5208 emit_int8((unsigned char)0xFF);
5209 emit_int8(0xC8 | encode);
5210 }
5211
5212 void Assembler::decq(Address dst) {
5213 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5214 InstructionMark im(this);
5215 prefixq(dst);
5216 emit_int8((unsigned char)0xFF);
5217 emit_operand(rcx, dst);
5218 }
5219
5220 void Assembler::fxrstor(Address src) {
5221 prefixq(src);
5222 emit_int8(0x0F);
5223 emit_int8((unsigned char)0xAE);
5224 emit_operand(as_Register(1), src);
5225 }
5226
5227 void Assembler::fxsave(Address dst) {
5228 prefixq(dst);
5229 emit_int8(0x0F);
5230 emit_int8((unsigned char)0xAE);
5231 emit_operand(as_Register(0), dst);
5232 }
5233
5234 void Assembler::idivq(Register src) {
5235 int encode = prefixq_and_encode(src->encoding());
5236 emit_int8((unsigned char)0xF7);
5237 emit_int8((unsigned char)(0xF8 | encode));
5238 }
5239
5240 void Assembler::imulq(Register dst, Register src) {
5241 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5242 emit_int8(0x0F);
5243 emit_int8((unsigned char)0xAF);
5244 emit_int8((unsigned char)(0xC0 | encode));
5245 }
5246
5247 void Assembler::imulq(Register dst, Register src, int value) {
5248 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5249 if (is8bit(value)) {
5250 emit_int8(0x6B);
5251 emit_int8((unsigned char)(0xC0 | encode));
5252 emit_int8(value & 0xFF);
5253 } else {
5254 emit_int8(0x69);
5255 emit_int8((unsigned char)(0xC0 | encode));
5256 emit_int32(value);
5257 }
5258 }
5259
5260 void Assembler::imulq(Register dst, Address src) {
5261 InstructionMark im(this);
5262 prefixq(src, dst);
5263 emit_int8(0x0F);
5264 emit_int8((unsigned char) 0xAF);
5265 emit_operand(dst, src);
5266 }
5267
5268 void Assembler::incl(Register dst) {
5269 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5270 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5271 int encode = prefix_and_encode(dst->encoding());
5272 emit_int8((unsigned char)0xFF);
5273 emit_int8((unsigned char)(0xC0 | encode));
5274 }
5275
5276 void Assembler::incq(Register dst) {
5277 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5278 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5279 int encode = prefixq_and_encode(dst->encoding());
5280 emit_int8((unsigned char)0xFF);
5281 emit_int8((unsigned char)(0xC0 | encode));
5282 }
5283
5284 void Assembler::incq(Address dst) {
5285 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5286 InstructionMark im(this);
5287 prefixq(dst);
5288 emit_int8((unsigned char)0xFF);
5289 emit_operand(rax, dst);
5290 }
5291
5292 void Assembler::lea(Register dst, Address src) {
5293 leaq(dst, src);
5294 }
5295
5296 void Assembler::leaq(Register dst, Address src) {
5297 InstructionMark im(this);
5298 prefixq(src, dst);
5299 emit_int8((unsigned char)0x8D);
5300 emit_operand(dst, src);
5301 }
5302
5303 void Assembler::mov64(Register dst, int64_t imm64) {
5304 InstructionMark im(this);
5305 int encode = prefixq_and_encode(dst->encoding());
5306 emit_int8((unsigned char)(0xB8 | encode));
5307 emit_int64(imm64);
5308 }
5309
5310 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5311 InstructionMark im(this);
5312 int encode = prefixq_and_encode(dst->encoding());
5313 emit_int8(0xB8 | encode);
5314 emit_data64(imm64, rspec);
5315 }
5316
5317 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5318 InstructionMark im(this);
5319 int encode = prefix_and_encode(dst->encoding());
5320 emit_int8((unsigned char)(0xB8 | encode));
5321 emit_data((int)imm32, rspec, narrow_oop_operand);
5322 }
5323
5324 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5325 InstructionMark im(this);
5326 prefix(dst);
5327 emit_int8((unsigned char)0xC7);
5328 emit_operand(rax, dst, 4);
5329 emit_data((int)imm32, rspec, narrow_oop_operand);
5330 }
5331
5332 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5333 InstructionMark im(this);
5334 int encode = prefix_and_encode(src1->encoding());
5335 emit_int8((unsigned char)0x81);
5336 emit_int8((unsigned char)(0xF8 | encode));
5337 emit_data((int)imm32, rspec, narrow_oop_operand);
5338 }
5339
5340 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5341 InstructionMark im(this);
5342 prefix(src1);
5343 emit_int8((unsigned char)0x81);
5344 emit_operand(rax, src1, 4);
5345 emit_data((int)imm32, rspec, narrow_oop_operand);
5346 }
5347
5348 void Assembler::lzcntq(Register dst, Register src) {
5349 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5350 emit_int8((unsigned char)0xF3);
5351 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5352 emit_int8(0x0F);
5353 emit_int8((unsigned char)0xBD);
5354 emit_int8((unsigned char)(0xC0 | encode));
5355 }
5356
5357 void Assembler::movdq(XMMRegister dst, Register src) {
5358 // table D-1 says MMX/SSE2
5359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5360 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5361 emit_int8(0x6E);
5362 emit_int8((unsigned char)(0xC0 | encode));
5363 }
5364
5365 void Assembler::movdq(Register dst, XMMRegister src) {
5366 // table D-1 says MMX/SSE2
5367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5368 // swap src/dst to get correct prefix
5369 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5370 emit_int8(0x7E);
5371 emit_int8((unsigned char)(0xC0 | encode));
5372 }
5373
5374 void Assembler::movq(Register dst, Register src) {
5375 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5376 emit_int8((unsigned char)0x8B);
5377 emit_int8((unsigned char)(0xC0 | encode));
5378 }
5379
5380 void Assembler::movq(Register dst, Address src) {
5381 InstructionMark im(this);
5382 prefixq(src, dst);
5383 emit_int8((unsigned char)0x8B);
5384 emit_operand(dst, src);
5385 }
5386
5387 void Assembler::movq(Address dst, Register src) {
5388 InstructionMark im(this);
5389 prefixq(dst, src);
5390 emit_int8((unsigned char)0x89);
5391 emit_operand(src, dst);
5392 }
5393
5394 void Assembler::movsbq(Register dst, Address src) {
5395 InstructionMark im(this);
5396 prefixq(src, dst);
5397 emit_int8(0x0F);
5398 emit_int8((unsigned char)0xBE);
5399 emit_operand(dst, src);
5400 }
5401
5402 void Assembler::movsbq(Register dst, Register src) {
5403 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5404 emit_int8(0x0F);
5405 emit_int8((unsigned char)0xBE);
5406 emit_int8((unsigned char)(0xC0 | encode));
5407 }
5408
5409 void Assembler::movslq(Register dst, int32_t imm32) {
5410 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5411 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5412 // as a result we shouldn't use until tested at runtime...
5413 ShouldNotReachHere();
5414 InstructionMark im(this);
5415 int encode = prefixq_and_encode(dst->encoding());
5416 emit_int8((unsigned char)(0xC7 | encode));
5417 emit_int32(imm32);
5418 }
5419
5420 void Assembler::movslq(Address dst, int32_t imm32) {
5421 assert(is_simm32(imm32), "lost bits");
5422 InstructionMark im(this);
5423 prefixq(dst);
5424 emit_int8((unsigned char)0xC7);
5425 emit_operand(rax, dst, 4);
5426 emit_int32(imm32);
5427 }
5428
5429 void Assembler::movslq(Register dst, Address src) {
5430 InstructionMark im(this);
5431 prefixq(src, dst);
5432 emit_int8(0x63);
5433 emit_operand(dst, src);
5434 }
5435
5436 void Assembler::movslq(Register dst, Register src) {
5437 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5438 emit_int8(0x63);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 }
5441
5442 void Assembler::movswq(Register dst, Address src) {
5443 InstructionMark im(this);
5444 prefixq(src, dst);
5445 emit_int8(0x0F);
5446 emit_int8((unsigned char)0xBF);
5447 emit_operand(dst, src);
5448 }
5449
5450 void Assembler::movswq(Register dst, Register src) {
5451 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5452 emit_int8((unsigned char)0x0F);
5453 emit_int8((unsigned char)0xBF);
5454 emit_int8((unsigned char)(0xC0 | encode));
5455 }
5456
5457 void Assembler::movzbq(Register dst, Address src) {
5458 InstructionMark im(this);
5459 prefixq(src, dst);
5460 emit_int8((unsigned char)0x0F);
5461 emit_int8((unsigned char)0xB6);
5462 emit_operand(dst, src);
5463 }
5464
5465 void Assembler::movzbq(Register dst, Register src) {
5466 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5467 emit_int8(0x0F);
5468 emit_int8((unsigned char)0xB6);
5469 emit_int8(0xC0 | encode);
5470 }
5471
5472 void Assembler::movzwq(Register dst, Address src) {
5473 InstructionMark im(this);
5474 prefixq(src, dst);
5475 emit_int8((unsigned char)0x0F);
5476 emit_int8((unsigned char)0xB7);
5477 emit_operand(dst, src);
5478 }
5479
5480 void Assembler::movzwq(Register dst, Register src) {
5481 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5482 emit_int8((unsigned char)0x0F);
5483 emit_int8((unsigned char)0xB7);
5484 emit_int8((unsigned char)(0xC0 | encode));
5485 }
5486
5487 void Assembler::mulq(Address src) {
5488 InstructionMark im(this);
5489 prefixq(src);
5490 emit_int8((unsigned char)0xF7);
5491 emit_operand(rsp, src);
5492 }
5493
5494 void Assembler::mulq(Register src) {
5495 int encode = prefixq_and_encode(src->encoding());
5496 emit_int8((unsigned char)0xF7);
5497 emit_int8((unsigned char)(0xE0 | encode));
5498 }
5499
5500 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
5501 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5502 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false);
5503 emit_int8((unsigned char)0xF6);
5504 emit_int8((unsigned char)(0xC0 | encode));
5505 }
5506
5507 void Assembler::negq(Register dst) {
5508 int encode = prefixq_and_encode(dst->encoding());
5509 emit_int8((unsigned char)0xF7);
5510 emit_int8((unsigned char)(0xD8 | encode));
5511 }
5512
5513 void Assembler::notq(Register dst) {
5514 int encode = prefixq_and_encode(dst->encoding());
5515 emit_int8((unsigned char)0xF7);
5516 emit_int8((unsigned char)(0xD0 | encode));
5517 }
5518
5519 void Assembler::orq(Address dst, int32_t imm32) {
5520 InstructionMark im(this);
5521 prefixq(dst);
5522 emit_int8((unsigned char)0x81);
5523 emit_operand(rcx, dst, 4);
5524 emit_int32(imm32);
5525 }
5526
5527 void Assembler::orq(Register dst, int32_t imm32) {
5528 (void) prefixq_and_encode(dst->encoding());
5529 emit_arith(0x81, 0xC8, dst, imm32);
5530 }
5531
5532 void Assembler::orq(Register dst, Address src) {
5533 InstructionMark im(this);
5534 prefixq(src, dst);
5535 emit_int8(0x0B);
5536 emit_operand(dst, src);
5537 }
5538
5539 void Assembler::orq(Register dst, Register src) {
5540 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5541 emit_arith(0x0B, 0xC0, dst, src);
5542 }
5543
5544 void Assembler::popa() { // 64bit
5545 movq(r15, Address(rsp, 0));
5546 movq(r14, Address(rsp, wordSize));
5547 movq(r13, Address(rsp, 2 * wordSize));
5548 movq(r12, Address(rsp, 3 * wordSize));
5549 movq(r11, Address(rsp, 4 * wordSize));
5550 movq(r10, Address(rsp, 5 * wordSize));
5551 movq(r9, Address(rsp, 6 * wordSize));
5552 movq(r8, Address(rsp, 7 * wordSize));
5553 movq(rdi, Address(rsp, 8 * wordSize));
5554 movq(rsi, Address(rsp, 9 * wordSize));
5555 movq(rbp, Address(rsp, 10 * wordSize));
5556 // skip rsp
5557 movq(rbx, Address(rsp, 12 * wordSize));
5558 movq(rdx, Address(rsp, 13 * wordSize));
5559 movq(rcx, Address(rsp, 14 * wordSize));
5560 movq(rax, Address(rsp, 15 * wordSize));
5561
5562 addq(rsp, 16 * wordSize);
5563 }
5564
5565 void Assembler::popcntq(Register dst, Address src) {
5566 assert(VM_Version::supports_popcnt(), "must support");
5567 InstructionMark im(this);
5568 emit_int8((unsigned char)0xF3);
5569 prefixq(src, dst);
5570 emit_int8((unsigned char)0x0F);
5571 emit_int8((unsigned char)0xB8);
5572 emit_operand(dst, src);
5573 }
5574
5575 void Assembler::popcntq(Register dst, Register src) {
5576 assert(VM_Version::supports_popcnt(), "must support");
5577 emit_int8((unsigned char)0xF3);
5578 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5579 emit_int8((unsigned char)0x0F);
5580 emit_int8((unsigned char)0xB8);
5581 emit_int8((unsigned char)(0xC0 | encode));
5582 }
5583
5584 void Assembler::popq(Address dst) {
5585 InstructionMark im(this);
5586 prefixq(dst);
5587 emit_int8((unsigned char)0x8F);
5588 emit_operand(rax, dst);
5589 }
5590
5591 void Assembler::pusha() { // 64bit
5592 // we have to store original rsp. ABI says that 128 bytes
5593 // below rsp are local scratch.
5594 movq(Address(rsp, -5 * wordSize), rsp);
5595
5596 subq(rsp, 16 * wordSize);
5597
5598 movq(Address(rsp, 15 * wordSize), rax);
5599 movq(Address(rsp, 14 * wordSize), rcx);
5600 movq(Address(rsp, 13 * wordSize), rdx);
5601 movq(Address(rsp, 12 * wordSize), rbx);
5602 // skip rsp
5603 movq(Address(rsp, 10 * wordSize), rbp);
5604 movq(Address(rsp, 9 * wordSize), rsi);
5605 movq(Address(rsp, 8 * wordSize), rdi);
5606 movq(Address(rsp, 7 * wordSize), r8);
5607 movq(Address(rsp, 6 * wordSize), r9);
5608 movq(Address(rsp, 5 * wordSize), r10);
5609 movq(Address(rsp, 4 * wordSize), r11);
5610 movq(Address(rsp, 3 * wordSize), r12);
5611 movq(Address(rsp, 2 * wordSize), r13);
5612 movq(Address(rsp, wordSize), r14);
5613 movq(Address(rsp, 0), r15);
5614 }
5615
5616 void Assembler::pushq(Address src) {
5617 InstructionMark im(this);
5618 prefixq(src);
5619 emit_int8((unsigned char)0xFF);
5620 emit_operand(rsi, src);
5621 }
5622
5623 void Assembler::rclq(Register dst, int imm8) {
5624 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5625 int encode = prefixq_and_encode(dst->encoding());
5626 if (imm8 == 1) {
5627 emit_int8((unsigned char)0xD1);
5628 emit_int8((unsigned char)(0xD0 | encode));
5629 } else {
5630 emit_int8((unsigned char)0xC1);
5631 emit_int8((unsigned char)(0xD0 | encode));
5632 emit_int8(imm8);
5633 }
5634 }
5635
5636 void Assembler::rorq(Register dst, int imm8) {
5637 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5638 int encode = prefixq_and_encode(dst->encoding());
5639 if (imm8 == 1) {
5640 emit_int8((unsigned char)0xD1);
5641 emit_int8((unsigned char)(0xC8 | encode));
5642 } else {
5643 emit_int8((unsigned char)0xC1);
5644 emit_int8((unsigned char)(0xc8 | encode));
5645 emit_int8(imm8);
5646 }
5647 }
5648
5649 void Assembler::rorxq(Register dst, Register src, int imm8) {
5650 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5651 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);
5652 emit_int8((unsigned char)0xF0);
5653 emit_int8((unsigned char)(0xC0 | encode));
5654 emit_int8(imm8);
5655 }
5656
5657 void Assembler::sarq(Register dst, int imm8) {
5658 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5659 int encode = prefixq_and_encode(dst->encoding());
5660 if (imm8 == 1) {
5661 emit_int8((unsigned char)0xD1);
5662 emit_int8((unsigned char)(0xF8 | encode));
5663 } else {
5664 emit_int8((unsigned char)0xC1);
5665 emit_int8((unsigned char)(0xF8 | encode));
5666 emit_int8(imm8);
5667 }
5668 }
5669
5670 void Assembler::sarq(Register dst) {
5671 int encode = prefixq_and_encode(dst->encoding());
5672 emit_int8((unsigned char)0xD3);
5673 emit_int8((unsigned char)(0xF8 | encode));
5674 }
5675
5676 void Assembler::sbbq(Address dst, int32_t imm32) {
5677 InstructionMark im(this);
5678 prefixq(dst);
5679 emit_arith_operand(0x81, rbx, dst, imm32);
5680 }
5681
5682 void Assembler::sbbq(Register dst, int32_t imm32) {
5683 (void) prefixq_and_encode(dst->encoding());
5684 emit_arith(0x81, 0xD8, dst, imm32);
5685 }
5686
5687 void Assembler::sbbq(Register dst, Address src) {
5688 InstructionMark im(this);
5689 prefixq(src, dst);
5690 emit_int8(0x1B);
5691 emit_operand(dst, src);
5692 }
5693
5694 void Assembler::sbbq(Register dst, Register src) {
5695 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5696 emit_arith(0x1B, 0xC0, dst, src);
5697 }
5698
5699 void Assembler::shlq(Register dst, int imm8) {
5700 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5701 int encode = prefixq_and_encode(dst->encoding());
5702 if (imm8 == 1) {
5703 emit_int8((unsigned char)0xD1);
5704 emit_int8((unsigned char)(0xE0 | encode));
5705 } else {
5706 emit_int8((unsigned char)0xC1);
5707 emit_int8((unsigned char)(0xE0 | encode));
5708 emit_int8(imm8);
5709 }
5710 }
5711
5712 void Assembler::shlq(Register dst) {
5713 int encode = prefixq_and_encode(dst->encoding());
5714 emit_int8((unsigned char)0xD3);
5715 emit_int8((unsigned char)(0xE0 | encode));
5716 }
5717
5718 void Assembler::shrq(Register dst, int imm8) {
5719 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5720 int encode = prefixq_and_encode(dst->encoding());
5721 emit_int8((unsigned char)0xC1);
5722 emit_int8((unsigned char)(0xE8 | encode));
5723 emit_int8(imm8);
5724 }
5725
5726 void Assembler::shrq(Register dst) {
5727 int encode = prefixq_and_encode(dst->encoding());
5728 emit_int8((unsigned char)0xD3);
5729 emit_int8(0xE8 | encode);
5730 }
5731
5732 void Assembler::subq(Address dst, int32_t imm32) {
5733 InstructionMark im(this);
5734 prefixq(dst);
5735 emit_arith_operand(0x81, rbp, dst, imm32);
5736 }
5737
5738 void Assembler::subq(Address dst, Register src) {
5739 InstructionMark im(this);
5740 prefixq(dst, src);
5741 emit_int8(0x29);
5742 emit_operand(src, dst);
5743 }
5744
5745 void Assembler::subq(Register dst, int32_t imm32) {
5746 (void) prefixq_and_encode(dst->encoding());
5747 emit_arith(0x81, 0xE8, dst, imm32);
5748 }
5749
5750 // Force generation of a 4 byte immediate value even if it fits into 8bit
5751 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5752 (void) prefixq_and_encode(dst->encoding());
5753 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5754 }
5755
5756 void Assembler::subq(Register dst, Address src) {
5757 InstructionMark im(this);
5758 prefixq(src, dst);
5759 emit_int8(0x2B);
5760 emit_operand(dst, src);
5761 }
5762
5763 void Assembler::subq(Register dst, Register src) {
5764 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5765 emit_arith(0x2B, 0xC0, dst, src);
5766 }
5767
5768 void Assembler::testq(Register dst, int32_t imm32) {
5769 // not using emit_arith because test
5770 // doesn't support sign-extension of
5771 // 8bit operands
5772 int encode = dst->encoding();
5773 if (encode == 0) {
5774 prefix(REX_W);
5775 emit_int8((unsigned char)0xA9);
5776 } else {
5777 encode = prefixq_and_encode(encode);
5778 emit_int8((unsigned char)0xF7);
5779 emit_int8((unsigned char)(0xC0 | encode));
5780 }
5781 emit_int32(imm32);
5782 }
5783
5784 void Assembler::testq(Register dst, Register src) {
5785 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5786 emit_arith(0x85, 0xC0, dst, src);
5787 }
5788
5789 void Assembler::xaddq(Address dst, Register src) {
5790 InstructionMark im(this);
5791 prefixq(dst, src);
5792 emit_int8(0x0F);
5793 emit_int8((unsigned char)0xC1);
5794 emit_operand(src, dst);
5795 }
5796
5797 void Assembler::xchgq(Register dst, Address src) {
5798 InstructionMark im(this);
5799 prefixq(src, dst);
5800 emit_int8((unsigned char)0x87);
5801 emit_operand(dst, src);
5802 }
5803
5804 void Assembler::xchgq(Register dst, Register src) {
5805 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5806 emit_int8((unsigned char)0x87);
5807 emit_int8((unsigned char)(0xc0 | encode));
5808 }
5809
5810 void Assembler::xorq(Register dst, Register src) {
5811 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5812 emit_arith(0x33, 0xC0, dst, src);
5813 }
5814
5815 void Assembler::xorq(Register dst, Address src) {
5816 InstructionMark im(this);
5817 prefixq(src, dst);
5818 emit_int8(0x33);
5819 emit_operand(dst, src);
5820 }
5821
5822 #endif // !LP64