1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "vm_version_x86.hpp" 30 31 class BiasedLockingCounters; 32 33 // Contains all the definitions needed for x86 assembly code generation. 34 35 // Calling convention 36 class Argument VALUE_OBJ_CLASS_SPEC { 37 public: 38 enum { 39 #ifdef _LP64 40 #ifdef _WIN64 41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 43 #else 44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 46 #endif // _WIN64 47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 49 #else 50 n_register_parameters = 0 // 0 registers used to pass arguments 51 #endif // _LP64 52 }; 53 }; 54 55 56 #ifdef _LP64 57 // Symbolically name the register arguments used by the c calling convention. 58 // Windows is different from linux/solaris. So much for standards... 59 60 #ifdef _WIN64 61 62 REGISTER_DECLARATION(Register, c_rarg0, rcx); 63 REGISTER_DECLARATION(Register, c_rarg1, rdx); 64 REGISTER_DECLARATION(Register, c_rarg2, r8); 65 REGISTER_DECLARATION(Register, c_rarg3, r9); 66 67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 71 72 #else 73 74 REGISTER_DECLARATION(Register, c_rarg0, rdi); 75 REGISTER_DECLARATION(Register, c_rarg1, rsi); 76 REGISTER_DECLARATION(Register, c_rarg2, rdx); 77 REGISTER_DECLARATION(Register, c_rarg3, rcx); 78 REGISTER_DECLARATION(Register, c_rarg4, r8); 79 REGISTER_DECLARATION(Register, c_rarg5, r9); 80 81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 89 90 #endif // _WIN64 91 92 // Symbolically name the register arguments used by the Java calling convention. 93 // We have control over the convention for java so we can do what we please. 94 // What pleases us is to offset the java calling convention so that when 95 // we call a suitable jni method the arguments are lined up and we don't 96 // have to do little shuffling. A suitable jni method is non-static and a 97 // small number of arguments (two fewer args on windows) 98 // 99 // |-------------------------------------------------------| 100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 101 // |-------------------------------------------------------| 102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 103 // | rdi rsi rdx rcx r8 r9 | solaris/linux 104 // |-------------------------------------------------------| 105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 106 // |-------------------------------------------------------| 107 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 111 // Windows runs out of register args here 112 #ifdef _WIN64 113 REGISTER_DECLARATION(Register, j_rarg3, rdi); 114 REGISTER_DECLARATION(Register, j_rarg4, rsi); 115 #else 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 118 #endif /* _WIN64 */ 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 120 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 129 130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 132 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 135 136 #else 137 // rscratch1 will apear in 32bit code that is dead but of course must compile 138 // Using noreg ensures if the dead code is incorrectly live and executed it 139 // will cause an assertion failure 140 #define rscratch1 noreg 141 #define rscratch2 noreg 142 143 #endif // _LP64 144 145 // JSR 292 fixed register usages: 146 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); 147 148 // Address is an abstraction used to represent a memory location 149 // using any of the amd64 addressing modes with one object. 150 // 151 // Note: A register location is represented via a Register, not 152 // via an address for efficiency & simplicity reasons. 153 154 class ArrayAddress; 155 156 class Address VALUE_OBJ_CLASS_SPEC { 157 public: 158 enum ScaleFactor { 159 no_scale = -1, 160 times_1 = 0, 161 times_2 = 1, 162 times_4 = 2, 163 times_8 = 3, 164 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 165 }; 166 static ScaleFactor times(int size) { 167 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 168 if (size == 8) return times_8; 169 if (size == 4) return times_4; 170 if (size == 2) return times_2; 171 return times_1; 172 } 173 static int scale_size(ScaleFactor scale) { 174 assert(scale != no_scale, ""); 175 assert(((1 << (int)times_1) == 1 && 176 (1 << (int)times_2) == 2 && 177 (1 << (int)times_4) == 4 && 178 (1 << (int)times_8) == 8), ""); 179 return (1 << (int)scale); 180 } 181 182 private: 183 Register _base; 184 Register _index; 185 ScaleFactor _scale; 186 int _disp; 187 RelocationHolder _rspec; 188 189 // Easily misused constructors make them private 190 // %%% can we make these go away? 191 NOT_LP64(Address(address loc, RelocationHolder spec);) 192 Address(int disp, address loc, relocInfo::relocType rtype); 193 Address(int disp, address loc, RelocationHolder spec); 194 195 public: 196 197 int disp() { return _disp; } 198 // creation 199 Address() 200 : _base(noreg), 201 _index(noreg), 202 _scale(no_scale), 203 _disp(0) { 204 } 205 206 // No default displacement otherwise Register can be implicitly 207 // converted to 0(Register) which is quite a different animal. 208 209 Address(Register base, int disp) 210 : _base(base), 211 _index(noreg), 212 _scale(no_scale), 213 _disp(disp) { 214 } 215 216 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 217 : _base (base), 218 _index(index), 219 _scale(scale), 220 _disp (disp) { 221 assert(!index->is_valid() == (scale == Address::no_scale), 222 "inconsistent address"); 223 } 224 225 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 226 : _base (base), 227 _index(index.register_or_noreg()), 228 _scale(scale), 229 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { 230 if (!index.is_register()) scale = Address::no_scale; 231 assert(!_index->is_valid() == (scale == Address::no_scale), 232 "inconsistent address"); 233 } 234 235 Address plus_disp(int disp) const { 236 Address a = (*this); 237 a._disp += disp; 238 return a; 239 } 240 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { 241 Address a = (*this); 242 a._disp += disp.constant_or_zero() * scale_size(scale); 243 if (disp.is_register()) { 244 assert(!a.index()->is_valid(), "competing indexes"); 245 a._index = disp.as_register(); 246 a._scale = scale; 247 } 248 return a; 249 } 250 bool is_same_address(Address a) const { 251 // disregard _rspec 252 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; 253 } 254 255 // The following two overloads are used in connection with the 256 // ByteSize type (see sizes.hpp). They simplify the use of 257 // ByteSize'd arguments in assembly code. Note that their equivalent 258 // for the optimized build are the member functions with int disp 259 // argument since ByteSize is mapped to an int type in that case. 260 // 261 // Note: DO NOT introduce similar overloaded functions for WordSize 262 // arguments as in the optimized mode, both ByteSize and WordSize 263 // are mapped to the same type and thus the compiler cannot make a 264 // distinction anymore (=> compiler errors). 265 266 #ifdef ASSERT 267 Address(Register base, ByteSize disp) 268 : _base(base), 269 _index(noreg), 270 _scale(no_scale), 271 _disp(in_bytes(disp)) { 272 } 273 274 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 275 : _base(base), 276 _index(index), 277 _scale(scale), 278 _disp(in_bytes(disp)) { 279 assert(!index->is_valid() == (scale == Address::no_scale), 280 "inconsistent address"); 281 } 282 283 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 284 : _base (base), 285 _index(index.register_or_noreg()), 286 _scale(scale), 287 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { 288 if (!index.is_register()) scale = Address::no_scale; 289 assert(!_index->is_valid() == (scale == Address::no_scale), 290 "inconsistent address"); 291 } 292 293 #endif // ASSERT 294 295 // accessors 296 bool uses(Register reg) const { return _base == reg || _index == reg; } 297 Register base() const { return _base; } 298 Register index() const { return _index; } 299 ScaleFactor scale() const { return _scale; } 300 int disp() const { return _disp; } 301 302 // Convert the raw encoding form into the form expected by the constructor for 303 // Address. An index of 4 (rsp) corresponds to having no index, so convert 304 // that to noreg for the Address constructor. 305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 306 307 static Address make_array(ArrayAddress); 308 309 private: 310 bool base_needs_rex() const { 311 return _base != noreg && _base->encoding() >= 8; 312 } 313 314 bool index_needs_rex() const { 315 return _index != noreg &&_index->encoding() >= 8; 316 } 317 318 relocInfo::relocType reloc() const { return _rspec.type(); } 319 320 friend class Assembler; 321 friend class MacroAssembler; 322 friend class LIR_Assembler; // base/index/scale/disp 323 }; 324 325 // 326 // AddressLiteral has been split out from Address because operands of this type 327 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 328 // the few instructions that need to deal with address literals are unique and the 329 // MacroAssembler does not have to implement every instruction in the Assembler 330 // in order to search for address literals that may need special handling depending 331 // on the instruction and the platform. As small step on the way to merging i486/amd64 332 // directories. 333 // 334 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 335 friend class ArrayAddress; 336 RelocationHolder _rspec; 337 // Typically we use AddressLiterals we want to use their rval 338 // However in some situations we want the lval (effect address) of the item. 339 // We provide a special factory for making those lvals. 340 bool _is_lval; 341 342 // If the target is far we'll need to load the ea of this to 343 // a register to reach it. Otherwise if near we can do rip 344 // relative addressing. 345 346 address _target; 347 348 protected: 349 // creation 350 AddressLiteral() 351 : _is_lval(false), 352 _target(NULL) 353 {} 354 355 public: 356 357 358 AddressLiteral(address target, relocInfo::relocType rtype); 359 360 AddressLiteral(address target, RelocationHolder const& rspec) 361 : _rspec(rspec), 362 _is_lval(false), 363 _target(target) 364 {} 365 366 AddressLiteral addr() { 367 AddressLiteral ret = *this; 368 ret._is_lval = true; 369 return ret; 370 } 371 372 373 private: 374 375 address target() { return _target; } 376 bool is_lval() { return _is_lval; } 377 378 relocInfo::relocType reloc() const { return _rspec.type(); } 379 const RelocationHolder& rspec() const { return _rspec; } 380 381 friend class Assembler; 382 friend class MacroAssembler; 383 friend class Address; 384 friend class LIR_Assembler; 385 }; 386 387 // Convience classes 388 class RuntimeAddress: public AddressLiteral { 389 390 public: 391 392 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 393 394 }; 395 396 class ExternalAddress: public AddressLiteral { 397 private: 398 static relocInfo::relocType reloc_for_target(address target) { 399 // Sometimes ExternalAddress is used for values which aren't 400 // exactly addresses, like the card table base. 401 // external_word_type can't be used for values in the first page 402 // so just skip the reloc in that case. 403 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 404 } 405 406 public: 407 408 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} 409 410 }; 411 412 class InternalAddress: public AddressLiteral { 413 414 public: 415 416 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 417 418 }; 419 420 // x86 can do array addressing as a single operation since disp can be an absolute 421 // address amd64 can't. We create a class that expresses the concept but does extra 422 // magic on amd64 to get the final result 423 424 class ArrayAddress VALUE_OBJ_CLASS_SPEC { 425 private: 426 427 AddressLiteral _base; 428 Address _index; 429 430 public: 431 432 ArrayAddress() {}; 433 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 434 AddressLiteral base() { return _base; } 435 Address index() { return _index; } 436 437 }; 438 439 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 440 441 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 442 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 443 // is what you get. The Assembler is generating code into a CodeBuffer. 444 445 class Assembler : public AbstractAssembler { 446 friend class AbstractAssembler; // for the non-virtual hack 447 friend class LIR_Assembler; // as_Address() 448 friend class StubGenerator; 449 450 public: 451 enum Condition { // The x86 condition codes used for conditional jumps/moves. 452 zero = 0x4, 453 notZero = 0x5, 454 equal = 0x4, 455 notEqual = 0x5, 456 less = 0xc, 457 lessEqual = 0xe, 458 greater = 0xf, 459 greaterEqual = 0xd, 460 below = 0x2, 461 belowEqual = 0x6, 462 above = 0x7, 463 aboveEqual = 0x3, 464 overflow = 0x0, 465 noOverflow = 0x1, 466 carrySet = 0x2, 467 carryClear = 0x3, 468 negative = 0x8, 469 positive = 0x9, 470 parity = 0xa, 471 noParity = 0xb 472 }; 473 474 enum Prefix { 475 // segment overrides 476 CS_segment = 0x2e, 477 SS_segment = 0x36, 478 DS_segment = 0x3e, 479 ES_segment = 0x26, 480 FS_segment = 0x64, 481 GS_segment = 0x65, 482 483 REX = 0x40, 484 485 REX_B = 0x41, 486 REX_X = 0x42, 487 REX_XB = 0x43, 488 REX_R = 0x44, 489 REX_RB = 0x45, 490 REX_RX = 0x46, 491 REX_RXB = 0x47, 492 493 REX_W = 0x48, 494 495 REX_WB = 0x49, 496 REX_WX = 0x4A, 497 REX_WXB = 0x4B, 498 REX_WR = 0x4C, 499 REX_WRB = 0x4D, 500 REX_WRX = 0x4E, 501 REX_WRXB = 0x4F, 502 503 VEX_3bytes = 0xC4, 504 VEX_2bytes = 0xC5 505 }; 506 507 enum VexPrefix { 508 VEX_B = 0x20, 509 VEX_X = 0x40, 510 VEX_R = 0x80, 511 VEX_W = 0x80 512 }; 513 514 enum VexSimdPrefix { 515 VEX_SIMD_NONE = 0x0, 516 VEX_SIMD_66 = 0x1, 517 VEX_SIMD_F3 = 0x2, 518 VEX_SIMD_F2 = 0x3 519 }; 520 521 enum VexOpcode { 522 VEX_OPCODE_NONE = 0x0, 523 VEX_OPCODE_0F = 0x1, 524 VEX_OPCODE_0F_38 = 0x2, 525 VEX_OPCODE_0F_3A = 0x3 526 }; 527 528 enum WhichOperand { 529 // input to locate_operand, and format code for relocations 530 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 531 disp32_operand = 1, // embedded 32-bit displacement or address 532 call32_operand = 2, // embedded 32-bit self-relative displacement 533 #ifndef _LP64 534 _WhichOperand_limit = 3 535 #else 536 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 537 _WhichOperand_limit = 4 538 #endif 539 }; 540 541 542 543 // NOTE: The general philopsophy of the declarations here is that 64bit versions 544 // of instructions are freely declared without the need for wrapping them an ifdef. 545 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 546 // In the .cpp file the implementations are wrapped so that they are dropped out 547 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL 548 // to the size it was prior to merging up the 32bit and 64bit assemblers. 549 // 550 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 551 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 552 553 private: 554 555 556 // 64bit prefixes 557 int prefix_and_encode(int reg_enc, bool byteinst = false); 558 int prefixq_and_encode(int reg_enc); 559 560 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); 561 int prefixq_and_encode(int dst_enc, int src_enc); 562 563 void prefix(Register reg); 564 void prefix(Address adr); 565 void prefixq(Address adr); 566 567 void prefix(Address adr, Register reg, bool byteinst = false); 568 void prefix(Address adr, XMMRegister reg); 569 void prefixq(Address adr, Register reg); 570 void prefixq(Address adr, XMMRegister reg); 571 572 void prefetch_prefix(Address src); 573 574 void rex_prefix(Address adr, XMMRegister xreg, 575 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 576 int rex_prefix_and_encode(int dst_enc, int src_enc, 577 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 578 579 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, 580 int nds_enc, VexSimdPrefix pre, VexOpcode opc, 581 bool vector256); 582 583 void vex_prefix(Address adr, int nds_enc, int xreg_enc, 584 VexSimdPrefix pre, VexOpcode opc, 585 bool vex_w, bool vector256); 586 587 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, 588 VexSimdPrefix pre, bool vector256 = false) { 589 int dst_enc = dst->encoding(); 590 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 591 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); 592 } 593 594 void vex_prefix_0F38(Register dst, Register nds, Address src) { 595 bool vex_w = false; 596 bool vector256 = false; 597 vex_prefix(src, nds->encoding(), dst->encoding(), 598 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 599 } 600 601 void vex_prefix_0F38_q(Register dst, Register nds, Address src) { 602 bool vex_w = true; 603 bool vector256 = false; 604 vex_prefix(src, nds->encoding(), dst->encoding(), 605 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 606 } 607 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 608 VexSimdPrefix pre, VexOpcode opc, 609 bool vex_w, bool vector256); 610 611 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { 612 bool vex_w = false; 613 bool vector256 = false; 614 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), 615 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 616 } 617 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { 618 bool vex_w = true; 619 bool vector256 = false; 620 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), 621 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 622 } 623 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 624 VexSimdPrefix pre, bool vector256 = false, 625 VexOpcode opc = VEX_OPCODE_0F) { 626 int src_enc = src->encoding(); 627 int dst_enc = dst->encoding(); 628 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 629 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); 630 } 631 632 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, 633 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 634 bool rex_w = false, bool vector256 = false); 635 636 void simd_prefix(XMMRegister dst, Address src, 637 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 638 simd_prefix(dst, xnoreg, src, pre, opc); 639 } 640 641 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { 642 simd_prefix(src, dst, pre); 643 } 644 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, 645 VexSimdPrefix pre) { 646 bool rex_w = true; 647 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); 648 } 649 650 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 651 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 652 bool rex_w = false, bool vector256 = false); 653 654 // Move/convert 32-bit integer value. 655 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, 656 VexSimdPrefix pre) { 657 // It is OK to cast from Register to XMMRegister to pass argument here 658 // since only encoding is used in simd_prefix_and_encode() and number of 659 // Gen and Xmm registers are the same. 660 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); 661 } 662 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { 663 return simd_prefix_and_encode(dst, xnoreg, src, pre); 664 } 665 int simd_prefix_and_encode(Register dst, XMMRegister src, 666 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 667 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); 668 } 669 670 // Move/convert 64-bit integer value. 671 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, 672 VexSimdPrefix pre) { 673 bool rex_w = true; 674 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); 675 } 676 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { 677 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); 678 } 679 int simd_prefix_and_encode_q(Register dst, XMMRegister src, 680 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 681 bool rex_w = true; 682 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); 683 } 684 685 // Helper functions for groups of instructions 686 void emit_arith_b(int op1, int op2, Register dst, int imm8); 687 688 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 689 // Force generation of a 4 byte immediate value even if it fits into 8bit 690 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 691 void emit_arith(int op1, int op2, Register dst, Register src); 692 693 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); 694 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); 695 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); 696 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); 697 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, 698 Address src, VexSimdPrefix pre, bool vector256); 699 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, 700 XMMRegister src, VexSimdPrefix pre, bool vector256); 701 702 void emit_operand(Register reg, 703 Register base, Register index, Address::ScaleFactor scale, 704 int disp, 705 RelocationHolder const& rspec, 706 int rip_relative_correction = 0); 707 708 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); 709 710 // operands that only take the original 32bit registers 711 void emit_operand32(Register reg, Address adr); 712 713 void emit_operand(XMMRegister reg, 714 Register base, Register index, Address::ScaleFactor scale, 715 int disp, 716 RelocationHolder const& rspec); 717 718 void emit_operand(XMMRegister reg, Address adr); 719 720 void emit_operand(MMXRegister reg, Address adr); 721 722 // workaround gcc (3.2.1-7) bug 723 void emit_operand(Address adr, MMXRegister reg); 724 725 726 // Immediate-to-memory forms 727 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 728 729 void emit_farith(int b1, int b2, int i); 730 731 732 protected: 733 #ifdef ASSERT 734 void check_relocation(RelocationHolder const& rspec, int format); 735 #endif 736 737 void emit_data(jint data, relocInfo::relocType rtype, int format); 738 void emit_data(jint data, RelocationHolder const& rspec, int format); 739 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 740 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 741 742 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 743 744 // These are all easily abused and hence protected 745 746 // 32BIT ONLY SECTION 747 #ifndef _LP64 748 // Make these disappear in 64bit mode since they would never be correct 749 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 750 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 751 752 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 753 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 754 755 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 756 #else 757 // 64BIT ONLY SECTION 758 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 759 760 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 761 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 762 763 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 764 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 765 #endif // _LP64 766 767 // These are unique in that we are ensured by the caller that the 32bit 768 // relative in these instructions will always be able to reach the potentially 769 // 64bit address described by entry. Since they can take a 64bit address they 770 // don't have the 32 suffix like the other instructions in this class. 771 772 void call_literal(address entry, RelocationHolder const& rspec); 773 void jmp_literal(address entry, RelocationHolder const& rspec); 774 775 // Avoid using directly section 776 // Instructions in this section are actually usable by anyone without danger 777 // of failure but have performance issues that are addressed my enhanced 778 // instructions which will do the proper thing base on the particular cpu. 779 // We protect them because we don't trust you... 780 781 // Don't use next inc() and dec() methods directly. INC & DEC instructions 782 // could cause a partial flag stall since they don't set CF flag. 783 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 784 // which call inc() & dec() or add() & sub() in accordance with 785 // the product flag UseIncDec value. 786 787 void decl(Register dst); 788 void decl(Address dst); 789 void decq(Register dst); 790 void decq(Address dst); 791 792 void incl(Register dst); 793 void incl(Address dst); 794 void incq(Register dst); 795 void incq(Address dst); 796 797 // New cpus require use of movsd and movss to avoid partial register stall 798 // when loading from memory. But for old Opteron use movlpd instead of movsd. 799 // The selection is done in MacroAssembler::movdbl() and movflt(). 800 801 // Move Scalar Single-Precision Floating-Point Values 802 void movss(XMMRegister dst, Address src); 803 void movss(XMMRegister dst, XMMRegister src); 804 void movss(Address dst, XMMRegister src); 805 806 // Move Scalar Double-Precision Floating-Point Values 807 void movsd(XMMRegister dst, Address src); 808 void movsd(XMMRegister dst, XMMRegister src); 809 void movsd(Address dst, XMMRegister src); 810 void movlpd(XMMRegister dst, Address src); 811 812 // New cpus require use of movaps and movapd to avoid partial register stall 813 // when moving between registers. 814 void movaps(XMMRegister dst, XMMRegister src); 815 void movapd(XMMRegister dst, XMMRegister src); 816 817 // End avoid using directly 818 819 820 // Instruction prefixes 821 void prefix(Prefix p); 822 823 public: 824 825 // Creation 826 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} 827 828 // Decoding 829 static address locate_operand(address inst, WhichOperand which); 830 static address locate_next_instruction(address inst); 831 832 // Utilities 833 static bool is_polling_page_far() NOT_LP64({ return false;}); 834 835 // Generic instructions 836 // Does 32bit or 64bit as needed for the platform. In some sense these 837 // belong in macro assembler but there is no need for both varieties to exist 838 839 void lea(Register dst, Address src); 840 841 void mov(Register dst, Register src); 842 843 void pusha(); 844 void popa(); 845 846 void pushf(); 847 void popf(); 848 849 void push(int32_t imm32); 850 851 void push(Register src); 852 853 void pop(Register dst); 854 855 // These are dummies to prevent surprise implicit conversions to Register 856 void push(void* v); 857 void pop(void* v); 858 859 // These do register sized moves/scans 860 void rep_mov(); 861 void rep_stos(); 862 void rep_stosb(); 863 void repne_scan(); 864 #ifdef _LP64 865 void repne_scanl(); 866 #endif 867 868 // Vanilla instructions in lexical order 869 870 void adcl(Address dst, int32_t imm32); 871 void adcl(Address dst, Register src); 872 void adcl(Register dst, int32_t imm32); 873 void adcl(Register dst, Address src); 874 void adcl(Register dst, Register src); 875 876 void adcq(Register dst, int32_t imm32); 877 void adcq(Register dst, Address src); 878 void adcq(Register dst, Register src); 879 880 void addl(Address dst, int32_t imm32); 881 void addl(Address dst, Register src); 882 void addl(Register dst, int32_t imm32); 883 void addl(Register dst, Address src); 884 void addl(Register dst, Register src); 885 886 void addq(Address dst, int32_t imm32); 887 void addq(Address dst, Register src); 888 void addq(Register dst, int32_t imm32); 889 void addq(Register dst, Address src); 890 void addq(Register dst, Register src); 891 892 #ifdef _LP64 893 //Add Unsigned Integers with Carry Flag 894 void adcxq(Register dst, Register src); 895 896 //Add Unsigned Integers with Overflow Flag 897 void adoxq(Register dst, Register src); 898 #endif 899 900 void addr_nop_4(); 901 void addr_nop_5(); 902 void addr_nop_7(); 903 void addr_nop_8(); 904 905 // Add Scalar Double-Precision Floating-Point Values 906 void addsd(XMMRegister dst, Address src); 907 void addsd(XMMRegister dst, XMMRegister src); 908 909 // Add Scalar Single-Precision Floating-Point Values 910 void addss(XMMRegister dst, Address src); 911 void addss(XMMRegister dst, XMMRegister src); 912 913 // AES instructions 914 void aesdec(XMMRegister dst, Address src); 915 void aesdec(XMMRegister dst, XMMRegister src); 916 void aesdeclast(XMMRegister dst, Address src); 917 void aesdeclast(XMMRegister dst, XMMRegister src); 918 void aesenc(XMMRegister dst, Address src); 919 void aesenc(XMMRegister dst, XMMRegister src); 920 void aesenclast(XMMRegister dst, Address src); 921 void aesenclast(XMMRegister dst, XMMRegister src); 922 923 924 void andl(Address dst, int32_t imm32); 925 void andl(Register dst, int32_t imm32); 926 void andl(Register dst, Address src); 927 void andl(Register dst, Register src); 928 929 void andq(Address dst, int32_t imm32); 930 void andq(Register dst, int32_t imm32); 931 void andq(Register dst, Address src); 932 void andq(Register dst, Register src); 933 934 // BMI instructions 935 void andnl(Register dst, Register src1, Register src2); 936 void andnl(Register dst, Register src1, Address src2); 937 void andnq(Register dst, Register src1, Register src2); 938 void andnq(Register dst, Register src1, Address src2); 939 940 void blsil(Register dst, Register src); 941 void blsil(Register dst, Address src); 942 void blsiq(Register dst, Register src); 943 void blsiq(Register dst, Address src); 944 945 void blsmskl(Register dst, Register src); 946 void blsmskl(Register dst, Address src); 947 void blsmskq(Register dst, Register src); 948 void blsmskq(Register dst, Address src); 949 950 void blsrl(Register dst, Register src); 951 void blsrl(Register dst, Address src); 952 void blsrq(Register dst, Register src); 953 void blsrq(Register dst, Address src); 954 955 void bsfl(Register dst, Register src); 956 void bsrl(Register dst, Register src); 957 958 #ifdef _LP64 959 void bsfq(Register dst, Register src); 960 void bsrq(Register dst, Register src); 961 #endif 962 963 void bswapl(Register reg); 964 965 void bswapq(Register reg); 966 967 void call(Label& L, relocInfo::relocType rtype); 968 void call(Register reg); // push pc; pc <- reg 969 void call(Address adr); // push pc; pc <- adr 970 971 void cdql(); 972 973 void cdqq(); 974 975 void cld(); 976 977 void clflush(Address adr); 978 979 void cmovl(Condition cc, Register dst, Register src); 980 void cmovl(Condition cc, Register dst, Address src); 981 982 void cmovq(Condition cc, Register dst, Register src); 983 void cmovq(Condition cc, Register dst, Address src); 984 985 986 void cmpb(Address dst, int imm8); 987 988 void cmpl(Address dst, int32_t imm32); 989 990 void cmpl(Register dst, int32_t imm32); 991 void cmpl(Register dst, Register src); 992 void cmpl(Register dst, Address src); 993 994 void cmpq(Address dst, int32_t imm32); 995 void cmpq(Address dst, Register src); 996 997 void cmpq(Register dst, int32_t imm32); 998 void cmpq(Register dst, Register src); 999 void cmpq(Register dst, Address src); 1000 1001 // these are dummies used to catch attempting to convert NULL to Register 1002 void cmpl(Register dst, void* junk); // dummy 1003 void cmpq(Register dst, void* junk); // dummy 1004 1005 void cmpw(Address dst, int imm16); 1006 1007 void cmpxchg8 (Address adr); 1008 1009 void cmpxchgb(Register reg, Address adr); 1010 void cmpxchgl(Register reg, Address adr); 1011 1012 void cmpxchgq(Register reg, Address adr); 1013 1014 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1015 void comisd(XMMRegister dst, Address src); 1016 void comisd(XMMRegister dst, XMMRegister src); 1017 1018 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1019 void comiss(XMMRegister dst, Address src); 1020 void comiss(XMMRegister dst, XMMRegister src); 1021 1022 // Identify processor type and features 1023 void cpuid(); 1024 1025 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 1026 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1027 void cvtsd2ss(XMMRegister dst, Address src); 1028 1029 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 1030 void cvtsi2sdl(XMMRegister dst, Register src); 1031 void cvtsi2sdl(XMMRegister dst, Address src); 1032 void cvtsi2sdq(XMMRegister dst, Register src); 1033 void cvtsi2sdq(XMMRegister dst, Address src); 1034 1035 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 1036 void cvtsi2ssl(XMMRegister dst, Register src); 1037 void cvtsi2ssl(XMMRegister dst, Address src); 1038 void cvtsi2ssq(XMMRegister dst, Register src); 1039 void cvtsi2ssq(XMMRegister dst, Address src); 1040 1041 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 1042 void cvtdq2pd(XMMRegister dst, XMMRegister src); 1043 1044 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 1045 void cvtdq2ps(XMMRegister dst, XMMRegister src); 1046 1047 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 1048 void cvtss2sd(XMMRegister dst, XMMRegister src); 1049 void cvtss2sd(XMMRegister dst, Address src); 1050 1051 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 1052 void cvttsd2sil(Register dst, Address src); 1053 void cvttsd2sil(Register dst, XMMRegister src); 1054 void cvttsd2siq(Register dst, XMMRegister src); 1055 1056 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 1057 void cvttss2sil(Register dst, XMMRegister src); 1058 void cvttss2siq(Register dst, XMMRegister src); 1059 1060 // Divide Scalar Double-Precision Floating-Point Values 1061 void divsd(XMMRegister dst, Address src); 1062 void divsd(XMMRegister dst, XMMRegister src); 1063 1064 // Divide Scalar Single-Precision Floating-Point Values 1065 void divss(XMMRegister dst, Address src); 1066 void divss(XMMRegister dst, XMMRegister src); 1067 1068 void emms(); 1069 1070 void fabs(); 1071 1072 void fadd(int i); 1073 1074 void fadd_d(Address src); 1075 void fadd_s(Address src); 1076 1077 // "Alternate" versions of x87 instructions place result down in FPU 1078 // stack instead of on TOS 1079 1080 void fadda(int i); // "alternate" fadd 1081 void faddp(int i = 1); 1082 1083 void fchs(); 1084 1085 void fcom(int i); 1086 1087 void fcomp(int i = 1); 1088 void fcomp_d(Address src); 1089 void fcomp_s(Address src); 1090 1091 void fcompp(); 1092 1093 void fcos(); 1094 1095 void fdecstp(); 1096 1097 void fdiv(int i); 1098 void fdiv_d(Address src); 1099 void fdivr_s(Address src); 1100 void fdiva(int i); // "alternate" fdiv 1101 void fdivp(int i = 1); 1102 1103 void fdivr(int i); 1104 void fdivr_d(Address src); 1105 void fdiv_s(Address src); 1106 1107 void fdivra(int i); // "alternate" reversed fdiv 1108 1109 void fdivrp(int i = 1); 1110 1111 void ffree(int i = 0); 1112 1113 void fild_d(Address adr); 1114 void fild_s(Address adr); 1115 1116 void fincstp(); 1117 1118 void finit(); 1119 1120 void fist_s (Address adr); 1121 void fistp_d(Address adr); 1122 void fistp_s(Address adr); 1123 1124 void fld1(); 1125 1126 void fld_d(Address adr); 1127 void fld_s(Address adr); 1128 void fld_s(int index); 1129 void fld_x(Address adr); // extended-precision (80-bit) format 1130 1131 void fldcw(Address src); 1132 1133 void fldenv(Address src); 1134 1135 void fldlg2(); 1136 1137 void fldln2(); 1138 1139 void fldz(); 1140 1141 void flog(); 1142 void flog10(); 1143 1144 void fmul(int i); 1145 1146 void fmul_d(Address src); 1147 void fmul_s(Address src); 1148 1149 void fmula(int i); // "alternate" fmul 1150 1151 void fmulp(int i = 1); 1152 1153 void fnsave(Address dst); 1154 1155 void fnstcw(Address src); 1156 1157 void fnstsw_ax(); 1158 1159 void fprem(); 1160 void fprem1(); 1161 1162 void frstor(Address src); 1163 1164 void fsin(); 1165 1166 void fsqrt(); 1167 1168 void fst_d(Address adr); 1169 void fst_s(Address adr); 1170 1171 void fstp_d(Address adr); 1172 void fstp_d(int index); 1173 void fstp_s(Address adr); 1174 void fstp_x(Address adr); // extended-precision (80-bit) format 1175 1176 void fsub(int i); 1177 void fsub_d(Address src); 1178 void fsub_s(Address src); 1179 1180 void fsuba(int i); // "alternate" fsub 1181 1182 void fsubp(int i = 1); 1183 1184 void fsubr(int i); 1185 void fsubr_d(Address src); 1186 void fsubr_s(Address src); 1187 1188 void fsubra(int i); // "alternate" reversed fsub 1189 1190 void fsubrp(int i = 1); 1191 1192 void ftan(); 1193 1194 void ftst(); 1195 1196 void fucomi(int i = 1); 1197 void fucomip(int i = 1); 1198 1199 void fwait(); 1200 1201 void fxch(int i = 1); 1202 1203 void fxrstor(Address src); 1204 1205 void fxsave(Address dst); 1206 1207 void fyl2x(); 1208 void frndint(); 1209 void f2xm1(); 1210 void fldl2e(); 1211 1212 void hlt(); 1213 1214 void idivl(Register src); 1215 void divl(Register src); // Unsigned division 1216 1217 #ifdef _LP64 1218 void idivq(Register src); 1219 #endif 1220 1221 void imull(Register dst, Register src); 1222 void imull(Register dst, Register src, int value); 1223 void imull(Register dst, Address src); 1224 1225 #ifdef _LP64 1226 void imulq(Register dst, Register src); 1227 void imulq(Register dst, Register src, int value); 1228 void imulq(Register dst, Address src); 1229 #endif 1230 1231 // jcc is the generic conditional branch generator to run- 1232 // time routines, jcc is used for branches to labels. jcc 1233 // takes a branch opcode (cc) and a label (L) and generates 1234 // either a backward branch or a forward branch and links it 1235 // to the label fixup chain. Usage: 1236 // 1237 // Label L; // unbound label 1238 // jcc(cc, L); // forward branch to unbound label 1239 // bind(L); // bind label to the current pc 1240 // jcc(cc, L); // backward branch to bound label 1241 // bind(L); // illegal: a label may be bound only once 1242 // 1243 // Note: The same Label can be used for forward and backward branches 1244 // but it may be bound only once. 1245 1246 void jcc(Condition cc, Label& L, bool maybe_short = true); 1247 1248 // Conditional jump to a 8-bit offset to L. 1249 // WARNING: be very careful using this for forward jumps. If the label is 1250 // not bound within an 8-bit offset of this instruction, a run-time error 1251 // will occur. 1252 void jccb(Condition cc, Label& L); 1253 1254 void jmp(Address entry); // pc <- entry 1255 1256 // Label operations & relative jumps (PPUM Appendix D) 1257 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L 1258 1259 void jmp(Register entry); // pc <- entry 1260 1261 // Unconditional 8-bit offset jump to L. 1262 // WARNING: be very careful using this for forward jumps. If the label is 1263 // not bound within an 8-bit offset of this instruction, a run-time error 1264 // will occur. 1265 void jmpb(Label& L); 1266 1267 void ldmxcsr( Address src ); 1268 1269 void leal(Register dst, Address src); 1270 1271 void leaq(Register dst, Address src); 1272 1273 void lfence(); 1274 1275 void lock(); 1276 1277 void lzcntl(Register dst, Register src); 1278 1279 #ifdef _LP64 1280 void lzcntq(Register dst, Register src); 1281 #endif 1282 1283 enum Membar_mask_bits { 1284 StoreStore = 1 << 3, 1285 LoadStore = 1 << 2, 1286 StoreLoad = 1 << 1, 1287 LoadLoad = 1 << 0 1288 }; 1289 1290 // Serializes memory and blows flags 1291 void membar(Membar_mask_bits order_constraint) { 1292 if (os::is_MP()) { 1293 // We only have to handle StoreLoad 1294 if (order_constraint & StoreLoad) { 1295 // All usable chips support "locked" instructions which suffice 1296 // as barriers, and are much faster than the alternative of 1297 // using cpuid instruction. We use here a locked add [esp-C],0. 1298 // This is conveniently otherwise a no-op except for blowing 1299 // flags, and introducing a false dependency on target memory 1300 // location. We can't do anything with flags, but we can avoid 1301 // memory dependencies in the current method by locked-adding 1302 // somewhere else on the stack. Doing [esp+C] will collide with 1303 // something on stack in current method, hence we go for [esp-C]. 1304 // It is convenient since it is almost always in data cache, for 1305 // any small C. We need to step back from SP to avoid data 1306 // dependencies with other things on below SP (callee-saves, for 1307 // example). Without a clear way to figure out the minimal safe 1308 // distance from SP, it makes sense to step back the complete 1309 // cache line, as this will also avoid possible second-order effects 1310 // with locked ops against the cache line. Our choice of offset 1311 // is bounded by x86 operand encoding, which should stay within 1312 // [-128; +127] to have the 8-byte displacement encoding. 1313 // 1314 // Any change to this code may need to revisit other places in 1315 // the code where this idiom is used, in particular the 1316 // orderAccess code. 1317 1318 int offset = -VM_Version::L1_line_size(); 1319 if (offset < -128) { 1320 offset = -128; 1321 } 1322 1323 lock(); 1324 addl(Address(rsp, offset), 0);// Assert the lock# signal here 1325 } 1326 } 1327 } 1328 1329 void mfence(); 1330 1331 // Moves 1332 1333 void mov64(Register dst, int64_t imm64); 1334 1335 void movb(Address dst, Register src); 1336 void movb(Address dst, int imm8); 1337 void movb(Register dst, Address src); 1338 1339 void movdl(XMMRegister dst, Register src); 1340 void movdl(Register dst, XMMRegister src); 1341 void movdl(XMMRegister dst, Address src); 1342 void movdl(Address dst, XMMRegister src); 1343 1344 // Move Double Quadword 1345 void movdq(XMMRegister dst, Register src); 1346 void movdq(Register dst, XMMRegister src); 1347 1348 // Move Aligned Double Quadword 1349 void movdqa(XMMRegister dst, XMMRegister src); 1350 void movdqa(XMMRegister dst, Address src); 1351 1352 // Move Unaligned Double Quadword 1353 void movdqu(Address dst, XMMRegister src); 1354 void movdqu(XMMRegister dst, Address src); 1355 void movdqu(XMMRegister dst, XMMRegister src); 1356 1357 // Move Unaligned 256bit Vector 1358 void vmovdqu(Address dst, XMMRegister src); 1359 void vmovdqu(XMMRegister dst, Address src); 1360 void vmovdqu(XMMRegister dst, XMMRegister src); 1361 1362 // Move lower 64bit to high 64bit in 128bit register 1363 void movlhps(XMMRegister dst, XMMRegister src); 1364 1365 void movl(Register dst, int32_t imm32); 1366 void movl(Address dst, int32_t imm32); 1367 void movl(Register dst, Register src); 1368 void movl(Register dst, Address src); 1369 void movl(Address dst, Register src); 1370 1371 // These dummies prevent using movl from converting a zero (like NULL) into Register 1372 // by giving the compiler two choices it can't resolve 1373 1374 void movl(Address dst, void* junk); 1375 void movl(Register dst, void* junk); 1376 1377 #ifdef _LP64 1378 void movq(Register dst, Register src); 1379 void movq(Register dst, Address src); 1380 void movq(Address dst, Register src); 1381 #endif 1382 1383 void movq(Address dst, MMXRegister src ); 1384 void movq(MMXRegister dst, Address src ); 1385 1386 #ifdef _LP64 1387 // These dummies prevent using movq from converting a zero (like NULL) into Register 1388 // by giving the compiler two choices it can't resolve 1389 1390 void movq(Address dst, void* dummy); 1391 void movq(Register dst, void* dummy); 1392 #endif 1393 1394 // Move Quadword 1395 void movq(Address dst, XMMRegister src); 1396 void movq(XMMRegister dst, Address src); 1397 1398 void movsbl(Register dst, Address src); 1399 void movsbl(Register dst, Register src); 1400 1401 #ifdef _LP64 1402 void movsbq(Register dst, Address src); 1403 void movsbq(Register dst, Register src); 1404 1405 // Move signed 32bit immediate to 64bit extending sign 1406 void movslq(Address dst, int32_t imm64); 1407 void movslq(Register dst, int32_t imm64); 1408 1409 void movslq(Register dst, Address src); 1410 void movslq(Register dst, Register src); 1411 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1412 #endif 1413 1414 void movswl(Register dst, Address src); 1415 void movswl(Register dst, Register src); 1416 1417 #ifdef _LP64 1418 void movswq(Register dst, Address src); 1419 void movswq(Register dst, Register src); 1420 #endif 1421 1422 void movw(Address dst, int imm16); 1423 void movw(Register dst, Address src); 1424 void movw(Address dst, Register src); 1425 1426 void movzbl(Register dst, Address src); 1427 void movzbl(Register dst, Register src); 1428 1429 #ifdef _LP64 1430 void movzbq(Register dst, Address src); 1431 void movzbq(Register dst, Register src); 1432 #endif 1433 1434 void movzwl(Register dst, Address src); 1435 void movzwl(Register dst, Register src); 1436 1437 #ifdef _LP64 1438 void movzwq(Register dst, Address src); 1439 void movzwq(Register dst, Register src); 1440 #endif 1441 1442 // Unsigned multiply with RAX destination register 1443 void mull(Address src); 1444 void mull(Register src); 1445 1446 #ifdef _LP64 1447 void mulq(Address src); 1448 void mulq(Register src); 1449 void mulxq(Register dst1, Register dst2, Register src); 1450 #endif 1451 1452 // Multiply Scalar Double-Precision Floating-Point Values 1453 void mulsd(XMMRegister dst, Address src); 1454 void mulsd(XMMRegister dst, XMMRegister src); 1455 1456 // Multiply Scalar Single-Precision Floating-Point Values 1457 void mulss(XMMRegister dst, Address src); 1458 void mulss(XMMRegister dst, XMMRegister src); 1459 1460 void negl(Register dst); 1461 1462 #ifdef _LP64 1463 void negq(Register dst); 1464 #endif 1465 1466 void nop(int i = 1); 1467 1468 void notl(Register dst); 1469 1470 #ifdef _LP64 1471 void notq(Register dst); 1472 #endif 1473 1474 void orl(Address dst, int32_t imm32); 1475 void orl(Register dst, int32_t imm32); 1476 void orl(Register dst, Address src); 1477 void orl(Register dst, Register src); 1478 1479 void orq(Address dst, int32_t imm32); 1480 void orq(Register dst, int32_t imm32); 1481 void orq(Register dst, Address src); 1482 void orq(Register dst, Register src); 1483 1484 // Pack with unsigned saturation 1485 void packuswb(XMMRegister dst, XMMRegister src); 1486 void packuswb(XMMRegister dst, Address src); 1487 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1488 1489 // Pemutation of 64bit words 1490 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); 1491 1492 void pause(); 1493 1494 // SSE4.2 string instructions 1495 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1496 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1497 1498 // SSE 4.1 extract 1499 void pextrd(Register dst, XMMRegister src, int imm8); 1500 void pextrq(Register dst, XMMRegister src, int imm8); 1501 1502 // SSE 4.1 insert 1503 void pinsrd(XMMRegister dst, Register src, int imm8); 1504 void pinsrq(XMMRegister dst, Register src, int imm8); 1505 1506 // SSE4.1 packed move 1507 void pmovzxbw(XMMRegister dst, XMMRegister src); 1508 void pmovzxbw(XMMRegister dst, Address src); 1509 1510 #ifndef _LP64 // no 32bit push/pop on amd64 1511 void popl(Address dst); 1512 #endif 1513 1514 #ifdef _LP64 1515 void popq(Address dst); 1516 #endif 1517 1518 void popcntl(Register dst, Address src); 1519 void popcntl(Register dst, Register src); 1520 1521 #ifdef _LP64 1522 void popcntq(Register dst, Address src); 1523 void popcntq(Register dst, Register src); 1524 #endif 1525 1526 // Prefetches (SSE, SSE2, 3DNOW only) 1527 1528 void prefetchnta(Address src); 1529 void prefetchr(Address src); 1530 void prefetcht0(Address src); 1531 void prefetcht1(Address src); 1532 void prefetcht2(Address src); 1533 void prefetchw(Address src); 1534 1535 // Shuffle Bytes 1536 void pshufb(XMMRegister dst, XMMRegister src); 1537 void pshufb(XMMRegister dst, Address src); 1538 1539 // Shuffle Packed Doublewords 1540 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1541 void pshufd(XMMRegister dst, Address src, int mode); 1542 1543 // Shuffle Packed Low Words 1544 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1545 void pshuflw(XMMRegister dst, Address src, int mode); 1546 1547 // Shift Right by bytes Logical DoubleQuadword Immediate 1548 void psrldq(XMMRegister dst, int shift); 1549 // Shift Left by bytes Logical DoubleQuadword Immediate 1550 void pslldq(XMMRegister dst, int shift); 1551 1552 // Logical Compare 128bit 1553 void ptest(XMMRegister dst, XMMRegister src); 1554 void ptest(XMMRegister dst, Address src); 1555 // Logical Compare 256bit 1556 void vptest(XMMRegister dst, XMMRegister src); 1557 void vptest(XMMRegister dst, Address src); 1558 1559 // Interleave Low Bytes 1560 void punpcklbw(XMMRegister dst, XMMRegister src); 1561 void punpcklbw(XMMRegister dst, Address src); 1562 1563 // Interleave Low Doublewords 1564 void punpckldq(XMMRegister dst, XMMRegister src); 1565 void punpckldq(XMMRegister dst, Address src); 1566 1567 // Interleave Low Quadwords 1568 void punpcklqdq(XMMRegister dst, XMMRegister src); 1569 1570 #ifndef _LP64 // no 32bit push/pop on amd64 1571 void pushl(Address src); 1572 #endif 1573 1574 void pushq(Address src); 1575 1576 void rcll(Register dst, int imm8); 1577 1578 void rclq(Register dst, int imm8); 1579 1580 void rdtsc(); 1581 1582 void ret(int imm16); 1583 1584 #ifdef _LP64 1585 void rorq(Register dst, int imm8); 1586 void rorxq(Register dst, Register src, int imm8); 1587 #endif 1588 1589 void sahf(); 1590 1591 void sarl(Register dst, int imm8); 1592 void sarl(Register dst); 1593 1594 void sarq(Register dst, int imm8); 1595 void sarq(Register dst); 1596 1597 void sbbl(Address dst, int32_t imm32); 1598 void sbbl(Register dst, int32_t imm32); 1599 void sbbl(Register dst, Address src); 1600 void sbbl(Register dst, Register src); 1601 1602 void sbbq(Address dst, int32_t imm32); 1603 void sbbq(Register dst, int32_t imm32); 1604 void sbbq(Register dst, Address src); 1605 void sbbq(Register dst, Register src); 1606 1607 void setb(Condition cc, Register dst); 1608 1609 void shldl(Register dst, Register src); 1610 1611 void shll(Register dst, int imm8); 1612 void shll(Register dst); 1613 1614 void shlq(Register dst, int imm8); 1615 void shlq(Register dst); 1616 1617 void shrdl(Register dst, Register src); 1618 1619 void shrl(Register dst, int imm8); 1620 void shrl(Register dst); 1621 1622 void shrq(Register dst, int imm8); 1623 void shrq(Register dst); 1624 1625 void smovl(); // QQQ generic? 1626 1627 // Compute Square Root of Scalar Double-Precision Floating-Point Value 1628 void sqrtsd(XMMRegister dst, Address src); 1629 void sqrtsd(XMMRegister dst, XMMRegister src); 1630 1631 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1632 void sqrtss(XMMRegister dst, Address src); 1633 void sqrtss(XMMRegister dst, XMMRegister src); 1634 1635 void std(); 1636 1637 void stmxcsr( Address dst ); 1638 1639 void subl(Address dst, int32_t imm32); 1640 void subl(Address dst, Register src); 1641 void subl(Register dst, int32_t imm32); 1642 void subl(Register dst, Address src); 1643 void subl(Register dst, Register src); 1644 1645 void subq(Address dst, int32_t imm32); 1646 void subq(Address dst, Register src); 1647 void subq(Register dst, int32_t imm32); 1648 void subq(Register dst, Address src); 1649 void subq(Register dst, Register src); 1650 1651 // Force generation of a 4 byte immediate value even if it fits into 8bit 1652 void subl_imm32(Register dst, int32_t imm32); 1653 void subq_imm32(Register dst, int32_t imm32); 1654 1655 // Subtract Scalar Double-Precision Floating-Point Values 1656 void subsd(XMMRegister dst, Address src); 1657 void subsd(XMMRegister dst, XMMRegister src); 1658 1659 // Subtract Scalar Single-Precision Floating-Point Values 1660 void subss(XMMRegister dst, Address src); 1661 void subss(XMMRegister dst, XMMRegister src); 1662 1663 void testb(Register dst, int imm8); 1664 1665 void testl(Register dst, int32_t imm32); 1666 void testl(Register dst, Register src); 1667 void testl(Register dst, Address src); 1668 1669 void testq(Register dst, int32_t imm32); 1670 void testq(Register dst, Register src); 1671 1672 // BMI - count trailing zeros 1673 void tzcntl(Register dst, Register src); 1674 void tzcntq(Register dst, Register src); 1675 1676 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1677 void ucomisd(XMMRegister dst, Address src); 1678 void ucomisd(XMMRegister dst, XMMRegister src); 1679 1680 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1681 void ucomiss(XMMRegister dst, Address src); 1682 void ucomiss(XMMRegister dst, XMMRegister src); 1683 1684 void xabort(int8_t imm8); 1685 1686 void xaddl(Address dst, Register src); 1687 1688 void xaddq(Address dst, Register src); 1689 1690 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); 1691 1692 void xchgl(Register reg, Address adr); 1693 void xchgl(Register dst, Register src); 1694 1695 void xchgq(Register reg, Address adr); 1696 void xchgq(Register dst, Register src); 1697 1698 void xend(); 1699 1700 // Get Value of Extended Control Register 1701 void xgetbv(); 1702 1703 void xorl(Register dst, int32_t imm32); 1704 void xorl(Register dst, Address src); 1705 void xorl(Register dst, Register src); 1706 1707 void xorq(Register dst, Address src); 1708 void xorq(Register dst, Register src); 1709 1710 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1711 1712 // AVX 3-operands scalar instructions (encoded with VEX prefix) 1713 1714 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 1715 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1716 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 1717 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1718 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 1719 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1720 void vdivss(XMMRegister dst, XMMRegister nds, Address src); 1721 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1722 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); 1723 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1724 void vmulss(XMMRegister dst, XMMRegister nds, Address src); 1725 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1726 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 1727 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1728 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 1729 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1730 1731 1732 //====================VECTOR ARITHMETIC===================================== 1733 1734 // Add Packed Floating-Point Values 1735 void addpd(XMMRegister dst, XMMRegister src); 1736 void addps(XMMRegister dst, XMMRegister src); 1737 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1738 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1739 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1740 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1741 1742 // Subtract Packed Floating-Point Values 1743 void subpd(XMMRegister dst, XMMRegister src); 1744 void subps(XMMRegister dst, XMMRegister src); 1745 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1746 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1747 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1748 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1749 1750 // Multiply Packed Floating-Point Values 1751 void mulpd(XMMRegister dst, XMMRegister src); 1752 void mulps(XMMRegister dst, XMMRegister src); 1753 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1754 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1755 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1756 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1757 1758 // Divide Packed Floating-Point Values 1759 void divpd(XMMRegister dst, XMMRegister src); 1760 void divps(XMMRegister dst, XMMRegister src); 1761 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1762 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1763 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1764 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1765 1766 // Bitwise Logical AND of Packed Floating-Point Values 1767 void andpd(XMMRegister dst, XMMRegister src); 1768 void andps(XMMRegister dst, XMMRegister src); 1769 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1770 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1771 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1772 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1773 1774 // Bitwise Logical XOR of Packed Floating-Point Values 1775 void xorpd(XMMRegister dst, XMMRegister src); 1776 void xorps(XMMRegister dst, XMMRegister src); 1777 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1778 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1779 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1780 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1781 1782 // Add packed integers 1783 void paddb(XMMRegister dst, XMMRegister src); 1784 void paddw(XMMRegister dst, XMMRegister src); 1785 void paddd(XMMRegister dst, XMMRegister src); 1786 void paddq(XMMRegister dst, XMMRegister src); 1787 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1788 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1789 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1790 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1791 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1792 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1793 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1794 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1795 1796 // Sub packed integers 1797 void psubb(XMMRegister dst, XMMRegister src); 1798 void psubw(XMMRegister dst, XMMRegister src); 1799 void psubd(XMMRegister dst, XMMRegister src); 1800 void psubq(XMMRegister dst, XMMRegister src); 1801 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1802 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1803 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1804 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1805 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1806 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1807 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1808 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1809 1810 // Multiply packed integers (only shorts and ints) 1811 void pmullw(XMMRegister dst, XMMRegister src); 1812 void pmulld(XMMRegister dst, XMMRegister src); 1813 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1814 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1815 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1816 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1817 1818 // Shift left packed integers 1819 void psllw(XMMRegister dst, int shift); 1820 void pslld(XMMRegister dst, int shift); 1821 void psllq(XMMRegister dst, int shift); 1822 void psllw(XMMRegister dst, XMMRegister shift); 1823 void pslld(XMMRegister dst, XMMRegister shift); 1824 void psllq(XMMRegister dst, XMMRegister shift); 1825 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1826 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1827 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1828 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1829 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1830 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1831 1832 // Logical shift right packed integers 1833 void psrlw(XMMRegister dst, int shift); 1834 void psrld(XMMRegister dst, int shift); 1835 void psrlq(XMMRegister dst, int shift); 1836 void psrlw(XMMRegister dst, XMMRegister shift); 1837 void psrld(XMMRegister dst, XMMRegister shift); 1838 void psrlq(XMMRegister dst, XMMRegister shift); 1839 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1840 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1841 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1842 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1843 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1844 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1845 1846 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) 1847 void psraw(XMMRegister dst, int shift); 1848 void psrad(XMMRegister dst, int shift); 1849 void psraw(XMMRegister dst, XMMRegister shift); 1850 void psrad(XMMRegister dst, XMMRegister shift); 1851 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1852 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1853 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1854 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1855 1856 // And packed integers 1857 void pand(XMMRegister dst, XMMRegister src); 1858 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1859 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1860 1861 // Or packed integers 1862 void por(XMMRegister dst, XMMRegister src); 1863 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1864 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1865 1866 // Xor packed integers 1867 void pxor(XMMRegister dst, XMMRegister src); 1868 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1869 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1870 1871 // Copy low 128bit into high 128bit of YMM registers. 1872 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1873 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1874 1875 // Load/store high 128bit of YMM registers which does not destroy other half. 1876 void vinsertf128h(XMMRegister dst, Address src); 1877 void vinserti128h(XMMRegister dst, Address src); 1878 void vextractf128h(Address dst, XMMRegister src); 1879 void vextracti128h(Address dst, XMMRegister src); 1880 1881 // duplicate 4-bytes integer data from src into 8 locations in dest 1882 void vpbroadcastd(XMMRegister dst, XMMRegister src); 1883 1884 // Carry-Less Multiplication Quadword 1885 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); 1886 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); 1887 1888 // AVX instruction which is used to clear upper 128 bits of YMM registers and 1889 // to avoid transaction penalty between AVX and SSE states. There is no 1890 // penalty if legacy SSE instructions are encoded using VEX prefix because 1891 // they always clear upper 128 bits. It should be used before calling 1892 // runtime code and native libraries. 1893 void vzeroupper(); 1894 1895 protected: 1896 // Next instructions require address alignment 16 bytes SSE mode. 1897 // They should be called only from corresponding MacroAssembler instructions. 1898 void andpd(XMMRegister dst, Address src); 1899 void andps(XMMRegister dst, Address src); 1900 void xorpd(XMMRegister dst, Address src); 1901 void xorps(XMMRegister dst, Address src); 1902 1903 }; 1904 1905 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP