1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
564 if (UseCLMUL && (UseSSE > 2)) {
565 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
566 UseCRC32Intrinsics = true;
567 }
568 } else if (UseCRC32Intrinsics) {
569 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
570 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
571 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
572 }
573
574 // The AES intrinsic stubs require AES instruction support (of course)
575 // but also require sse3 mode for instructions it use.
576 if (UseAES && (UseSSE > 2)) {
577 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
578 UseAESIntrinsics = true;
579 }
580 } else if (UseAESIntrinsics) {
581 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
582 warning("AES intrinsics are not available on this CPU");
583 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
584 }
585
586 if (UseSHA) {
587 warning("SHA instructions are not available on this CPU");
588 FLAG_SET_DEFAULT(UseSHA, false);
589 }
590 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
591 warning("SHA intrinsics are not available on this CPU");
592 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
593 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
594 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
595 }
596
597 // Adjust RTM (Restricted Transactional Memory) flags
598 if (!supports_rtm() && UseRTMLocking) {
599 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
600 // setting during arguments processing. See use_biased_locking().
601 // VM_Version_init() is executed after UseBiasedLocking is used
602 // in Thread::allocate().
603 vm_exit_during_initialization("RTM instructions are not available on this CPU");
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1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
564 if (UseCLMUL && (UseSSE > 2)) {
565 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
566 UseCRC32Intrinsics = true;
567 }
568 } else if (UseCRC32Intrinsics) {
569 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
570 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
571 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
572 }
573
574 // The AES intrinsic stubs require AES instruction support (of course)
575 // but also require sse3 mode for instructions it use.
576 if (UseAES && (UseSSE > 2)) {
577 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
578 UseAESIntrinsics = true;
579 }
580 } else if (UseAESIntrinsics) {
581 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
582 warning("AES intrinsics are not available on this CPU");
583 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
584 }
585
586 // GHASH/GCM intrinsics
587 if (UseCLMUL && (UseSSE > 2)) {
588 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
589 UseGHASHIntrinsics = true;
590 }
591 } else if (UseGHASHIntrinsics) {
592 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
593 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
594 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
595 }
596
597 if (UseSHA) {
598 warning("SHA instructions are not available on this CPU");
599 FLAG_SET_DEFAULT(UseSHA, false);
600 }
601 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
602 warning("SHA intrinsics are not available on this CPU");
603 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
604 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
605 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
606 }
607
608 // Adjust RTM (Restricted Transactional Memory) flags
609 if (!supports_rtm() && UseRTMLocking) {
610 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
611 // setting during arguments processing. See use_biased_locking().
612 // VM_Version_init() is executed after UseBiasedLocking is used
613 // in Thread::allocate().
614 vm_exit_during_initialization("RTM instructions are not available on this CPU");
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