1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27
28 #include "asm/register.hpp"
29
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
33
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
37
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
43
44 public:
45 // op carries format info; see page 62 & 267
46
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
53
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
62
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
81
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
97
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fsrc_op3 = 0x36,
132 xmulx_op3 = 0x36,
133 impdep2_op3 = 0x37,
134 stpartialf_op3 = 0x37,
135 jmpl_op3 = 0x38,
136 rett_op3 = 0x39,
137 trap_op3 = 0x3a,
138 flush_op3 = 0x3b,
139 save_op3 = 0x3c,
140 restore_op3 = 0x3d,
141 done_op3 = 0x3e,
142 retry_op3 = 0x3e,
143
144 lduw_op3 = 0x00,
145 ldub_op3 = 0x01,
146 lduh_op3 = 0x02,
147 ldd_op3 = 0x03,
148 stw_op3 = 0x04,
149 stb_op3 = 0x05,
150 sth_op3 = 0x06,
151 std_op3 = 0x07,
152 ldsw_op3 = 0x08,
153 ldsb_op3 = 0x09,
154 ldsh_op3 = 0x0a,
155 ldx_op3 = 0x0b,
156
157 stx_op3 = 0x0e,
158 swap_op3 = 0x0f,
159
160 stwa_op3 = 0x14,
161 stxa_op3 = 0x1e,
162
163 ldf_op3 = 0x20,
164 ldfsr_op3 = 0x21,
165 ldqf_op3 = 0x22,
166 lddf_op3 = 0x23,
167 stf_op3 = 0x24,
168 stfsr_op3 = 0x25,
169 stqf_op3 = 0x26,
170 stdf_op3 = 0x27,
171
172 prefetch_op3 = 0x2d,
173
174 casa_op3 = 0x3c,
175 casxa_op3 = 0x3e,
176
177 mftoi_op3 = 0x36,
178
179 alt_bit_op3 = 0x10,
180 cc_bit_op3 = 0x10
181 };
182
183 enum opfs {
184 // selected opfs
185 edge8n_opf = 0x01,
186
187 fmovs_opf = 0x01,
188 fmovd_opf = 0x02,
189
190 fnegs_opf = 0x05,
191 fnegd_opf = 0x06,
192
193 alignaddr_opf = 0x18,
194
195 fadds_opf = 0x41,
196 faddd_opf = 0x42,
197 fsubs_opf = 0x45,
198 fsubd_opf = 0x46,
199
200 faligndata_opf = 0x48,
201
202 fmuls_opf = 0x49,
203 fmuld_opf = 0x4a,
204 fdivs_opf = 0x4d,
205 fdivd_opf = 0x4e,
206
207 fcmps_opf = 0x51,
208 fcmpd_opf = 0x52,
209
210 fstox_opf = 0x81,
211 fdtox_opf = 0x82,
212 fxtos_opf = 0x84,
213 fxtod_opf = 0x88,
214 fitos_opf = 0xc4,
215 fdtos_opf = 0xc6,
216 fitod_opf = 0xc8,
217 fstod_opf = 0xc9,
218 fstoi_opf = 0xd1,
219 fdtoi_opf = 0xd2,
220
221 mdtox_opf = 0x110,
222 mstouw_opf = 0x111,
223 mstosw_opf = 0x113,
224 xmulx_opf = 0x115,
225 xmulxhi_opf = 0x116,
226 mxtod_opf = 0x118,
227 mwtos_opf = 0x119,
228
229 aes_kexpand0_opf = 0x130,
230 aes_kexpand2_opf = 0x131,
231
232 sha1_opf = 0x141,
233 sha256_opf = 0x142,
234 sha512_opf = 0x143
235 };
236
237 enum op5s {
238 aes_eround01_op5 = 0x00,
239 aes_eround23_op5 = 0x01,
240 aes_dround01_op5 = 0x02,
241 aes_dround23_op5 = 0x03,
242 aes_eround01_l_op5 = 0x04,
243 aes_eround23_l_op5 = 0x05,
244 aes_dround01_l_op5 = 0x06,
245 aes_dround23_l_op5 = 0x07,
246 aes_kexpand1_op5 = 0x08
247 };
248
249 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
250
251 enum Condition {
252 // for FBfcc & FBPfcc instruction
253 f_never = 0,
254 f_notEqual = 1,
255 f_notZero = 1,
256 f_lessOrGreater = 2,
257 f_unorderedOrLess = 3,
258 f_less = 4,
259 f_unorderedOrGreater = 5,
260 f_greater = 6,
261 f_unordered = 7,
262 f_always = 8,
263 f_equal = 9,
264 f_zero = 9,
265 f_unorderedOrEqual = 10,
266 f_greaterOrEqual = 11,
267 f_unorderedOrGreaterOrEqual = 12,
268 f_lessOrEqual = 13,
269 f_unorderedOrLessOrEqual = 14,
270 f_ordered = 15,
271
272 // V8 coproc, pp 123 v8 manual
273
274 cp_always = 8,
275 cp_never = 0,
276 cp_3 = 7,
277 cp_2 = 6,
278 cp_2or3 = 5,
279 cp_1 = 4,
280 cp_1or3 = 3,
281 cp_1or2 = 2,
282 cp_1or2or3 = 1,
283 cp_0 = 9,
284 cp_0or3 = 10,
285 cp_0or2 = 11,
286 cp_0or2or3 = 12,
287 cp_0or1 = 13,
288 cp_0or1or3 = 14,
289 cp_0or1or2 = 15,
290
291
292 // for integers
293
294 never = 0,
295 equal = 1,
296 zero = 1,
297 lessEqual = 2,
298 less = 3,
299 lessEqualUnsigned = 4,
300 lessUnsigned = 5,
301 carrySet = 5,
302 negative = 6,
303 overflowSet = 7,
304 always = 8,
305 notEqual = 9,
306 notZero = 9,
307 greater = 10,
308 greaterEqual = 11,
309 greaterUnsigned = 12,
310 greaterEqualUnsigned = 13,
311 carryClear = 13,
312 positive = 14,
313 overflowClear = 15
314 };
315
316 enum CC {
317 icc = 0, xcc = 2,
318 // ptr_cc is the correct condition code for a pointer or intptr_t:
319 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
320 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
321 };
322
323 enum PrefetchFcn {
324 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
325 };
326
327 public:
328 // Helper functions for groups of instructions
329
330 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
331
332 enum Membar_mask_bits { // page 184, v9
333 StoreStore = 1 << 3,
334 LoadStore = 1 << 2,
335 StoreLoad = 1 << 1,
336 LoadLoad = 1 << 0,
337
338 Sync = 1 << 6,
339 MemIssue = 1 << 5,
340 Lookaside = 1 << 4
341 };
342
343 static bool is_in_wdisp_range(address a, address b, int nbits) {
344 intptr_t d = intptr_t(b) - intptr_t(a);
345 return is_simm(d, nbits + 2);
346 }
347
348 address target_distance(Label& L) {
349 // Assembler::target(L) should be called only when
350 // a branch instruction is emitted since non-bound
351 // labels record current pc() as a branch address.
352 if (L.is_bound()) return target(L);
353 // Return current address for non-bound labels.
354 return pc();
355 }
356
357 // test if label is in simm16 range in words (wdisp16).
358 bool is_in_wdisp16_range(Label& L) {
359 return is_in_wdisp_range(target_distance(L), pc(), 16);
360 }
361 // test if the distance between two addresses fits in simm30 range in words
362 static bool is_in_wdisp30_range(address a, address b) {
363 return is_in_wdisp_range(a, b, 30);
364 }
365
366 enum ASIs { // page 72, v9
367 ASI_PRIMARY = 0x80,
368 ASI_PRIMARY_NOFAULT = 0x82,
369 ASI_PRIMARY_LITTLE = 0x88,
370 // 8x8-bit partial store
371 ASI_PST8_PRIMARY = 0xC0,
372 // Block initializing store
373 ASI_ST_BLKINIT_PRIMARY = 0xE2,
374 // Most-Recently-Used (MRU) BIS variant
375 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
376 // add more from book as needed
377 };
378
379 protected:
380 // helpers
381
382 // x is supposed to fit in a field "nbits" wide
383 // and be sign-extended. Check the range.
384
385 static void assert_signed_range(intptr_t x, int nbits) {
386 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
387 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
388 }
389
390 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
391 assert( (x & 3) == 0, "not word aligned");
392 assert_signed_range(x, nbits + 2);
393 }
394
395 static void assert_unsigned_const(int x, int nbits) {
396 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
397 }
398
399 // fields: note bits numbered from LSB = 0,
400 // fields known by inclusive bit range
401
402 static int fmask(juint hi_bit, juint lo_bit) {
403 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
404 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
405 }
406
407 // inverse of u_field
408
409 static int inv_u_field(int x, int hi_bit, int lo_bit) {
410 juint r = juint(x) >> lo_bit;
411 r &= fmask( hi_bit, lo_bit);
412 return int(r);
413 }
414
415
416 // signed version: extract from field and sign-extend
417
418 static int inv_s_field(int x, int hi_bit, int lo_bit) {
419 int sign_shift = 31 - hi_bit;
420 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
421 }
422
423 // given a field that ranges from hi_bit to lo_bit (inclusive,
424 // LSB = 0), and an unsigned value for the field,
425 // shift it into the field
426
427 #ifdef ASSERT
428 static int u_field(int x, int hi_bit, int lo_bit) {
429 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
430 "value out of range");
431 int r = x << lo_bit;
432 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
433 return r;
434 }
435 #else
436 // make sure this is inlined as it will reduce code size significantly
437 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
438 #endif
439
440 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
441 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
442 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
443 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
444
445 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
446
447 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
448 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
449 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
450
451 static int op( int x) { return u_field(x, 31, 30); }
452 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
453 static int fcn( int x) { return u_field(x, 29, 25); }
454 static int op3( int x) { return u_field(x, 24, 19); }
455 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
456 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
457 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
458 static int cond( int x) { return u_field(x, 28, 25); }
459 static int cond_mov( int x) { return u_field(x, 17, 14); }
460 static int rcond( RCondition x) { return u_field(x, 12, 10); }
461 static int op2( int x) { return u_field(x, 24, 22); }
462 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
463 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
464 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
465 static int imm_asi( int x) { return u_field(x, 12, 5); }
466 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
467 static int opf_low6( int w) { return u_field(w, 10, 5); }
468 static int opf_low5( int w) { return u_field(w, 9, 5); }
469 static int op5( int x) { return u_field(x, 8, 5); }
470 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
471 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
472 static int opf( int x) { return u_field(x, 13, 5); }
473
474 static bool is_cbcond( int x ) {
475 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
476 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
477 }
478 static bool is_cxb( int x ) {
479 assert(is_cbcond(x), "wrong instruction");
480 return (x & (1<<21)) != 0;
481 }
482 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
483 static int inv_cond_cbcond(int x) {
484 assert(is_cbcond(x), "wrong instruction");
485 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
486 }
487
488 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
489 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
490
491 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
492 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
493 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
494 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
495
496 // some float instructions use this encoding on the op3 field
497 static int alt_op3(int op, FloatRegisterImpl::Width w) {
498 int r;
499 switch(w) {
500 case FloatRegisterImpl::S: r = op + 0; break;
501 case FloatRegisterImpl::D: r = op + 3; break;
502 case FloatRegisterImpl::Q: r = op + 2; break;
503 default: ShouldNotReachHere(); break;
504 }
505 return op3(r);
506 }
507
508
509 // compute inverse of simm
510 static int inv_simm(int x, int nbits) {
511 return (int)(x << (32 - nbits)) >> (32 - nbits);
512 }
513
514 static int inv_simm13( int x ) { return inv_simm(x, 13); }
515
516 // signed immediate, in low bits, nbits long
517 static int simm(int x, int nbits) {
518 assert_signed_range(x, nbits);
519 return x & (( 1 << nbits ) - 1);
520 }
521
522 // compute inverse of wdisp16
523 static intptr_t inv_wdisp16(int x, intptr_t pos) {
524 int lo = x & (( 1 << 14 ) - 1);
525 int hi = (x >> 20) & 3;
526 if (hi >= 2) hi |= ~1;
527 return (((hi << 14) | lo) << 2) + pos;
528 }
529
530 // word offset, 14 bits at LSend, 2 bits at B21, B20
531 static int wdisp16(intptr_t x, intptr_t off) {
532 intptr_t xx = x - off;
533 assert_signed_word_disp_range(xx, 16);
534 int r = (xx >> 2) & ((1 << 14) - 1)
535 | ( ( (xx>>(2+14)) & 3 ) << 20 );
536 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
537 return r;
538 }
539
540 // compute inverse of wdisp10
541 static intptr_t inv_wdisp10(int x, intptr_t pos) {
542 assert(is_cbcond(x), "wrong instruction");
543 int lo = inv_u_field(x, 12, 5);
544 int hi = (x >> 19) & 3;
545 if (hi >= 2) hi |= ~1;
546 return (((hi << 8) | lo) << 2) + pos;
547 }
548
549 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
550 static int wdisp10(intptr_t x, intptr_t off) {
551 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
552 intptr_t xx = x - off;
553 assert_signed_word_disp_range(xx, 10);
554 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
555 | ( ( (xx >> (2+8)) & 3 ) << 19 );
556 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
557 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
558 return r;
559 }
560
561 // word displacement in low-order nbits bits
562
563 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
564 int pre_sign_extend = x & (( 1 << nbits ) - 1);
565 int r = pre_sign_extend >= ( 1 << (nbits-1) )
566 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
567 : pre_sign_extend;
568 return (r << 2) + pos;
569 }
570
571 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
572 intptr_t xx = x - off;
573 assert_signed_word_disp_range(xx, nbits);
574 int r = (xx >> 2) & (( 1 << nbits ) - 1);
575 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
576 return r;
577 }
578
579
580 // Extract the top 32 bits in a 64 bit word
581 static int32_t hi32( int64_t x ) {
582 int32_t r = int32_t( (uint64_t)x >> 32 );
583 return r;
584 }
585
586 // given a sethi instruction, extract the constant, left-justified
587 static int inv_hi22( int x ) {
588 return x << 10;
589 }
590
591 // create an imm22 field, given a 32-bit left-justified constant
592 static int hi22( int x ) {
593 int r = int( juint(x) >> 10 );
594 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
595 return r;
596 }
597
598 // create a low10 __value__ (not a field) for a given a 32-bit constant
599 static int low10( int x ) {
600 return x & ((1 << 10) - 1);
601 }
602
603 // AES crypto instructions supported only on certain processors
604 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
605
606 // SHA crypto instructions supported only on certain processors
607 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
608 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
609 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
610
611 // instruction only in VIS1
612 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
613
614 // instruction only in VIS2
615 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
616
617 // instruction only in VIS3
618 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
619
620 // instruction only in v9
621 static void v9_only() { } // do nothing
622
623 // instruction deprecated in v9
624 static void v9_dep() { } // do nothing for now
625
626 // v8 has no CC field
627 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
628
629 protected:
630 // Simple delay-slot scheme:
631 // In order to check the programmer, the assembler keeps track of deley slots.
632 // It forbids CTIs in delay slots (conservative, but should be OK).
633 // Also, when putting an instruction into a delay slot, you must say
634 // asm->delayed()->add(...), in order to check that you don't omit
635 // delay-slot instructions.
636 // To implement this, we use a simple FSA
637
638 #ifdef ASSERT
639 #define CHECK_DELAY
640 #endif
641 #ifdef CHECK_DELAY
642 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
643 #endif
644
645 public:
646 // Tells assembler next instruction must NOT be in delay slot.
647 // Use at start of multinstruction macros.
648 void assert_not_delayed() {
649 // This is a separate overloading to avoid creation of string constants
650 // in non-asserted code--with some compilers this pollutes the object code.
651 #ifdef CHECK_DELAY
652 assert_not_delayed("next instruction should not be a delay slot");
653 #endif
654 }
655 void assert_not_delayed(const char* msg) {
656 #ifdef CHECK_DELAY
657 assert(delay_state == no_delay, msg);
658 #endif
659 }
660
661 protected:
662 // Insert a nop if the previous is cbcond
663 void insert_nop_after_cbcond() {
664 if (UseCBCond && cbcond_before()) {
665 nop();
666 }
667 }
668 // Delay slot helpers
669 // cti is called when emitting control-transfer instruction,
670 // BEFORE doing the emitting.
671 // Only effective when assertion-checking is enabled.
672 void cti() {
673 // A cbcond instruction immediately followed by a CTI
674 // instruction introduces pipeline stalls, we need to avoid that.
675 no_cbcond_before();
676 #ifdef CHECK_DELAY
677 assert_not_delayed("cti should not be in delay slot");
678 #endif
679 }
680
681 // called when emitting cti with a delay slot, AFTER emitting
682 void has_delay_slot() {
683 #ifdef CHECK_DELAY
684 assert_not_delayed("just checking");
685 delay_state = at_delay_slot;
686 #endif
687 }
688
689 // cbcond instruction should not be generated one after an other
690 bool cbcond_before() {
691 if (offset() == 0) return false; // it is first instruction
692 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
693 return is_cbcond(x);
694 }
695
696 void no_cbcond_before() {
697 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
698 }
699 public:
700
701 bool use_cbcond(Label& L) {
702 if (!UseCBCond || cbcond_before()) return false;
703 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
704 assert( (x & 3) == 0, "not word aligned");
705 return is_simm12(x);
706 }
707
708 // Tells assembler you know that next instruction is delayed
709 Assembler* delayed() {
710 #ifdef CHECK_DELAY
711 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
712 delay_state = filling_delay_slot;
713 #endif
714 return this;
715 }
716
717 void flush() {
718 #ifdef CHECK_DELAY
719 assert ( delay_state == no_delay, "ending code with a delay slot");
720 #endif
721 AbstractAssembler::flush();
722 }
723
724 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
725 inline void emit_data(int x) { emit_int32(x); }
726 inline void emit_data(int, RelocationHolder const&);
727 inline void emit_data(int, relocInfo::relocType rtype);
728 // helper for above fcns
729 inline void check_delay();
730
731
732 public:
733 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
734
735 // pp 135 (addc was addx in v8)
736
737 inline void add(Register s1, Register s2, Register d );
738 inline void add(Register s1, int simm13a, Register d );
739
740 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
741 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
742 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
743 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
744 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
745 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
746
747
748 // 4-operand AES instructions
749
750 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
751 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
752 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
753 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
754 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
755 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
756 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
757 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
758 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
759
760
761 // 3-operand AES instructions
762
763 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
764 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
765
766 // pp 136
767
768 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
769 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
770
771 // compare and branch
772 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
773 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
774
775 protected: // use MacroAssembler::br instead
776
777 // pp 138
778
779 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
780 inline void fb( Condition c, bool a, Label& L );
781
782 // pp 141
783
784 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
785 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
786
787 // pp 144
788
789 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
790 inline void br( Condition c, bool a, Label& L );
791
792 // pp 146
793
794 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
795 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
796
797 // pp 149
798
799 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
800 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
801
802 public:
803
804 // pp 150
805
806 // These instructions compare the contents of s2 with the contents of
807 // memory at address in s1. If the values are equal, the contents of memory
808 // at address s1 is swapped with the data in d. If the values are not equal,
809 // the the contents of memory at s1 is loaded into d, without the swap.
810
811 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
812 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
813
814 // pp 152
815
816 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
817 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
818 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
819 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
820 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
821 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
822 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
823 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
824
825 // pp 155
826
827 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
828 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
829
830 // pp 156
831
832 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
833 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
834
835 // pp 157
836
837 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
838 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
839
840 // pp 159
841
842 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
843 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
844
845 // pp 160
846
847 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
848
849 // pp 161
850
851 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
852 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
853
854 // pp 162
855
856 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
857
858 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
859
860 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
861
862 // pp 163
863
864 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
865 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
866 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
867
868 // FXORs/FXORd instructions
869
870 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
871
872 // pp 164
873
874 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
875
876 // pp 165
877
878 inline void flush( Register s1, Register s2 );
879 inline void flush( Register s1, int simm13a);
880
881 // pp 167
882
883 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
884
885 // pp 168
886
887 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
888 // v8 unimp == illtrap(0)
889
890 // pp 169
891
892 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
893 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
894
895 // pp 170
896
897 void jmpl( Register s1, Register s2, Register d );
898 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
899
900 // 171
901
902 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
903 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
904
905
906 inline void ldfsr( Register s1, Register s2 );
907 inline void ldfsr( Register s1, int simm13a);
908 inline void ldxfsr( Register s1, Register s2 );
909 inline void ldxfsr( Register s1, int simm13a);
910
911 // 173
912
913 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
914 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
915
916 // pp 175, lduw is ld on v8
917
918 inline void ldsb( Register s1, Register s2, Register d );
919 inline void ldsb( Register s1, int simm13a, Register d);
920 inline void ldsh( Register s1, Register s2, Register d );
921 inline void ldsh( Register s1, int simm13a, Register d);
922 inline void ldsw( Register s1, Register s2, Register d );
923 inline void ldsw( Register s1, int simm13a, Register d);
924 inline void ldub( Register s1, Register s2, Register d );
925 inline void ldub( Register s1, int simm13a, Register d);
926 inline void lduh( Register s1, Register s2, Register d );
927 inline void lduh( Register s1, int simm13a, Register d);
928 inline void lduw( Register s1, Register s2, Register d );
929 inline void lduw( Register s1, int simm13a, Register d);
930 inline void ldx( Register s1, Register s2, Register d );
931 inline void ldx( Register s1, int simm13a, Register d);
932 inline void ldd( Register s1, Register s2, Register d );
933 inline void ldd( Register s1, int simm13a, Register d);
934
935 // pp 177
936
937 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
938 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
939 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
940 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
941 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
942 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
943 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
944 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
945 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
946 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
947 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
948 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
949 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
950 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
951
952 // pp 181
953
954 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
955 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
956 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
957 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
958 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
959 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
960 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
961 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
962 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
963 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
964 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
965 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
966 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
967 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
968 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
969 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
970 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
971 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
972 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
973 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
974 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
975 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
976 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
977 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
978
979 // pp 183
980
981 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
982
983 // pp 185
984
985 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
986
987 // pp 189
988
989 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
990
991 // pp 191
992
993 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
994 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
995
996 // pp 195
997
998 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
999 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1000
1001 // pp 196
1002
1003 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1004 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1005 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1006 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1007 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1008 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1009
1010 // pp 197
1011
1012 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1013 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1014 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1015 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1016 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1017 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1018 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1019 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1020
1021 // pp 201
1022
1023 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1024
1025
1026 // pp 202
1027
1028 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1029 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1030
1031 // pp 203
1032
1033 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1034 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1035
1036 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1037 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1038
1039 // pp 208
1040
1041 // not implementing read privileged register
1042
1043 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1044 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1045 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1046 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1047 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1048 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1049
1050 // pp 213
1051
1052 inline void rett( Register s1, Register s2);
1053 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1054
1055 // pp 214
1056
1057 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1058 void save( Register s1, int simm13a, Register d ) {
1059 // make sure frame is at least large enough for the register save area
1060 assert(-simm13a >= 16 * wordSize, "frame too small");
1061 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1062 }
1063
1064 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1065 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1066
1067 // pp 216
1068
1069 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
1070 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
1071
1072 // pp 217
1073
1074 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1075 // pp 218
1076
1077 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1078 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1079 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1080 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1081 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1082 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1083
1084 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1085 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1086 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1087 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1088 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1089 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1090
1091 // pp 220
1092
1093 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1094
1095 // pp 221
1096
1097 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1098
1099 // pp 222
1100
1101 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1102 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1103
1104 inline void stfsr( Register s1, Register s2 );
1105 inline void stfsr( Register s1, int simm13a);
1106 inline void stxfsr( Register s1, Register s2 );
1107 inline void stxfsr( Register s1, int simm13a);
1108
1109 // pp 224
1110
1111 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1112 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1113
1114 // p 226
1115
1116 inline void stb( Register d, Register s1, Register s2 );
1117 inline void stb( Register d, Register s1, int simm13a);
1118 inline void sth( Register d, Register s1, Register s2 );
1119 inline void sth( Register d, Register s1, int simm13a);
1120 inline void stw( Register d, Register s1, Register s2 );
1121 inline void stw( Register d, Register s1, int simm13a);
1122 inline void stx( Register d, Register s1, Register s2 );
1123 inline void stx( Register d, Register s1, int simm13a);
1124 inline void std( Register d, Register s1, Register s2 );
1125 inline void std( Register d, Register s1, int simm13a);
1126
1127 // pp 177
1128
1129 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1130 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1131 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1132 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1133 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1134 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1135 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1136 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1137 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1138 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1139
1140 // pp 230
1141
1142 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1143 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1144
1145 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1146 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1147 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1148 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1149 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1150 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1151
1152 // pp 231
1153
1154 inline void swap( Register s1, Register s2, Register d );
1155 inline void swap( Register s1, int simm13a, Register d);
1156
1157 // pp 232
1158
1159 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1160 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1161
1162 // pp 234, note op in book is wrong, see pp 268
1163
1164 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1165 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1166
1167 // pp 235
1168
1169 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1170 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1171
1172 // pp 237
1173
1174 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1175 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1176 // simple uncond. trap
1177 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1178
1179 // pp 239 omit write priv register for now
1180
1181 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1182 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1183 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1184 rs1(s) |
1185 op3(wrreg_op3) |
1186 u_field(2, 29, 25) |
1187 immed(true) |
1188 simm(simm13a, 13)); }
1189 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1190 // wrasi(d, imm) stores (d xor imm) to asi
1191 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1192 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1193 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1194
1195 // VIS1 instructions
1196
1197 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1198
1199 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1200
1201 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1202
1203 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1204
1205 // VIS2 instructions
1206
1207 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1208
1209 // VIS3 instructions
1210
1211 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1212 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1213 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1214
1215 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1216 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1217
1218 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1219 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1220
1221 // Crypto SHA instructions
1222
1223 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1224 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1225 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1226
1227 // Creation
1228 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1229 #ifdef CHECK_DELAY
1230 delay_state = no_delay;
1231 #endif
1232 }
1233 };
1234
1235 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP