1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "runtime/java.hpp"
  29 #include "runtime/os.hpp"
  30 #include "runtime/stubCodeGenerator.hpp"
  31 #include "vm_version_sparc.hpp"
  32 
  33 int VM_Version::_features = VM_Version::unknown_m;
  34 const char* VM_Version::_features_str = "";
  35 unsigned int VM_Version::_L2_data_cache_line_size = 0;
  36 
  37 void VM_Version::initialize() {
  38   _features = determine_features();
  39   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  40   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  41   PrefetchFieldsAhead         = prefetch_fields_ahead();
  42 
  43   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
  44   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
  45   if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
  46 
  47   // Allocation prefetch settings
  48   intx cache_line_size = prefetch_data_size();
  49   if( cache_line_size > AllocatePrefetchStepSize )
  50     AllocatePrefetchStepSize = cache_line_size;
  51 
  52   assert(AllocatePrefetchLines > 0, "invalid value");
  53   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
  54     AllocatePrefetchLines = 3;
  55   assert(AllocateInstancePrefetchLines > 0, "invalid value");
  56   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
  57     AllocateInstancePrefetchLines = 1;
  58 
  59   AllocatePrefetchDistance = allocate_prefetch_distance();
  60   AllocatePrefetchStyle    = allocate_prefetch_style();
  61 
  62   assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
  63          (AllocatePrefetchDistance > 0), "invalid value");
  64   if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
  65       (AllocatePrefetchDistance <= 0)) {
  66     AllocatePrefetchDistance = AllocatePrefetchStepSize;
  67   }
  68 
  69   if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
  70     warning("BIS instructions are not available on this CPU");
  71     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
  72   }
  73 
  74   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
  75 
  76   assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
  77   if (ArraycopySrcPrefetchDistance >= 4096)
  78     ArraycopySrcPrefetchDistance = 4064;
  79   assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
  80   if (ArraycopyDstPrefetchDistance >= 4096)
  81     ArraycopyDstPrefetchDistance = 4064;
  82 
  83   UseSSE = 0; // Only on x86 and x64
  84 
  85   _supports_cx8 = has_v9();
  86   _supports_atomic_getset4 = true; // swap instruction
  87 
  88   // There are Fujitsu Sparc64 CPUs which support blk_init as well so
  89   // we have to take this check out of the 'is_niagara()' block below.
  90   if (has_blk_init()) {
  91     // When using CMS or G1, we cannot use memset() in BOT updates
  92     // because the sun4v/CMT version in libc_psr uses BIS which
  93     // exposes "phantom zeros" to concurrent readers. See 6948537.
  94     if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
  95       FLAG_SET_DEFAULT(UseMemSetInBOT, false);
  96     }
  97     // Issue a stern warning if the user has explicitly set
  98     // UseMemSetInBOT (it is known to cause issues), but allow
  99     // use for experimentation and debugging.
 100     if (UseConcMarkSweepGC || UseG1GC) {
 101       if (UseMemSetInBOT) {
 102         assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
 103         warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
 104                 " on sun4v; please understand that you are using at your own risk!");
 105       }
 106     }
 107   }
 108 
 109   if (is_niagara()) {
 110     // Indirect branch is the same cost as direct
 111     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
 112       FLAG_SET_DEFAULT(UseInlineCaches, false);
 113     }
 114     // Align loops on a single instruction boundary.
 115     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
 116       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
 117     }
 118 #ifdef _LP64
 119     // 32-bit oops don't make sense for the 64-bit VM on sparc
 120     // since the 32-bit VM has the same registers and smaller objects.
 121     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
 122     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
 123 #endif // _LP64
 124 #ifdef COMPILER2
 125     // Indirect branch is the same cost as direct
 126     if (FLAG_IS_DEFAULT(UseJumpTables)) {
 127       FLAG_SET_DEFAULT(UseJumpTables, true);
 128     }
 129     // Single-issue, so entry and loop tops are
 130     // aligned on a single instruction boundary
 131     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
 132       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
 133     }
 134     if (is_niagara_plus()) {
 135       if (has_blk_init() && UseTLAB &&
 136           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
 137         // Use BIS instruction for TLAB allocation prefetch.
 138         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
 139         if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 140           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
 141         }
 142         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 143           // Use smaller prefetch distance with BIS
 144           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
 145         }
 146       }
 147       if (is_T4()) {
 148         // Double number of prefetched cache lines on T4
 149         // since L2 cache line size is smaller (32 bytes).
 150         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
 151           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
 152         }
 153         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
 154           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
 155         }
 156       }
 157       if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 158         // Use different prefetch distance without BIS
 159         FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
 160       }
 161       if (AllocatePrefetchInstr == 1) {
 162         // Need a space at the end of TLAB for BIS since it
 163         // will fault when accessing memory outside of heap.
 164 
 165         // +1 for rounding up to next cache line, +1 to be safe
 166         int lines = AllocatePrefetchLines + 2;
 167         int step_size = AllocatePrefetchStepSize;
 168         int distance = AllocatePrefetchDistance;
 169         _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
 170       }
 171     }
 172 #endif
 173   }
 174 
 175   // Use hardware population count instruction if available.
 176   if (has_hardware_popc()) {
 177     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 178       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 179     }
 180   } else if (UsePopCountInstruction) {
 181     warning("POPC instruction is not available on this CPU");
 182     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 183   }
 184 
 185   // T4 and newer Sparc cpus have new compare and branch instruction.
 186   if (has_cbcond()) {
 187     if (FLAG_IS_DEFAULT(UseCBCond)) {
 188       FLAG_SET_DEFAULT(UseCBCond, true);
 189     }
 190   } else if (UseCBCond) {
 191     warning("CBCOND instruction is not available on this CPU");
 192     FLAG_SET_DEFAULT(UseCBCond, false);
 193   }
 194 
 195   assert(BlockZeroingLowLimit > 0, "invalid value");
 196   if (has_block_zeroing() && cache_line_size > 0) {
 197     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 198       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 199     }
 200   } else if (UseBlockZeroing) {
 201     warning("BIS zeroing instructions are not available on this CPU");
 202     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 203   }
 204 
 205   assert(BlockCopyLowLimit > 0, "invalid value");
 206   if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
 207     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
 208       FLAG_SET_DEFAULT(UseBlockCopy, true);
 209     }
 210   } else if (UseBlockCopy) {
 211     warning("BIS instructions are not available or expensive on this CPU");
 212     FLAG_SET_DEFAULT(UseBlockCopy, false);
 213   }
 214 
 215 #ifdef COMPILER2
 216   // T4 and newer Sparc cpus have fast RDPC.
 217   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 218     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 219   }
 220 
 221   // Currently not supported anywhere.
 222   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 223 
 224   MaxVectorSize = 8;
 225 
 226   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 227 #endif
 228 
 229   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 230   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 231 
 232   char buf[512];
 233   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 234                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 235                (has_hardware_popc() ? ", popc" : ""),
 236                (has_vis1() ? ", vis1" : ""),
 237                (has_vis2() ? ", vis2" : ""),
 238                (has_vis3() ? ", vis3" : ""),
 239                (has_blk_init() ? ", blk_init" : ""),
 240                (has_cbcond() ? ", cbcond" : ""),
 241                (has_aes() ? ", aes" : ""),
 242                (has_sha1() ? ", sha1" : ""),
 243                (has_sha256() ? ", sha256" : ""),
 244                (has_sha512() ? ", sha512" : ""),
 245                (is_ultra3() ? ", ultra3" : ""),
 246                (is_sun4v() ? ", sun4v" : ""),
 247                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 248                (is_sparc64() ? ", sparc64" : ""),
 249                (!has_hardware_mul32() ? ", no-mul32" : ""),
 250                (!has_hardware_div32() ? ", no-div32" : ""),
 251                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 252 
 253   // buf is started with ", " or is empty
 254   _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
 255 
 256   // UseVIS is set to the smallest of what hardware supports and what
 257   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 258   // older UltraSparc which do not support it.
 259   if (UseVIS > 3) UseVIS=3;
 260   if (UseVIS < 0) UseVIS=0;
 261   if (!has_vis3()) // Drop to 2 if no VIS3 support
 262     UseVIS = MIN2((intx)2,UseVIS);
 263   if (!has_vis2()) // Drop to 1 if no VIS2 support
 264     UseVIS = MIN2((intx)1,UseVIS);
 265   if (!has_vis1()) // Drop to 0 if no VIS1 support
 266     UseVIS = 0;
 267 
 268   // SPARC T4 and above should have support for AES instructions
 269   if (has_aes()) {
 270     if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
 271       if (FLAG_IS_DEFAULT(UseAES)) {
 272         FLAG_SET_DEFAULT(UseAES, true);
 273       }
 274       if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 275         FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 276       }
 277       // we disable both the AES flags if either of them is disabled on the command line
 278       if (!UseAES || !UseAESIntrinsics) {
 279         FLAG_SET_DEFAULT(UseAES, false);
 280         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 281       }
 282     } else {
 283         if (UseAES || UseAESIntrinsics) {
 284           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 285           if (UseAES) {
 286             FLAG_SET_DEFAULT(UseAES, false);
 287           }
 288           if (UseAESIntrinsics) {
 289             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 290           }
 291         }
 292     }
 293   } else if (UseAES || UseAESIntrinsics) {
 294     warning("AES instructions are not available on this CPU");
 295     if (UseAES) {
 296       FLAG_SET_DEFAULT(UseAES, false);
 297     }
 298     if (UseAESIntrinsics) {
 299       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 300     }
 301   }
 302 
 303   // GHASH/GCM intrinsics
 304   if (has_vis3() && (UseVIS > 2)) {
 305     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 306       UseGHASHIntrinsics = true;
 307     }
 308   } else if (UseGHASHIntrinsics) {
 309     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 310       warning("GHASH intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 311     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 312   } 
 313       
 314   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 315   if (has_sha1() || has_sha256() || has_sha512()) {
 316     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 317       if (FLAG_IS_DEFAULT(UseSHA)) {
 318         FLAG_SET_DEFAULT(UseSHA, true);
 319       }
 320     } else {
 321       if (UseSHA) {
 322         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 323         FLAG_SET_DEFAULT(UseSHA, false);
 324       }
 325     }
 326   } else if (UseSHA) {
 327     warning("SHA instructions are not available on this CPU");
 328     FLAG_SET_DEFAULT(UseSHA, false);
 329   }
 330 
 331   if (!UseSHA) {
 332     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 333     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 334     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 335   } else {
 336     if (has_sha1()) {
 337       if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 338         FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 339       }
 340     } else if (UseSHA1Intrinsics) {
 341       warning("SHA1 instruction is not available on this CPU.");
 342       FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 343     }
 344     if (has_sha256()) {
 345       if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 346         FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 347       }
 348     } else if (UseSHA256Intrinsics) {
 349       warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
 350       FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 351     }
 352 
 353     if (has_sha512()) {
 354       if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 355         FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 356       }
 357     } else if (UseSHA512Intrinsics) {
 358       warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
 359       FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 360     }
 361     if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 362       FLAG_SET_DEFAULT(UseSHA, false);
 363     }
 364   }
 365 
 366   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 367     (cache_line_size > ContendedPaddingWidth))
 368     ContendedPaddingWidth = cache_line_size;
 369 
 370   // This machine does not allow unaligned memory accesses
 371   if (UseUnalignedAccesses) {
 372     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 373       warning("Unaligned memory access is not available on this CPU");
 374     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 375   }
 376 
 377 #ifndef PRODUCT
 378   if (PrintMiscellaneous && Verbose) {
 379     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 380     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 381     tty->print("Allocation");
 382     if (AllocatePrefetchStyle <= 0) {
 383       tty->print_cr(": no prefetching");
 384     } else {
 385       tty->print(" prefetching: ");
 386       if (AllocatePrefetchInstr == 0) {
 387           tty->print("PREFETCH");
 388       } else if (AllocatePrefetchInstr == 1) {
 389           tty->print("BIS");
 390       }
 391       if (AllocatePrefetchLines > 1) {
 392         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 393       } else {
 394         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
 395       }
 396     }
 397     if (PrefetchCopyIntervalInBytes > 0) {
 398       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
 399     }
 400     if (PrefetchScanIntervalInBytes > 0) {
 401       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
 402     }
 403     if (PrefetchFieldsAhead > 0) {
 404       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
 405     }
 406     if (ContendedPaddingWidth > 0) {
 407       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
 408     }
 409   }
 410 #endif // PRODUCT
 411 }
 412 
 413 void VM_Version::print_features() {
 414   tty->print_cr("Version:%s", cpu_features());
 415 }
 416 
 417 int VM_Version::determine_features() {
 418   if (UseV8InstrsOnly) {
 419     NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
 420     return generic_v8_m;
 421   }
 422 
 423   int features = platform_features(unknown_m); // platform_features() is os_arch specific
 424 
 425   if (features == unknown_m) {
 426     features = generic_v9_m;
 427     warning("Cannot recognize SPARC version. Default to V9");
 428   }
 429 
 430   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
 431   if (UseNiagaraInstrs) { // Force code generation for Niagara
 432     if (is_T_family(features)) {
 433       // Happy to accomodate...
 434     } else {
 435       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
 436       features |= T_family_m;
 437     }
 438   } else {
 439     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
 440       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
 441       features &= ~(T_family_m | T1_model_m);
 442     } else {
 443       // Happy to accomodate...
 444     }
 445   }
 446 
 447   return features;
 448 }
 449 
 450 static int saved_features = 0;
 451 
 452 void VM_Version::allow_all() {
 453   saved_features = _features;
 454   _features      = all_features_m;
 455 }
 456 
 457 void VM_Version::revert() {
 458   _features = saved_features;
 459 }
 460 
 461 unsigned int VM_Version::calc_parallel_worker_threads() {
 462   unsigned int result;
 463   if (is_M_series()) {
 464     // for now, use same gc thread calculation for M-series as for niagara-plus
 465     // in future, we may want to tweak parameters for nof_parallel_worker_thread
 466     result = nof_parallel_worker_threads(5, 16, 8);
 467   } else if (is_niagara_plus()) {
 468     result = nof_parallel_worker_threads(5, 16, 8);
 469   } else {
 470     result = nof_parallel_worker_threads(5, 8, 8);
 471   }
 472   return result;
 473 }
--- EOF ---