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src/cpu/sparc/vm/vm_version_sparc.cpp

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 283         if (UseAES || UseAESIntrinsics) {
 284           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 285           if (UseAES) {
 286             FLAG_SET_DEFAULT(UseAES, false);
 287           }
 288           if (UseAESIntrinsics) {
 289             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 290           }
 291         }
 292     }
 293   } else if (UseAES || UseAESIntrinsics) {
 294     warning("AES instructions are not available on this CPU");
 295     if (UseAES) {
 296       FLAG_SET_DEFAULT(UseAES, false);
 297     }
 298     if (UseAESIntrinsics) {
 299       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 300     }
 301   }
 302 











 303   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 304   if (has_sha1() || has_sha256() || has_sha512()) {
 305     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 306       if (FLAG_IS_DEFAULT(UseSHA)) {
 307         FLAG_SET_DEFAULT(UseSHA, true);
 308       }
 309     } else {
 310       if (UseSHA) {
 311         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 312         FLAG_SET_DEFAULT(UseSHA, false);
 313       }
 314     }
 315   } else if (UseSHA) {
 316     warning("SHA instructions are not available on this CPU");
 317     FLAG_SET_DEFAULT(UseSHA, false);
 318   }
 319 
 320   if (!UseSHA) {
 321     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 322     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);




 283         if (UseAES || UseAESIntrinsics) {
 284           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 285           if (UseAES) {
 286             FLAG_SET_DEFAULT(UseAES, false);
 287           }
 288           if (UseAESIntrinsics) {
 289             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 290           }
 291         }
 292     }
 293   } else if (UseAES || UseAESIntrinsics) {
 294     warning("AES instructions are not available on this CPU");
 295     if (UseAES) {
 296       FLAG_SET_DEFAULT(UseAES, false);
 297     }
 298     if (UseAESIntrinsics) {
 299       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 300     }
 301   }
 302 
 303   // GHASH/GCM intrinsics
 304   if (has_vis3() && (UseVIS > 2)) {
 305     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 306       UseGHASHIntrinsics = true;
 307     }
 308   } else if (UseGHASHIntrinsics) {
 309     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 310       warning("GHASH intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 311     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 312   } 
 313       
 314   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 315   if (has_sha1() || has_sha256() || has_sha512()) {
 316     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 317       if (FLAG_IS_DEFAULT(UseSHA)) {
 318         FLAG_SET_DEFAULT(UseSHA, true);
 319       }
 320     } else {
 321       if (UseSHA) {
 322         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 323         FLAG_SET_DEFAULT(UseSHA, false);
 324       }
 325     }
 326   } else if (UseSHA) {
 327     warning("SHA instructions are not available on this CPU");
 328     FLAG_SET_DEFAULT(UseSHA, false);
 329   }
 330 
 331   if (!UseSHA) {
 332     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 333     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);


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