1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableModRefBS.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/interfaceSupport.hpp" 35 #include "runtime/objectMonitor.hpp" 36 #include "runtime/os.hpp" 37 #include "runtime/sharedRuntime.hpp" 38 #include "runtime/stubRoutines.hpp" 39 #include "utilities/macros.hpp" 40 #if INCLUDE_ALL_GCS 41 #include "gc/g1/g1CollectedHeap.inline.hpp" 42 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 43 #include "gc/g1/heapRegion.hpp" 44 #endif // INCLUDE_ALL_GCS 45 46 #ifdef PRODUCT 47 #define BLOCK_COMMENT(str) /* nothing */ 48 #define STOP(error) stop(error) 49 #else 50 #define BLOCK_COMMENT(str) block_comment(str) 51 #define STOP(error) block_comment(error); stop(error) 52 #endif 53 54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 55 // Implementation of AddressLiteral 56 57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 59 // -----------------Table 4.5 -------------------- // 60 16, 32, 64, // EVEX_FV(0) 61 4, 4, 4, // EVEX_FV(1) - with Evex.b 62 16, 32, 64, // EVEX_FV(2) - with Evex.w 63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 64 8, 16, 32, // EVEX_HV(0) 65 4, 4, 4, // EVEX_HV(1) - with Evex.b 66 // -----------------Table 4.6 -------------------- // 67 16, 32, 64, // EVEX_FVM(0) 68 1, 1, 1, // EVEX_T1S(0) 69 2, 2, 2, // EVEX_T1S(1) 70 4, 4, 4, // EVEX_T1S(2) 71 8, 8, 8, // EVEX_T1S(3) 72 4, 4, 4, // EVEX_T1F(0) 73 8, 8, 8, // EVEX_T1F(1) 74 8, 8, 8, // EVEX_T2(0) 75 0, 16, 16, // EVEX_T2(1) 76 0, 16, 16, // EVEX_T4(0) 77 0, 0, 32, // EVEX_T4(1) 78 0, 0, 32, // EVEX_T8(0) 79 8, 16, 32, // EVEX_HVM(0) 80 4, 8, 16, // EVEX_QVM(0) 81 2, 4, 8, // EVEX_OVM(0) 82 16, 16, 16, // EVEX_M128(0) 83 8, 32, 64, // EVEX_DUP(0) 84 0, 0, 0 // EVEX_NTUP 85 }; 86 87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 88 _is_lval = false; 89 _target = target; 90 switch (rtype) { 91 case relocInfo::oop_type: 92 case relocInfo::metadata_type: 93 // Oops are a special case. Normally they would be their own section 94 // but in cases like icBuffer they are literals in the code stream that 95 // we don't have a section for. We use none so that we get a literal address 96 // which is always patchable. 97 break; 98 case relocInfo::external_word_type: 99 _rspec = external_word_Relocation::spec(target); 100 break; 101 case relocInfo::internal_word_type: 102 _rspec = internal_word_Relocation::spec(target); 103 break; 104 case relocInfo::opt_virtual_call_type: 105 _rspec = opt_virtual_call_Relocation::spec(); 106 break; 107 case relocInfo::static_call_type: 108 _rspec = static_call_Relocation::spec(); 109 break; 110 case relocInfo::runtime_call_type: 111 _rspec = runtime_call_Relocation::spec(); 112 break; 113 case relocInfo::poll_type: 114 case relocInfo::poll_return_type: 115 _rspec = Relocation::spec_simple(rtype); 116 break; 117 case relocInfo::none: 118 break; 119 default: 120 ShouldNotReachHere(); 121 break; 122 } 123 } 124 125 // Implementation of Address 126 127 #ifdef _LP64 128 129 Address Address::make_array(ArrayAddress adr) { 130 // Not implementable on 64bit machines 131 // Should have been handled higher up the call chain. 132 ShouldNotReachHere(); 133 return Address(); 134 } 135 136 // exceedingly dangerous constructor 137 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 138 _base = noreg; 139 _index = noreg; 140 _scale = no_scale; 141 _disp = disp; 142 switch (rtype) { 143 case relocInfo::external_word_type: 144 _rspec = external_word_Relocation::spec(loc); 145 break; 146 case relocInfo::internal_word_type: 147 _rspec = internal_word_Relocation::spec(loc); 148 break; 149 case relocInfo::runtime_call_type: 150 // HMM 151 _rspec = runtime_call_Relocation::spec(); 152 break; 153 case relocInfo::poll_type: 154 case relocInfo::poll_return_type: 155 _rspec = Relocation::spec_simple(rtype); 156 break; 157 case relocInfo::none: 158 break; 159 default: 160 ShouldNotReachHere(); 161 } 162 } 163 #else // LP64 164 165 Address Address::make_array(ArrayAddress adr) { 166 AddressLiteral base = adr.base(); 167 Address index = adr.index(); 168 assert(index._disp == 0, "must not have disp"); // maybe it can? 169 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 170 array._rspec = base._rspec; 171 return array; 172 } 173 174 // exceedingly dangerous constructor 175 Address::Address(address loc, RelocationHolder spec) { 176 _base = noreg; 177 _index = noreg; 178 _scale = no_scale; 179 _disp = (intptr_t) loc; 180 _rspec = spec; 181 } 182 183 #endif // _LP64 184 185 186 187 // Convert the raw encoding form into the form expected by the constructor for 188 // Address. An index of 4 (rsp) corresponds to having no index, so convert 189 // that to noreg for the Address constructor. 190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 191 RelocationHolder rspec; 192 if (disp_reloc != relocInfo::none) { 193 rspec = Relocation::spec_simple(disp_reloc); 194 } 195 bool valid_index = index != rsp->encoding(); 196 if (valid_index) { 197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 198 madr._rspec = rspec; 199 return madr; 200 } else { 201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 202 madr._rspec = rspec; 203 return madr; 204 } 205 } 206 207 // Implementation of Assembler 208 209 int AbstractAssembler::code_fill_byte() { 210 return (u_char)'\xF4'; // hlt 211 } 212 213 // make this go away someday 214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 215 if (rtype == relocInfo::none) 216 emit_int32(data); 217 else 218 emit_data(data, Relocation::spec_simple(rtype), format); 219 } 220 221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 222 assert(imm_operand == 0, "default format must be immediate in this file"); 223 assert(inst_mark() != NULL, "must be inside InstructionMark"); 224 if (rspec.type() != relocInfo::none) { 225 #ifdef ASSERT 226 check_relocation(rspec, format); 227 #endif 228 // Do not use AbstractAssembler::relocate, which is not intended for 229 // embedded words. Instead, relocate to the enclosing instruction. 230 231 // hack. call32 is too wide for mask so use disp32 232 if (format == call32_operand) 233 code_section()->relocate(inst_mark(), rspec, disp32_operand); 234 else 235 code_section()->relocate(inst_mark(), rspec, format); 236 } 237 emit_int32(data); 238 } 239 240 static int encode(Register r) { 241 int enc = r->encoding(); 242 if (enc >= 8) { 243 enc -= 8; 244 } 245 return enc; 246 } 247 248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 249 assert(dst->has_byte_register(), "must have byte register"); 250 assert(isByte(op1) && isByte(op2), "wrong opcode"); 251 assert(isByte(imm8), "not a byte"); 252 assert((op1 & 0x01) == 0, "should be 8bit operation"); 253 emit_int8(op1); 254 emit_int8(op2 | encode(dst)); 255 emit_int8(imm8); 256 } 257 258 259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 260 assert(isByte(op1) && isByte(op2), "wrong opcode"); 261 assert((op1 & 0x01) == 1, "should be 32bit operation"); 262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 263 if (is8bit(imm32)) { 264 emit_int8(op1 | 0x02); // set sign bit 265 emit_int8(op2 | encode(dst)); 266 emit_int8(imm32 & 0xFF); 267 } else { 268 emit_int8(op1); 269 emit_int8(op2 | encode(dst)); 270 emit_int32(imm32); 271 } 272 } 273 274 // Force generation of a 4 byte immediate value even if it fits into 8bit 275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 276 assert(isByte(op1) && isByte(op2), "wrong opcode"); 277 assert((op1 & 0x01) == 1, "should be 32bit operation"); 278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 279 emit_int8(op1); 280 emit_int8(op2 | encode(dst)); 281 emit_int32(imm32); 282 } 283 284 // immediate-to-memory forms 285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 286 assert((op1 & 0x01) == 1, "should be 32bit operation"); 287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 288 if (is8bit(imm32)) { 289 emit_int8(op1 | 0x02); // set sign bit 290 emit_operand(rm, adr, 1); 291 emit_int8(imm32 & 0xFF); 292 } else { 293 emit_int8(op1); 294 emit_operand(rm, adr, 4); 295 emit_int32(imm32); 296 } 297 } 298 299 300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 301 assert(isByte(op1) && isByte(op2), "wrong opcode"); 302 emit_int8(op1); 303 emit_int8(op2 | encode(dst) << 3 | encode(src)); 304 } 305 306 307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 309 int mod_idx = 0; 310 // We will test if the displacement fits the compressed format and if so 311 // apply the compression to the displacment iff the result is8bit. 312 if (VM_Version::supports_evex() && is_evex_inst) { 313 switch (cur_tuple_type) { 314 case EVEX_FV: 315 if ((cur_encoding & VEX_W) == VEX_W) { 316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 317 } else { 318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 319 } 320 break; 321 322 case EVEX_HV: 323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 324 break; 325 326 case EVEX_FVM: 327 break; 328 329 case EVEX_T1S: 330 switch (in_size_in_bits) { 331 case EVEX_8bit: 332 break; 333 334 case EVEX_16bit: 335 mod_idx = 1; 336 break; 337 338 case EVEX_32bit: 339 mod_idx = 2; 340 break; 341 342 case EVEX_64bit: 343 mod_idx = 3; 344 break; 345 } 346 break; 347 348 case EVEX_T1F: 349 case EVEX_T2: 350 case EVEX_T4: 351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 352 break; 353 354 case EVEX_T8: 355 break; 356 357 case EVEX_HVM: 358 break; 359 360 case EVEX_QVM: 361 break; 362 363 case EVEX_OVM: 364 break; 365 366 case EVEX_M128: 367 break; 368 369 case EVEX_DUP: 370 break; 371 372 default: 373 assert(0, "no valid evex tuple_table entry"); 374 break; 375 } 376 377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 379 if ((disp % disp_factor) == 0) { 380 int new_disp = disp / disp_factor; 381 if ((-0x80 <= new_disp && new_disp < 0x80)) { 382 disp = new_disp; 383 } 384 } else { 385 return false; 386 } 387 } 388 } 389 return (-0x80 <= disp && disp < 0x80); 390 } 391 392 393 bool Assembler::emit_compressed_disp_byte(int &disp) { 394 int mod_idx = 0; 395 // We will test if the displacement fits the compressed format and if so 396 // apply the compression to the displacment iff the result is8bit. 397 if (VM_Version::supports_evex() && is_evex_instruction) { 398 switch (tuple_type) { 399 case EVEX_FV: 400 if ((evex_encoding & VEX_W) == VEX_W) { 401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 402 } else { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 404 } 405 break; 406 407 case EVEX_HV: 408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 409 break; 410 411 case EVEX_FVM: 412 break; 413 414 case EVEX_T1S: 415 switch (input_size_in_bits) { 416 case EVEX_8bit: 417 break; 418 419 case EVEX_16bit: 420 mod_idx = 1; 421 break; 422 423 case EVEX_32bit: 424 mod_idx = 2; 425 break; 426 427 case EVEX_64bit: 428 mod_idx = 3; 429 break; 430 } 431 break; 432 433 case EVEX_T1F: 434 case EVEX_T2: 435 case EVEX_T4: 436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0; 437 break; 438 439 case EVEX_T8: 440 break; 441 442 case EVEX_HVM: 443 break; 444 445 case EVEX_QVM: 446 break; 447 448 case EVEX_OVM: 449 break; 450 451 case EVEX_M128: 452 break; 453 454 case EVEX_DUP: 455 break; 456 457 default: 458 assert(0, "no valid evex tuple_table entry"); 459 break; 460 } 461 462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) { 463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len]; 464 if ((disp % disp_factor) == 0) { 465 int new_disp = disp / disp_factor; 466 if (is8bit(new_disp)) { 467 disp = new_disp; 468 } 469 } else { 470 return false; 471 } 472 } 473 } 474 return is8bit(disp); 475 } 476 477 478 void Assembler::emit_operand(Register reg, Register base, Register index, 479 Address::ScaleFactor scale, int disp, 480 RelocationHolder const& rspec, 481 int rip_relative_correction) { 482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 483 484 // Encode the registers as needed in the fields they are used in 485 486 int regenc = encode(reg) << 3; 487 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 488 int baseenc = base->is_valid() ? encode(base) : 0; 489 490 if (base->is_valid()) { 491 if (index->is_valid()) { 492 assert(scale != Address::no_scale, "inconsistent address"); 493 // [base + index*scale + disp] 494 if (disp == 0 && rtype == relocInfo::none && 495 base != rbp LP64_ONLY(&& base != r13)) { 496 // [base + index*scale] 497 // [00 reg 100][ss index base] 498 assert(index != rsp, "illegal addressing mode"); 499 emit_int8(0x04 | regenc); 500 emit_int8(scale << 6 | indexenc | baseenc); 501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 502 // [base + index*scale + imm8] 503 // [01 reg 100][ss index base] imm8 504 assert(index != rsp, "illegal addressing mode"); 505 emit_int8(0x44 | regenc); 506 emit_int8(scale << 6 | indexenc | baseenc); 507 emit_int8(disp & 0xFF); 508 } else { 509 // [base + index*scale + disp32] 510 // [10 reg 100][ss index base] disp32 511 assert(index != rsp, "illegal addressing mode"); 512 emit_int8(0x84 | regenc); 513 emit_int8(scale << 6 | indexenc | baseenc); 514 emit_data(disp, rspec, disp32_operand); 515 } 516 } else if (base == rsp LP64_ONLY(|| base == r12)) { 517 // [rsp + disp] 518 if (disp == 0 && rtype == relocInfo::none) { 519 // [rsp] 520 // [00 reg 100][00 100 100] 521 emit_int8(0x04 | regenc); 522 emit_int8(0x24); 523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 524 // [rsp + imm8] 525 // [01 reg 100][00 100 100] disp8 526 emit_int8(0x44 | regenc); 527 emit_int8(0x24); 528 emit_int8(disp & 0xFF); 529 } else { 530 // [rsp + imm32] 531 // [10 reg 100][00 100 100] disp32 532 emit_int8(0x84 | regenc); 533 emit_int8(0x24); 534 emit_data(disp, rspec, disp32_operand); 535 } 536 } else { 537 // [base + disp] 538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 539 if (disp == 0 && rtype == relocInfo::none && 540 base != rbp LP64_ONLY(&& base != r13)) { 541 // [base] 542 // [00 reg base] 543 emit_int8(0x00 | regenc | baseenc); 544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 545 // [base + disp8] 546 // [01 reg base] disp8 547 emit_int8(0x40 | regenc | baseenc); 548 emit_int8(disp & 0xFF); 549 } else { 550 // [base + disp32] 551 // [10 reg base] disp32 552 emit_int8(0x80 | regenc | baseenc); 553 emit_data(disp, rspec, disp32_operand); 554 } 555 } 556 } else { 557 if (index->is_valid()) { 558 assert(scale != Address::no_scale, "inconsistent address"); 559 // [index*scale + disp] 560 // [00 reg 100][ss index 101] disp32 561 assert(index != rsp, "illegal addressing mode"); 562 emit_int8(0x04 | regenc); 563 emit_int8(scale << 6 | indexenc | 0x05); 564 emit_data(disp, rspec, disp32_operand); 565 } else if (rtype != relocInfo::none ) { 566 // [disp] (64bit) RIP-RELATIVE (32bit) abs 567 // [00 000 101] disp32 568 569 emit_int8(0x05 | regenc); 570 // Note that the RIP-rel. correction applies to the generated 571 // disp field, but _not_ to the target address in the rspec. 572 573 // disp was created by converting the target address minus the pc 574 // at the start of the instruction. That needs more correction here. 575 // intptr_t disp = target - next_ip; 576 assert(inst_mark() != NULL, "must be inside InstructionMark"); 577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 578 int64_t adjusted = disp; 579 // Do rip-rel adjustment for 64bit 580 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 581 assert(is_simm32(adjusted), 582 "must be 32bit offset (RIP relative address)"); 583 emit_data((int32_t) adjusted, rspec, disp32_operand); 584 585 } else { 586 // 32bit never did this, did everything as the rip-rel/disp code above 587 // [disp] ABSOLUTE 588 // [00 reg 100][00 100 101] disp32 589 emit_int8(0x04 | regenc); 590 emit_int8(0x25); 591 emit_data(disp, rspec, disp32_operand); 592 } 593 } 594 is_evex_instruction = false; 595 } 596 597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 598 Address::ScaleFactor scale, int disp, 599 RelocationHolder const& rspec) { 600 if (UseAVX > 2) { 601 int xreg_enc = reg->encoding(); 602 if (xreg_enc > 15) { 603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 604 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 605 return; 606 } 607 } 608 emit_operand((Register)reg, base, index, scale, disp, rspec); 609 } 610 611 // Secret local extension to Assembler::WhichOperand: 612 #define end_pc_operand (_WhichOperand_limit) 613 614 address Assembler::locate_operand(address inst, WhichOperand which) { 615 // Decode the given instruction, and return the address of 616 // an embedded 32-bit operand word. 617 618 // If "which" is disp32_operand, selects the displacement portion 619 // of an effective address specifier. 620 // If "which" is imm64_operand, selects the trailing immediate constant. 621 // If "which" is call32_operand, selects the displacement of a call or jump. 622 // Caller is responsible for ensuring that there is such an operand, 623 // and that it is 32/64 bits wide. 624 625 // If "which" is end_pc_operand, find the end of the instruction. 626 627 address ip = inst; 628 bool is_64bit = false; 629 630 debug_only(bool has_disp32 = false); 631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 632 633 again_after_prefix: 634 switch (0xFF & *ip++) { 635 636 // These convenience macros generate groups of "case" labels for the switch. 637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 639 case (x)+4: case (x)+5: case (x)+6: case (x)+7 640 #define REP16(x) REP8((x)+0): \ 641 case REP8((x)+8) 642 643 case CS_segment: 644 case SS_segment: 645 case DS_segment: 646 case ES_segment: 647 case FS_segment: 648 case GS_segment: 649 // Seems dubious 650 LP64_ONLY(assert(false, "shouldn't have that prefix")); 651 assert(ip == inst+1, "only one prefix allowed"); 652 goto again_after_prefix; 653 654 case 0x67: 655 case REX: 656 case REX_B: 657 case REX_X: 658 case REX_XB: 659 case REX_R: 660 case REX_RB: 661 case REX_RX: 662 case REX_RXB: 663 NOT_LP64(assert(false, "64bit prefixes")); 664 goto again_after_prefix; 665 666 case REX_W: 667 case REX_WB: 668 case REX_WX: 669 case REX_WXB: 670 case REX_WR: 671 case REX_WRB: 672 case REX_WRX: 673 case REX_WRXB: 674 NOT_LP64(assert(false, "64bit prefixes")); 675 is_64bit = true; 676 goto again_after_prefix; 677 678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 679 case 0x88: // movb a, r 680 case 0x89: // movl a, r 681 case 0x8A: // movb r, a 682 case 0x8B: // movl r, a 683 case 0x8F: // popl a 684 debug_only(has_disp32 = true); 685 break; 686 687 case 0x68: // pushq #32 688 if (which == end_pc_operand) { 689 return ip + 4; 690 } 691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 692 return ip; // not produced by emit_operand 693 694 case 0x66: // movw ... (size prefix) 695 again_after_size_prefix2: 696 switch (0xFF & *ip++) { 697 case REX: 698 case REX_B: 699 case REX_X: 700 case REX_XB: 701 case REX_R: 702 case REX_RB: 703 case REX_RX: 704 case REX_RXB: 705 case REX_W: 706 case REX_WB: 707 case REX_WX: 708 case REX_WXB: 709 case REX_WR: 710 case REX_WRB: 711 case REX_WRX: 712 case REX_WRXB: 713 NOT_LP64(assert(false, "64bit prefix found")); 714 goto again_after_size_prefix2; 715 case 0x8B: // movw r, a 716 case 0x89: // movw a, r 717 debug_only(has_disp32 = true); 718 break; 719 case 0xC7: // movw a, #16 720 debug_only(has_disp32 = true); 721 tail_size = 2; // the imm16 722 break; 723 case 0x0F: // several SSE/SSE2 variants 724 ip--; // reparse the 0x0F 725 goto again_after_prefix; 726 default: 727 ShouldNotReachHere(); 728 } 729 break; 730 731 case REP8(0xB8): // movl/q r, #32/#64(oop?) 732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 733 // these asserts are somewhat nonsensical 734 #ifndef _LP64 735 assert(which == imm_operand || which == disp32_operand, 736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))); 737 #else 738 assert((which == call32_operand || which == imm_operand) && is_64bit || 739 which == narrow_oop_operand && !is_64bit, 740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))); 741 #endif // _LP64 742 return ip; 743 744 case 0x69: // imul r, a, #32 745 case 0xC7: // movl a, #32(oop?) 746 tail_size = 4; 747 debug_only(has_disp32 = true); // has both kinds of operands! 748 break; 749 750 case 0x0F: // movx..., etc. 751 switch (0xFF & *ip++) { 752 case 0x3A: // pcmpestri 753 tail_size = 1; 754 case 0x38: // ptest, pmovzxbw 755 ip++; // skip opcode 756 debug_only(has_disp32 = true); // has both kinds of operands! 757 break; 758 759 case 0x70: // pshufd r, r/a, #8 760 debug_only(has_disp32 = true); // has both kinds of operands! 761 case 0x73: // psrldq r, #8 762 tail_size = 1; 763 break; 764 765 case 0x12: // movlps 766 case 0x28: // movaps 767 case 0x2E: // ucomiss 768 case 0x2F: // comiss 769 case 0x54: // andps 770 case 0x55: // andnps 771 case 0x56: // orps 772 case 0x57: // xorps 773 case 0x6E: // movd 774 case 0x7E: // movd 775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 776 debug_only(has_disp32 = true); 777 break; 778 779 case 0xAD: // shrd r, a, %cl 780 case 0xAF: // imul r, a 781 case 0xBE: // movsbl r, a (movsxb) 782 case 0xBF: // movswl r, a (movsxw) 783 case 0xB6: // movzbl r, a (movzxb) 784 case 0xB7: // movzwl r, a (movzxw) 785 case REP16(0x40): // cmovl cc, r, a 786 case 0xB0: // cmpxchgb 787 case 0xB1: // cmpxchg 788 case 0xC1: // xaddl 789 case 0xC7: // cmpxchg8 790 case REP16(0x90): // setcc a 791 debug_only(has_disp32 = true); 792 // fall out of the switch to decode the address 793 break; 794 795 case 0xC4: // pinsrw r, a, #8 796 debug_only(has_disp32 = true); 797 case 0xC5: // pextrw r, r, #8 798 tail_size = 1; // the imm8 799 break; 800 801 case 0xAC: // shrd r, a, #8 802 debug_only(has_disp32 = true); 803 tail_size = 1; // the imm8 804 break; 805 806 case REP16(0x80): // jcc rdisp32 807 if (which == end_pc_operand) return ip + 4; 808 assert(which == call32_operand, "jcc has no disp32 or imm"); 809 return ip; 810 default: 811 ShouldNotReachHere(); 812 } 813 break; 814 815 case 0x81: // addl a, #32; addl r, #32 816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 817 // on 32bit in the case of cmpl, the imm might be an oop 818 tail_size = 4; 819 debug_only(has_disp32 = true); // has both kinds of operands! 820 break; 821 822 case 0x83: // addl a, #8; addl r, #8 823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 824 debug_only(has_disp32 = true); // has both kinds of operands! 825 tail_size = 1; 826 break; 827 828 case 0x9B: 829 switch (0xFF & *ip++) { 830 case 0xD9: // fnstcw a 831 debug_only(has_disp32 = true); 832 break; 833 default: 834 ShouldNotReachHere(); 835 } 836 break; 837 838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 839 case REP4(0x10): // adc... 840 case REP4(0x20): // and... 841 case REP4(0x30): // xor... 842 case REP4(0x08): // or... 843 case REP4(0x18): // sbb... 844 case REP4(0x28): // sub... 845 case 0xF7: // mull a 846 case 0x8D: // lea r, a 847 case 0x87: // xchg r, a 848 case REP4(0x38): // cmp... 849 case 0x85: // test r, a 850 debug_only(has_disp32 = true); // has both kinds of operands! 851 break; 852 853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 854 case 0xC6: // movb a, #8 855 case 0x80: // cmpb a, #8 856 case 0x6B: // imul r, a, #8 857 debug_only(has_disp32 = true); // has both kinds of operands! 858 tail_size = 1; // the imm8 859 break; 860 861 case 0xC4: // VEX_3bytes 862 case 0xC5: // VEX_2bytes 863 assert((UseAVX > 0), "shouldn't have VEX prefix"); 864 assert(ip == inst+1, "no prefixes allowed"); 865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 866 // but they have prefix 0x0F and processed when 0x0F processed above. 867 // 868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 869 // instructions (these instructions are not supported in 64-bit mode). 870 // To distinguish them bits [7:6] are set in the VEX second byte since 871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 872 // those VEX bits REX and vvvv bits are inverted. 873 // 874 // Fortunately C2 doesn't generate these instructions so we don't need 875 // to check for them in product version. 876 877 // Check second byte 878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 879 880 // First byte 881 if ((0xFF & *inst) == VEX_3bytes) { 882 ip++; // third byte 883 is_64bit = ((VEX_W & *ip) == VEX_W); 884 } 885 ip++; // opcode 886 // To find the end of instruction (which == end_pc_operand). 887 switch (0xFF & *ip) { 888 case 0x61: // pcmpestri r, r/a, #8 889 case 0x70: // pshufd r, r/a, #8 890 case 0x73: // psrldq r, #8 891 tail_size = 1; // the imm8 892 break; 893 default: 894 break; 895 } 896 ip++; // skip opcode 897 debug_only(has_disp32 = true); // has both kinds of operands! 898 break; 899 900 case 0x62: // EVEX_4bytes 901 assert((UseAVX > 0), "shouldn't have EVEX prefix"); 902 assert(ip == inst+1, "no prefixes allowed"); 903 // no EVEX collisions, all instructions that have 0x62 opcodes 904 // have EVEX versions and are subopcodes of 0x66 905 ip++; // skip P0 and exmaine W in P1 906 is_64bit = ((VEX_W & *ip) == VEX_W); 907 ip++; // move to P2 908 ip++; // skip P2, move to opcode 909 // To find the end of instruction (which == end_pc_operand). 910 switch (0xFF & *ip) { 911 case 0x61: // pcmpestri r, r/a, #8 912 case 0x70: // pshufd r, r/a, #8 913 case 0x73: // psrldq r, #8 914 tail_size = 1; // the imm8 915 break; 916 default: 917 break; 918 } 919 ip++; // skip opcode 920 debug_only(has_disp32 = true); // has both kinds of operands! 921 break; 922 923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 926 case 0xDD: // fld_d a; fst_d a; fstp_d a 927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 928 case 0xDF: // fild_d a; fistp_d a 929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 932 debug_only(has_disp32 = true); 933 break; 934 935 case 0xE8: // call rdisp32 936 case 0xE9: // jmp rdisp32 937 if (which == end_pc_operand) return ip + 4; 938 assert(which == call32_operand, "call has no disp32 or imm"); 939 return ip; 940 941 case 0xF0: // Lock 942 assert(os::is_MP(), "only on MP"); 943 goto again_after_prefix; 944 945 case 0xF3: // For SSE 946 case 0xF2: // For SSE2 947 switch (0xFF & *ip++) { 948 case REX: 949 case REX_B: 950 case REX_X: 951 case REX_XB: 952 case REX_R: 953 case REX_RB: 954 case REX_RX: 955 case REX_RXB: 956 case REX_W: 957 case REX_WB: 958 case REX_WX: 959 case REX_WXB: 960 case REX_WR: 961 case REX_WRB: 962 case REX_WRX: 963 case REX_WRXB: 964 NOT_LP64(assert(false, "found 64bit prefix")); 965 ip++; 966 default: 967 ip++; 968 } 969 debug_only(has_disp32 = true); // has both kinds of operands! 970 break; 971 972 default: 973 ShouldNotReachHere(); 974 975 #undef REP8 976 #undef REP16 977 } 978 979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 980 #ifdef _LP64 981 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 982 #else 983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 985 #endif // LP64 986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 987 988 // parse the output of emit_operand 989 int op2 = 0xFF & *ip++; 990 int base = op2 & 0x07; 991 int op3 = -1; 992 const int b100 = 4; 993 const int b101 = 5; 994 if (base == b100 && (op2 >> 6) != 3) { 995 op3 = 0xFF & *ip++; 996 base = op3 & 0x07; // refetch the base 997 } 998 // now ip points at the disp (if any) 999 1000 switch (op2 >> 6) { 1001 case 0: 1002 // [00 reg 100][ss index base] 1003 // [00 reg 100][00 100 esp] 1004 // [00 reg base] 1005 // [00 reg 100][ss index 101][disp32] 1006 // [00 reg 101] [disp32] 1007 1008 if (base == b101) { 1009 if (which == disp32_operand) 1010 return ip; // caller wants the disp32 1011 ip += 4; // skip the disp32 1012 } 1013 break; 1014 1015 case 1: 1016 // [01 reg 100][ss index base][disp8] 1017 // [01 reg 100][00 100 esp][disp8] 1018 // [01 reg base] [disp8] 1019 ip += 1; // skip the disp8 1020 break; 1021 1022 case 2: 1023 // [10 reg 100][ss index base][disp32] 1024 // [10 reg 100][00 100 esp][disp32] 1025 // [10 reg base] [disp32] 1026 if (which == disp32_operand) 1027 return ip; // caller wants the disp32 1028 ip += 4; // skip the disp32 1029 break; 1030 1031 case 3: 1032 // [11 reg base] (not a memory addressing mode) 1033 break; 1034 } 1035 1036 if (which == end_pc_operand) { 1037 return ip + tail_size; 1038 } 1039 1040 #ifdef _LP64 1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1042 #else 1043 assert(which == imm_operand, "instruction has only an imm field"); 1044 #endif // LP64 1045 return ip; 1046 } 1047 1048 address Assembler::locate_next_instruction(address inst) { 1049 // Secretly share code with locate_operand: 1050 return locate_operand(inst, end_pc_operand); 1051 } 1052 1053 1054 #ifdef ASSERT 1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1056 address inst = inst_mark(); 1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1058 address opnd; 1059 1060 Relocation* r = rspec.reloc(); 1061 if (r->type() == relocInfo::none) { 1062 return; 1063 } else if (r->is_call() || format == call32_operand) { 1064 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1065 opnd = locate_operand(inst, call32_operand); 1066 } else if (r->is_data()) { 1067 assert(format == imm_operand || format == disp32_operand 1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1069 opnd = locate_operand(inst, (WhichOperand)format); 1070 } else { 1071 assert(format == imm_operand, "cannot specify a format"); 1072 return; 1073 } 1074 assert(opnd == pc(), "must put operand where relocs can find it"); 1075 } 1076 #endif // ASSERT 1077 1078 void Assembler::emit_operand32(Register reg, Address adr) { 1079 assert(reg->encoding() < 8, "no extended registers"); 1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1082 adr._rspec); 1083 } 1084 1085 void Assembler::emit_operand(Register reg, Address adr, 1086 int rip_relative_correction) { 1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1088 adr._rspec, 1089 rip_relative_correction); 1090 } 1091 1092 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1094 adr._rspec); 1095 } 1096 1097 // MMX operations 1098 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1101 } 1102 1103 // work around gcc (3.2.1-7a) bug 1104 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1107 } 1108 1109 1110 void Assembler::emit_farith(int b1, int b2, int i) { 1111 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1112 assert(0 <= i && i < 8, "illegal stack offset"); 1113 emit_int8(b1); 1114 emit_int8(b2 + i); 1115 } 1116 1117 1118 // Now the Assembler instructions (identical for 32/64 bits) 1119 1120 void Assembler::adcl(Address dst, int32_t imm32) { 1121 InstructionMark im(this); 1122 prefix(dst); 1123 emit_arith_operand(0x81, rdx, dst, imm32); 1124 } 1125 1126 void Assembler::adcl(Address dst, Register src) { 1127 InstructionMark im(this); 1128 prefix(dst, src); 1129 emit_int8(0x11); 1130 emit_operand(src, dst); 1131 } 1132 1133 void Assembler::adcl(Register dst, int32_t imm32) { 1134 prefix(dst); 1135 emit_arith(0x81, 0xD0, dst, imm32); 1136 } 1137 1138 void Assembler::adcl(Register dst, Address src) { 1139 InstructionMark im(this); 1140 prefix(src, dst); 1141 emit_int8(0x13); 1142 emit_operand(dst, src); 1143 } 1144 1145 void Assembler::adcl(Register dst, Register src) { 1146 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1147 emit_arith(0x13, 0xC0, dst, src); 1148 } 1149 1150 void Assembler::addl(Address dst, int32_t imm32) { 1151 InstructionMark im(this); 1152 prefix(dst); 1153 emit_arith_operand(0x81, rax, dst, imm32); 1154 } 1155 1156 void Assembler::addl(Address dst, Register src) { 1157 InstructionMark im(this); 1158 prefix(dst, src); 1159 emit_int8(0x01); 1160 emit_operand(src, dst); 1161 } 1162 1163 void Assembler::addl(Register dst, int32_t imm32) { 1164 prefix(dst); 1165 emit_arith(0x81, 0xC0, dst, imm32); 1166 } 1167 1168 void Assembler::addl(Register dst, Address src) { 1169 InstructionMark im(this); 1170 prefix(src, dst); 1171 emit_int8(0x03); 1172 emit_operand(dst, src); 1173 } 1174 1175 void Assembler::addl(Register dst, Register src) { 1176 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1177 emit_arith(0x03, 0xC0, dst, src); 1178 } 1179 1180 void Assembler::addr_nop_4() { 1181 assert(UseAddressNop, "no CPU support"); 1182 // 4 bytes: NOP DWORD PTR [EAX+0] 1183 emit_int8(0x0F); 1184 emit_int8(0x1F); 1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1186 emit_int8(0); // 8-bits offset (1 byte) 1187 } 1188 1189 void Assembler::addr_nop_5() { 1190 assert(UseAddressNop, "no CPU support"); 1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1192 emit_int8(0x0F); 1193 emit_int8(0x1F); 1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1196 emit_int8(0); // 8-bits offset (1 byte) 1197 } 1198 1199 void Assembler::addr_nop_7() { 1200 assert(UseAddressNop, "no CPU support"); 1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1202 emit_int8(0x0F); 1203 emit_int8(0x1F); 1204 emit_int8((unsigned char)0x80); 1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1206 emit_int32(0); // 32-bits offset (4 bytes) 1207 } 1208 1209 void Assembler::addr_nop_8() { 1210 assert(UseAddressNop, "no CPU support"); 1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1212 emit_int8(0x0F); 1213 emit_int8(0x1F); 1214 emit_int8((unsigned char)0x84); 1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1217 emit_int32(0); // 32-bits offset (4 bytes) 1218 } 1219 1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1221 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1222 if (VM_Version::supports_evex()) { 1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2); 1224 } else { 1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); 1226 } 1227 } 1228 1229 void Assembler::addsd(XMMRegister dst, Address src) { 1230 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1231 if (VM_Version::supports_evex()) { 1232 tuple_type = EVEX_T1S; 1233 input_size_in_bits = EVEX_64bit; 1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2); 1235 } else { 1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); 1237 } 1238 } 1239 1240 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1241 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); 1243 } 1244 1245 void Assembler::addss(XMMRegister dst, Address src) { 1246 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1247 if (VM_Version::supports_evex()) { 1248 tuple_type = EVEX_T1S; 1249 input_size_in_bits = EVEX_32bit; 1250 } 1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); 1252 } 1253 1254 void Assembler::aesdec(XMMRegister dst, Address src) { 1255 assert(VM_Version::supports_aes(), ""); 1256 InstructionMark im(this); 1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false, 1258 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1259 emit_int8((unsigned char)0xDE); 1260 emit_operand(dst, src); 1261 } 1262 1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1264 assert(VM_Version::supports_aes(), ""); 1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 1266 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1267 emit_int8((unsigned char)0xDE); 1268 emit_int8(0xC0 | encode); 1269 } 1270 1271 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1272 assert(VM_Version::supports_aes(), ""); 1273 InstructionMark im(this); 1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false, 1275 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1276 emit_int8((unsigned char)0xDF); 1277 emit_operand(dst, src); 1278 } 1279 1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1281 assert(VM_Version::supports_aes(), ""); 1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 1283 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1284 emit_int8((unsigned char)0xDF); 1285 emit_int8((unsigned char)(0xC0 | encode)); 1286 } 1287 1288 void Assembler::aesenc(XMMRegister dst, Address src) { 1289 assert(VM_Version::supports_aes(), ""); 1290 InstructionMark im(this); 1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false, 1292 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1293 emit_int8((unsigned char)0xDC); 1294 emit_operand(dst, src); 1295 } 1296 1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1298 assert(VM_Version::supports_aes(), ""); 1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 1300 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1301 emit_int8((unsigned char)0xDC); 1302 emit_int8(0xC0 | encode); 1303 } 1304 1305 void Assembler::aesenclast(XMMRegister dst, Address src) { 1306 assert(VM_Version::supports_aes(), ""); 1307 InstructionMark im(this); 1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false, 1309 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1310 emit_int8((unsigned char)0xDD); 1311 emit_operand(dst, src); 1312 } 1313 1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1315 assert(VM_Version::supports_aes(), ""); 1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 1317 VEX_OPCODE_0F_38, false, AVX_128bit, true); 1318 emit_int8((unsigned char)0xDD); 1319 emit_int8((unsigned char)(0xC0 | encode)); 1320 } 1321 1322 1323 void Assembler::andl(Address dst, int32_t imm32) { 1324 InstructionMark im(this); 1325 prefix(dst); 1326 emit_int8((unsigned char)0x81); 1327 emit_operand(rsp, dst, 4); 1328 emit_int32(imm32); 1329 } 1330 1331 void Assembler::andl(Register dst, int32_t imm32) { 1332 prefix(dst); 1333 emit_arith(0x81, 0xE0, dst, imm32); 1334 } 1335 1336 void Assembler::andl(Register dst, Address src) { 1337 InstructionMark im(this); 1338 prefix(src, dst); 1339 emit_int8(0x23); 1340 emit_operand(dst, src); 1341 } 1342 1343 void Assembler::andl(Register dst, Register src) { 1344 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1345 emit_arith(0x23, 0xC0, dst, src); 1346 } 1347 1348 void Assembler::andnl(Register dst, Register src1, Register src2) { 1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1350 int encode = vex_prefix_0F38_and_encode(dst, src1, src2, false); 1351 emit_int8((unsigned char)0xF2); 1352 emit_int8((unsigned char)(0xC0 | encode)); 1353 } 1354 1355 void Assembler::andnl(Register dst, Register src1, Address src2) { 1356 InstructionMark im(this); 1357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1358 vex_prefix_0F38(dst, src1, src2, false); 1359 emit_int8((unsigned char)0xF2); 1360 emit_operand(dst, src2); 1361 } 1362 1363 void Assembler::bsfl(Register dst, Register src) { 1364 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1365 emit_int8(0x0F); 1366 emit_int8((unsigned char)0xBC); 1367 emit_int8((unsigned char)(0xC0 | encode)); 1368 } 1369 1370 void Assembler::bsrl(Register dst, Register src) { 1371 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1372 emit_int8(0x0F); 1373 emit_int8((unsigned char)0xBD); 1374 emit_int8((unsigned char)(0xC0 | encode)); 1375 } 1376 1377 void Assembler::bswapl(Register reg) { // bswap 1378 int encode = prefix_and_encode(reg->encoding()); 1379 emit_int8(0x0F); 1380 emit_int8((unsigned char)(0xC8 | encode)); 1381 } 1382 1383 void Assembler::blsil(Register dst, Register src) { 1384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1385 int encode = vex_prefix_0F38_and_encode(rbx, dst, src, false); 1386 emit_int8((unsigned char)0xF3); 1387 emit_int8((unsigned char)(0xC0 | encode)); 1388 } 1389 1390 void Assembler::blsil(Register dst, Address src) { 1391 InstructionMark im(this); 1392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1393 vex_prefix_0F38(rbx, dst, src, false); 1394 emit_int8((unsigned char)0xF3); 1395 emit_operand(rbx, src); 1396 } 1397 1398 void Assembler::blsmskl(Register dst, Register src) { 1399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1400 int encode = vex_prefix_0F38_and_encode(rdx, dst, src, false); 1401 emit_int8((unsigned char)0xF3); 1402 emit_int8((unsigned char)(0xC0 | encode)); 1403 } 1404 1405 void Assembler::blsmskl(Register dst, Address src) { 1406 InstructionMark im(this); 1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1408 vex_prefix_0F38(rdx, dst, src, false); 1409 emit_int8((unsigned char)0xF3); 1410 emit_operand(rdx, src); 1411 } 1412 1413 void Assembler::blsrl(Register dst, Register src) { 1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1415 int encode = vex_prefix_0F38_and_encode(rcx, dst, src, false); 1416 emit_int8((unsigned char)0xF3); 1417 emit_int8((unsigned char)(0xC0 | encode)); 1418 } 1419 1420 void Assembler::blsrl(Register dst, Address src) { 1421 InstructionMark im(this); 1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1423 vex_prefix_0F38(rcx, dst, src, false); 1424 emit_int8((unsigned char)0xF3); 1425 emit_operand(rcx, src); 1426 } 1427 1428 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1429 // suspect disp32 is always good 1430 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1431 1432 if (L.is_bound()) { 1433 const int long_size = 5; 1434 int offs = (int)( target(L) - pc() ); 1435 assert(offs <= 0, "assembler error"); 1436 InstructionMark im(this); 1437 // 1110 1000 #32-bit disp 1438 emit_int8((unsigned char)0xE8); 1439 emit_data(offs - long_size, rtype, operand); 1440 } else { 1441 InstructionMark im(this); 1442 // 1110 1000 #32-bit disp 1443 L.add_patch_at(code(), locator()); 1444 1445 emit_int8((unsigned char)0xE8); 1446 emit_data(int(0), rtype, operand); 1447 } 1448 } 1449 1450 void Assembler::call(Register dst) { 1451 int encode = prefix_and_encode(dst->encoding()); 1452 emit_int8((unsigned char)0xFF); 1453 emit_int8((unsigned char)(0xD0 | encode)); 1454 } 1455 1456 1457 void Assembler::call(Address adr) { 1458 InstructionMark im(this); 1459 prefix(adr); 1460 emit_int8((unsigned char)0xFF); 1461 emit_operand(rdx, adr); 1462 } 1463 1464 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1465 assert(entry != NULL, "call most probably wrong"); 1466 InstructionMark im(this); 1467 emit_int8((unsigned char)0xE8); 1468 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1469 assert(is_simm32(disp), "must be 32bit offset (call2)"); 1470 // Technically, should use call32_operand, but this format is 1471 // implied by the fact that we're emitting a call instruction. 1472 1473 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1474 emit_data((int) disp, rspec, operand); 1475 } 1476 1477 void Assembler::cdql() { 1478 emit_int8((unsigned char)0x99); 1479 } 1480 1481 void Assembler::cld() { 1482 emit_int8((unsigned char)0xFC); 1483 } 1484 1485 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1486 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1487 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1488 emit_int8(0x0F); 1489 emit_int8(0x40 | cc); 1490 emit_int8((unsigned char)(0xC0 | encode)); 1491 } 1492 1493 1494 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1495 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1496 prefix(src, dst); 1497 emit_int8(0x0F); 1498 emit_int8(0x40 | cc); 1499 emit_operand(dst, src); 1500 } 1501 1502 void Assembler::cmpb(Address dst, int imm8) { 1503 InstructionMark im(this); 1504 prefix(dst); 1505 emit_int8((unsigned char)0x80); 1506 emit_operand(rdi, dst, 1); 1507 emit_int8(imm8); 1508 } 1509 1510 void Assembler::cmpl(Address dst, int32_t imm32) { 1511 InstructionMark im(this); 1512 prefix(dst); 1513 emit_int8((unsigned char)0x81); 1514 emit_operand(rdi, dst, 4); 1515 emit_int32(imm32); 1516 } 1517 1518 void Assembler::cmpl(Register dst, int32_t imm32) { 1519 prefix(dst); 1520 emit_arith(0x81, 0xF8, dst, imm32); 1521 } 1522 1523 void Assembler::cmpl(Register dst, Register src) { 1524 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1525 emit_arith(0x3B, 0xC0, dst, src); 1526 } 1527 1528 1529 void Assembler::cmpl(Register dst, Address src) { 1530 InstructionMark im(this); 1531 prefix(src, dst); 1532 emit_int8((unsigned char)0x3B); 1533 emit_operand(dst, src); 1534 } 1535 1536 void Assembler::cmpw(Address dst, int imm16) { 1537 InstructionMark im(this); 1538 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1539 emit_int8(0x66); 1540 emit_int8((unsigned char)0x81); 1541 emit_operand(rdi, dst, 2); 1542 emit_int16(imm16); 1543 } 1544 1545 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1546 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1547 // The ZF is set if the compared values were equal, and cleared otherwise. 1548 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1549 InstructionMark im(this); 1550 prefix(adr, reg); 1551 emit_int8(0x0F); 1552 emit_int8((unsigned char)0xB1); 1553 emit_operand(reg, adr); 1554 } 1555 1556 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1557 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1558 // The ZF is set if the compared values were equal, and cleared otherwise. 1559 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1560 InstructionMark im(this); 1561 prefix(adr, reg, true); 1562 emit_int8(0x0F); 1563 emit_int8((unsigned char)0xB0); 1564 emit_operand(reg, adr); 1565 } 1566 1567 void Assembler::comisd(XMMRegister dst, Address src) { 1568 // NOTE: dbx seems to decode this as comiss even though the 1569 // 0x66 is there. Strangly ucomisd comes out correct 1570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1571 if (VM_Version::supports_evex()) { 1572 tuple_type = EVEX_T1S; 1573 input_size_in_bits = EVEX_64bit; 1574 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true); 1575 } else { 1576 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); 1577 } 1578 } 1579 1580 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1581 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1582 if (VM_Version::supports_evex()) { 1583 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true); 1584 } else { 1585 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); 1586 } 1587 } 1588 1589 void Assembler::comiss(XMMRegister dst, Address src) { 1590 if (VM_Version::supports_evex()) { 1591 tuple_type = EVEX_T1S; 1592 input_size_in_bits = EVEX_32bit; 1593 } 1594 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1595 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true); 1596 } 1597 1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1599 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1600 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true); 1601 } 1602 1603 void Assembler::cpuid() { 1604 emit_int8(0x0F); 1605 emit_int8((unsigned char)0xA2); 1606 } 1607 1608 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1609 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1610 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); 1611 } 1612 1613 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1615 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); 1616 } 1617 1618 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1619 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1620 if (VM_Version::supports_evex()) { 1621 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2); 1622 } else { 1623 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); 1624 } 1625 } 1626 1627 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1629 if (VM_Version::supports_evex()) { 1630 tuple_type = EVEX_T1F; 1631 input_size_in_bits = EVEX_64bit; 1632 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2); 1633 } else { 1634 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); 1635 } 1636 } 1637 1638 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1640 int encode = 0; 1641 if (VM_Version::supports_evex()) { 1642 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true); 1643 } else { 1644 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false); 1645 } 1646 emit_int8(0x2A); 1647 emit_int8((unsigned char)(0xC0 | encode)); 1648 } 1649 1650 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1651 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1652 if (VM_Version::supports_evex()) { 1653 tuple_type = EVEX_T1S; 1654 input_size_in_bits = EVEX_32bit; 1655 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true); 1656 } else { 1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); 1658 } 1659 } 1660 1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1662 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true); 1664 emit_int8(0x2A); 1665 emit_int8((unsigned char)(0xC0 | encode)); 1666 } 1667 1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1669 if (VM_Version::supports_evex()) { 1670 tuple_type = EVEX_T1S; 1671 input_size_in_bits = EVEX_32bit; 1672 } 1673 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true); 1675 } 1676 1677 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1678 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1679 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); 1680 } 1681 1682 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1683 if (VM_Version::supports_evex()) { 1684 tuple_type = EVEX_T1S; 1685 input_size_in_bits = EVEX_32bit; 1686 } 1687 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1688 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); 1689 } 1690 1691 1692 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1693 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1694 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true); 1695 emit_int8(0x2C); 1696 emit_int8((unsigned char)(0xC0 | encode)); 1697 } 1698 1699 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1700 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1701 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true); 1702 emit_int8(0x2C); 1703 emit_int8((unsigned char)(0xC0 | encode)); 1704 } 1705 1706 void Assembler::decl(Address dst) { 1707 // Don't use it directly. Use MacroAssembler::decrement() instead. 1708 InstructionMark im(this); 1709 prefix(dst); 1710 emit_int8((unsigned char)0xFF); 1711 emit_operand(rcx, dst); 1712 } 1713 1714 void Assembler::divsd(XMMRegister dst, Address src) { 1715 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1716 if (VM_Version::supports_evex()) { 1717 tuple_type = EVEX_T1S; 1718 input_size_in_bits = EVEX_64bit; 1719 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2); 1720 } else { 1721 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); 1722 } 1723 } 1724 1725 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1726 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1727 if (VM_Version::supports_evex()) { 1728 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2); 1729 } else { 1730 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); 1731 } 1732 } 1733 1734 void Assembler::divss(XMMRegister dst, Address src) { 1735 if (VM_Version::supports_evex()) { 1736 tuple_type = EVEX_T1S; 1737 input_size_in_bits = EVEX_32bit; 1738 } 1739 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1740 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); 1741 } 1742 1743 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1744 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1745 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); 1746 } 1747 1748 void Assembler::emms() { 1749 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1750 emit_int8(0x0F); 1751 emit_int8(0x77); 1752 } 1753 1754 void Assembler::hlt() { 1755 emit_int8((unsigned char)0xF4); 1756 } 1757 1758 void Assembler::idivl(Register src) { 1759 int encode = prefix_and_encode(src->encoding()); 1760 emit_int8((unsigned char)0xF7); 1761 emit_int8((unsigned char)(0xF8 | encode)); 1762 } 1763 1764 void Assembler::divl(Register src) { // Unsigned 1765 int encode = prefix_and_encode(src->encoding()); 1766 emit_int8((unsigned char)0xF7); 1767 emit_int8((unsigned char)(0xF0 | encode)); 1768 } 1769 1770 void Assembler::imull(Register dst, Register src) { 1771 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1772 emit_int8(0x0F); 1773 emit_int8((unsigned char)0xAF); 1774 emit_int8((unsigned char)(0xC0 | encode)); 1775 } 1776 1777 1778 void Assembler::imull(Register dst, Register src, int value) { 1779 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1780 if (is8bit(value)) { 1781 emit_int8(0x6B); 1782 emit_int8((unsigned char)(0xC0 | encode)); 1783 emit_int8(value & 0xFF); 1784 } else { 1785 emit_int8(0x69); 1786 emit_int8((unsigned char)(0xC0 | encode)); 1787 emit_int32(value); 1788 } 1789 } 1790 1791 void Assembler::imull(Register dst, Address src) { 1792 InstructionMark im(this); 1793 prefix(src, dst); 1794 emit_int8(0x0F); 1795 emit_int8((unsigned char) 0xAF); 1796 emit_operand(dst, src); 1797 } 1798 1799 1800 void Assembler::incl(Address dst) { 1801 // Don't use it directly. Use MacroAssembler::increment() instead. 1802 InstructionMark im(this); 1803 prefix(dst); 1804 emit_int8((unsigned char)0xFF); 1805 emit_operand(rax, dst); 1806 } 1807 1808 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 1809 InstructionMark im(this); 1810 assert((0 <= cc) && (cc < 16), "illegal cc"); 1811 if (L.is_bound()) { 1812 address dst = target(L); 1813 assert(dst != NULL, "jcc most probably wrong"); 1814 1815 const int short_size = 2; 1816 const int long_size = 6; 1817 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 1818 if (maybe_short && is8bit(offs - short_size)) { 1819 // 0111 tttn #8-bit disp 1820 emit_int8(0x70 | cc); 1821 emit_int8((offs - short_size) & 0xFF); 1822 } else { 1823 // 0000 1111 1000 tttn #32-bit disp 1824 assert(is_simm32(offs - long_size), 1825 "must be 32bit offset (call4)"); 1826 emit_int8(0x0F); 1827 emit_int8((unsigned char)(0x80 | cc)); 1828 emit_int32(offs - long_size); 1829 } 1830 } else { 1831 // Note: could eliminate cond. jumps to this jump if condition 1832 // is the same however, seems to be rather unlikely case. 1833 // Note: use jccb() if label to be bound is very close to get 1834 // an 8-bit displacement 1835 L.add_patch_at(code(), locator()); 1836 emit_int8(0x0F); 1837 emit_int8((unsigned char)(0x80 | cc)); 1838 emit_int32(0); 1839 } 1840 } 1841 1842 void Assembler::jccb(Condition cc, Label& L) { 1843 if (L.is_bound()) { 1844 const int short_size = 2; 1845 address entry = target(L); 1846 #ifdef ASSERT 1847 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 1848 intptr_t delta = short_branch_delta(); 1849 if (delta != 0) { 1850 dist += (dist < 0 ? (-delta) :delta); 1851 } 1852 assert(is8bit(dist), "Dispacement too large for a short jmp"); 1853 #endif 1854 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 1855 // 0111 tttn #8-bit disp 1856 emit_int8(0x70 | cc); 1857 emit_int8((offs - short_size) & 0xFF); 1858 } else { 1859 InstructionMark im(this); 1860 L.add_patch_at(code(), locator()); 1861 emit_int8(0x70 | cc); 1862 emit_int8(0); 1863 } 1864 } 1865 1866 void Assembler::jmp(Address adr) { 1867 InstructionMark im(this); 1868 prefix(adr); 1869 emit_int8((unsigned char)0xFF); 1870 emit_operand(rsp, adr); 1871 } 1872 1873 void Assembler::jmp(Label& L, bool maybe_short) { 1874 if (L.is_bound()) { 1875 address entry = target(L); 1876 assert(entry != NULL, "jmp most probably wrong"); 1877 InstructionMark im(this); 1878 const int short_size = 2; 1879 const int long_size = 5; 1880 intptr_t offs = entry - pc(); 1881 if (maybe_short && is8bit(offs - short_size)) { 1882 emit_int8((unsigned char)0xEB); 1883 emit_int8((offs - short_size) & 0xFF); 1884 } else { 1885 emit_int8((unsigned char)0xE9); 1886 emit_int32(offs - long_size); 1887 } 1888 } else { 1889 // By default, forward jumps are always 32-bit displacements, since 1890 // we can't yet know where the label will be bound. If you're sure that 1891 // the forward jump will not run beyond 256 bytes, use jmpb to 1892 // force an 8-bit displacement. 1893 InstructionMark im(this); 1894 L.add_patch_at(code(), locator()); 1895 emit_int8((unsigned char)0xE9); 1896 emit_int32(0); 1897 } 1898 } 1899 1900 void Assembler::jmp(Register entry) { 1901 int encode = prefix_and_encode(entry->encoding()); 1902 emit_int8((unsigned char)0xFF); 1903 emit_int8((unsigned char)(0xE0 | encode)); 1904 } 1905 1906 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 1907 InstructionMark im(this); 1908 emit_int8((unsigned char)0xE9); 1909 assert(dest != NULL, "must have a target"); 1910 intptr_t disp = dest - (pc() + sizeof(int32_t)); 1911 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 1912 emit_data(disp, rspec.reloc(), call32_operand); 1913 } 1914 1915 void Assembler::jmpb(Label& L) { 1916 if (L.is_bound()) { 1917 const int short_size = 2; 1918 address entry = target(L); 1919 assert(entry != NULL, "jmp most probably wrong"); 1920 #ifdef ASSERT 1921 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 1922 intptr_t delta = short_branch_delta(); 1923 if (delta != 0) { 1924 dist += (dist < 0 ? (-delta) :delta); 1925 } 1926 assert(is8bit(dist), "Dispacement too large for a short jmp"); 1927 #endif 1928 intptr_t offs = entry - pc(); 1929 emit_int8((unsigned char)0xEB); 1930 emit_int8((offs - short_size) & 0xFF); 1931 } else { 1932 InstructionMark im(this); 1933 L.add_patch_at(code(), locator()); 1934 emit_int8((unsigned char)0xEB); 1935 emit_int8(0); 1936 } 1937 } 1938 1939 void Assembler::ldmxcsr( Address src) { 1940 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1941 InstructionMark im(this); 1942 prefix(src); 1943 emit_int8(0x0F); 1944 emit_int8((unsigned char)0xAE); 1945 emit_operand(as_Register(2), src); 1946 } 1947 1948 void Assembler::leal(Register dst, Address src) { 1949 InstructionMark im(this); 1950 #ifdef _LP64 1951 emit_int8(0x67); // addr32 1952 prefix(src, dst); 1953 #endif // LP64 1954 emit_int8((unsigned char)0x8D); 1955 emit_operand(dst, src); 1956 } 1957 1958 void Assembler::lfence() { 1959 emit_int8(0x0F); 1960 emit_int8((unsigned char)0xAE); 1961 emit_int8((unsigned char)0xE8); 1962 } 1963 1964 void Assembler::lock() { 1965 emit_int8((unsigned char)0xF0); 1966 } 1967 1968 void Assembler::lzcntl(Register dst, Register src) { 1969 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 1970 emit_int8((unsigned char)0xF3); 1971 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1972 emit_int8(0x0F); 1973 emit_int8((unsigned char)0xBD); 1974 emit_int8((unsigned char)(0xC0 | encode)); 1975 } 1976 1977 // Emit mfence instruction 1978 void Assembler::mfence() { 1979 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 1980 emit_int8(0x0F); 1981 emit_int8((unsigned char)0xAE); 1982 emit_int8((unsigned char)0xF0); 1983 } 1984 1985 void Assembler::mov(Register dst, Register src) { 1986 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 1987 } 1988 1989 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 1990 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1991 if (VM_Version::supports_evex()) { 1992 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true); 1993 } else { 1994 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); 1995 } 1996 } 1997 1998 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 1999 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2000 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); 2001 } 2002 2003 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2004 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2005 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F, 2006 false, AVX_128bit); 2007 emit_int8(0x16); 2008 emit_int8((unsigned char)(0xC0 | encode)); 2009 } 2010 2011 void Assembler::movb(Register dst, Address src) { 2012 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2013 InstructionMark im(this); 2014 prefix(src, dst, true); 2015 emit_int8((unsigned char)0x8A); 2016 emit_operand(dst, src); 2017 } 2018 2019 void Assembler::kmovq(KRegister dst, KRegister src) { 2020 NOT_LP64(assert(VM_Version::supports_evex(), "")); 2021 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, 2022 true, VEX_OPCODE_0F, true); 2023 emit_int8((unsigned char)0x90); 2024 emit_int8((unsigned char)(0xC0 | encode)); 2025 } 2026 2027 void Assembler::kmovq(KRegister dst, Address src) { 2028 NOT_LP64(assert(VM_Version::supports_evex(), "")); 2029 int dst_enc = dst->encoding(); 2030 int nds_enc = 0; 2031 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE, 2032 VEX_OPCODE_0F, true, AVX_128bit, true, true); 2033 emit_int8((unsigned char)0x90); 2034 emit_operand((Register)dst, src); 2035 } 2036 2037 void Assembler::kmovq(Address dst, KRegister src) { 2038 NOT_LP64(assert(VM_Version::supports_evex(), "")); 2039 int src_enc = src->encoding(); 2040 int nds_enc = 0; 2041 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE, 2042 VEX_OPCODE_0F, true, AVX_128bit, true, true); 2043 emit_int8((unsigned char)0x90); 2044 emit_operand((Register)src, dst); 2045 } 2046 2047 void Assembler::kmovql(KRegister dst, Register src) { 2048 NOT_LP64(assert(VM_Version::supports_evex(), "")); 2049 bool supports_bw = VM_Version::supports_avx512bw(); 2050 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE; 2051 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, 2052 VEX_OPCODE_0F, supports_bw); 2053 emit_int8((unsigned char)0x92); 2054 emit_int8((unsigned char)(0xC0 | encode)); 2055 } 2056 2057 void Assembler::kmovdl(KRegister dst, Register src) { 2058 NOT_LP64(assert(VM_Version::supports_evex(), "")); 2059 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE; 2060 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false); 2061 emit_int8((unsigned char)0x92); 2062 emit_int8((unsigned char)(0xC0 | encode)); 2063 } 2064 2065 void Assembler::movb(Address dst, int imm8) { 2066 InstructionMark im(this); 2067 prefix(dst); 2068 emit_int8((unsigned char)0xC6); 2069 emit_operand(rax, dst, 1); 2070 emit_int8(imm8); 2071 } 2072 2073 2074 void Assembler::movb(Address dst, Register src) { 2075 assert(src->has_byte_register(), "must have byte register"); 2076 InstructionMark im(this); 2077 prefix(dst, src, true); 2078 emit_int8((unsigned char)0x88); 2079 emit_operand(src, dst); 2080 } 2081 2082 void Assembler::movdl(XMMRegister dst, Register src) { 2083 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2084 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true); 2085 emit_int8(0x6E); 2086 emit_int8((unsigned char)(0xC0 | encode)); 2087 } 2088 2089 void Assembler::movdl(Register dst, XMMRegister src) { 2090 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2091 // swap src/dst to get correct prefix 2092 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true); 2093 emit_int8(0x7E); 2094 emit_int8((unsigned char)(0xC0 | encode)); 2095 } 2096 2097 void Assembler::movdl(XMMRegister dst, Address src) { 2098 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2099 if (VM_Version::supports_evex()) { 2100 tuple_type = EVEX_T1S; 2101 input_size_in_bits = EVEX_32bit; 2102 } 2103 InstructionMark im(this); 2104 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F); 2105 emit_int8(0x6E); 2106 emit_operand(dst, src); 2107 } 2108 2109 void Assembler::movdl(Address dst, XMMRegister src) { 2110 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2111 if (VM_Version::supports_evex()) { 2112 tuple_type = EVEX_T1S; 2113 input_size_in_bits = EVEX_32bit; 2114 } 2115 InstructionMark im(this); 2116 simd_prefix(dst, src, VEX_SIMD_66, true); 2117 emit_int8(0x7E); 2118 emit_operand(src, dst); 2119 } 2120 2121 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2122 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2123 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); 2124 } 2125 2126 void Assembler::movdqa(XMMRegister dst, Address src) { 2127 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2128 if (VM_Version::supports_evex()) { 2129 tuple_type = EVEX_FVM; 2130 } 2131 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); 2132 } 2133 2134 void Assembler::movdqu(XMMRegister dst, Address src) { 2135 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2136 if (VM_Version::supports_evex()) { 2137 tuple_type = EVEX_FVM; 2138 } 2139 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); 2140 } 2141 2142 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2143 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2144 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); 2145 } 2146 2147 void Assembler::movdqu(Address dst, XMMRegister src) { 2148 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2149 if (VM_Version::supports_evex()) { 2150 tuple_type = EVEX_FVM; 2151 } 2152 InstructionMark im(this); 2153 simd_prefix(dst, src, VEX_SIMD_F3, false); 2154 emit_int8(0x7F); 2155 emit_operand(src, dst); 2156 } 2157 2158 // Move Unaligned 256bit Vector 2159 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2160 assert(UseAVX > 0, ""); 2161 if (VM_Version::supports_evex()) { 2162 tuple_type = EVEX_FVM; 2163 } 2164 int vector_len = AVX_256bit; 2165 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len); 2166 emit_int8(0x6F); 2167 emit_int8((unsigned char)(0xC0 | encode)); 2168 } 2169 2170 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2171 assert(UseAVX > 0, ""); 2172 if (VM_Version::supports_evex()) { 2173 tuple_type = EVEX_FVM; 2174 } 2175 InstructionMark im(this); 2176 int vector_len = AVX_256bit; 2177 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false); 2178 emit_int8(0x6F); 2179 emit_operand(dst, src); 2180 } 2181 2182 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2183 assert(UseAVX > 0, ""); 2184 if (VM_Version::supports_evex()) { 2185 tuple_type = EVEX_FVM; 2186 } 2187 InstructionMark im(this); 2188 int vector_len = AVX_256bit; 2189 // swap src<->dst for encoding 2190 assert(src != xnoreg, "sanity"); 2191 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false); 2192 emit_int8(0x7F); 2193 emit_operand(src, dst); 2194 } 2195 2196 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2197 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) { 2198 assert(UseAVX > 0, ""); 2199 int src_enc = src->encoding(); 2200 int dst_enc = dst->encoding(); 2201 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F, 2202 true, vector_len, false, false); 2203 emit_int8(0x6F); 2204 emit_int8((unsigned char)(0xC0 | encode)); 2205 } 2206 2207 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) { 2208 assert(UseAVX > 0, ""); 2209 InstructionMark im(this); 2210 if (VM_Version::supports_evex()) { 2211 tuple_type = EVEX_FVM; 2212 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false); 2213 } else { 2214 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false); 2215 } 2216 emit_int8(0x6F); 2217 emit_operand(dst, src); 2218 } 2219 2220 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) { 2221 assert(UseAVX > 0, ""); 2222 InstructionMark im(this); 2223 assert(src != xnoreg, "sanity"); 2224 if (VM_Version::supports_evex()) { 2225 tuple_type = EVEX_FVM; 2226 // swap src<->dst for encoding 2227 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false); 2228 } else { 2229 // swap src<->dst for encoding 2230 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false); 2231 } 2232 emit_int8(0x7F); 2233 emit_operand(src, dst); 2234 } 2235 2236 // Uses zero extension on 64bit 2237 2238 void Assembler::movl(Register dst, int32_t imm32) { 2239 int encode = prefix_and_encode(dst->encoding()); 2240 emit_int8((unsigned char)(0xB8 | encode)); 2241 emit_int32(imm32); 2242 } 2243 2244 void Assembler::movl(Register dst, Register src) { 2245 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2246 emit_int8((unsigned char)0x8B); 2247 emit_int8((unsigned char)(0xC0 | encode)); 2248 } 2249 2250 void Assembler::movl(Register dst, Address src) { 2251 InstructionMark im(this); 2252 prefix(src, dst); 2253 emit_int8((unsigned char)0x8B); 2254 emit_operand(dst, src); 2255 } 2256 2257 void Assembler::movl(Address dst, int32_t imm32) { 2258 InstructionMark im(this); 2259 prefix(dst); 2260 emit_int8((unsigned char)0xC7); 2261 emit_operand(rax, dst, 4); 2262 emit_int32(imm32); 2263 } 2264 2265 void Assembler::movl(Address dst, Register src) { 2266 InstructionMark im(this); 2267 prefix(dst, src); 2268 emit_int8((unsigned char)0x89); 2269 emit_operand(src, dst); 2270 } 2271 2272 // New cpus require to use movsd and movss to avoid partial register stall 2273 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2274 // The selection is done in MacroAssembler::movdbl() and movflt(). 2275 void Assembler::movlpd(XMMRegister dst, Address src) { 2276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2277 if (VM_Version::supports_evex()) { 2278 tuple_type = EVEX_T1S; 2279 input_size_in_bits = EVEX_32bit; 2280 } 2281 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true); 2282 } 2283 2284 void Assembler::movq( MMXRegister dst, Address src ) { 2285 assert( VM_Version::supports_mmx(), "" ); 2286 emit_int8(0x0F); 2287 emit_int8(0x6F); 2288 emit_operand(dst, src); 2289 } 2290 2291 void Assembler::movq( Address dst, MMXRegister src ) { 2292 assert( VM_Version::supports_mmx(), "" ); 2293 emit_int8(0x0F); 2294 emit_int8(0x7F); 2295 // workaround gcc (3.2.1-7a) bug 2296 // In that version of gcc with only an emit_operand(MMX, Address) 2297 // gcc will tail jump and try and reverse the parameters completely 2298 // obliterating dst in the process. By having a version available 2299 // that doesn't need to swap the args at the tail jump the bug is 2300 // avoided. 2301 emit_operand(dst, src); 2302 } 2303 2304 void Assembler::movq(XMMRegister dst, Address src) { 2305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2306 InstructionMark im(this); 2307 if (VM_Version::supports_evex()) { 2308 tuple_type = EVEX_T1S; 2309 input_size_in_bits = EVEX_64bit; 2310 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true); 2311 } else { 2312 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F); 2313 } 2314 emit_int8(0x7E); 2315 emit_operand(dst, src); 2316 } 2317 2318 void Assembler::movq(Address dst, XMMRegister src) { 2319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2320 InstructionMark im(this); 2321 if (VM_Version::supports_evex()) { 2322 tuple_type = EVEX_T1S; 2323 input_size_in_bits = EVEX_64bit; 2324 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true, 2325 VEX_OPCODE_0F, true, AVX_128bit); 2326 } else { 2327 simd_prefix(dst, src, VEX_SIMD_66, true); 2328 } 2329 emit_int8((unsigned char)0xD6); 2330 emit_operand(src, dst); 2331 } 2332 2333 void Assembler::movsbl(Register dst, Address src) { // movsxb 2334 InstructionMark im(this); 2335 prefix(src, dst); 2336 emit_int8(0x0F); 2337 emit_int8((unsigned char)0xBE); 2338 emit_operand(dst, src); 2339 } 2340 2341 void Assembler::movsbl(Register dst, Register src) { // movsxb 2342 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2343 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); 2344 emit_int8(0x0F); 2345 emit_int8((unsigned char)0xBE); 2346 emit_int8((unsigned char)(0xC0 | encode)); 2347 } 2348 2349 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2351 if (VM_Version::supports_evex()) { 2352 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true); 2353 } else { 2354 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); 2355 } 2356 } 2357 2358 void Assembler::movsd(XMMRegister dst, Address src) { 2359 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2360 if (VM_Version::supports_evex()) { 2361 tuple_type = EVEX_T1S; 2362 input_size_in_bits = EVEX_64bit; 2363 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true); 2364 } else { 2365 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); 2366 } 2367 } 2368 2369 void Assembler::movsd(Address dst, XMMRegister src) { 2370 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2371 InstructionMark im(this); 2372 if (VM_Version::supports_evex()) { 2373 tuple_type = EVEX_T1S; 2374 input_size_in_bits = EVEX_64bit; 2375 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2); 2376 } else { 2377 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false); 2378 } 2379 emit_int8(0x11); 2380 emit_operand(src, dst); 2381 } 2382 2383 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2384 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2385 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true); 2386 } 2387 2388 void Assembler::movss(XMMRegister dst, Address src) { 2389 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2390 if (VM_Version::supports_evex()) { 2391 tuple_type = EVEX_T1S; 2392 input_size_in_bits = EVEX_32bit; 2393 } 2394 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true); 2395 } 2396 2397 void Assembler::movss(Address dst, XMMRegister src) { 2398 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2399 if (VM_Version::supports_evex()) { 2400 tuple_type = EVEX_T1S; 2401 input_size_in_bits = EVEX_32bit; 2402 } 2403 InstructionMark im(this); 2404 simd_prefix(dst, src, VEX_SIMD_F3, false); 2405 emit_int8(0x11); 2406 emit_operand(src, dst); 2407 } 2408 2409 void Assembler::movswl(Register dst, Address src) { // movsxw 2410 InstructionMark im(this); 2411 prefix(src, dst); 2412 emit_int8(0x0F); 2413 emit_int8((unsigned char)0xBF); 2414 emit_operand(dst, src); 2415 } 2416 2417 void Assembler::movswl(Register dst, Register src) { // movsxw 2418 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2419 emit_int8(0x0F); 2420 emit_int8((unsigned char)0xBF); 2421 emit_int8((unsigned char)(0xC0 | encode)); 2422 } 2423 2424 void Assembler::movw(Address dst, int imm16) { 2425 InstructionMark im(this); 2426 2427 emit_int8(0x66); // switch to 16-bit mode 2428 prefix(dst); 2429 emit_int8((unsigned char)0xC7); 2430 emit_operand(rax, dst, 2); 2431 emit_int16(imm16); 2432 } 2433 2434 void Assembler::movw(Register dst, Address src) { 2435 InstructionMark im(this); 2436 emit_int8(0x66); 2437 prefix(src, dst); 2438 emit_int8((unsigned char)0x8B); 2439 emit_operand(dst, src); 2440 } 2441 2442 void Assembler::movw(Address dst, Register src) { 2443 InstructionMark im(this); 2444 emit_int8(0x66); 2445 prefix(dst, src); 2446 emit_int8((unsigned char)0x89); 2447 emit_operand(src, dst); 2448 } 2449 2450 void Assembler::movzbl(Register dst, Address src) { // movzxb 2451 InstructionMark im(this); 2452 prefix(src, dst); 2453 emit_int8(0x0F); 2454 emit_int8((unsigned char)0xB6); 2455 emit_operand(dst, src); 2456 } 2457 2458 void Assembler::movzbl(Register dst, Register src) { // movzxb 2459 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2460 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); 2461 emit_int8(0x0F); 2462 emit_int8((unsigned char)0xB6); 2463 emit_int8(0xC0 | encode); 2464 } 2465 2466 void Assembler::movzwl(Register dst, Address src) { // movzxw 2467 InstructionMark im(this); 2468 prefix(src, dst); 2469 emit_int8(0x0F); 2470 emit_int8((unsigned char)0xB7); 2471 emit_operand(dst, src); 2472 } 2473 2474 void Assembler::movzwl(Register dst, Register src) { // movzxw 2475 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2476 emit_int8(0x0F); 2477 emit_int8((unsigned char)0xB7); 2478 emit_int8(0xC0 | encode); 2479 } 2480 2481 void Assembler::mull(Address src) { 2482 InstructionMark im(this); 2483 prefix(src); 2484 emit_int8((unsigned char)0xF7); 2485 emit_operand(rsp, src); 2486 } 2487 2488 void Assembler::mull(Register src) { 2489 int encode = prefix_and_encode(src->encoding()); 2490 emit_int8((unsigned char)0xF7); 2491 emit_int8((unsigned char)(0xE0 | encode)); 2492 } 2493 2494 void Assembler::mulsd(XMMRegister dst, Address src) { 2495 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2496 if (VM_Version::supports_evex()) { 2497 tuple_type = EVEX_T1S; 2498 input_size_in_bits = EVEX_64bit; 2499 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2); 2500 } else { 2501 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); 2502 } 2503 } 2504 2505 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2506 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2507 if (VM_Version::supports_evex()) { 2508 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2); 2509 } else { 2510 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); 2511 } 2512 } 2513 2514 void Assembler::mulss(XMMRegister dst, Address src) { 2515 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2516 if (VM_Version::supports_evex()) { 2517 tuple_type = EVEX_T1S; 2518 input_size_in_bits = EVEX_32bit; 2519 } 2520 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); 2521 } 2522 2523 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 2524 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2525 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); 2526 } 2527 2528 void Assembler::negl(Register dst) { 2529 int encode = prefix_and_encode(dst->encoding()); 2530 emit_int8((unsigned char)0xF7); 2531 emit_int8((unsigned char)(0xD8 | encode)); 2532 } 2533 2534 void Assembler::nop(int i) { 2535 #ifdef ASSERT 2536 assert(i > 0, " "); 2537 // The fancy nops aren't currently recognized by debuggers making it a 2538 // pain to disassemble code while debugging. If asserts are on clearly 2539 // speed is not an issue so simply use the single byte traditional nop 2540 // to do alignment. 2541 2542 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 2543 return; 2544 2545 #endif // ASSERT 2546 2547 if (UseAddressNop && VM_Version::is_intel()) { 2548 // 2549 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 2550 // 1: 0x90 2551 // 2: 0x66 0x90 2552 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2553 // 4: 0x0F 0x1F 0x40 0x00 2554 // 5: 0x0F 0x1F 0x44 0x00 0x00 2555 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2556 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2557 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2558 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2559 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2560 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2561 2562 // The rest coding is Intel specific - don't use consecutive address nops 2563 2564 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2565 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2566 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2567 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2568 2569 while(i >= 15) { 2570 // For Intel don't generate consecutive addess nops (mix with regular nops) 2571 i -= 15; 2572 emit_int8(0x66); // size prefix 2573 emit_int8(0x66); // size prefix 2574 emit_int8(0x66); // size prefix 2575 addr_nop_8(); 2576 emit_int8(0x66); // size prefix 2577 emit_int8(0x66); // size prefix 2578 emit_int8(0x66); // size prefix 2579 emit_int8((unsigned char)0x90); 2580 // nop 2581 } 2582 switch (i) { 2583 case 14: 2584 emit_int8(0x66); // size prefix 2585 case 13: 2586 emit_int8(0x66); // size prefix 2587 case 12: 2588 addr_nop_8(); 2589 emit_int8(0x66); // size prefix 2590 emit_int8(0x66); // size prefix 2591 emit_int8(0x66); // size prefix 2592 emit_int8((unsigned char)0x90); 2593 // nop 2594 break; 2595 case 11: 2596 emit_int8(0x66); // size prefix 2597 case 10: 2598 emit_int8(0x66); // size prefix 2599 case 9: 2600 emit_int8(0x66); // size prefix 2601 case 8: 2602 addr_nop_8(); 2603 break; 2604 case 7: 2605 addr_nop_7(); 2606 break; 2607 case 6: 2608 emit_int8(0x66); // size prefix 2609 case 5: 2610 addr_nop_5(); 2611 break; 2612 case 4: 2613 addr_nop_4(); 2614 break; 2615 case 3: 2616 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 2617 emit_int8(0x66); // size prefix 2618 case 2: 2619 emit_int8(0x66); // size prefix 2620 case 1: 2621 emit_int8((unsigned char)0x90); 2622 // nop 2623 break; 2624 default: 2625 assert(i == 0, " "); 2626 } 2627 return; 2628 } 2629 if (UseAddressNop && VM_Version::is_amd()) { 2630 // 2631 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 2632 // 1: 0x90 2633 // 2: 0x66 0x90 2634 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2635 // 4: 0x0F 0x1F 0x40 0x00 2636 // 5: 0x0F 0x1F 0x44 0x00 0x00 2637 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2638 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2639 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2640 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2641 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2642 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2643 2644 // The rest coding is AMD specific - use consecutive address nops 2645 2646 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 2647 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 2648 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2649 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2650 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2651 // Size prefixes (0x66) are added for larger sizes 2652 2653 while(i >= 22) { 2654 i -= 11; 2655 emit_int8(0x66); // size prefix 2656 emit_int8(0x66); // size prefix 2657 emit_int8(0x66); // size prefix 2658 addr_nop_8(); 2659 } 2660 // Generate first nop for size between 21-12 2661 switch (i) { 2662 case 21: 2663 i -= 1; 2664 emit_int8(0x66); // size prefix 2665 case 20: 2666 case 19: 2667 i -= 1; 2668 emit_int8(0x66); // size prefix 2669 case 18: 2670 case 17: 2671 i -= 1; 2672 emit_int8(0x66); // size prefix 2673 case 16: 2674 case 15: 2675 i -= 8; 2676 addr_nop_8(); 2677 break; 2678 case 14: 2679 case 13: 2680 i -= 7; 2681 addr_nop_7(); 2682 break; 2683 case 12: 2684 i -= 6; 2685 emit_int8(0x66); // size prefix 2686 addr_nop_5(); 2687 break; 2688 default: 2689 assert(i < 12, " "); 2690 } 2691 2692 // Generate second nop for size between 11-1 2693 switch (i) { 2694 case 11: 2695 emit_int8(0x66); // size prefix 2696 case 10: 2697 emit_int8(0x66); // size prefix 2698 case 9: 2699 emit_int8(0x66); // size prefix 2700 case 8: 2701 addr_nop_8(); 2702 break; 2703 case 7: 2704 addr_nop_7(); 2705 break; 2706 case 6: 2707 emit_int8(0x66); // size prefix 2708 case 5: 2709 addr_nop_5(); 2710 break; 2711 case 4: 2712 addr_nop_4(); 2713 break; 2714 case 3: 2715 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 2716 emit_int8(0x66); // size prefix 2717 case 2: 2718 emit_int8(0x66); // size prefix 2719 case 1: 2720 emit_int8((unsigned char)0x90); 2721 // nop 2722 break; 2723 default: 2724 assert(i == 0, " "); 2725 } 2726 return; 2727 } 2728 2729 // Using nops with size prefixes "0x66 0x90". 2730 // From AMD Optimization Guide: 2731 // 1: 0x90 2732 // 2: 0x66 0x90 2733 // 3: 0x66 0x66 0x90 2734 // 4: 0x66 0x66 0x66 0x90 2735 // 5: 0x66 0x66 0x90 0x66 0x90 2736 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 2737 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 2738 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 2739 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 2740 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 2741 // 2742 while(i > 12) { 2743 i -= 4; 2744 emit_int8(0x66); // size prefix 2745 emit_int8(0x66); 2746 emit_int8(0x66); 2747 emit_int8((unsigned char)0x90); 2748 // nop 2749 } 2750 // 1 - 12 nops 2751 if(i > 8) { 2752 if(i > 9) { 2753 i -= 1; 2754 emit_int8(0x66); 2755 } 2756 i -= 3; 2757 emit_int8(0x66); 2758 emit_int8(0x66); 2759 emit_int8((unsigned char)0x90); 2760 } 2761 // 1 - 8 nops 2762 if(i > 4) { 2763 if(i > 6) { 2764 i -= 1; 2765 emit_int8(0x66); 2766 } 2767 i -= 3; 2768 emit_int8(0x66); 2769 emit_int8(0x66); 2770 emit_int8((unsigned char)0x90); 2771 } 2772 switch (i) { 2773 case 4: 2774 emit_int8(0x66); 2775 case 3: 2776 emit_int8(0x66); 2777 case 2: 2778 emit_int8(0x66); 2779 case 1: 2780 emit_int8((unsigned char)0x90); 2781 break; 2782 default: 2783 assert(i == 0, " "); 2784 } 2785 } 2786 2787 void Assembler::notl(Register dst) { 2788 int encode = prefix_and_encode(dst->encoding()); 2789 emit_int8((unsigned char)0xF7); 2790 emit_int8((unsigned char)(0xD0 | encode)); 2791 } 2792 2793 void Assembler::orl(Address dst, int32_t imm32) { 2794 InstructionMark im(this); 2795 prefix(dst); 2796 emit_arith_operand(0x81, rcx, dst, imm32); 2797 } 2798 2799 void Assembler::orl(Register dst, int32_t imm32) { 2800 prefix(dst); 2801 emit_arith(0x81, 0xC8, dst, imm32); 2802 } 2803 2804 void Assembler::orl(Register dst, Address src) { 2805 InstructionMark im(this); 2806 prefix(src, dst); 2807 emit_int8(0x0B); 2808 emit_operand(dst, src); 2809 } 2810 2811 void Assembler::orl(Register dst, Register src) { 2812 (void) prefix_and_encode(dst->encoding(), src->encoding()); 2813 emit_arith(0x0B, 0xC0, dst, src); 2814 } 2815 2816 void Assembler::orl(Address dst, Register src) { 2817 InstructionMark im(this); 2818 prefix(dst, src); 2819 emit_int8(0x09); 2820 emit_operand(src, dst); 2821 } 2822 2823 void Assembler::packuswb(XMMRegister dst, Address src) { 2824 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2825 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 2826 if (VM_Version::supports_evex()) { 2827 tuple_type = EVEX_FV; 2828 input_size_in_bits = EVEX_32bit; 2829 } 2830 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, 2831 false, (VM_Version::supports_avx512dq() == false)); 2832 } 2833 2834 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 2835 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2836 emit_simd_arith(0x67, dst, src, VEX_SIMD_66, 2837 false, (VM_Version::supports_avx512dq() == false)); 2838 } 2839 2840 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 2841 assert(UseAVX > 0, "some form of AVX must be enabled"); 2842 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len, 2843 false, (VM_Version::supports_avx512dq() == false)); 2844 } 2845 2846 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 2847 assert(VM_Version::supports_avx2(), ""); 2848 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, 2849 VEX_OPCODE_0F_3A, true, vector_len); 2850 emit_int8(0x00); 2851 emit_int8(0xC0 | encode); 2852 emit_int8(imm8); 2853 } 2854 2855 void Assembler::pause() { 2856 emit_int8((unsigned char)0xF3); 2857 emit_int8((unsigned char)0x90); 2858 } 2859 2860 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 2861 assert(VM_Version::supports_sse4_2(), ""); 2862 InstructionMark im(this); 2863 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A, 2864 false, AVX_128bit, true); 2865 emit_int8(0x61); 2866 emit_operand(dst, src); 2867 emit_int8(imm8); 2868 } 2869 2870 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 2871 assert(VM_Version::supports_sse4_2(), ""); 2872 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, 2873 VEX_OPCODE_0F_3A, false, AVX_128bit, true); 2874 emit_int8(0x61); 2875 emit_int8((unsigned char)(0xC0 | encode)); 2876 emit_int8(imm8); 2877 } 2878 2879 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 2880 assert(VM_Version::supports_sse4_1(), ""); 2881 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A, 2882 false, AVX_128bit, (VM_Version::supports_avx512dq() == false)); 2883 emit_int8(0x16); 2884 emit_int8((unsigned char)(0xC0 | encode)); 2885 emit_int8(imm8); 2886 } 2887 2888 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 2889 assert(VM_Version::supports_sse4_1(), ""); 2890 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A, 2891 false, AVX_128bit, (VM_Version::supports_avx512dq() == false)); 2892 emit_int8(0x16); 2893 emit_int8((unsigned char)(0xC0 | encode)); 2894 emit_int8(imm8); 2895 } 2896 2897 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 2898 assert(VM_Version::supports_sse4_1(), ""); 2899 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A, 2900 false, AVX_128bit, (VM_Version::supports_avx512dq() == false)); 2901 emit_int8(0x22); 2902 emit_int8((unsigned char)(0xC0 | encode)); 2903 emit_int8(imm8); 2904 } 2905 2906 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 2907 assert(VM_Version::supports_sse4_1(), ""); 2908 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A, 2909 false, AVX_128bit, (VM_Version::supports_avx512dq() == false)); 2910 emit_int8(0x22); 2911 emit_int8((unsigned char)(0xC0 | encode)); 2912 emit_int8(imm8); 2913 } 2914 2915 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 2916 assert(VM_Version::supports_sse4_1(), ""); 2917 if (VM_Version::supports_evex()) { 2918 tuple_type = EVEX_HVM; 2919 } 2920 InstructionMark im(this); 2921 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38); 2922 emit_int8(0x30); 2923 emit_operand(dst, src); 2924 } 2925 2926 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 2927 assert(VM_Version::supports_sse4_1(), ""); 2928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38); 2929 emit_int8(0x30); 2930 emit_int8((unsigned char)(0xC0 | encode)); 2931 } 2932 2933 // generic 2934 void Assembler::pop(Register dst) { 2935 int encode = prefix_and_encode(dst->encoding()); 2936 emit_int8(0x58 | encode); 2937 } 2938 2939 void Assembler::popcntl(Register dst, Address src) { 2940 assert(VM_Version::supports_popcnt(), "must support"); 2941 InstructionMark im(this); 2942 emit_int8((unsigned char)0xF3); 2943 prefix(src, dst); 2944 emit_int8(0x0F); 2945 emit_int8((unsigned char)0xB8); 2946 emit_operand(dst, src); 2947 } 2948 2949 void Assembler::popcntl(Register dst, Register src) { 2950 assert(VM_Version::supports_popcnt(), "must support"); 2951 emit_int8((unsigned char)0xF3); 2952 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2953 emit_int8(0x0F); 2954 emit_int8((unsigned char)0xB8); 2955 emit_int8((unsigned char)(0xC0 | encode)); 2956 } 2957 2958 void Assembler::popf() { 2959 emit_int8((unsigned char)0x9D); 2960 } 2961 2962 #ifndef _LP64 // no 32bit push/pop on amd64 2963 void Assembler::popl(Address dst) { 2964 // NOTE: this will adjust stack by 8byte on 64bits 2965 InstructionMark im(this); 2966 prefix(dst); 2967 emit_int8((unsigned char)0x8F); 2968 emit_operand(rax, dst); 2969 } 2970 #endif 2971 2972 void Assembler::prefetch_prefix(Address src) { 2973 prefix(src); 2974 emit_int8(0x0F); 2975 } 2976 2977 void Assembler::prefetchnta(Address src) { 2978 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2979 InstructionMark im(this); 2980 prefetch_prefix(src); 2981 emit_int8(0x18); 2982 emit_operand(rax, src); // 0, src 2983 } 2984 2985 void Assembler::prefetchr(Address src) { 2986 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 2987 InstructionMark im(this); 2988 prefetch_prefix(src); 2989 emit_int8(0x0D); 2990 emit_operand(rax, src); // 0, src 2991 } 2992 2993 void Assembler::prefetcht0(Address src) { 2994 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 2995 InstructionMark im(this); 2996 prefetch_prefix(src); 2997 emit_int8(0x18); 2998 emit_operand(rcx, src); // 1, src 2999 } 3000 3001 void Assembler::prefetcht1(Address src) { 3002 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3003 InstructionMark im(this); 3004 prefetch_prefix(src); 3005 emit_int8(0x18); 3006 emit_operand(rdx, src); // 2, src 3007 } 3008 3009 void Assembler::prefetcht2(Address src) { 3010 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3011 InstructionMark im(this); 3012 prefetch_prefix(src); 3013 emit_int8(0x18); 3014 emit_operand(rbx, src); // 3, src 3015 } 3016 3017 void Assembler::prefetchw(Address src) { 3018 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3019 InstructionMark im(this); 3020 prefetch_prefix(src); 3021 emit_int8(0x0D); 3022 emit_operand(rcx, src); // 1, src 3023 } 3024 3025 void Assembler::prefix(Prefix p) { 3026 emit_int8(p); 3027 } 3028 3029 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 3030 assert(VM_Version::supports_ssse3(), ""); 3031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38, 3032 false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 3033 emit_int8(0x00); 3034 emit_int8((unsigned char)(0xC0 | encode)); 3035 } 3036 3037 void Assembler::pshufb(XMMRegister dst, Address src) { 3038 assert(VM_Version::supports_ssse3(), ""); 3039 if (VM_Version::supports_evex()) { 3040 tuple_type = EVEX_FVM; 3041 } 3042 InstructionMark im(this); 3043 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38, 3044 false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 3045 emit_int8(0x00); 3046 emit_operand(dst, src); 3047 } 3048 3049 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 3050 assert(isByte(mode), "invalid value"); 3051 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3052 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); 3053 emit_int8(mode & 0xFF); 3054 3055 } 3056 3057 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 3058 assert(isByte(mode), "invalid value"); 3059 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3060 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3061 if (VM_Version::supports_evex()) { 3062 tuple_type = EVEX_FV; 3063 input_size_in_bits = EVEX_32bit; 3064 } 3065 InstructionMark im(this); 3066 simd_prefix(dst, src, VEX_SIMD_66, false); 3067 emit_int8(0x70); 3068 emit_operand(dst, src); 3069 emit_int8(mode & 0xFF); 3070 } 3071 3072 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3073 assert(isByte(mode), "invalid value"); 3074 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3075 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false, 3076 (VM_Version::supports_avx512bw() == false)); 3077 emit_int8(mode & 0xFF); 3078 } 3079 3080 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 3081 assert(isByte(mode), "invalid value"); 3082 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3083 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3084 if (VM_Version::supports_evex()) { 3085 tuple_type = EVEX_FVM; 3086 } 3087 InstructionMark im(this); 3088 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F, 3089 false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 3090 emit_int8(0x70); 3091 emit_operand(dst, src); 3092 emit_int8(mode & 0xFF); 3093 } 3094 3095 void Assembler::psrldq(XMMRegister dst, int shift) { 3096 // Shift 128 bit value in xmm register by number of bytes. 3097 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3098 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 3099 emit_int8(0x73); 3100 emit_int8((unsigned char)(0xC0 | encode)); 3101 emit_int8(shift); 3102 } 3103 3104 void Assembler::pslldq(XMMRegister dst, int shift) { 3105 // Shift left 128 bit value in xmm register by number of bytes. 3106 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3107 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 3108 emit_int8(0x73); 3109 emit_int8((unsigned char)(0xC0 | encode)); 3110 emit_int8(shift); 3111 } 3112 3113 void Assembler::ptest(XMMRegister dst, Address src) { 3114 assert(VM_Version::supports_sse4_1(), ""); 3115 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3116 InstructionMark im(this); 3117 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38); 3118 emit_int8(0x17); 3119 emit_operand(dst, src); 3120 } 3121 3122 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 3123 assert(VM_Version::supports_sse4_1(), ""); 3124 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, 3125 false, VEX_OPCODE_0F_38); 3126 emit_int8(0x17); 3127 emit_int8((unsigned char)(0xC0 | encode)); 3128 } 3129 3130 void Assembler::vptest(XMMRegister dst, Address src) { 3131 assert(VM_Version::supports_avx(), ""); 3132 InstructionMark im(this); 3133 int vector_len = AVX_256bit; 3134 assert(dst != xnoreg, "sanity"); 3135 int dst_enc = dst->encoding(); 3136 // swap src<->dst for encoding 3137 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len); 3138 emit_int8(0x17); 3139 emit_operand(dst, src); 3140 } 3141 3142 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 3143 assert(VM_Version::supports_avx(), ""); 3144 int vector_len = AVX_256bit; 3145 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, 3146 vector_len, VEX_OPCODE_0F_38); 3147 emit_int8(0x17); 3148 emit_int8((unsigned char)(0xC0 | encode)); 3149 } 3150 3151 void Assembler::punpcklbw(XMMRegister dst, Address src) { 3152 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3153 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3154 if (VM_Version::supports_evex()) { 3155 tuple_type = EVEX_FVM; 3156 } 3157 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); 3158 } 3159 3160 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 3161 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3162 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); 3163 } 3164 3165 void Assembler::punpckldq(XMMRegister dst, Address src) { 3166 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3167 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3168 if (VM_Version::supports_evex()) { 3169 tuple_type = EVEX_FV; 3170 input_size_in_bits = EVEX_32bit; 3171 } 3172 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); 3173 } 3174 3175 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 3176 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3177 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); 3178 } 3179 3180 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 3181 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3182 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); 3183 } 3184 3185 void Assembler::push(int32_t imm32) { 3186 // in 64bits we push 64bits onto the stack but only 3187 // take a 32bit immediate 3188 emit_int8(0x68); 3189 emit_int32(imm32); 3190 } 3191 3192 void Assembler::push(Register src) { 3193 int encode = prefix_and_encode(src->encoding()); 3194 3195 emit_int8(0x50 | encode); 3196 } 3197 3198 void Assembler::pushf() { 3199 emit_int8((unsigned char)0x9C); 3200 } 3201 3202 #ifndef _LP64 // no 32bit push/pop on amd64 3203 void Assembler::pushl(Address src) { 3204 // Note this will push 64bit on 64bit 3205 InstructionMark im(this); 3206 prefix(src); 3207 emit_int8((unsigned char)0xFF); 3208 emit_operand(rsi, src); 3209 } 3210 #endif 3211 3212 void Assembler::rcll(Register dst, int imm8) { 3213 assert(isShiftCount(imm8), "illegal shift count"); 3214 int encode = prefix_and_encode(dst->encoding()); 3215 if (imm8 == 1) { 3216 emit_int8((unsigned char)0xD1); 3217 emit_int8((unsigned char)(0xD0 | encode)); 3218 } else { 3219 emit_int8((unsigned char)0xC1); 3220 emit_int8((unsigned char)0xD0 | encode); 3221 emit_int8(imm8); 3222 } 3223 } 3224 3225 void Assembler::rdtsc() { 3226 emit_int8((unsigned char)0x0F); 3227 emit_int8((unsigned char)0x31); 3228 } 3229 3230 // copies data from [esi] to [edi] using rcx pointer sized words 3231 // generic 3232 void Assembler::rep_mov() { 3233 emit_int8((unsigned char)0xF3); 3234 // MOVSQ 3235 LP64_ONLY(prefix(REX_W)); 3236 emit_int8((unsigned char)0xA5); 3237 } 3238 3239 // sets rcx bytes with rax, value at [edi] 3240 void Assembler::rep_stosb() { 3241 emit_int8((unsigned char)0xF3); // REP 3242 LP64_ONLY(prefix(REX_W)); 3243 emit_int8((unsigned char)0xAA); // STOSB 3244 } 3245 3246 // sets rcx pointer sized words with rax, value at [edi] 3247 // generic 3248 void Assembler::rep_stos() { 3249 emit_int8((unsigned char)0xF3); // REP 3250 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 3251 emit_int8((unsigned char)0xAB); 3252 } 3253 3254 // scans rcx pointer sized words at [edi] for occurance of rax, 3255 // generic 3256 void Assembler::repne_scan() { // repne_scan 3257 emit_int8((unsigned char)0xF2); 3258 // SCASQ 3259 LP64_ONLY(prefix(REX_W)); 3260 emit_int8((unsigned char)0xAF); 3261 } 3262 3263 #ifdef _LP64 3264 // scans rcx 4 byte words at [edi] for occurance of rax, 3265 // generic 3266 void Assembler::repne_scanl() { // repne_scan 3267 emit_int8((unsigned char)0xF2); 3268 // SCASL 3269 emit_int8((unsigned char)0xAF); 3270 } 3271 #endif 3272 3273 void Assembler::ret(int imm16) { 3274 if (imm16 == 0) { 3275 emit_int8((unsigned char)0xC3); 3276 } else { 3277 emit_int8((unsigned char)0xC2); 3278 emit_int16(imm16); 3279 } 3280 } 3281 3282 void Assembler::sahf() { 3283 #ifdef _LP64 3284 // Not supported in 64bit mode 3285 ShouldNotReachHere(); 3286 #endif 3287 emit_int8((unsigned char)0x9E); 3288 } 3289 3290 void Assembler::sarl(Register dst, int imm8) { 3291 int encode = prefix_and_encode(dst->encoding()); 3292 assert(isShiftCount(imm8), "illegal shift count"); 3293 if (imm8 == 1) { 3294 emit_int8((unsigned char)0xD1); 3295 emit_int8((unsigned char)(0xF8 | encode)); 3296 } else { 3297 emit_int8((unsigned char)0xC1); 3298 emit_int8((unsigned char)(0xF8 | encode)); 3299 emit_int8(imm8); 3300 } 3301 } 3302 3303 void Assembler::sarl(Register dst) { 3304 int encode = prefix_and_encode(dst->encoding()); 3305 emit_int8((unsigned char)0xD3); 3306 emit_int8((unsigned char)(0xF8 | encode)); 3307 } 3308 3309 void Assembler::sbbl(Address dst, int32_t imm32) { 3310 InstructionMark im(this); 3311 prefix(dst); 3312 emit_arith_operand(0x81, rbx, dst, imm32); 3313 } 3314 3315 void Assembler::sbbl(Register dst, int32_t imm32) { 3316 prefix(dst); 3317 emit_arith(0x81, 0xD8, dst, imm32); 3318 } 3319 3320 3321 void Assembler::sbbl(Register dst, Address src) { 3322 InstructionMark im(this); 3323 prefix(src, dst); 3324 emit_int8(0x1B); 3325 emit_operand(dst, src); 3326 } 3327 3328 void Assembler::sbbl(Register dst, Register src) { 3329 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3330 emit_arith(0x1B, 0xC0, dst, src); 3331 } 3332 3333 void Assembler::setb(Condition cc, Register dst) { 3334 assert(0 <= cc && cc < 16, "illegal cc"); 3335 int encode = prefix_and_encode(dst->encoding(), true); 3336 emit_int8(0x0F); 3337 emit_int8((unsigned char)0x90 | cc); 3338 emit_int8((unsigned char)(0xC0 | encode)); 3339 } 3340 3341 void Assembler::shll(Register dst, int imm8) { 3342 assert(isShiftCount(imm8), "illegal shift count"); 3343 int encode = prefix_and_encode(dst->encoding()); 3344 if (imm8 == 1 ) { 3345 emit_int8((unsigned char)0xD1); 3346 emit_int8((unsigned char)(0xE0 | encode)); 3347 } else { 3348 emit_int8((unsigned char)0xC1); 3349 emit_int8((unsigned char)(0xE0 | encode)); 3350 emit_int8(imm8); 3351 } 3352 } 3353 3354 void Assembler::shll(Register dst) { 3355 int encode = prefix_and_encode(dst->encoding()); 3356 emit_int8((unsigned char)0xD3); 3357 emit_int8((unsigned char)(0xE0 | encode)); 3358 } 3359 3360 void Assembler::shrl(Register dst, int imm8) { 3361 assert(isShiftCount(imm8), "illegal shift count"); 3362 int encode = prefix_and_encode(dst->encoding()); 3363 emit_int8((unsigned char)0xC1); 3364 emit_int8((unsigned char)(0xE8 | encode)); 3365 emit_int8(imm8); 3366 } 3367 3368 void Assembler::shrl(Register dst) { 3369 int encode = prefix_and_encode(dst->encoding()); 3370 emit_int8((unsigned char)0xD3); 3371 emit_int8((unsigned char)(0xE8 | encode)); 3372 } 3373 3374 // copies a single word from [esi] to [edi] 3375 void Assembler::smovl() { 3376 emit_int8((unsigned char)0xA5); 3377 } 3378 3379 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 3380 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3381 if (VM_Version::supports_evex()) { 3382 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2); 3383 } else { 3384 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); 3385 } 3386 } 3387 3388 void Assembler::sqrtsd(XMMRegister dst, Address src) { 3389 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3390 if (VM_Version::supports_evex()) { 3391 tuple_type = EVEX_T1S; 3392 input_size_in_bits = EVEX_64bit; 3393 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2); 3394 } else { 3395 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); 3396 } 3397 } 3398 3399 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 3400 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3401 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); 3402 } 3403 3404 void Assembler::std() { 3405 emit_int8((unsigned char)0xFD); 3406 } 3407 3408 void Assembler::sqrtss(XMMRegister dst, Address src) { 3409 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3410 if (VM_Version::supports_evex()) { 3411 tuple_type = EVEX_T1S; 3412 input_size_in_bits = EVEX_32bit; 3413 } 3414 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); 3415 } 3416 3417 void Assembler::stmxcsr( Address dst) { 3418 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3419 InstructionMark im(this); 3420 prefix(dst); 3421 emit_int8(0x0F); 3422 emit_int8((unsigned char)0xAE); 3423 emit_operand(as_Register(3), dst); 3424 } 3425 3426 void Assembler::subl(Address dst, int32_t imm32) { 3427 InstructionMark im(this); 3428 prefix(dst); 3429 emit_arith_operand(0x81, rbp, dst, imm32); 3430 } 3431 3432 void Assembler::subl(Address dst, Register src) { 3433 InstructionMark im(this); 3434 prefix(dst, src); 3435 emit_int8(0x29); 3436 emit_operand(src, dst); 3437 } 3438 3439 void Assembler::subl(Register dst, int32_t imm32) { 3440 prefix(dst); 3441 emit_arith(0x81, 0xE8, dst, imm32); 3442 } 3443 3444 // Force generation of a 4 byte immediate value even if it fits into 8bit 3445 void Assembler::subl_imm32(Register dst, int32_t imm32) { 3446 prefix(dst); 3447 emit_arith_imm32(0x81, 0xE8, dst, imm32); 3448 } 3449 3450 void Assembler::subl(Register dst, Address src) { 3451 InstructionMark im(this); 3452 prefix(src, dst); 3453 emit_int8(0x2B); 3454 emit_operand(dst, src); 3455 } 3456 3457 void Assembler::subl(Register dst, Register src) { 3458 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3459 emit_arith(0x2B, 0xC0, dst, src); 3460 } 3461 3462 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 3463 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3464 if (VM_Version::supports_evex()) { 3465 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2); 3466 } else { 3467 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); 3468 } 3469 } 3470 3471 void Assembler::subsd(XMMRegister dst, Address src) { 3472 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3473 if (VM_Version::supports_evex()) { 3474 tuple_type = EVEX_T1S; 3475 input_size_in_bits = EVEX_64bit; 3476 } 3477 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2); 3478 } 3479 3480 void Assembler::subss(XMMRegister dst, XMMRegister src) { 3481 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3482 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); 3483 } 3484 3485 void Assembler::subss(XMMRegister dst, Address src) { 3486 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3487 if (VM_Version::supports_evex()) { 3488 tuple_type = EVEX_T1S; 3489 input_size_in_bits = EVEX_32bit; 3490 } 3491 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); 3492 } 3493 3494 void Assembler::testb(Register dst, int imm8) { 3495 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 3496 (void) prefix_and_encode(dst->encoding(), true); 3497 emit_arith_b(0xF6, 0xC0, dst, imm8); 3498 } 3499 3500 void Assembler::testl(Register dst, int32_t imm32) { 3501 // not using emit_arith because test 3502 // doesn't support sign-extension of 3503 // 8bit operands 3504 int encode = dst->encoding(); 3505 if (encode == 0) { 3506 emit_int8((unsigned char)0xA9); 3507 } else { 3508 encode = prefix_and_encode(encode); 3509 emit_int8((unsigned char)0xF7); 3510 emit_int8((unsigned char)(0xC0 | encode)); 3511 } 3512 emit_int32(imm32); 3513 } 3514 3515 void Assembler::testl(Register dst, Register src) { 3516 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3517 emit_arith(0x85, 0xC0, dst, src); 3518 } 3519 3520 void Assembler::testl(Register dst, Address src) { 3521 InstructionMark im(this); 3522 prefix(src, dst); 3523 emit_int8((unsigned char)0x85); 3524 emit_operand(dst, src); 3525 } 3526 3527 void Assembler::tzcntl(Register dst, Register src) { 3528 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 3529 emit_int8((unsigned char)0xF3); 3530 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3531 emit_int8(0x0F); 3532 emit_int8((unsigned char)0xBC); 3533 emit_int8((unsigned char)0xC0 | encode); 3534 } 3535 3536 void Assembler::tzcntq(Register dst, Register src) { 3537 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 3538 emit_int8((unsigned char)0xF3); 3539 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 3540 emit_int8(0x0F); 3541 emit_int8((unsigned char)0xBC); 3542 emit_int8((unsigned char)(0xC0 | encode)); 3543 } 3544 3545 void Assembler::ucomisd(XMMRegister dst, Address src) { 3546 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3547 if (VM_Version::supports_evex()) { 3548 tuple_type = EVEX_T1S; 3549 input_size_in_bits = EVEX_64bit; 3550 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true); 3551 } else { 3552 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); 3553 } 3554 } 3555 3556 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 3557 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3558 if (VM_Version::supports_evex()) { 3559 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true); 3560 } else { 3561 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); 3562 } 3563 } 3564 3565 void Assembler::ucomiss(XMMRegister dst, Address src) { 3566 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3567 if (VM_Version::supports_evex()) { 3568 tuple_type = EVEX_T1S; 3569 input_size_in_bits = EVEX_32bit; 3570 } 3571 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true); 3572 } 3573 3574 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 3575 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3576 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true); 3577 } 3578 3579 void Assembler::xabort(int8_t imm8) { 3580 emit_int8((unsigned char)0xC6); 3581 emit_int8((unsigned char)0xF8); 3582 emit_int8((unsigned char)(imm8 & 0xFF)); 3583 } 3584 3585 void Assembler::xaddl(Address dst, Register src) { 3586 InstructionMark im(this); 3587 prefix(dst, src); 3588 emit_int8(0x0F); 3589 emit_int8((unsigned char)0xC1); 3590 emit_operand(src, dst); 3591 } 3592 3593 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 3594 InstructionMark im(this); 3595 relocate(rtype); 3596 if (abort.is_bound()) { 3597 address entry = target(abort); 3598 assert(entry != NULL, "abort entry NULL"); 3599 intptr_t offset = entry - pc(); 3600 emit_int8((unsigned char)0xC7); 3601 emit_int8((unsigned char)0xF8); 3602 emit_int32(offset - 6); // 2 opcode + 4 address 3603 } else { 3604 abort.add_patch_at(code(), locator()); 3605 emit_int8((unsigned char)0xC7); 3606 emit_int8((unsigned char)0xF8); 3607 emit_int32(0); 3608 } 3609 } 3610 3611 void Assembler::xchgl(Register dst, Address src) { // xchg 3612 InstructionMark im(this); 3613 prefix(src, dst); 3614 emit_int8((unsigned char)0x87); 3615 emit_operand(dst, src); 3616 } 3617 3618 void Assembler::xchgl(Register dst, Register src) { 3619 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3620 emit_int8((unsigned char)0x87); 3621 emit_int8((unsigned char)(0xC0 | encode)); 3622 } 3623 3624 void Assembler::xend() { 3625 emit_int8((unsigned char)0x0F); 3626 emit_int8((unsigned char)0x01); 3627 emit_int8((unsigned char)0xD5); 3628 } 3629 3630 void Assembler::xgetbv() { 3631 emit_int8(0x0F); 3632 emit_int8(0x01); 3633 emit_int8((unsigned char)0xD0); 3634 } 3635 3636 void Assembler::xorl(Register dst, int32_t imm32) { 3637 prefix(dst); 3638 emit_arith(0x81, 0xF0, dst, imm32); 3639 } 3640 3641 void Assembler::xorl(Register dst, Address src) { 3642 InstructionMark im(this); 3643 prefix(src, dst); 3644 emit_int8(0x33); 3645 emit_operand(dst, src); 3646 } 3647 3648 void Assembler::xorl(Register dst, Register src) { 3649 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3650 emit_arith(0x33, 0xC0, dst, src); 3651 } 3652 3653 3654 // AVX 3-operands scalar float-point arithmetic instructions 3655 3656 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 3657 assert(VM_Version::supports_avx(), ""); 3658 if (VM_Version::supports_evex()) { 3659 tuple_type = EVEX_T1S; 3660 input_size_in_bits = EVEX_64bit; 3661 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3662 } else { 3663 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3664 } 3665 } 3666 3667 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3668 assert(VM_Version::supports_avx(), ""); 3669 if (VM_Version::supports_evex()) { 3670 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3671 } else { 3672 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3673 } 3674 } 3675 3676 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 3677 assert(VM_Version::supports_avx(), ""); 3678 if (VM_Version::supports_evex()) { 3679 tuple_type = EVEX_T1S; 3680 input_size_in_bits = EVEX_32bit; 3681 } 3682 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3683 } 3684 3685 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3686 assert(VM_Version::supports_avx(), ""); 3687 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3688 } 3689 3690 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 3691 assert(VM_Version::supports_avx(), ""); 3692 if (VM_Version::supports_evex()) { 3693 tuple_type = EVEX_T1S; 3694 input_size_in_bits = EVEX_64bit; 3695 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3696 } else { 3697 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3698 } 3699 } 3700 3701 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3702 assert(VM_Version::supports_avx(), ""); 3703 if (VM_Version::supports_evex()) { 3704 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3705 } else { 3706 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3707 } 3708 } 3709 3710 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 3711 assert(VM_Version::supports_avx(), ""); 3712 if (VM_Version::supports_evex()) { 3713 tuple_type = EVEX_T1S; 3714 input_size_in_bits = EVEX_32bit; 3715 } 3716 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3717 } 3718 3719 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3720 assert(VM_Version::supports_avx(), ""); 3721 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3722 } 3723 3724 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 3725 assert(VM_Version::supports_avx(), ""); 3726 if (VM_Version::supports_evex()) { 3727 tuple_type = EVEX_T1S; 3728 input_size_in_bits = EVEX_64bit; 3729 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3730 } else { 3731 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3732 } 3733 } 3734 3735 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3736 assert(VM_Version::supports_avx(), ""); 3737 if (VM_Version::supports_evex()) { 3738 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3739 } else { 3740 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3741 } 3742 } 3743 3744 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 3745 assert(VM_Version::supports_avx(), ""); 3746 if (VM_Version::supports_evex()) { 3747 tuple_type = EVEX_T1S; 3748 input_size_in_bits = EVEX_32bit; 3749 } 3750 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3751 } 3752 3753 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3754 assert(VM_Version::supports_avx(), ""); 3755 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3756 } 3757 3758 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 3759 assert(VM_Version::supports_avx(), ""); 3760 if (VM_Version::supports_evex()) { 3761 tuple_type = EVEX_T1S; 3762 input_size_in_bits = EVEX_64bit; 3763 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3764 } else { 3765 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3766 } 3767 } 3768 3769 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3770 assert(VM_Version::supports_avx(), ""); 3771 if (VM_Version::supports_evex()) { 3772 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3773 } else { 3774 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit); 3775 } 3776 } 3777 3778 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 3779 assert(VM_Version::supports_avx(), ""); 3780 if (VM_Version::supports_evex()) { 3781 tuple_type = EVEX_T1S; 3782 input_size_in_bits = EVEX_32bit; 3783 } 3784 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3785 } 3786 3787 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 3788 assert(VM_Version::supports_avx(), ""); 3789 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit); 3790 } 3791 3792 //====================VECTOR ARITHMETIC===================================== 3793 3794 // Float-point vector arithmetic 3795 3796 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 3797 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3798 if (VM_Version::supports_evex()) { 3799 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66); 3800 } else { 3801 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); 3802 } 3803 } 3804 3805 void Assembler::addps(XMMRegister dst, XMMRegister src) { 3806 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3807 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); 3808 } 3809 3810 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3811 assert(VM_Version::supports_avx(), ""); 3812 if (VM_Version::supports_evex()) { 3813 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len); 3814 } else { 3815 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len); 3816 } 3817 } 3818 3819 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3820 assert(VM_Version::supports_avx(), ""); 3821 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len); 3822 } 3823 3824 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3825 assert(VM_Version::supports_avx(), ""); 3826 if (VM_Version::supports_evex()) { 3827 tuple_type = EVEX_FV; 3828 input_size_in_bits = EVEX_64bit; 3829 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len); 3830 } else { 3831 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len); 3832 } 3833 } 3834 3835 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3836 assert(VM_Version::supports_avx(), ""); 3837 if (VM_Version::supports_evex()) { 3838 tuple_type = EVEX_FV; 3839 input_size_in_bits = EVEX_32bit; 3840 } 3841 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len); 3842 } 3843 3844 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 3845 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3846 if (VM_Version::supports_evex()) { 3847 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66); 3848 } else { 3849 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); 3850 } 3851 } 3852 3853 void Assembler::subps(XMMRegister dst, XMMRegister src) { 3854 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3855 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); 3856 } 3857 3858 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3859 assert(VM_Version::supports_avx(), ""); 3860 if (VM_Version::supports_evex()) { 3861 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len); 3862 } else { 3863 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len); 3864 } 3865 } 3866 3867 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3868 assert(VM_Version::supports_avx(), ""); 3869 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len); 3870 } 3871 3872 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3873 assert(VM_Version::supports_avx(), ""); 3874 if (VM_Version::supports_evex()) { 3875 tuple_type = EVEX_FV; 3876 input_size_in_bits = EVEX_64bit; 3877 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len); 3878 } else { 3879 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len); 3880 } 3881 } 3882 3883 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3884 assert(VM_Version::supports_avx(), ""); 3885 if (VM_Version::supports_evex()) { 3886 tuple_type = EVEX_FV; 3887 input_size_in_bits = EVEX_32bit; 3888 } 3889 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len); 3890 } 3891 3892 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 3893 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3894 if (VM_Version::supports_evex()) { 3895 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66); 3896 } else { 3897 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); 3898 } 3899 } 3900 3901 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 3902 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3903 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); 3904 } 3905 3906 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3907 assert(VM_Version::supports_avx(), ""); 3908 if (VM_Version::supports_evex()) { 3909 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len); 3910 } else { 3911 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len); 3912 } 3913 } 3914 3915 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3916 assert(VM_Version::supports_avx(), ""); 3917 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len); 3918 } 3919 3920 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3921 assert(VM_Version::supports_avx(), ""); 3922 if (VM_Version::supports_evex()) { 3923 tuple_type = EVEX_FV; 3924 input_size_in_bits = EVEX_64bit; 3925 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len); 3926 } else { 3927 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len); 3928 } 3929 } 3930 3931 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3932 assert(VM_Version::supports_avx(), ""); 3933 if (VM_Version::supports_evex()) { 3934 tuple_type = EVEX_FV; 3935 input_size_in_bits = EVEX_32bit; 3936 } 3937 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len); 3938 } 3939 3940 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 3941 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3942 if (VM_Version::supports_evex()) { 3943 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66); 3944 } else { 3945 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); 3946 } 3947 } 3948 3949 void Assembler::divps(XMMRegister dst, XMMRegister src) { 3950 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3951 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); 3952 } 3953 3954 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3955 assert(VM_Version::supports_avx(), ""); 3956 if (VM_Version::supports_evex()) { 3957 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len); 3958 } else { 3959 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len); 3960 } 3961 } 3962 3963 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3964 assert(VM_Version::supports_avx(), ""); 3965 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len); 3966 } 3967 3968 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3969 assert(VM_Version::supports_avx(), ""); 3970 if (VM_Version::supports_evex()) { 3971 tuple_type = EVEX_FV; 3972 input_size_in_bits = EVEX_64bit; 3973 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len); 3974 } else { 3975 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len); 3976 } 3977 } 3978 3979 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3980 assert(VM_Version::supports_avx(), ""); 3981 if (VM_Version::supports_evex()) { 3982 tuple_type = EVEX_FV; 3983 input_size_in_bits = EVEX_32bit; 3984 } 3985 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len); 3986 } 3987 3988 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 3989 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3990 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 3991 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66); 3992 } else { 3993 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true); 3994 } 3995 } 3996 3997 void Assembler::andps(XMMRegister dst, XMMRegister src) { 3998 NOT_LP64(assert(VM_Version::supports_sse(), "")); 3999 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false, 4000 (VM_Version::supports_avx512dq() == false)); 4001 } 4002 4003 void Assembler::andps(XMMRegister dst, Address src) { 4004 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4005 if (VM_Version::supports_evex()) { 4006 tuple_type = EVEX_FV; 4007 input_size_in_bits = EVEX_32bit; 4008 } 4009 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, 4010 false, (VM_Version::supports_avx512dq() == false)); 4011 } 4012 4013 void Assembler::andpd(XMMRegister dst, Address src) { 4014 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4015 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4016 tuple_type = EVEX_FV; 4017 input_size_in_bits = EVEX_64bit; 4018 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66); 4019 } else { 4020 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true); 4021 } 4022 } 4023 4024 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4025 assert(VM_Version::supports_avx(), ""); 4026 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4027 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len); 4028 } else { 4029 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true); 4030 } 4031 } 4032 4033 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4034 assert(VM_Version::supports_avx(), ""); 4035 bool legacy_mode = (VM_Version::supports_avx512dq() == false); 4036 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode); 4037 } 4038 4039 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4040 assert(VM_Version::supports_avx(), ""); 4041 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4042 tuple_type = EVEX_FV; 4043 input_size_in_bits = EVEX_64bit; 4044 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len); 4045 } else { 4046 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true); 4047 } 4048 } 4049 4050 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4051 assert(VM_Version::supports_avx(), ""); 4052 if (VM_Version::supports_evex()) { 4053 tuple_type = EVEX_FV; 4054 input_size_in_bits = EVEX_32bit; 4055 } 4056 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, 4057 (VM_Version::supports_avx512dq() == false)); 4058 } 4059 4060 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 4061 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4062 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4063 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66); 4064 } else { 4065 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true); 4066 } 4067 } 4068 4069 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 4070 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4071 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, 4072 false, (VM_Version::supports_avx512dq() == false)); 4073 } 4074 4075 void Assembler::xorpd(XMMRegister dst, Address src) { 4076 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4077 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4078 tuple_type = EVEX_FV; 4079 input_size_in_bits = EVEX_64bit; 4080 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66); 4081 } else { 4082 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true); 4083 } 4084 } 4085 4086 void Assembler::xorps(XMMRegister dst, Address src) { 4087 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4088 if (VM_Version::supports_evex()) { 4089 tuple_type = EVEX_FV; 4090 input_size_in_bits = EVEX_32bit; 4091 } 4092 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false, 4093 (VM_Version::supports_avx512dq() == false)); 4094 } 4095 4096 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4097 assert(VM_Version::supports_avx(), ""); 4098 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4099 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len); 4100 } else { 4101 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true); 4102 } 4103 } 4104 4105 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4106 assert(VM_Version::supports_avx(), ""); 4107 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, 4108 (VM_Version::supports_avx512dq() == false)); 4109 } 4110 4111 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4112 assert(VM_Version::supports_avx(), ""); 4113 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { 4114 tuple_type = EVEX_FV; 4115 input_size_in_bits = EVEX_64bit; 4116 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len); 4117 } else { 4118 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true); 4119 } 4120 } 4121 4122 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4123 assert(VM_Version::supports_avx(), ""); 4124 if (VM_Version::supports_evex()) { 4125 tuple_type = EVEX_FV; 4126 input_size_in_bits = EVEX_32bit; 4127 } 4128 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len, 4129 (VM_Version::supports_avx512dq() == false)); 4130 } 4131 4132 // Integer vector arithmetic 4133 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4134 assert(VM_Version::supports_avx() && (vector_len == 0) || 4135 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 4136 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, 4137 VEX_OPCODE_0F_38, true, false); 4138 emit_int8(0x01); 4139 emit_int8((unsigned char)(0xC0 | encode)); 4140 } 4141 4142 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4143 assert(VM_Version::supports_avx() && (vector_len == 0) || 4144 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 4145 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, 4146 VEX_OPCODE_0F_38, true, false); 4147 emit_int8(0x02); 4148 emit_int8((unsigned char)(0xC0 | encode)); 4149 } 4150 4151 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 4152 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4153 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); 4154 } 4155 4156 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 4157 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4158 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); 4159 } 4160 4161 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 4162 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4163 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); 4164 } 4165 4166 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 4167 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4168 if (VM_Version::supports_evex()) { 4169 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66); 4170 } else { 4171 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); 4172 } 4173 } 4174 4175 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 4176 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 4177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 4178 VEX_OPCODE_0F_38, false, AVX_128bit, true); 4179 emit_int8(0x01); 4180 emit_int8((unsigned char)(0xC0 | encode)); 4181 } 4182 4183 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 4184 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 4185 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 4186 VEX_OPCODE_0F_38, false, AVX_128bit, true); 4187 emit_int8(0x02); 4188 emit_int8((unsigned char)(0xC0 | encode)); 4189 } 4190 4191 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4192 assert(UseAVX > 0, "requires some form of AVX"); 4193 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len, 4194 (VM_Version::supports_avx512bw() == false)); 4195 } 4196 4197 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4198 assert(UseAVX > 0, "requires some form of AVX"); 4199 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len, 4200 (VM_Version::supports_avx512bw() == false)); 4201 } 4202 4203 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4204 assert(UseAVX > 0, "requires some form of AVX"); 4205 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len); 4206 } 4207 4208 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4209 assert(UseAVX > 0, "requires some form of AVX"); 4210 if (VM_Version::supports_evex()) { 4211 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len); 4212 } else { 4213 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len); 4214 } 4215 } 4216 4217 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4218 assert(UseAVX > 0, "requires some form of AVX"); 4219 if (VM_Version::supports_evex()) { 4220 tuple_type = EVEX_FVM; 4221 } 4222 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len); 4223 } 4224 4225 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4226 assert(UseAVX > 0, "requires some form of AVX"); 4227 if (VM_Version::supports_evex()) { 4228 tuple_type = EVEX_FVM; 4229 } 4230 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len); 4231 } 4232 4233 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4234 assert(UseAVX > 0, "requires some form of AVX"); 4235 if (VM_Version::supports_evex()) { 4236 tuple_type = EVEX_FV; 4237 input_size_in_bits = EVEX_32bit; 4238 } 4239 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len); 4240 } 4241 4242 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4243 assert(UseAVX > 0, "requires some form of AVX"); 4244 if (VM_Version::supports_evex()) { 4245 tuple_type = EVEX_FV; 4246 input_size_in_bits = EVEX_64bit; 4247 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len); 4248 } else { 4249 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len); 4250 } 4251 } 4252 4253 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 4254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4255 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); 4256 } 4257 4258 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 4259 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4260 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); 4261 } 4262 4263 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 4264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4265 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); 4266 } 4267 4268 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 4269 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4270 if (VM_Version::supports_evex()) { 4271 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66); 4272 } else { 4273 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); 4274 } 4275 } 4276 4277 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4278 assert(UseAVX > 0, "requires some form of AVX"); 4279 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, 4280 (VM_Version::supports_avx512bw() == false)); 4281 } 4282 4283 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4284 assert(UseAVX > 0, "requires some form of AVX"); 4285 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, 4286 (VM_Version::supports_avx512bw() == false)); 4287 } 4288 4289 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4290 assert(UseAVX > 0, "requires some form of AVX"); 4291 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len); 4292 } 4293 4294 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4295 assert(UseAVX > 0, "requires some form of AVX"); 4296 if (VM_Version::supports_evex()) { 4297 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len); 4298 } else { 4299 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len); 4300 } 4301 } 4302 4303 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4304 assert(UseAVX > 0, "requires some form of AVX"); 4305 if (VM_Version::supports_evex()) { 4306 tuple_type = EVEX_FVM; 4307 } 4308 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len, 4309 (VM_Version::supports_avx512bw() == false)); 4310 } 4311 4312 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4313 assert(UseAVX > 0, "requires some form of AVX"); 4314 if (VM_Version::supports_evex()) { 4315 tuple_type = EVEX_FVM; 4316 } 4317 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len, 4318 (VM_Version::supports_avx512bw() == false)); 4319 } 4320 4321 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4322 assert(UseAVX > 0, "requires some form of AVX"); 4323 if (VM_Version::supports_evex()) { 4324 tuple_type = EVEX_FV; 4325 input_size_in_bits = EVEX_32bit; 4326 } 4327 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len); 4328 } 4329 4330 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4331 assert(UseAVX > 0, "requires some form of AVX"); 4332 if (VM_Version::supports_evex()) { 4333 tuple_type = EVEX_FV; 4334 input_size_in_bits = EVEX_64bit; 4335 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len); 4336 } else { 4337 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len); 4338 } 4339 } 4340 4341 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 4342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4343 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66, 4344 (VM_Version::supports_avx512bw() == false)); 4345 } 4346 4347 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 4348 assert(VM_Version::supports_sse4_1(), ""); 4349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, 4350 false, VEX_OPCODE_0F_38); 4351 emit_int8(0x40); 4352 emit_int8((unsigned char)(0xC0 | encode)); 4353 } 4354 4355 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4356 assert(UseAVX > 0, "requires some form of AVX"); 4357 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len, 4358 (VM_Version::supports_avx512bw() == false)); 4359 } 4360 4361 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4362 assert(UseAVX > 0, "requires some form of AVX"); 4363 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, 4364 vector_len, VEX_OPCODE_0F_38); 4365 emit_int8(0x40); 4366 emit_int8((unsigned char)(0xC0 | encode)); 4367 } 4368 4369 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4370 assert(UseAVX > 2, "requires some form of AVX"); 4371 int src_enc = src->encoding(); 4372 int dst_enc = dst->encoding(); 4373 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 4374 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, 4375 VEX_OPCODE_0F_38, true, vector_len, false, false); 4376 emit_int8(0x40); 4377 emit_int8((unsigned char)(0xC0 | encode)); 4378 } 4379 4380 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4381 assert(UseAVX > 0, "requires some form of AVX"); 4382 if (VM_Version::supports_evex()) { 4383 tuple_type = EVEX_FVM; 4384 } 4385 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len); 4386 } 4387 4388 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4389 assert(UseAVX > 0, "requires some form of AVX"); 4390 if (VM_Version::supports_evex()) { 4391 tuple_type = EVEX_FV; 4392 input_size_in_bits = EVEX_32bit; 4393 } 4394 InstructionMark im(this); 4395 int dst_enc = dst->encoding(); 4396 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 4397 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, 4398 VEX_OPCODE_0F_38, false, vector_len); 4399 emit_int8(0x40); 4400 emit_operand(dst, src); 4401 } 4402 4403 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4404 assert(UseAVX > 0, "requires some form of AVX"); 4405 if (VM_Version::supports_evex()) { 4406 tuple_type = EVEX_FV; 4407 input_size_in_bits = EVEX_64bit; 4408 } 4409 InstructionMark im(this); 4410 int dst_enc = dst->encoding(); 4411 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 4412 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len); 4413 emit_int8(0x40); 4414 emit_operand(dst, src); 4415 } 4416 4417 // Shift packed integers left by specified number of bits. 4418 void Assembler::psllw(XMMRegister dst, int shift) { 4419 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4420 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 4421 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, 4422 false, AVX_128bit, (VM_Version::supports_avx512bw() == false)); 4423 emit_int8(0x71); 4424 emit_int8((unsigned char)(0xC0 | encode)); 4425 emit_int8(shift & 0xFF); 4426 } 4427 4428 void Assembler::pslld(XMMRegister dst, int shift) { 4429 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4430 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 4431 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false); 4432 emit_int8(0x72); 4433 emit_int8((unsigned char)(0xC0 | encode)); 4434 emit_int8(shift & 0xFF); 4435 } 4436 4437 void Assembler::psllq(XMMRegister dst, int shift) { 4438 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4439 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 4440 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true); 4441 emit_int8(0x73); 4442 emit_int8((unsigned char)(0xC0 | encode)); 4443 emit_int8(shift & 0xFF); 4444 } 4445 4446 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 4447 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4448 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false, 4449 (VM_Version::supports_avx512bw() == false)); 4450 } 4451 4452 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 4453 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4454 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); 4455 } 4456 4457 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 4458 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4459 if (VM_Version::supports_evex()) { 4460 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66); 4461 } else { 4462 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); 4463 } 4464 } 4465 4466 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4467 assert(UseAVX > 0, "requires some form of AVX"); 4468 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 4469 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len, 4470 (VM_Version::supports_avx512bw() == false)); 4471 emit_int8(shift & 0xFF); 4472 } 4473 4474 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4475 assert(UseAVX > 0, "requires some form of AVX"); 4476 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 4477 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len); 4478 emit_int8(shift & 0xFF); 4479 } 4480 4481 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4482 assert(UseAVX > 0, "requires some form of AVX"); 4483 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 4484 if (VM_Version::supports_evex()) { 4485 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len); 4486 } else { 4487 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len); 4488 } 4489 emit_int8(shift & 0xFF); 4490 } 4491 4492 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4493 assert(UseAVX > 0, "requires some form of AVX"); 4494 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len, 4495 (VM_Version::supports_avx512bw() == false)); 4496 } 4497 4498 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4499 assert(UseAVX > 0, "requires some form of AVX"); 4500 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len); 4501 } 4502 4503 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4504 assert(UseAVX > 0, "requires some form of AVX"); 4505 if (VM_Version::supports_evex()) { 4506 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len); 4507 } else { 4508 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len); 4509 } 4510 } 4511 4512 // Shift packed integers logically right by specified number of bits. 4513 void Assembler::psrlw(XMMRegister dst, int shift) { 4514 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4515 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 4516 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, 4517 (VM_Version::supports_avx512bw() == false)); 4518 emit_int8(0x71); 4519 emit_int8((unsigned char)(0xC0 | encode)); 4520 emit_int8(shift & 0xFF); 4521 } 4522 4523 void Assembler::psrld(XMMRegister dst, int shift) { 4524 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4525 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 4526 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false); 4527 emit_int8(0x72); 4528 emit_int8((unsigned char)(0xC0 | encode)); 4529 emit_int8(shift & 0xFF); 4530 } 4531 4532 void Assembler::psrlq(XMMRegister dst, int shift) { 4533 // Do not confuse it with psrldq SSE2 instruction which 4534 // shifts 128 bit value in xmm register by number of bytes. 4535 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4536 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 4537 int encode = 0; 4538 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) { 4539 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false); 4540 } else { 4541 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true); 4542 } 4543 emit_int8(0x73); 4544 emit_int8((unsigned char)(0xC0 | encode)); 4545 emit_int8(shift & 0xFF); 4546 } 4547 4548 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 4549 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4550 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false, 4551 (VM_Version::supports_avx512bw() == false)); 4552 } 4553 4554 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 4555 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4556 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); 4557 } 4558 4559 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 4560 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4561 if (VM_Version::supports_evex()) { 4562 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66); 4563 } else { 4564 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); 4565 } 4566 } 4567 4568 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4569 assert(UseAVX > 0, "requires some form of AVX"); 4570 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 4571 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len, 4572 (VM_Version::supports_avx512bw() == false)); 4573 emit_int8(shift & 0xFF); 4574 } 4575 4576 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4577 assert(UseAVX > 0, "requires some form of AVX"); 4578 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 4579 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len); 4580 emit_int8(shift & 0xFF); 4581 } 4582 4583 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4584 assert(UseAVX > 0, "requires some form of AVX"); 4585 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 4586 if (VM_Version::supports_evex()) { 4587 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len); 4588 } else { 4589 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len); 4590 } 4591 emit_int8(shift & 0xFF); 4592 } 4593 4594 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4595 assert(UseAVX > 0, "requires some form of AVX"); 4596 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len, 4597 (VM_Version::supports_avx512bw() == false)); 4598 } 4599 4600 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4601 assert(UseAVX > 0, "requires some form of AVX"); 4602 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len); 4603 } 4604 4605 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4606 assert(UseAVX > 0, "requires some form of AVX"); 4607 if (VM_Version::supports_evex()) { 4608 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len); 4609 } else { 4610 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len); 4611 } 4612 } 4613 4614 // Shift packed integers arithmetically right by specified number of bits. 4615 void Assembler::psraw(XMMRegister dst, int shift) { 4616 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4617 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 4618 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, 4619 (VM_Version::supports_avx512bw() == false)); 4620 emit_int8(0x71); 4621 emit_int8((unsigned char)(0xC0 | encode)); 4622 emit_int8(shift & 0xFF); 4623 } 4624 4625 void Assembler::psrad(XMMRegister dst, int shift) { 4626 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4627 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 4628 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false); 4629 emit_int8(0x72); 4630 emit_int8((unsigned char)(0xC0 | encode)); 4631 emit_int8(shift & 0xFF); 4632 } 4633 4634 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 4635 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4636 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66, 4637 (VM_Version::supports_avx512bw() == false)); 4638 } 4639 4640 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 4641 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4642 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); 4643 } 4644 4645 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4646 assert(UseAVX > 0, "requires some form of AVX"); 4647 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 4648 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len, 4649 (VM_Version::supports_avx512bw() == false)); 4650 emit_int8(shift & 0xFF); 4651 } 4652 4653 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 4654 assert(UseAVX > 0, "requires some form of AVX"); 4655 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 4656 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len); 4657 emit_int8(shift & 0xFF); 4658 } 4659 4660 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4661 assert(UseAVX > 0, "requires some form of AVX"); 4662 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len, 4663 (VM_Version::supports_avx512bw() == false)); 4664 } 4665 4666 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 4667 assert(UseAVX > 0, "requires some form of AVX"); 4668 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len); 4669 } 4670 4671 4672 // AND packed integers 4673 void Assembler::pand(XMMRegister dst, XMMRegister src) { 4674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4675 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); 4676 } 4677 4678 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4679 assert(UseAVX > 0, "requires some form of AVX"); 4680 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len); 4681 } 4682 4683 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4684 assert(UseAVX > 0, "requires some form of AVX"); 4685 if (VM_Version::supports_evex()) { 4686 tuple_type = EVEX_FV; 4687 input_size_in_bits = EVEX_32bit; 4688 } 4689 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len); 4690 } 4691 4692 void Assembler::por(XMMRegister dst, XMMRegister src) { 4693 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4694 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); 4695 } 4696 4697 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4698 assert(UseAVX > 0, "requires some form of AVX"); 4699 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len); 4700 } 4701 4702 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4703 assert(UseAVX > 0, "requires some form of AVX"); 4704 if (VM_Version::supports_evex()) { 4705 tuple_type = EVEX_FV; 4706 input_size_in_bits = EVEX_32bit; 4707 } 4708 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len); 4709 } 4710 4711 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 4712 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4713 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); 4714 } 4715 4716 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4717 assert(UseAVX > 0, "requires some form of AVX"); 4718 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len); 4719 } 4720 4721 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4722 assert(UseAVX > 0, "requires some form of AVX"); 4723 if (VM_Version::supports_evex()) { 4724 tuple_type = EVEX_FV; 4725 input_size_in_bits = EVEX_32bit; 4726 } 4727 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len); 4728 } 4729 4730 4731 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4732 assert(VM_Version::supports_avx(), ""); 4733 int vector_len = AVX_256bit; 4734 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A); 4735 emit_int8(0x18); 4736 emit_int8((unsigned char)(0xC0 | encode)); 4737 // 0x00 - insert into lower 128 bits 4738 // 0x01 - insert into upper 128 bits 4739 emit_int8(0x01); 4740 } 4741 4742 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4743 assert(VM_Version::supports_evex(), ""); 4744 int vector_len = AVX_512bit; 4745 int src_enc = src->encoding(); 4746 int dst_enc = dst->encoding(); 4747 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 4748 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, 4749 VEX_OPCODE_0F_3A, true, vector_len, false, false); 4750 emit_int8(0x1A); 4751 emit_int8((unsigned char)(0xC0 | encode)); 4752 // 0x00 - insert into lower 256 bits 4753 // 0x01 - insert into upper 256 bits 4754 emit_int8(0x01); 4755 } 4756 4757 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) { 4758 assert(VM_Version::supports_avx(), ""); 4759 if (VM_Version::supports_evex()) { 4760 tuple_type = EVEX_T4; 4761 input_size_in_bits = EVEX_64bit; 4762 } 4763 InstructionMark im(this); 4764 int vector_len = AVX_512bit; 4765 assert(dst != xnoreg, "sanity"); 4766 int dst_enc = dst->encoding(); 4767 // swap src<->dst for encoding 4768 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len); 4769 emit_int8(0x1A); 4770 emit_operand(dst, src); 4771 // 0x01 - insert into upper 128 bits 4772 emit_int8(0x01); 4773 } 4774 4775 void Assembler::vinsertf128h(XMMRegister dst, Address src) { 4776 assert(VM_Version::supports_avx(), ""); 4777 if (VM_Version::supports_evex()) { 4778 tuple_type = EVEX_T4; 4779 input_size_in_bits = EVEX_32bit; 4780 } 4781 InstructionMark im(this); 4782 int vector_len = AVX_256bit; 4783 assert(dst != xnoreg, "sanity"); 4784 int dst_enc = dst->encoding(); 4785 // swap src<->dst for encoding 4786 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len); 4787 emit_int8(0x18); 4788 emit_operand(dst, src); 4789 // 0x01 - insert into upper 128 bits 4790 emit_int8(0x01); 4791 } 4792 4793 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) { 4794 assert(VM_Version::supports_avx(), ""); 4795 int vector_len = AVX_256bit; 4796 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A); 4797 emit_int8(0x19); 4798 emit_int8((unsigned char)(0xC0 | encode)); 4799 // 0x00 - insert into lower 128 bits 4800 // 0x01 - insert into upper 128 bits 4801 emit_int8(0x01); 4802 } 4803 4804 void Assembler::vextractf128h(Address dst, XMMRegister src) { 4805 assert(VM_Version::supports_avx(), ""); 4806 if (VM_Version::supports_evex()) { 4807 tuple_type = EVEX_T4; 4808 input_size_in_bits = EVEX_32bit; 4809 } 4810 InstructionMark im(this); 4811 int vector_len = AVX_256bit; 4812 assert(src != xnoreg, "sanity"); 4813 int src_enc = src->encoding(); 4814 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len); 4815 emit_int8(0x19); 4816 emit_operand(src, dst); 4817 // 0x01 - extract from upper 128 bits 4818 emit_int8(0x01); 4819 } 4820 4821 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4822 assert(VM_Version::supports_avx2(), ""); 4823 int vector_len = AVX_256bit; 4824 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A); 4825 emit_int8(0x38); 4826 emit_int8((unsigned char)(0xC0 | encode)); 4827 // 0x00 - insert into lower 128 bits 4828 // 0x01 - insert into upper 128 bits 4829 emit_int8(0x01); 4830 } 4831 4832 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4833 assert(VM_Version::supports_evex(), ""); 4834 int vector_len = AVX_512bit; 4835 int src_enc = src->encoding(); 4836 int dst_enc = dst->encoding(); 4837 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 4838 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4839 VM_Version::supports_avx512dq(), vector_len, false, false); 4840 emit_int8(0x38); 4841 emit_int8((unsigned char)(0xC0 | encode)); 4842 // 0x00 - insert into lower 256 bits 4843 // 0x01 - insert into upper 256 bits 4844 emit_int8(0x01); 4845 } 4846 4847 void Assembler::vinserti128h(XMMRegister dst, Address src) { 4848 assert(VM_Version::supports_avx2(), ""); 4849 if (VM_Version::supports_evex()) { 4850 tuple_type = EVEX_T4; 4851 input_size_in_bits = EVEX_32bit; 4852 } 4853 InstructionMark im(this); 4854 int vector_len = AVX_256bit; 4855 assert(dst != xnoreg, "sanity"); 4856 int dst_enc = dst->encoding(); 4857 // swap src<->dst for encoding 4858 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len); 4859 emit_int8(0x38); 4860 emit_operand(dst, src); 4861 // 0x01 - insert into upper 128 bits 4862 emit_int8(0x01); 4863 } 4864 4865 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) { 4866 assert(VM_Version::supports_avx(), ""); 4867 int vector_len = AVX_256bit; 4868 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A); 4869 emit_int8(0x39); 4870 emit_int8((unsigned char)(0xC0 | encode)); 4871 // 0x00 - insert into lower 128 bits 4872 // 0x01 - insert into upper 128 bits 4873 emit_int8(0x01); 4874 } 4875 4876 void Assembler::vextracti128h(Address dst, XMMRegister src) { 4877 assert(VM_Version::supports_avx2(), ""); 4878 if (VM_Version::supports_evex()) { 4879 tuple_type = EVEX_T4; 4880 input_size_in_bits = EVEX_32bit; 4881 } 4882 InstructionMark im(this); 4883 int vector_len = AVX_256bit; 4884 assert(src != xnoreg, "sanity"); 4885 int src_enc = src->encoding(); 4886 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len); 4887 emit_int8(0x39); 4888 emit_operand(src, dst); 4889 // 0x01 - extract from upper 128 bits 4890 emit_int8(0x01); 4891 } 4892 4893 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) { 4894 assert(VM_Version::supports_evex(), ""); 4895 int vector_len = AVX_512bit; 4896 int src_enc = src->encoding(); 4897 int dst_enc = dst->encoding(); 4898 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4899 true, vector_len, false, false); 4900 emit_int8(0x3B); 4901 emit_int8((unsigned char)(0xC0 | encode)); 4902 // 0x01 - extract from upper 256 bits 4903 emit_int8(0x01); 4904 } 4905 4906 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) { 4907 assert(VM_Version::supports_evex(), ""); 4908 int vector_len = AVX_512bit; 4909 int src_enc = src->encoding(); 4910 int dst_enc = dst->encoding(); 4911 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4912 VM_Version::supports_avx512dq(), vector_len, false, false); 4913 emit_int8(0x39); 4914 emit_int8((unsigned char)(0xC0 | encode)); 4915 // 0x01 - extract from bits 255:128 4916 // 0x02 - extract from bits 383:256 4917 // 0x03 - extract from bits 511:384 4918 emit_int8(value & 0x3); 4919 } 4920 4921 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) { 4922 assert(VM_Version::supports_evex(), ""); 4923 int vector_len = AVX_512bit; 4924 int src_enc = src->encoding(); 4925 int dst_enc = dst->encoding(); 4926 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4927 VM_Version::supports_avx512dq(), vector_len, false, false); 4928 emit_int8(0x1B); 4929 emit_int8((unsigned char)(0xC0 | encode)); 4930 // 0x01 - extract from upper 256 bits 4931 emit_int8(0x01); 4932 } 4933 4934 void Assembler::vextractf64x4h(Address dst, XMMRegister src) { 4935 assert(VM_Version::supports_avx2(), ""); 4936 tuple_type = EVEX_T4; 4937 input_size_in_bits = EVEX_64bit; 4938 InstructionMark im(this); 4939 int vector_len = AVX_512bit; 4940 assert(src != xnoreg, "sanity"); 4941 int src_enc = src->encoding(); 4942 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4943 VM_Version::supports_avx512dq(), vector_len); 4944 emit_int8(0x1B); 4945 emit_operand(src, dst); 4946 // 0x01 - extract from upper 128 bits 4947 emit_int8(0x01); 4948 } 4949 4950 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) { 4951 assert(VM_Version::supports_evex(), ""); 4952 int vector_len = AVX_512bit; 4953 int src_enc = src->encoding(); 4954 int dst_enc = dst->encoding(); 4955 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, 4956 VEX_OPCODE_0F_3A, false, vector_len, false, false); 4957 emit_int8(0x19); 4958 emit_int8((unsigned char)(0xC0 | encode)); 4959 // 0x01 - extract from bits 255:128 4960 // 0x02 - extract from bits 383:256 4961 // 0x03 - extract from bits 511:384 4962 emit_int8(value & 0x3); 4963 } 4964 4965 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) { 4966 assert(VM_Version::supports_evex(), ""); 4967 int vector_len = AVX_512bit; 4968 int src_enc = src->encoding(); 4969 int dst_enc = dst->encoding(); 4970 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, 4971 VM_Version::supports_avx512dq(), vector_len, false, false); 4972 emit_int8(0x19); 4973 emit_int8((unsigned char)(0xC0 | encode)); 4974 // 0x01 - extract from bits 255:128 4975 // 0x02 - extract from bits 383:256 4976 // 0x03 - extract from bits 511:384 4977 emit_int8(value & 0x3); 4978 } 4979 4980 // duplicate 4-bytes integer data from src into 8 locations in dest 4981 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { 4982 assert(VM_Version::supports_avx2(), ""); 4983 int vector_len = AVX_256bit; 4984 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, 4985 vector_len, VEX_OPCODE_0F_38, false); 4986 emit_int8(0x58); 4987 emit_int8((unsigned char)(0xC0 | encode)); 4988 } 4989 4990 // duplicate 4-bytes integer data from src into 8 locations in dest 4991 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 4992 assert(VM_Version::supports_evex(), ""); 4993 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, 4994 vector_len, VEX_OPCODE_0F_38, false); 4995 emit_int8(0x58); 4996 emit_int8((unsigned char)(0xC0 | encode)); 4997 } 4998 4999 // Carry-Less Multiplication Quadword 5000 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 5001 assert(VM_Version::supports_clmul(), ""); 5002 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, 5003 VEX_OPCODE_0F_3A, false, AVX_128bit, true); 5004 emit_int8(0x44); 5005 emit_int8((unsigned char)(0xC0 | encode)); 5006 emit_int8((unsigned char)mask); 5007 } 5008 5009 // Carry-Less Multiplication Quadword 5010 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 5011 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 5012 int vector_len = AVX_128bit; 5013 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, 5014 vector_len, VEX_OPCODE_0F_3A, true); 5015 emit_int8(0x44); 5016 emit_int8((unsigned char)(0xC0 | encode)); 5017 emit_int8((unsigned char)mask); 5018 } 5019 5020 void Assembler::vzeroupper() { 5021 assert(VM_Version::supports_avx(), ""); 5022 if (UseAVX < 3) 5023 { 5024 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); 5025 emit_int8(0x77); 5026 } 5027 } 5028 5029 5030 #ifndef _LP64 5031 // 32bit only pieces of the assembler 5032 5033 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 5034 // NO PREFIX AS NEVER 64BIT 5035 InstructionMark im(this); 5036 emit_int8((unsigned char)0x81); 5037 emit_int8((unsigned char)(0xF8 | src1->encoding())); 5038 emit_data(imm32, rspec, 0); 5039 } 5040 5041 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 5042 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 5043 InstructionMark im(this); 5044 emit_int8((unsigned char)0x81); 5045 emit_operand(rdi, src1); 5046 emit_data(imm32, rspec, 0); 5047 } 5048 5049 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 5050 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 5051 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 5052 void Assembler::cmpxchg8(Address adr) { 5053 InstructionMark im(this); 5054 emit_int8(0x0F); 5055 emit_int8((unsigned char)0xC7); 5056 emit_operand(rcx, adr); 5057 } 5058 5059 void Assembler::decl(Register dst) { 5060 // Don't use it directly. Use MacroAssembler::decrementl() instead. 5061 emit_int8(0x48 | dst->encoding()); 5062 } 5063 5064 #endif // _LP64 5065 5066 // 64bit typically doesn't use the x87 but needs to for the trig funcs 5067 5068 void Assembler::fabs() { 5069 emit_int8((unsigned char)0xD9); 5070 emit_int8((unsigned char)0xE1); 5071 } 5072 5073 void Assembler::fadd(int i) { 5074 emit_farith(0xD8, 0xC0, i); 5075 } 5076 5077 void Assembler::fadd_d(Address src) { 5078 InstructionMark im(this); 5079 emit_int8((unsigned char)0xDC); 5080 emit_operand32(rax, src); 5081 } 5082 5083 void Assembler::fadd_s(Address src) { 5084 InstructionMark im(this); 5085 emit_int8((unsigned char)0xD8); 5086 emit_operand32(rax, src); 5087 } 5088 5089 void Assembler::fadda(int i) { 5090 emit_farith(0xDC, 0xC0, i); 5091 } 5092 5093 void Assembler::faddp(int i) { 5094 emit_farith(0xDE, 0xC0, i); 5095 } 5096 5097 void Assembler::fchs() { 5098 emit_int8((unsigned char)0xD9); 5099 emit_int8((unsigned char)0xE0); 5100 } 5101 5102 void Assembler::fcom(int i) { 5103 emit_farith(0xD8, 0xD0, i); 5104 } 5105 5106 void Assembler::fcomp(int i) { 5107 emit_farith(0xD8, 0xD8, i); 5108 } 5109 5110 void Assembler::fcomp_d(Address src) { 5111 InstructionMark im(this); 5112 emit_int8((unsigned char)0xDC); 5113 emit_operand32(rbx, src); 5114 } 5115 5116 void Assembler::fcomp_s(Address src) { 5117 InstructionMark im(this); 5118 emit_int8((unsigned char)0xD8); 5119 emit_operand32(rbx, src); 5120 } 5121 5122 void Assembler::fcompp() { 5123 emit_int8((unsigned char)0xDE); 5124 emit_int8((unsigned char)0xD9); 5125 } 5126 5127 void Assembler::fcos() { 5128 emit_int8((unsigned char)0xD9); 5129 emit_int8((unsigned char)0xFF); 5130 } 5131 5132 void Assembler::fdecstp() { 5133 emit_int8((unsigned char)0xD9); 5134 emit_int8((unsigned char)0xF6); 5135 } 5136 5137 void Assembler::fdiv(int i) { 5138 emit_farith(0xD8, 0xF0, i); 5139 } 5140 5141 void Assembler::fdiv_d(Address src) { 5142 InstructionMark im(this); 5143 emit_int8((unsigned char)0xDC); 5144 emit_operand32(rsi, src); 5145 } 5146 5147 void Assembler::fdiv_s(Address src) { 5148 InstructionMark im(this); 5149 emit_int8((unsigned char)0xD8); 5150 emit_operand32(rsi, src); 5151 } 5152 5153 void Assembler::fdiva(int i) { 5154 emit_farith(0xDC, 0xF8, i); 5155 } 5156 5157 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 5158 // is erroneous for some of the floating-point instructions below. 5159 5160 void Assembler::fdivp(int i) { 5161 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 5162 } 5163 5164 void Assembler::fdivr(int i) { 5165 emit_farith(0xD8, 0xF8, i); 5166 } 5167 5168 void Assembler::fdivr_d(Address src) { 5169 InstructionMark im(this); 5170 emit_int8((unsigned char)0xDC); 5171 emit_operand32(rdi, src); 5172 } 5173 5174 void Assembler::fdivr_s(Address src) { 5175 InstructionMark im(this); 5176 emit_int8((unsigned char)0xD8); 5177 emit_operand32(rdi, src); 5178 } 5179 5180 void Assembler::fdivra(int i) { 5181 emit_farith(0xDC, 0xF0, i); 5182 } 5183 5184 void Assembler::fdivrp(int i) { 5185 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 5186 } 5187 5188 void Assembler::ffree(int i) { 5189 emit_farith(0xDD, 0xC0, i); 5190 } 5191 5192 void Assembler::fild_d(Address adr) { 5193 InstructionMark im(this); 5194 emit_int8((unsigned char)0xDF); 5195 emit_operand32(rbp, adr); 5196 } 5197 5198 void Assembler::fild_s(Address adr) { 5199 InstructionMark im(this); 5200 emit_int8((unsigned char)0xDB); 5201 emit_operand32(rax, adr); 5202 } 5203 5204 void Assembler::fincstp() { 5205 emit_int8((unsigned char)0xD9); 5206 emit_int8((unsigned char)0xF7); 5207 } 5208 5209 void Assembler::finit() { 5210 emit_int8((unsigned char)0x9B); 5211 emit_int8((unsigned char)0xDB); 5212 emit_int8((unsigned char)0xE3); 5213 } 5214 5215 void Assembler::fist_s(Address adr) { 5216 InstructionMark im(this); 5217 emit_int8((unsigned char)0xDB); 5218 emit_operand32(rdx, adr); 5219 } 5220 5221 void Assembler::fistp_d(Address adr) { 5222 InstructionMark im(this); 5223 emit_int8((unsigned char)0xDF); 5224 emit_operand32(rdi, adr); 5225 } 5226 5227 void Assembler::fistp_s(Address adr) { 5228 InstructionMark im(this); 5229 emit_int8((unsigned char)0xDB); 5230 emit_operand32(rbx, adr); 5231 } 5232 5233 void Assembler::fld1() { 5234 emit_int8((unsigned char)0xD9); 5235 emit_int8((unsigned char)0xE8); 5236 } 5237 5238 void Assembler::fld_d(Address adr) { 5239 InstructionMark im(this); 5240 emit_int8((unsigned char)0xDD); 5241 emit_operand32(rax, adr); 5242 } 5243 5244 void Assembler::fld_s(Address adr) { 5245 InstructionMark im(this); 5246 emit_int8((unsigned char)0xD9); 5247 emit_operand32(rax, adr); 5248 } 5249 5250 5251 void Assembler::fld_s(int index) { 5252 emit_farith(0xD9, 0xC0, index); 5253 } 5254 5255 void Assembler::fld_x(Address adr) { 5256 InstructionMark im(this); 5257 emit_int8((unsigned char)0xDB); 5258 emit_operand32(rbp, adr); 5259 } 5260 5261 void Assembler::fldcw(Address src) { 5262 InstructionMark im(this); 5263 emit_int8((unsigned char)0xD9); 5264 emit_operand32(rbp, src); 5265 } 5266 5267 void Assembler::fldenv(Address src) { 5268 InstructionMark im(this); 5269 emit_int8((unsigned char)0xD9); 5270 emit_operand32(rsp, src); 5271 } 5272 5273 void Assembler::fldlg2() { 5274 emit_int8((unsigned char)0xD9); 5275 emit_int8((unsigned char)0xEC); 5276 } 5277 5278 void Assembler::fldln2() { 5279 emit_int8((unsigned char)0xD9); 5280 emit_int8((unsigned char)0xED); 5281 } 5282 5283 void Assembler::fldz() { 5284 emit_int8((unsigned char)0xD9); 5285 emit_int8((unsigned char)0xEE); 5286 } 5287 5288 void Assembler::flog() { 5289 fldln2(); 5290 fxch(); 5291 fyl2x(); 5292 } 5293 5294 void Assembler::flog10() { 5295 fldlg2(); 5296 fxch(); 5297 fyl2x(); 5298 } 5299 5300 void Assembler::fmul(int i) { 5301 emit_farith(0xD8, 0xC8, i); 5302 } 5303 5304 void Assembler::fmul_d(Address src) { 5305 InstructionMark im(this); 5306 emit_int8((unsigned char)0xDC); 5307 emit_operand32(rcx, src); 5308 } 5309 5310 void Assembler::fmul_s(Address src) { 5311 InstructionMark im(this); 5312 emit_int8((unsigned char)0xD8); 5313 emit_operand32(rcx, src); 5314 } 5315 5316 void Assembler::fmula(int i) { 5317 emit_farith(0xDC, 0xC8, i); 5318 } 5319 5320 void Assembler::fmulp(int i) { 5321 emit_farith(0xDE, 0xC8, i); 5322 } 5323 5324 void Assembler::fnsave(Address dst) { 5325 InstructionMark im(this); 5326 emit_int8((unsigned char)0xDD); 5327 emit_operand32(rsi, dst); 5328 } 5329 5330 void Assembler::fnstcw(Address src) { 5331 InstructionMark im(this); 5332 emit_int8((unsigned char)0x9B); 5333 emit_int8((unsigned char)0xD9); 5334 emit_operand32(rdi, src); 5335 } 5336 5337 void Assembler::fnstsw_ax() { 5338 emit_int8((unsigned char)0xDF); 5339 emit_int8((unsigned char)0xE0); 5340 } 5341 5342 void Assembler::fprem() { 5343 emit_int8((unsigned char)0xD9); 5344 emit_int8((unsigned char)0xF8); 5345 } 5346 5347 void Assembler::fprem1() { 5348 emit_int8((unsigned char)0xD9); 5349 emit_int8((unsigned char)0xF5); 5350 } 5351 5352 void Assembler::frstor(Address src) { 5353 InstructionMark im(this); 5354 emit_int8((unsigned char)0xDD); 5355 emit_operand32(rsp, src); 5356 } 5357 5358 void Assembler::fsin() { 5359 emit_int8((unsigned char)0xD9); 5360 emit_int8((unsigned char)0xFE); 5361 } 5362 5363 void Assembler::fsqrt() { 5364 emit_int8((unsigned char)0xD9); 5365 emit_int8((unsigned char)0xFA); 5366 } 5367 5368 void Assembler::fst_d(Address adr) { 5369 InstructionMark im(this); 5370 emit_int8((unsigned char)0xDD); 5371 emit_operand32(rdx, adr); 5372 } 5373 5374 void Assembler::fst_s(Address adr) { 5375 InstructionMark im(this); 5376 emit_int8((unsigned char)0xD9); 5377 emit_operand32(rdx, adr); 5378 } 5379 5380 void Assembler::fstp_d(Address adr) { 5381 InstructionMark im(this); 5382 emit_int8((unsigned char)0xDD); 5383 emit_operand32(rbx, adr); 5384 } 5385 5386 void Assembler::fstp_d(int index) { 5387 emit_farith(0xDD, 0xD8, index); 5388 } 5389 5390 void Assembler::fstp_s(Address adr) { 5391 InstructionMark im(this); 5392 emit_int8((unsigned char)0xD9); 5393 emit_operand32(rbx, adr); 5394 } 5395 5396 void Assembler::fstp_x(Address adr) { 5397 InstructionMark im(this); 5398 emit_int8((unsigned char)0xDB); 5399 emit_operand32(rdi, adr); 5400 } 5401 5402 void Assembler::fsub(int i) { 5403 emit_farith(0xD8, 0xE0, i); 5404 } 5405 5406 void Assembler::fsub_d(Address src) { 5407 InstructionMark im(this); 5408 emit_int8((unsigned char)0xDC); 5409 emit_operand32(rsp, src); 5410 } 5411 5412 void Assembler::fsub_s(Address src) { 5413 InstructionMark im(this); 5414 emit_int8((unsigned char)0xD8); 5415 emit_operand32(rsp, src); 5416 } 5417 5418 void Assembler::fsuba(int i) { 5419 emit_farith(0xDC, 0xE8, i); 5420 } 5421 5422 void Assembler::fsubp(int i) { 5423 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 5424 } 5425 5426 void Assembler::fsubr(int i) { 5427 emit_farith(0xD8, 0xE8, i); 5428 } 5429 5430 void Assembler::fsubr_d(Address src) { 5431 InstructionMark im(this); 5432 emit_int8((unsigned char)0xDC); 5433 emit_operand32(rbp, src); 5434 } 5435 5436 void Assembler::fsubr_s(Address src) { 5437 InstructionMark im(this); 5438 emit_int8((unsigned char)0xD8); 5439 emit_operand32(rbp, src); 5440 } 5441 5442 void Assembler::fsubra(int i) { 5443 emit_farith(0xDC, 0xE0, i); 5444 } 5445 5446 void Assembler::fsubrp(int i) { 5447 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 5448 } 5449 5450 void Assembler::ftan() { 5451 emit_int8((unsigned char)0xD9); 5452 emit_int8((unsigned char)0xF2); 5453 emit_int8((unsigned char)0xDD); 5454 emit_int8((unsigned char)0xD8); 5455 } 5456 5457 void Assembler::ftst() { 5458 emit_int8((unsigned char)0xD9); 5459 emit_int8((unsigned char)0xE4); 5460 } 5461 5462 void Assembler::fucomi(int i) { 5463 // make sure the instruction is supported (introduced for P6, together with cmov) 5464 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 5465 emit_farith(0xDB, 0xE8, i); 5466 } 5467 5468 void Assembler::fucomip(int i) { 5469 // make sure the instruction is supported (introduced for P6, together with cmov) 5470 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 5471 emit_farith(0xDF, 0xE8, i); 5472 } 5473 5474 void Assembler::fwait() { 5475 emit_int8((unsigned char)0x9B); 5476 } 5477 5478 void Assembler::fxch(int i) { 5479 emit_farith(0xD9, 0xC8, i); 5480 } 5481 5482 void Assembler::fyl2x() { 5483 emit_int8((unsigned char)0xD9); 5484 emit_int8((unsigned char)0xF1); 5485 } 5486 5487 void Assembler::frndint() { 5488 emit_int8((unsigned char)0xD9); 5489 emit_int8((unsigned char)0xFC); 5490 } 5491 5492 void Assembler::f2xm1() { 5493 emit_int8((unsigned char)0xD9); 5494 emit_int8((unsigned char)0xF0); 5495 } 5496 5497 void Assembler::fldl2e() { 5498 emit_int8((unsigned char)0xD9); 5499 emit_int8((unsigned char)0xEA); 5500 } 5501 5502 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 5503 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 5504 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 5505 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 5506 5507 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 5508 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 5509 if (pre > 0) { 5510 emit_int8(simd_pre[pre]); 5511 } 5512 if (rex_w) { 5513 prefixq(adr, xreg); 5514 } else { 5515 prefix(adr, xreg); 5516 } 5517 if (opc > 0) { 5518 emit_int8(0x0F); 5519 int opc2 = simd_opc[opc]; 5520 if (opc2 > 0) { 5521 emit_int8(opc2); 5522 } 5523 } 5524 } 5525 5526 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 5527 if (pre > 0) { 5528 emit_int8(simd_pre[pre]); 5529 } 5530 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : 5531 prefix_and_encode(dst_enc, src_enc); 5532 if (opc > 0) { 5533 emit_int8(0x0F); 5534 int opc2 = simd_opc[opc]; 5535 if (opc2 > 0) { 5536 emit_int8(opc2); 5537 } 5538 } 5539 return encode; 5540 } 5541 5542 5543 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) { 5544 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 5545 prefix(VEX_3bytes); 5546 5547 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 5548 byte1 = (~byte1) & 0xE0; 5549 byte1 |= opc; 5550 emit_int8(byte1); 5551 5552 int byte2 = ((~nds_enc) & 0xf) << 3; 5553 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 5554 emit_int8(byte2); 5555 } else { 5556 prefix(VEX_2bytes); 5557 5558 int byte1 = vex_r ? VEX_R : 0; 5559 byte1 = (~byte1) & 0x80; 5560 byte1 |= ((~nds_enc) & 0xf) << 3; 5561 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 5562 emit_int8(byte1); 5563 } 5564 } 5565 5566 // This is a 4 byte encoding 5567 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v, 5568 int nds_enc, VexSimdPrefix pre, VexOpcode opc, 5569 bool is_extended_context, bool is_merge_context, 5570 int vector_len, bool no_mask_reg ){ 5571 // EVEX 0x62 prefix 5572 prefix(EVEX_4bytes); 5573 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0); 5574 5575 // P0: byte 2, initialized to RXBR`00mm 5576 // instead of not'd 5577 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 5578 byte2 = (~byte2) & 0xF0; 5579 // confine opc opcode extensions in mm bits to lower two bits 5580 // of form {0F, 0F_38, 0F_3A} 5581 byte2 |= opc; 5582 emit_int8(byte2); 5583 5584 // P1: byte 3 as Wvvvv1pp 5585 int byte3 = ((~nds_enc) & 0xf) << 3; 5586 // p[10] is always 1 5587 byte3 |= EVEX_F; 5588 byte3 |= (vex_w & 1) << 7; 5589 // confine pre opcode extensions in pp bits to lower two bits 5590 // of form {66, F3, F2} 5591 byte3 |= pre; 5592 emit_int8(byte3); 5593 5594 // P2: byte 4 as zL'Lbv'aaa 5595 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now) 5596 // EVEX.v` for extending EVEX.vvvv or VIDX 5597 byte4 |= (evex_v ? 0: EVEX_V); 5598 // third EXEC.b for broadcast actions 5599 byte4 |= (is_extended_context ? EVEX_Rb : 0); 5600 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 5601 byte4 |= ((vector_len) & 0x3) << 5; 5602 // last is EVEX.z for zero/merge actions 5603 byte4 |= (is_merge_context ? EVEX_Z : 0); 5604 emit_int8(byte4); 5605 } 5606 5607 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, 5608 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) { 5609 bool vex_r = (xreg_enc >= 8); 5610 bool vex_b = adr.base_needs_rex(); 5611 bool vex_x = adr.index_needs_rex(); 5612 avx_vector_len = vector_len; 5613 5614 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit 5615 if (VM_Version::supports_avx512vl() == false) { 5616 switch (vector_len) { 5617 case AVX_128bit: 5618 case AVX_256bit: 5619 legacy_mode = true; 5620 break; 5621 } 5622 } 5623 5624 if ((UseAVX > 2) && (legacy_mode == false)) 5625 { 5626 bool evex_r = (xreg_enc >= 16); 5627 bool evex_v = (nds_enc >= 16); 5628 is_evex_instruction = true; 5629 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg); 5630 } else { 5631 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len); 5632 } 5633 } 5634 5635 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, 5636 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) { 5637 bool vex_r = (dst_enc >= 8); 5638 bool vex_b = (src_enc >= 8); 5639 bool vex_x = false; 5640 avx_vector_len = vector_len; 5641 5642 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit 5643 if (VM_Version::supports_avx512vl() == false) { 5644 switch (vector_len) { 5645 case AVX_128bit: 5646 case AVX_256bit: 5647 legacy_mode = true; 5648 break; 5649 } 5650 } 5651 5652 if ((UseAVX > 2) && (legacy_mode == false)) 5653 { 5654 bool evex_r = (dst_enc >= 16); 5655 bool evex_v = (nds_enc >= 16); 5656 // can use vex_x as bank extender on rm encoding 5657 vex_x = (src_enc >= 16); 5658 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg); 5659 } else { 5660 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len); 5661 } 5662 5663 // return modrm byte components for operands 5664 return (((dst_enc & 7) << 3) | (src_enc & 7)); 5665 } 5666 5667 5668 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 5669 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) { 5670 if (UseAVX > 0) { 5671 int xreg_enc = xreg->encoding(); 5672 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 5673 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg); 5674 } else { 5675 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 5676 rex_prefix(adr, xreg, pre, opc, rex_w); 5677 } 5678 } 5679 5680 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 5681 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) { 5682 int dst_enc = dst->encoding(); 5683 int src_enc = src->encoding(); 5684 if (UseAVX > 0) { 5685 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 5686 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg); 5687 } else { 5688 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 5689 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); 5690 } 5691 } 5692 5693 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre, 5694 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) { 5695 int dst_enc = dst->encoding(); 5696 int src_enc = src->encoding(); 5697 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 5698 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg); 5699 } 5700 5701 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre, 5702 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) { 5703 int dst_enc = dst->encoding(); 5704 int src_enc = src->encoding(); 5705 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 5706 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg); 5707 } 5708 5709 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) { 5710 InstructionMark im(this); 5711 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode); 5712 emit_int8(opcode); 5713 emit_operand(dst, src); 5714 } 5715 5716 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) { 5717 InstructionMark im(this); 5718 simd_prefix_q(dst, dst, src, pre, no_mask_reg); 5719 emit_int8(opcode); 5720 emit_operand(dst, src); 5721 } 5722 5723 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) { 5724 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode); 5725 emit_int8(opcode); 5726 emit_int8((unsigned char)(0xC0 | encode)); 5727 } 5728 5729 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) { 5730 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit); 5731 emit_int8(opcode); 5732 emit_int8((unsigned char)(0xC0 | encode)); 5733 } 5734 5735 // Versions with no second source register (non-destructive source). 5736 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) { 5737 InstructionMark im(this); 5738 simd_prefix(dst, xnoreg, src, pre, opNoRegMask); 5739 emit_int8(opcode); 5740 emit_operand(dst, src); 5741 } 5742 5743 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) { 5744 InstructionMark im(this); 5745 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask); 5746 emit_int8(opcode); 5747 emit_operand(dst, src); 5748 } 5749 5750 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) { 5751 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit); 5752 emit_int8(opcode); 5753 emit_int8((unsigned char)(0xC0 | encode)); 5754 } 5755 5756 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) { 5757 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit); 5758 emit_int8(opcode); 5759 emit_int8((unsigned char)(0xC0 | encode)); 5760 } 5761 5762 // 3-operands AVX instructions 5763 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src, 5764 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) { 5765 InstructionMark im(this); 5766 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode); 5767 emit_int8(opcode); 5768 emit_operand(dst, src); 5769 } 5770 5771 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, 5772 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) { 5773 InstructionMark im(this); 5774 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg); 5775 emit_int8(opcode); 5776 emit_operand(dst, src); 5777 } 5778 5779 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, 5780 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) { 5781 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg); 5782 emit_int8(opcode); 5783 emit_int8((unsigned char)(0xC0 | encode)); 5784 } 5785 5786 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, 5787 VexSimdPrefix pre, int vector_len, bool no_mask_reg) { 5788 int src_enc = src->encoding(); 5789 int dst_enc = dst->encoding(); 5790 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 5791 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg); 5792 emit_int8(opcode); 5793 emit_int8((unsigned char)(0xC0 | encode)); 5794 } 5795 5796 #ifndef _LP64 5797 5798 void Assembler::incl(Register dst) { 5799 // Don't use it directly. Use MacroAssembler::incrementl() instead. 5800 emit_int8(0x40 | dst->encoding()); 5801 } 5802 5803 void Assembler::lea(Register dst, Address src) { 5804 leal(dst, src); 5805 } 5806 5807 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 5808 InstructionMark im(this); 5809 emit_int8((unsigned char)0xC7); 5810 emit_operand(rax, dst); 5811 emit_data((int)imm32, rspec, 0); 5812 } 5813 5814 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 5815 InstructionMark im(this); 5816 int encode = prefix_and_encode(dst->encoding()); 5817 emit_int8((unsigned char)(0xB8 | encode)); 5818 emit_data((int)imm32, rspec, 0); 5819 } 5820 5821 void Assembler::popa() { // 32bit 5822 emit_int8(0x61); 5823 } 5824 5825 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 5826 InstructionMark im(this); 5827 emit_int8(0x68); 5828 emit_data(imm32, rspec, 0); 5829 } 5830 5831 void Assembler::pusha() { // 32bit 5832 emit_int8(0x60); 5833 } 5834 5835 void Assembler::set_byte_if_not_zero(Register dst) { 5836 emit_int8(0x0F); 5837 emit_int8((unsigned char)0x95); 5838 emit_int8((unsigned char)(0xE0 | dst->encoding())); 5839 } 5840 5841 void Assembler::shldl(Register dst, Register src) { 5842 emit_int8(0x0F); 5843 emit_int8((unsigned char)0xA5); 5844 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 5845 } 5846 5847 void Assembler::shrdl(Register dst, Register src) { 5848 emit_int8(0x0F); 5849 emit_int8((unsigned char)0xAD); 5850 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 5851 } 5852 5853 #else // LP64 5854 5855 void Assembler::set_byte_if_not_zero(Register dst) { 5856 int enc = prefix_and_encode(dst->encoding(), true); 5857 emit_int8(0x0F); 5858 emit_int8((unsigned char)0x95); 5859 emit_int8((unsigned char)(0xE0 | enc)); 5860 } 5861 5862 // 64bit only pieces of the assembler 5863 // This should only be used by 64bit instructions that can use rip-relative 5864 // it cannot be used by instructions that want an immediate value. 5865 5866 bool Assembler::reachable(AddressLiteral adr) { 5867 int64_t disp; 5868 // None will force a 64bit literal to the code stream. Likely a placeholder 5869 // for something that will be patched later and we need to certain it will 5870 // always be reachable. 5871 if (adr.reloc() == relocInfo::none) { 5872 return false; 5873 } 5874 if (adr.reloc() == relocInfo::internal_word_type) { 5875 // This should be rip relative and easily reachable. 5876 return true; 5877 } 5878 if (adr.reloc() == relocInfo::virtual_call_type || 5879 adr.reloc() == relocInfo::opt_virtual_call_type || 5880 adr.reloc() == relocInfo::static_call_type || 5881 adr.reloc() == relocInfo::static_stub_type ) { 5882 // This should be rip relative within the code cache and easily 5883 // reachable until we get huge code caches. (At which point 5884 // ic code is going to have issues). 5885 return true; 5886 } 5887 if (adr.reloc() != relocInfo::external_word_type && 5888 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 5889 adr.reloc() != relocInfo::poll_type && // relocs to identify them 5890 adr.reloc() != relocInfo::runtime_call_type ) { 5891 return false; 5892 } 5893 5894 // Stress the correction code 5895 if (ForceUnreachable) { 5896 // Must be runtimecall reloc, see if it is in the codecache 5897 // Flipping stuff in the codecache to be unreachable causes issues 5898 // with things like inline caches where the additional instructions 5899 // are not handled. 5900 if (CodeCache::find_blob(adr._target) == NULL) { 5901 return false; 5902 } 5903 } 5904 // For external_word_type/runtime_call_type if it is reachable from where we 5905 // are now (possibly a temp buffer) and where we might end up 5906 // anywhere in the codeCache then we are always reachable. 5907 // This would have to change if we ever save/restore shared code 5908 // to be more pessimistic. 5909 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 5910 if (!is_simm32(disp)) return false; 5911 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 5912 if (!is_simm32(disp)) return false; 5913 5914 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 5915 5916 // Because rip relative is a disp + address_of_next_instruction and we 5917 // don't know the value of address_of_next_instruction we apply a fudge factor 5918 // to make sure we will be ok no matter the size of the instruction we get placed into. 5919 // We don't have to fudge the checks above here because they are already worst case. 5920 5921 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 5922 // + 4 because better safe than sorry. 5923 const int fudge = 12 + 4; 5924 if (disp < 0) { 5925 disp -= fudge; 5926 } else { 5927 disp += fudge; 5928 } 5929 return is_simm32(disp); 5930 } 5931 5932 // Check if the polling page is not reachable from the code cache using rip-relative 5933 // addressing. 5934 bool Assembler::is_polling_page_far() { 5935 intptr_t addr = (intptr_t)os::get_polling_page(); 5936 return ForceUnreachable || 5937 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 5938 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 5939 } 5940 5941 void Assembler::emit_data64(jlong data, 5942 relocInfo::relocType rtype, 5943 int format) { 5944 if (rtype == relocInfo::none) { 5945 emit_int64(data); 5946 } else { 5947 emit_data64(data, Relocation::spec_simple(rtype), format); 5948 } 5949 } 5950 5951 void Assembler::emit_data64(jlong data, 5952 RelocationHolder const& rspec, 5953 int format) { 5954 assert(imm_operand == 0, "default format must be immediate in this file"); 5955 assert(imm_operand == format, "must be immediate"); 5956 assert(inst_mark() != NULL, "must be inside InstructionMark"); 5957 // Do not use AbstractAssembler::relocate, which is not intended for 5958 // embedded words. Instead, relocate to the enclosing instruction. 5959 code_section()->relocate(inst_mark(), rspec, format); 5960 #ifdef ASSERT 5961 check_relocation(rspec, format); 5962 #endif 5963 emit_int64(data); 5964 } 5965 5966 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 5967 if (reg_enc >= 8) { 5968 prefix(REX_B); 5969 reg_enc -= 8; 5970 } else if (byteinst && reg_enc >= 4) { 5971 prefix(REX); 5972 } 5973 return reg_enc; 5974 } 5975 5976 int Assembler::prefixq_and_encode(int reg_enc) { 5977 if (reg_enc < 8) { 5978 prefix(REX_W); 5979 } else { 5980 prefix(REX_WB); 5981 reg_enc -= 8; 5982 } 5983 return reg_enc; 5984 } 5985 5986 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { 5987 if (dst_enc < 8) { 5988 if (src_enc >= 8) { 5989 prefix(REX_B); 5990 src_enc -= 8; 5991 } else if (byteinst && src_enc >= 4) { 5992 prefix(REX); 5993 } 5994 } else { 5995 if (src_enc < 8) { 5996 prefix(REX_R); 5997 } else { 5998 prefix(REX_RB); 5999 src_enc -= 8; 6000 } 6001 dst_enc -= 8; 6002 } 6003 return dst_enc << 3 | src_enc; 6004 } 6005 6006 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 6007 if (dst_enc < 8) { 6008 if (src_enc < 8) { 6009 prefix(REX_W); 6010 } else { 6011 prefix(REX_WB); 6012 src_enc -= 8; 6013 } 6014 } else { 6015 if (src_enc < 8) { 6016 prefix(REX_WR); 6017 } else { 6018 prefix(REX_WRB); 6019 src_enc -= 8; 6020 } 6021 dst_enc -= 8; 6022 } 6023 return dst_enc << 3 | src_enc; 6024 } 6025 6026 void Assembler::prefix(Register reg) { 6027 if (reg->encoding() >= 8) { 6028 prefix(REX_B); 6029 } 6030 } 6031 6032 void Assembler::prefix(Address adr) { 6033 if (adr.base_needs_rex()) { 6034 if (adr.index_needs_rex()) { 6035 prefix(REX_XB); 6036 } else { 6037 prefix(REX_B); 6038 } 6039 } else { 6040 if (adr.index_needs_rex()) { 6041 prefix(REX_X); 6042 } 6043 } 6044 } 6045 6046 void Assembler::prefixq(Address adr) { 6047 if (adr.base_needs_rex()) { 6048 if (adr.index_needs_rex()) { 6049 prefix(REX_WXB); 6050 } else { 6051 prefix(REX_WB); 6052 } 6053 } else { 6054 if (adr.index_needs_rex()) { 6055 prefix(REX_WX); 6056 } else { 6057 prefix(REX_W); 6058 } 6059 } 6060 } 6061 6062 6063 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 6064 if (reg->encoding() < 8) { 6065 if (adr.base_needs_rex()) { 6066 if (adr.index_needs_rex()) { 6067 prefix(REX_XB); 6068 } else { 6069 prefix(REX_B); 6070 } 6071 } else { 6072 if (adr.index_needs_rex()) { 6073 prefix(REX_X); 6074 } else if (byteinst && reg->encoding() >= 4 ) { 6075 prefix(REX); 6076 } 6077 } 6078 } else { 6079 if (adr.base_needs_rex()) { 6080 if (adr.index_needs_rex()) { 6081 prefix(REX_RXB); 6082 } else { 6083 prefix(REX_RB); 6084 } 6085 } else { 6086 if (adr.index_needs_rex()) { 6087 prefix(REX_RX); 6088 } else { 6089 prefix(REX_R); 6090 } 6091 } 6092 } 6093 } 6094 6095 void Assembler::prefixq(Address adr, Register src) { 6096 if (src->encoding() < 8) { 6097 if (adr.base_needs_rex()) { 6098 if (adr.index_needs_rex()) { 6099 prefix(REX_WXB); 6100 } else { 6101 prefix(REX_WB); 6102 } 6103 } else { 6104 if (adr.index_needs_rex()) { 6105 prefix(REX_WX); 6106 } else { 6107 prefix(REX_W); 6108 } 6109 } 6110 } else { 6111 if (adr.base_needs_rex()) { 6112 if (adr.index_needs_rex()) { 6113 prefix(REX_WRXB); 6114 } else { 6115 prefix(REX_WRB); 6116 } 6117 } else { 6118 if (adr.index_needs_rex()) { 6119 prefix(REX_WRX); 6120 } else { 6121 prefix(REX_WR); 6122 } 6123 } 6124 } 6125 } 6126 6127 void Assembler::prefix(Address adr, XMMRegister reg) { 6128 if (reg->encoding() < 8) { 6129 if (adr.base_needs_rex()) { 6130 if (adr.index_needs_rex()) { 6131 prefix(REX_XB); 6132 } else { 6133 prefix(REX_B); 6134 } 6135 } else { 6136 if (adr.index_needs_rex()) { 6137 prefix(REX_X); 6138 } 6139 } 6140 } else { 6141 if (adr.base_needs_rex()) { 6142 if (adr.index_needs_rex()) { 6143 prefix(REX_RXB); 6144 } else { 6145 prefix(REX_RB); 6146 } 6147 } else { 6148 if (adr.index_needs_rex()) { 6149 prefix(REX_RX); 6150 } else { 6151 prefix(REX_R); 6152 } 6153 } 6154 } 6155 } 6156 6157 void Assembler::prefixq(Address adr, XMMRegister src) { 6158 if (src->encoding() < 8) { 6159 if (adr.base_needs_rex()) { 6160 if (adr.index_needs_rex()) { 6161 prefix(REX_WXB); 6162 } else { 6163 prefix(REX_WB); 6164 } 6165 } else { 6166 if (adr.index_needs_rex()) { 6167 prefix(REX_WX); 6168 } else { 6169 prefix(REX_W); 6170 } 6171 } 6172 } else { 6173 if (adr.base_needs_rex()) { 6174 if (adr.index_needs_rex()) { 6175 prefix(REX_WRXB); 6176 } else { 6177 prefix(REX_WRB); 6178 } 6179 } else { 6180 if (adr.index_needs_rex()) { 6181 prefix(REX_WRX); 6182 } else { 6183 prefix(REX_WR); 6184 } 6185 } 6186 } 6187 } 6188 6189 void Assembler::adcq(Register dst, int32_t imm32) { 6190 (void) prefixq_and_encode(dst->encoding()); 6191 emit_arith(0x81, 0xD0, dst, imm32); 6192 } 6193 6194 void Assembler::adcq(Register dst, Address src) { 6195 InstructionMark im(this); 6196 prefixq(src, dst); 6197 emit_int8(0x13); 6198 emit_operand(dst, src); 6199 } 6200 6201 void Assembler::adcq(Register dst, Register src) { 6202 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6203 emit_arith(0x13, 0xC0, dst, src); 6204 } 6205 6206 void Assembler::addq(Address dst, int32_t imm32) { 6207 InstructionMark im(this); 6208 prefixq(dst); 6209 emit_arith_operand(0x81, rax, dst,imm32); 6210 } 6211 6212 void Assembler::addq(Address dst, Register src) { 6213 InstructionMark im(this); 6214 prefixq(dst, src); 6215 emit_int8(0x01); 6216 emit_operand(src, dst); 6217 } 6218 6219 void Assembler::addq(Register dst, int32_t imm32) { 6220 (void) prefixq_and_encode(dst->encoding()); 6221 emit_arith(0x81, 0xC0, dst, imm32); 6222 } 6223 6224 void Assembler::addq(Register dst, Address src) { 6225 InstructionMark im(this); 6226 prefixq(src, dst); 6227 emit_int8(0x03); 6228 emit_operand(dst, src); 6229 } 6230 6231 void Assembler::addq(Register dst, Register src) { 6232 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6233 emit_arith(0x03, 0xC0, dst, src); 6234 } 6235 6236 void Assembler::adcxq(Register dst, Register src) { 6237 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 6238 emit_int8((unsigned char)0x66); 6239 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6240 emit_int8(0x0F); 6241 emit_int8(0x38); 6242 emit_int8((unsigned char)0xF6); 6243 emit_int8((unsigned char)(0xC0 | encode)); 6244 } 6245 6246 void Assembler::adoxq(Register dst, Register src) { 6247 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 6248 emit_int8((unsigned char)0xF3); 6249 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6250 emit_int8(0x0F); 6251 emit_int8(0x38); 6252 emit_int8((unsigned char)0xF6); 6253 emit_int8((unsigned char)(0xC0 | encode)); 6254 } 6255 6256 void Assembler::andq(Address dst, int32_t imm32) { 6257 InstructionMark im(this); 6258 prefixq(dst); 6259 emit_int8((unsigned char)0x81); 6260 emit_operand(rsp, dst, 4); 6261 emit_int32(imm32); 6262 } 6263 6264 void Assembler::andq(Register dst, int32_t imm32) { 6265 (void) prefixq_and_encode(dst->encoding()); 6266 emit_arith(0x81, 0xE0, dst, imm32); 6267 } 6268 6269 void Assembler::andq(Register dst, Address src) { 6270 InstructionMark im(this); 6271 prefixq(src, dst); 6272 emit_int8(0x23); 6273 emit_operand(dst, src); 6274 } 6275 6276 void Assembler::andq(Register dst, Register src) { 6277 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6278 emit_arith(0x23, 0xC0, dst, src); 6279 } 6280 6281 void Assembler::andnq(Register dst, Register src1, Register src2) { 6282 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6283 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2); 6284 emit_int8((unsigned char)0xF2); 6285 emit_int8((unsigned char)(0xC0 | encode)); 6286 } 6287 6288 void Assembler::andnq(Register dst, Register src1, Address src2) { 6289 if (VM_Version::supports_evex()) { 6290 tuple_type = EVEX_T1S; 6291 input_size_in_bits = EVEX_64bit; 6292 } 6293 InstructionMark im(this); 6294 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6295 vex_prefix_0F38_q(dst, src1, src2); 6296 emit_int8((unsigned char)0xF2); 6297 emit_operand(dst, src2); 6298 } 6299 6300 void Assembler::bsfq(Register dst, Register src) { 6301 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6302 emit_int8(0x0F); 6303 emit_int8((unsigned char)0xBC); 6304 emit_int8((unsigned char)(0xC0 | encode)); 6305 } 6306 6307 void Assembler::bsrq(Register dst, Register src) { 6308 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6309 emit_int8(0x0F); 6310 emit_int8((unsigned char)0xBD); 6311 emit_int8((unsigned char)(0xC0 | encode)); 6312 } 6313 6314 void Assembler::bswapq(Register reg) { 6315 int encode = prefixq_and_encode(reg->encoding()); 6316 emit_int8(0x0F); 6317 emit_int8((unsigned char)(0xC8 | encode)); 6318 } 6319 6320 void Assembler::blsiq(Register dst, Register src) { 6321 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6322 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src); 6323 emit_int8((unsigned char)0xF3); 6324 emit_int8((unsigned char)(0xC0 | encode)); 6325 } 6326 6327 void Assembler::blsiq(Register dst, Address src) { 6328 InstructionMark im(this); 6329 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6330 vex_prefix_0F38_q(rbx, dst, src); 6331 emit_int8((unsigned char)0xF3); 6332 emit_operand(rbx, src); 6333 } 6334 6335 void Assembler::blsmskq(Register dst, Register src) { 6336 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6337 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src); 6338 emit_int8((unsigned char)0xF3); 6339 emit_int8((unsigned char)(0xC0 | encode)); 6340 } 6341 6342 void Assembler::blsmskq(Register dst, Address src) { 6343 InstructionMark im(this); 6344 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6345 vex_prefix_0F38_q(rdx, dst, src); 6346 emit_int8((unsigned char)0xF3); 6347 emit_operand(rdx, src); 6348 } 6349 6350 void Assembler::blsrq(Register dst, Register src) { 6351 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6352 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src); 6353 emit_int8((unsigned char)0xF3); 6354 emit_int8((unsigned char)(0xC0 | encode)); 6355 } 6356 6357 void Assembler::blsrq(Register dst, Address src) { 6358 InstructionMark im(this); 6359 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 6360 vex_prefix_0F38_q(rcx, dst, src); 6361 emit_int8((unsigned char)0xF3); 6362 emit_operand(rcx, src); 6363 } 6364 6365 void Assembler::cdqq() { 6366 prefix(REX_W); 6367 emit_int8((unsigned char)0x99); 6368 } 6369 6370 void Assembler::clflush(Address adr) { 6371 prefix(adr); 6372 emit_int8(0x0F); 6373 emit_int8((unsigned char)0xAE); 6374 emit_operand(rdi, adr); 6375 } 6376 6377 void Assembler::cmovq(Condition cc, Register dst, Register src) { 6378 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6379 emit_int8(0x0F); 6380 emit_int8(0x40 | cc); 6381 emit_int8((unsigned char)(0xC0 | encode)); 6382 } 6383 6384 void Assembler::cmovq(Condition cc, Register dst, Address src) { 6385 InstructionMark im(this); 6386 prefixq(src, dst); 6387 emit_int8(0x0F); 6388 emit_int8(0x40 | cc); 6389 emit_operand(dst, src); 6390 } 6391 6392 void Assembler::cmpq(Address dst, int32_t imm32) { 6393 InstructionMark im(this); 6394 prefixq(dst); 6395 emit_int8((unsigned char)0x81); 6396 emit_operand(rdi, dst, 4); 6397 emit_int32(imm32); 6398 } 6399 6400 void Assembler::cmpq(Register dst, int32_t imm32) { 6401 (void) prefixq_and_encode(dst->encoding()); 6402 emit_arith(0x81, 0xF8, dst, imm32); 6403 } 6404 6405 void Assembler::cmpq(Address dst, Register src) { 6406 InstructionMark im(this); 6407 prefixq(dst, src); 6408 emit_int8(0x3B); 6409 emit_operand(src, dst); 6410 } 6411 6412 void Assembler::cmpq(Register dst, Register src) { 6413 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6414 emit_arith(0x3B, 0xC0, dst, src); 6415 } 6416 6417 void Assembler::cmpq(Register dst, Address src) { 6418 InstructionMark im(this); 6419 prefixq(src, dst); 6420 emit_int8(0x3B); 6421 emit_operand(dst, src); 6422 } 6423 6424 void Assembler::cmpxchgq(Register reg, Address adr) { 6425 InstructionMark im(this); 6426 prefixq(adr, reg); 6427 emit_int8(0x0F); 6428 emit_int8((unsigned char)0xB1); 6429 emit_operand(reg, adr); 6430 } 6431 6432 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 6433 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6434 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true); 6435 emit_int8(0x2A); 6436 emit_int8((unsigned char)(0xC0 | encode)); 6437 } 6438 6439 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 6440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6441 if (VM_Version::supports_evex()) { 6442 tuple_type = EVEX_T1S; 6443 input_size_in_bits = EVEX_32bit; 6444 } 6445 InstructionMark im(this); 6446 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true); 6447 emit_int8(0x2A); 6448 emit_operand(dst, src); 6449 } 6450 6451 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 6452 NOT_LP64(assert(VM_Version::supports_sse(), "")); 6453 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true); 6454 emit_int8(0x2A); 6455 emit_int8((unsigned char)(0xC0 | encode)); 6456 } 6457 6458 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 6459 NOT_LP64(assert(VM_Version::supports_sse(), "")); 6460 if (VM_Version::supports_evex()) { 6461 tuple_type = EVEX_T1S; 6462 input_size_in_bits = EVEX_32bit; 6463 } 6464 InstructionMark im(this); 6465 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true); 6466 emit_int8(0x2A); 6467 emit_operand(dst, src); 6468 } 6469 6470 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 6471 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6472 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true); 6473 emit_int8(0x2C); 6474 emit_int8((unsigned char)(0xC0 | encode)); 6475 } 6476 6477 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 6478 NOT_LP64(assert(VM_Version::supports_sse(), "")); 6479 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true); 6480 emit_int8(0x2C); 6481 emit_int8((unsigned char)(0xC0 | encode)); 6482 } 6483 6484 void Assembler::decl(Register dst) { 6485 // Don't use it directly. Use MacroAssembler::decrementl() instead. 6486 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 6487 int encode = prefix_and_encode(dst->encoding()); 6488 emit_int8((unsigned char)0xFF); 6489 emit_int8((unsigned char)(0xC8 | encode)); 6490 } 6491 6492 void Assembler::decq(Register dst) { 6493 // Don't use it directly. Use MacroAssembler::decrementq() instead. 6494 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 6495 int encode = prefixq_and_encode(dst->encoding()); 6496 emit_int8((unsigned char)0xFF); 6497 emit_int8(0xC8 | encode); 6498 } 6499 6500 void Assembler::decq(Address dst) { 6501 // Don't use it directly. Use MacroAssembler::decrementq() instead. 6502 InstructionMark im(this); 6503 prefixq(dst); 6504 emit_int8((unsigned char)0xFF); 6505 emit_operand(rcx, dst); 6506 } 6507 6508 void Assembler::fxrstor(Address src) { 6509 prefixq(src); 6510 emit_int8(0x0F); 6511 emit_int8((unsigned char)0xAE); 6512 emit_operand(as_Register(1), src); 6513 } 6514 6515 void Assembler::fxsave(Address dst) { 6516 prefixq(dst); 6517 emit_int8(0x0F); 6518 emit_int8((unsigned char)0xAE); 6519 emit_operand(as_Register(0), dst); 6520 } 6521 6522 void Assembler::idivq(Register src) { 6523 int encode = prefixq_and_encode(src->encoding()); 6524 emit_int8((unsigned char)0xF7); 6525 emit_int8((unsigned char)(0xF8 | encode)); 6526 } 6527 6528 void Assembler::imulq(Register dst, Register src) { 6529 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6530 emit_int8(0x0F); 6531 emit_int8((unsigned char)0xAF); 6532 emit_int8((unsigned char)(0xC0 | encode)); 6533 } 6534 6535 void Assembler::imulq(Register dst, Register src, int value) { 6536 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6537 if (is8bit(value)) { 6538 emit_int8(0x6B); 6539 emit_int8((unsigned char)(0xC0 | encode)); 6540 emit_int8(value & 0xFF); 6541 } else { 6542 emit_int8(0x69); 6543 emit_int8((unsigned char)(0xC0 | encode)); 6544 emit_int32(value); 6545 } 6546 } 6547 6548 void Assembler::imulq(Register dst, Address src) { 6549 InstructionMark im(this); 6550 prefixq(src, dst); 6551 emit_int8(0x0F); 6552 emit_int8((unsigned char) 0xAF); 6553 emit_operand(dst, src); 6554 } 6555 6556 void Assembler::incl(Register dst) { 6557 // Don't use it directly. Use MacroAssembler::incrementl() instead. 6558 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 6559 int encode = prefix_and_encode(dst->encoding()); 6560 emit_int8((unsigned char)0xFF); 6561 emit_int8((unsigned char)(0xC0 | encode)); 6562 } 6563 6564 void Assembler::incq(Register dst) { 6565 // Don't use it directly. Use MacroAssembler::incrementq() instead. 6566 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 6567 int encode = prefixq_and_encode(dst->encoding()); 6568 emit_int8((unsigned char)0xFF); 6569 emit_int8((unsigned char)(0xC0 | encode)); 6570 } 6571 6572 void Assembler::incq(Address dst) { 6573 // Don't use it directly. Use MacroAssembler::incrementq() instead. 6574 InstructionMark im(this); 6575 prefixq(dst); 6576 emit_int8((unsigned char)0xFF); 6577 emit_operand(rax, dst); 6578 } 6579 6580 void Assembler::lea(Register dst, Address src) { 6581 leaq(dst, src); 6582 } 6583 6584 void Assembler::leaq(Register dst, Address src) { 6585 InstructionMark im(this); 6586 prefixq(src, dst); 6587 emit_int8((unsigned char)0x8D); 6588 emit_operand(dst, src); 6589 } 6590 6591 void Assembler::mov64(Register dst, int64_t imm64) { 6592 InstructionMark im(this); 6593 int encode = prefixq_and_encode(dst->encoding()); 6594 emit_int8((unsigned char)(0xB8 | encode)); 6595 emit_int64(imm64); 6596 } 6597 6598 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 6599 InstructionMark im(this); 6600 int encode = prefixq_and_encode(dst->encoding()); 6601 emit_int8(0xB8 | encode); 6602 emit_data64(imm64, rspec); 6603 } 6604 6605 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 6606 InstructionMark im(this); 6607 int encode = prefix_and_encode(dst->encoding()); 6608 emit_int8((unsigned char)(0xB8 | encode)); 6609 emit_data((int)imm32, rspec, narrow_oop_operand); 6610 } 6611 6612 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 6613 InstructionMark im(this); 6614 prefix(dst); 6615 emit_int8((unsigned char)0xC7); 6616 emit_operand(rax, dst, 4); 6617 emit_data((int)imm32, rspec, narrow_oop_operand); 6618 } 6619 6620 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 6621 InstructionMark im(this); 6622 int encode = prefix_and_encode(src1->encoding()); 6623 emit_int8((unsigned char)0x81); 6624 emit_int8((unsigned char)(0xF8 | encode)); 6625 emit_data((int)imm32, rspec, narrow_oop_operand); 6626 } 6627 6628 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 6629 InstructionMark im(this); 6630 prefix(src1); 6631 emit_int8((unsigned char)0x81); 6632 emit_operand(rax, src1, 4); 6633 emit_data((int)imm32, rspec, narrow_oop_operand); 6634 } 6635 6636 void Assembler::lzcntq(Register dst, Register src) { 6637 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 6638 emit_int8((unsigned char)0xF3); 6639 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6640 emit_int8(0x0F); 6641 emit_int8((unsigned char)0xBD); 6642 emit_int8((unsigned char)(0xC0 | encode)); 6643 } 6644 6645 void Assembler::movdq(XMMRegister dst, Register src) { 6646 // table D-1 says MMX/SSE2 6647 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6648 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true); 6649 emit_int8(0x6E); 6650 emit_int8((unsigned char)(0xC0 | encode)); 6651 } 6652 6653 void Assembler::movdq(Register dst, XMMRegister src) { 6654 // table D-1 says MMX/SSE2 6655 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 6656 // swap src/dst to get correct prefix 6657 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true); 6658 emit_int8(0x7E); 6659 emit_int8((unsigned char)(0xC0 | encode)); 6660 } 6661 6662 void Assembler::movq(Register dst, Register src) { 6663 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6664 emit_int8((unsigned char)0x8B); 6665 emit_int8((unsigned char)(0xC0 | encode)); 6666 } 6667 6668 void Assembler::movq(Register dst, Address src) { 6669 InstructionMark im(this); 6670 prefixq(src, dst); 6671 emit_int8((unsigned char)0x8B); 6672 emit_operand(dst, src); 6673 } 6674 6675 void Assembler::movq(Address dst, Register src) { 6676 InstructionMark im(this); 6677 prefixq(dst, src); 6678 emit_int8((unsigned char)0x89); 6679 emit_operand(src, dst); 6680 } 6681 6682 void Assembler::movsbq(Register dst, Address src) { 6683 InstructionMark im(this); 6684 prefixq(src, dst); 6685 emit_int8(0x0F); 6686 emit_int8((unsigned char)0xBE); 6687 emit_operand(dst, src); 6688 } 6689 6690 void Assembler::movsbq(Register dst, Register src) { 6691 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6692 emit_int8(0x0F); 6693 emit_int8((unsigned char)0xBE); 6694 emit_int8((unsigned char)(0xC0 | encode)); 6695 } 6696 6697 void Assembler::movslq(Register dst, int32_t imm32) { 6698 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 6699 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 6700 // as a result we shouldn't use until tested at runtime... 6701 ShouldNotReachHere(); 6702 InstructionMark im(this); 6703 int encode = prefixq_and_encode(dst->encoding()); 6704 emit_int8((unsigned char)(0xC7 | encode)); 6705 emit_int32(imm32); 6706 } 6707 6708 void Assembler::movslq(Address dst, int32_t imm32) { 6709 assert(is_simm32(imm32), "lost bits"); 6710 InstructionMark im(this); 6711 prefixq(dst); 6712 emit_int8((unsigned char)0xC7); 6713 emit_operand(rax, dst, 4); 6714 emit_int32(imm32); 6715 } 6716 6717 void Assembler::movslq(Register dst, Address src) { 6718 InstructionMark im(this); 6719 prefixq(src, dst); 6720 emit_int8(0x63); 6721 emit_operand(dst, src); 6722 } 6723 6724 void Assembler::movslq(Register dst, Register src) { 6725 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6726 emit_int8(0x63); 6727 emit_int8((unsigned char)(0xC0 | encode)); 6728 } 6729 6730 void Assembler::movswq(Register dst, Address src) { 6731 InstructionMark im(this); 6732 prefixq(src, dst); 6733 emit_int8(0x0F); 6734 emit_int8((unsigned char)0xBF); 6735 emit_operand(dst, src); 6736 } 6737 6738 void Assembler::movswq(Register dst, Register src) { 6739 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6740 emit_int8((unsigned char)0x0F); 6741 emit_int8((unsigned char)0xBF); 6742 emit_int8((unsigned char)(0xC0 | encode)); 6743 } 6744 6745 void Assembler::movzbq(Register dst, Address src) { 6746 InstructionMark im(this); 6747 prefixq(src, dst); 6748 emit_int8((unsigned char)0x0F); 6749 emit_int8((unsigned char)0xB6); 6750 emit_operand(dst, src); 6751 } 6752 6753 void Assembler::movzbq(Register dst, Register src) { 6754 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6755 emit_int8(0x0F); 6756 emit_int8((unsigned char)0xB6); 6757 emit_int8(0xC0 | encode); 6758 } 6759 6760 void Assembler::movzwq(Register dst, Address src) { 6761 InstructionMark im(this); 6762 prefixq(src, dst); 6763 emit_int8((unsigned char)0x0F); 6764 emit_int8((unsigned char)0xB7); 6765 emit_operand(dst, src); 6766 } 6767 6768 void Assembler::movzwq(Register dst, Register src) { 6769 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6770 emit_int8((unsigned char)0x0F); 6771 emit_int8((unsigned char)0xB7); 6772 emit_int8((unsigned char)(0xC0 | encode)); 6773 } 6774 6775 void Assembler::mulq(Address src) { 6776 InstructionMark im(this); 6777 prefixq(src); 6778 emit_int8((unsigned char)0xF7); 6779 emit_operand(rsp, src); 6780 } 6781 6782 void Assembler::mulq(Register src) { 6783 int encode = prefixq_and_encode(src->encoding()); 6784 emit_int8((unsigned char)0xF7); 6785 emit_int8((unsigned char)(0xE0 | encode)); 6786 } 6787 6788 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 6789 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 6790 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), 6791 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false); 6792 emit_int8((unsigned char)0xF6); 6793 emit_int8((unsigned char)(0xC0 | encode)); 6794 } 6795 6796 void Assembler::negq(Register dst) { 6797 int encode = prefixq_and_encode(dst->encoding()); 6798 emit_int8((unsigned char)0xF7); 6799 emit_int8((unsigned char)(0xD8 | encode)); 6800 } 6801 6802 void Assembler::notq(Register dst) { 6803 int encode = prefixq_and_encode(dst->encoding()); 6804 emit_int8((unsigned char)0xF7); 6805 emit_int8((unsigned char)(0xD0 | encode)); 6806 } 6807 6808 void Assembler::orq(Address dst, int32_t imm32) { 6809 InstructionMark im(this); 6810 prefixq(dst); 6811 emit_int8((unsigned char)0x81); 6812 emit_operand(rcx, dst, 4); 6813 emit_int32(imm32); 6814 } 6815 6816 void Assembler::orq(Register dst, int32_t imm32) { 6817 (void) prefixq_and_encode(dst->encoding()); 6818 emit_arith(0x81, 0xC8, dst, imm32); 6819 } 6820 6821 void Assembler::orq(Register dst, Address src) { 6822 InstructionMark im(this); 6823 prefixq(src, dst); 6824 emit_int8(0x0B); 6825 emit_operand(dst, src); 6826 } 6827 6828 void Assembler::orq(Register dst, Register src) { 6829 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6830 emit_arith(0x0B, 0xC0, dst, src); 6831 } 6832 6833 void Assembler::popa() { // 64bit 6834 movq(r15, Address(rsp, 0)); 6835 movq(r14, Address(rsp, wordSize)); 6836 movq(r13, Address(rsp, 2 * wordSize)); 6837 movq(r12, Address(rsp, 3 * wordSize)); 6838 movq(r11, Address(rsp, 4 * wordSize)); 6839 movq(r10, Address(rsp, 5 * wordSize)); 6840 movq(r9, Address(rsp, 6 * wordSize)); 6841 movq(r8, Address(rsp, 7 * wordSize)); 6842 movq(rdi, Address(rsp, 8 * wordSize)); 6843 movq(rsi, Address(rsp, 9 * wordSize)); 6844 movq(rbp, Address(rsp, 10 * wordSize)); 6845 // skip rsp 6846 movq(rbx, Address(rsp, 12 * wordSize)); 6847 movq(rdx, Address(rsp, 13 * wordSize)); 6848 movq(rcx, Address(rsp, 14 * wordSize)); 6849 movq(rax, Address(rsp, 15 * wordSize)); 6850 6851 addq(rsp, 16 * wordSize); 6852 } 6853 6854 void Assembler::popcntq(Register dst, Address src) { 6855 assert(VM_Version::supports_popcnt(), "must support"); 6856 InstructionMark im(this); 6857 emit_int8((unsigned char)0xF3); 6858 prefixq(src, dst); 6859 emit_int8((unsigned char)0x0F); 6860 emit_int8((unsigned char)0xB8); 6861 emit_operand(dst, src); 6862 } 6863 6864 void Assembler::popcntq(Register dst, Register src) { 6865 assert(VM_Version::supports_popcnt(), "must support"); 6866 emit_int8((unsigned char)0xF3); 6867 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 6868 emit_int8((unsigned char)0x0F); 6869 emit_int8((unsigned char)0xB8); 6870 emit_int8((unsigned char)(0xC0 | encode)); 6871 } 6872 6873 void Assembler::popq(Address dst) { 6874 InstructionMark im(this); 6875 prefixq(dst); 6876 emit_int8((unsigned char)0x8F); 6877 emit_operand(rax, dst); 6878 } 6879 6880 void Assembler::pusha() { // 64bit 6881 // we have to store original rsp. ABI says that 128 bytes 6882 // below rsp are local scratch. 6883 movq(Address(rsp, -5 * wordSize), rsp); 6884 6885 subq(rsp, 16 * wordSize); 6886 6887 movq(Address(rsp, 15 * wordSize), rax); 6888 movq(Address(rsp, 14 * wordSize), rcx); 6889 movq(Address(rsp, 13 * wordSize), rdx); 6890 movq(Address(rsp, 12 * wordSize), rbx); 6891 // skip rsp 6892 movq(Address(rsp, 10 * wordSize), rbp); 6893 movq(Address(rsp, 9 * wordSize), rsi); 6894 movq(Address(rsp, 8 * wordSize), rdi); 6895 movq(Address(rsp, 7 * wordSize), r8); 6896 movq(Address(rsp, 6 * wordSize), r9); 6897 movq(Address(rsp, 5 * wordSize), r10); 6898 movq(Address(rsp, 4 * wordSize), r11); 6899 movq(Address(rsp, 3 * wordSize), r12); 6900 movq(Address(rsp, 2 * wordSize), r13); 6901 movq(Address(rsp, wordSize), r14); 6902 movq(Address(rsp, 0), r15); 6903 } 6904 6905 void Assembler::pushq(Address src) { 6906 InstructionMark im(this); 6907 prefixq(src); 6908 emit_int8((unsigned char)0xFF); 6909 emit_operand(rsi, src); 6910 } 6911 6912 void Assembler::rclq(Register dst, int imm8) { 6913 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 6914 int encode = prefixq_and_encode(dst->encoding()); 6915 if (imm8 == 1) { 6916 emit_int8((unsigned char)0xD1); 6917 emit_int8((unsigned char)(0xD0 | encode)); 6918 } else { 6919 emit_int8((unsigned char)0xC1); 6920 emit_int8((unsigned char)(0xD0 | encode)); 6921 emit_int8(imm8); 6922 } 6923 } 6924 6925 void Assembler::rcrq(Register dst, int imm8) { 6926 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 6927 int encode = prefixq_and_encode(dst->encoding()); 6928 if (imm8 == 1) { 6929 emit_int8((unsigned char)0xD1); 6930 emit_int8((unsigned char)(0xD8 | encode)); 6931 } else { 6932 emit_int8((unsigned char)0xC1); 6933 emit_int8((unsigned char)(0xD8 | encode)); 6934 emit_int8(imm8); 6935 } 6936 } 6937 6938 void Assembler::rorq(Register dst, int imm8) { 6939 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 6940 int encode = prefixq_and_encode(dst->encoding()); 6941 if (imm8 == 1) { 6942 emit_int8((unsigned char)0xD1); 6943 emit_int8((unsigned char)(0xC8 | encode)); 6944 } else { 6945 emit_int8((unsigned char)0xC1); 6946 emit_int8((unsigned char)(0xc8 | encode)); 6947 emit_int8(imm8); 6948 } 6949 } 6950 6951 void Assembler::rorxq(Register dst, Register src, int imm8) { 6952 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 6953 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, 6954 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false); 6955 emit_int8((unsigned char)0xF0); 6956 emit_int8((unsigned char)(0xC0 | encode)); 6957 emit_int8(imm8); 6958 } 6959 6960 void Assembler::sarq(Register dst, int imm8) { 6961 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 6962 int encode = prefixq_and_encode(dst->encoding()); 6963 if (imm8 == 1) { 6964 emit_int8((unsigned char)0xD1); 6965 emit_int8((unsigned char)(0xF8 | encode)); 6966 } else { 6967 emit_int8((unsigned char)0xC1); 6968 emit_int8((unsigned char)(0xF8 | encode)); 6969 emit_int8(imm8); 6970 } 6971 } 6972 6973 void Assembler::sarq(Register dst) { 6974 int encode = prefixq_and_encode(dst->encoding()); 6975 emit_int8((unsigned char)0xD3); 6976 emit_int8((unsigned char)(0xF8 | encode)); 6977 } 6978 6979 void Assembler::sbbq(Address dst, int32_t imm32) { 6980 InstructionMark im(this); 6981 prefixq(dst); 6982 emit_arith_operand(0x81, rbx, dst, imm32); 6983 } 6984 6985 void Assembler::sbbq(Register dst, int32_t imm32) { 6986 (void) prefixq_and_encode(dst->encoding()); 6987 emit_arith(0x81, 0xD8, dst, imm32); 6988 } 6989 6990 void Assembler::sbbq(Register dst, Address src) { 6991 InstructionMark im(this); 6992 prefixq(src, dst); 6993 emit_int8(0x1B); 6994 emit_operand(dst, src); 6995 } 6996 6997 void Assembler::sbbq(Register dst, Register src) { 6998 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 6999 emit_arith(0x1B, 0xC0, dst, src); 7000 } 7001 7002 void Assembler::shlq(Register dst, int imm8) { 7003 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 7004 int encode = prefixq_and_encode(dst->encoding()); 7005 if (imm8 == 1) { 7006 emit_int8((unsigned char)0xD1); 7007 emit_int8((unsigned char)(0xE0 | encode)); 7008 } else { 7009 emit_int8((unsigned char)0xC1); 7010 emit_int8((unsigned char)(0xE0 | encode)); 7011 emit_int8(imm8); 7012 } 7013 } 7014 7015 void Assembler::shlq(Register dst) { 7016 int encode = prefixq_and_encode(dst->encoding()); 7017 emit_int8((unsigned char)0xD3); 7018 emit_int8((unsigned char)(0xE0 | encode)); 7019 } 7020 7021 void Assembler::shrq(Register dst, int imm8) { 7022 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 7023 int encode = prefixq_and_encode(dst->encoding()); 7024 emit_int8((unsigned char)0xC1); 7025 emit_int8((unsigned char)(0xE8 | encode)); 7026 emit_int8(imm8); 7027 } 7028 7029 void Assembler::shrq(Register dst) { 7030 int encode = prefixq_and_encode(dst->encoding()); 7031 emit_int8((unsigned char)0xD3); 7032 emit_int8(0xE8 | encode); 7033 } 7034 7035 void Assembler::subq(Address dst, int32_t imm32) { 7036 InstructionMark im(this); 7037 prefixq(dst); 7038 emit_arith_operand(0x81, rbp, dst, imm32); 7039 } 7040 7041 void Assembler::subq(Address dst, Register src) { 7042 InstructionMark im(this); 7043 prefixq(dst, src); 7044 emit_int8(0x29); 7045 emit_operand(src, dst); 7046 } 7047 7048 void Assembler::subq(Register dst, int32_t imm32) { 7049 (void) prefixq_and_encode(dst->encoding()); 7050 emit_arith(0x81, 0xE8, dst, imm32); 7051 } 7052 7053 // Force generation of a 4 byte immediate value even if it fits into 8bit 7054 void Assembler::subq_imm32(Register dst, int32_t imm32) { 7055 (void) prefixq_and_encode(dst->encoding()); 7056 emit_arith_imm32(0x81, 0xE8, dst, imm32); 7057 } 7058 7059 void Assembler::subq(Register dst, Address src) { 7060 InstructionMark im(this); 7061 prefixq(src, dst); 7062 emit_int8(0x2B); 7063 emit_operand(dst, src); 7064 } 7065 7066 void Assembler::subq(Register dst, Register src) { 7067 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7068 emit_arith(0x2B, 0xC0, dst, src); 7069 } 7070 7071 void Assembler::testq(Register dst, int32_t imm32) { 7072 // not using emit_arith because test 7073 // doesn't support sign-extension of 7074 // 8bit operands 7075 int encode = dst->encoding(); 7076 if (encode == 0) { 7077 prefix(REX_W); 7078 emit_int8((unsigned char)0xA9); 7079 } else { 7080 encode = prefixq_and_encode(encode); 7081 emit_int8((unsigned char)0xF7); 7082 emit_int8((unsigned char)(0xC0 | encode)); 7083 } 7084 emit_int32(imm32); 7085 } 7086 7087 void Assembler::testq(Register dst, Register src) { 7088 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7089 emit_arith(0x85, 0xC0, dst, src); 7090 } 7091 7092 void Assembler::xaddq(Address dst, Register src) { 7093 InstructionMark im(this); 7094 prefixq(dst, src); 7095 emit_int8(0x0F); 7096 emit_int8((unsigned char)0xC1); 7097 emit_operand(src, dst); 7098 } 7099 7100 void Assembler::xchgq(Register dst, Address src) { 7101 InstructionMark im(this); 7102 prefixq(src, dst); 7103 emit_int8((unsigned char)0x87); 7104 emit_operand(dst, src); 7105 } 7106 7107 void Assembler::xchgq(Register dst, Register src) { 7108 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7109 emit_int8((unsigned char)0x87); 7110 emit_int8((unsigned char)(0xc0 | encode)); 7111 } 7112 7113 void Assembler::xorq(Register dst, Register src) { 7114 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7115 emit_arith(0x33, 0xC0, dst, src); 7116 } 7117 7118 void Assembler::xorq(Register dst, Address src) { 7119 InstructionMark im(this); 7120 prefixq(src, dst); 7121 emit_int8(0x33); 7122 emit_operand(dst, src); 7123 } 7124 7125 #endif // !LP64