1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument VALUE_OBJ_CLASS_SPEC {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address VALUE_OBJ_CLASS_SPEC {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   ScaleFactor      _scale;
 188   int              _disp;
 189   RelocationHolder _rspec;
 190 
 191   // Easily misused constructors make them private
 192   // %%% can we make these go away?
 193   NOT_LP64(Address(address loc, RelocationHolder spec);)
 194   Address(int disp, address loc, relocInfo::relocType rtype);
 195   Address(int disp, address loc, RelocationHolder spec);
 196 
 197  public:
 198 
 199  int disp() { return _disp; }
 200   // creation
 201   Address()
 202     : _base(noreg),
 203       _index(noreg),
 204       _scale(no_scale),
 205       _disp(0) {
 206   }
 207 
 208   // No default displacement otherwise Register can be implicitly
 209   // converted to 0(Register) which is quite a different animal.
 210 
 211   Address(Register base, int disp)
 212     : _base(base),
 213       _index(noreg),
 214       _scale(no_scale),
 215       _disp(disp) {
 216   }
 217 
 218   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 219     : _base (base),
 220       _index(index),
 221       _scale(scale),
 222       _disp (disp) {
 223     assert(!index->is_valid() == (scale == Address::no_scale),
 224            "inconsistent address");
 225   }
 226 
 227   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 228     : _base (base),
 229       _index(index.register_or_noreg()),
 230       _scale(scale),
 231       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 232     if (!index.is_register())  scale = Address::no_scale;
 233     assert(!_index->is_valid() == (scale == Address::no_scale),
 234            "inconsistent address");
 235   }
 236 
 237   Address plus_disp(int disp) const {
 238     Address a = (*this);
 239     a._disp += disp;
 240     return a;
 241   }
 242   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 243     Address a = (*this);
 244     a._disp += disp.constant_or_zero() * scale_size(scale);
 245     if (disp.is_register()) {
 246       assert(!a.index()->is_valid(), "competing indexes");
 247       a._index = disp.as_register();
 248       a._scale = scale;
 249     }
 250     return a;
 251   }
 252   bool is_same_address(Address a) const {
 253     // disregard _rspec
 254     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 255   }
 256 
 257   // The following two overloads are used in connection with the
 258   // ByteSize type (see sizes.hpp).  They simplify the use of
 259   // ByteSize'd arguments in assembly code. Note that their equivalent
 260   // for the optimized build are the member functions with int disp
 261   // argument since ByteSize is mapped to an int type in that case.
 262   //
 263   // Note: DO NOT introduce similar overloaded functions for WordSize
 264   // arguments as in the optimized mode, both ByteSize and WordSize
 265   // are mapped to the same type and thus the compiler cannot make a
 266   // distinction anymore (=> compiler errors).
 267 
 268 #ifdef ASSERT
 269   Address(Register base, ByteSize disp)
 270     : _base(base),
 271       _index(noreg),
 272       _scale(no_scale),
 273       _disp(in_bytes(disp)) {
 274   }
 275 
 276   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 277     : _base(base),
 278       _index(index),
 279       _scale(scale),
 280       _disp(in_bytes(disp)) {
 281     assert(!index->is_valid() == (scale == Address::no_scale),
 282            "inconsistent address");
 283   }
 284 
 285   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 286     : _base (base),
 287       _index(index.register_or_noreg()),
 288       _scale(scale),
 289       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 290     if (!index.is_register())  scale = Address::no_scale;
 291     assert(!_index->is_valid() == (scale == Address::no_scale),
 292            "inconsistent address");
 293   }
 294 
 295 #endif // ASSERT
 296 
 297   // accessors
 298   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 299   Register    base()             const { return _base;  }
 300   Register    index()            const { return _index; }
 301   ScaleFactor scale()            const { return _scale; }
 302   int         disp()             const { return _disp;  }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base != noreg && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index != noreg &&_index->encoding() >= 8;
 318   }
 319 
 320   relocInfo::relocType reloc() const { return _rspec.type(); }
 321 
 322   friend class Assembler;
 323   friend class MacroAssembler;
 324   friend class LIR_Assembler; // base/index/scale/disp
 325 };
 326 
 327 //
 328 // AddressLiteral has been split out from Address because operands of this type
 329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 330 // the few instructions that need to deal with address literals are unique and the
 331 // MacroAssembler does not have to implement every instruction in the Assembler
 332 // in order to search for address literals that may need special handling depending
 333 // on the instruction and the platform. As small step on the way to merging i486/amd64
 334 // directories.
 335 //
 336 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 337   friend class ArrayAddress;
 338   RelocationHolder _rspec;
 339   // Typically we use AddressLiterals we want to use their rval
 340   // However in some situations we want the lval (effect address) of the item.
 341   // We provide a special factory for making those lvals.
 342   bool _is_lval;
 343 
 344   // If the target is far we'll need to load the ea of this to
 345   // a register to reach it. Otherwise if near we can do rip
 346   // relative addressing.
 347 
 348   address          _target;
 349 
 350  protected:
 351   // creation
 352   AddressLiteral()
 353     : _is_lval(false),
 354       _target(NULL)
 355   {}
 356 
 357   public:
 358 
 359 
 360   AddressLiteral(address target, relocInfo::relocType rtype);
 361 
 362   AddressLiteral(address target, RelocationHolder const& rspec)
 363     : _rspec(rspec),
 364       _is_lval(false),
 365       _target(target)
 366   {}
 367 
 368   AddressLiteral addr() {
 369     AddressLiteral ret = *this;
 370     ret._is_lval = true;
 371     return ret;
 372   }
 373 
 374 
 375  private:
 376 
 377   address target() { return _target; }
 378   bool is_lval() { return _is_lval; }
 379 
 380   relocInfo::relocType reloc() const { return _rspec.type(); }
 381   const RelocationHolder& rspec() const { return _rspec; }
 382 
 383   friend class Assembler;
 384   friend class MacroAssembler;
 385   friend class Address;
 386   friend class LIR_Assembler;
 387 };
 388 
 389 // Convience classes
 390 class RuntimeAddress: public AddressLiteral {
 391 
 392   public:
 393 
 394   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 395 
 396 };
 397 
 398 class ExternalAddress: public AddressLiteral {
 399  private:
 400   static relocInfo::relocType reloc_for_target(address target) {
 401     // Sometimes ExternalAddress is used for values which aren't
 402     // exactly addresses, like the card table base.
 403     // external_word_type can't be used for values in the first page
 404     // so just skip the reloc in that case.
 405     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 406   }
 407 
 408  public:
 409 
 410   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 411 
 412 };
 413 
 414 class InternalAddress: public AddressLiteral {
 415 
 416   public:
 417 
 418   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 419 
 420 };
 421 
 422 // x86 can do array addressing as a single operation since disp can be an absolute
 423 // address amd64 can't. We create a class that expresses the concept but does extra
 424 // magic on amd64 to get the final result
 425 
 426 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 427   private:
 428 
 429   AddressLiteral _base;
 430   Address        _index;
 431 
 432   public:
 433 
 434   ArrayAddress() {};
 435   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 436   AddressLiteral base() { return _base; }
 437   Address index() { return _index; }
 438 
 439 };
 440 
 441 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512*2 / wordSize);
 442 
 443 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 444 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 445 // is what you get. The Assembler is generating code into a CodeBuffer.
 446 
 447 class Assembler : public AbstractAssembler  {
 448   friend class AbstractAssembler; // for the non-virtual hack
 449   friend class LIR_Assembler; // as_Address()
 450   friend class StubGenerator;
 451 
 452  public:
 453   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 454     zero          = 0x4,
 455     notZero       = 0x5,
 456     equal         = 0x4,
 457     notEqual      = 0x5,
 458     less          = 0xc,
 459     lessEqual     = 0xe,
 460     greater       = 0xf,
 461     greaterEqual  = 0xd,
 462     below         = 0x2,
 463     belowEqual    = 0x6,
 464     above         = 0x7,
 465     aboveEqual    = 0x3,
 466     overflow      = 0x0,
 467     noOverflow    = 0x1,
 468     carrySet      = 0x2,
 469     carryClear    = 0x3,
 470     negative      = 0x8,
 471     positive      = 0x9,
 472     parity        = 0xa,
 473     noParity      = 0xb
 474   };
 475 
 476   enum Prefix {
 477     // segment overrides
 478     CS_segment = 0x2e,
 479     SS_segment = 0x36,
 480     DS_segment = 0x3e,
 481     ES_segment = 0x26,
 482     FS_segment = 0x64,
 483     GS_segment = 0x65,
 484 
 485     REX        = 0x40,
 486 
 487     REX_B      = 0x41,
 488     REX_X      = 0x42,
 489     REX_XB     = 0x43,
 490     REX_R      = 0x44,
 491     REX_RB     = 0x45,
 492     REX_RX     = 0x46,
 493     REX_RXB    = 0x47,
 494 
 495     REX_W      = 0x48,
 496 
 497     REX_WB     = 0x49,
 498     REX_WX     = 0x4A,
 499     REX_WXB    = 0x4B,
 500     REX_WR     = 0x4C,
 501     REX_WRB    = 0x4D,
 502     REX_WRX    = 0x4E,
 503     REX_WRXB   = 0x4F,
 504 
 505     VEX_3bytes = 0xC4,
 506     VEX_2bytes = 0xC5,
 507     EVEX_4bytes = 0x62
 508   };
 509 
 510   enum VexPrefix {
 511     VEX_B = 0x20,
 512     VEX_X = 0x40,
 513     VEX_R = 0x80,
 514     VEX_W = 0x80
 515   };
 516 
 517   enum ExexPrefix {
 518     EVEX_F  = 0x04,
 519     EVEX_V  = 0x08,
 520     EVEX_Rb = 0x10,
 521     EVEX_X  = 0x40,
 522     EVEX_Z  = 0x80
 523   };
 524 
 525   enum VexSimdPrefix {
 526     VEX_SIMD_NONE = 0x0,
 527     VEX_SIMD_66   = 0x1,
 528     VEX_SIMD_F3   = 0x2,
 529     VEX_SIMD_F2   = 0x3
 530   };
 531 
 532   enum VexOpcode {
 533     VEX_OPCODE_NONE  = 0x0,
 534     VEX_OPCODE_0F    = 0x1,
 535     VEX_OPCODE_0F_38 = 0x2,
 536     VEX_OPCODE_0F_3A = 0x3
 537   };
 538 
 539   enum AvxVectorLen {
 540     AVX_128bit = 0x0,
 541     AVX_256bit = 0x1,
 542     AVX_512bit = 0x2,
 543     AVX_NoVec  = 0x4
 544   };
 545 
 546   enum EvexTupleType {
 547     EVEX_FV   = 0,
 548     EVEX_HV   = 4,
 549     EVEX_FVM  = 6,
 550     EVEX_T1S  = 7,
 551     EVEX_T1F  = 11,
 552     EVEX_T2   = 13,
 553     EVEX_T4   = 15,
 554     EVEX_T8   = 17,
 555     EVEX_HVM  = 18,
 556     EVEX_QVM  = 19,
 557     EVEX_OVM  = 20,
 558     EVEX_M128 = 21,
 559     EVEX_DUP  = 22,
 560     EVEX_ETUP = 23
 561   };
 562 
 563   enum EvexInputSizeInBits {
 564     EVEX_8bit  = 0,
 565     EVEX_16bit = 1,
 566     EVEX_32bit = 2,
 567     EVEX_64bit = 3
 568   };
 569 
 570   enum WhichOperand {
 571     // input to locate_operand, and format code for relocations
 572     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 573     disp32_operand = 1,          // embedded 32-bit displacement or address
 574     call32_operand = 2,          // embedded 32-bit self-relative displacement
 575 #ifndef _LP64
 576     _WhichOperand_limit = 3
 577 #else
 578      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 579     _WhichOperand_limit = 4
 580 #endif
 581   };
 582 
 583 
 584 
 585   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 586   // of instructions are freely declared without the need for wrapping them an ifdef.
 587   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 588   // In the .cpp file the implementations are wrapped so that they are dropped out
 589   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 590   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 591   //
 592   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 593   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 594 
 595 private:
 596 
 597   int evex_encoding;
 598   int input_size_in_bits;
 599   int avx_vector_len;
 600   int tuple_type;
 601   bool is_evex_instruction;
 602 
 603   // 64bit prefixes
 604   int prefix_and_encode(int reg_enc, bool byteinst = false);
 605   int prefixq_and_encode(int reg_enc);
 606 
 607   int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
 608   int prefixq_and_encode(int dst_enc, int src_enc);
 609 
 610   void prefix(Register reg);
 611   void prefix(Address adr);
 612   void prefixq(Address adr);
 613 
 614   void prefix(Address adr, Register reg,  bool byteinst = false);
 615   void prefix(Address adr, XMMRegister reg);
 616   void prefixq(Address adr, Register reg);
 617   void prefixq(Address adr, XMMRegister reg);
 618 
 619   void prefetch_prefix(Address src);
 620 
 621   void rex_prefix(Address adr, XMMRegister xreg,
 622                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 623   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 624                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 625 
 626   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
 627                   int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 628                   int vector_len);
 629 
 630   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
 631                    int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 632                    bool is_extended_context, bool is_merge_context,
 633                    int vector_len, bool no_mask_reg );
 634 
 635   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 636                   VexSimdPrefix pre, VexOpcode opc,
 637                   bool vex_w, int vector_len,
 638                   bool legacy_mode = false, bool no_mask_reg = false);
 639 
 640   void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
 641                   VexSimdPrefix pre, int vector_len = AVX_128bit,
 642                   bool no_mask_reg = false, bool legacy_mode = false) {
 643     int dst_enc = dst->encoding();
 644     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 645     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector_len, legacy_mode, no_mask_reg);
 646   }
 647 
 648   void vex_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 649                     VexSimdPrefix pre, int vector_len = AVX_128bit,
 650                     bool no_mask_reg = false) {
 651     int dst_enc = dst->encoding();
 652     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 653     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
 654   }
 655 
 656   void vex_prefix_0F38(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 657     bool vex_w = false;
 658     int vector_len = AVX_128bit;
 659     vex_prefix(src, nds->encoding(), dst->encoding(),
 660                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 661                vector_len, no_mask_reg);
 662   }
 663 
 664   void vex_prefix_0F38_q(Register dst, Register nds, Address src, bool no_mask_reg = false) {
 665     bool vex_w = true;
 666     int vector_len = AVX_128bit;
 667     vex_prefix(src, nds->encoding(), dst->encoding(),
 668                VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
 669                vector_len, no_mask_reg);
 670   }
 671   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 672                              VexSimdPrefix pre, VexOpcode opc,
 673                              bool vex_w, int vector_len,
 674                              bool legacy_mode, bool no_mask_reg);
 675 
 676   int  vex_prefix_0F38_and_encode(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 677     bool vex_w = false;
 678     int vector_len = AVX_128bit;
 679     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 680                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 681                                  false, no_mask_reg);
 682   }
 683   int  vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src, bool no_mask_reg = false) {
 684     bool vex_w = true;
 685     int vector_len = AVX_128bit;
 686     return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 687                                  VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
 688                                  false, no_mask_reg);
 689   }
 690   int  vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 691                              VexSimdPrefix pre, int vector_len = AVX_128bit,
 692                              VexOpcode opc = VEX_OPCODE_0F, bool legacy_mode = false,
 693                              bool no_mask_reg = false) {
 694     int src_enc = src->encoding();
 695     int dst_enc = dst->encoding();
 696     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
 697     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector_len, legacy_mode, no_mask_reg);
 698   }
 699 
 700   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
 701                    VexSimdPrefix pre, bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F,
 702                    bool rex_w = false, int vector_len = AVX_128bit, bool legacy_mode = false);
 703 
 704   void simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre,
 705                    bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F) {
 706     simd_prefix(dst, xnoreg, src, pre, no_mask_reg, opc);
 707   }
 708 
 709   void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
 710     simd_prefix(src, dst, pre, no_mask_reg);
 711   }
 712   void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 713                      VexSimdPrefix pre, bool no_mask_reg = false) {
 714     bool rex_w = true;
 715     simd_prefix(dst, nds, src, pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
 716   }
 717 
 718   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 719                              VexSimdPrefix pre, bool no_mask_reg,
 720                              VexOpcode opc = VEX_OPCODE_0F,
 721                              bool rex_w = false, int vector_len = AVX_128bit,
 722                              bool legacy_mode = false);
 723 
 724   int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src,
 725                              VexSimdPrefix pre, bool no_mask_reg,
 726                              VexOpcode opc = VEX_OPCODE_0F,
 727                              bool rex_w = false, int vector_len = AVX_128bit);
 728 
 729   int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src,
 730                              VexSimdPrefix pre, bool no_mask_reg,
 731                              VexOpcode opc = VEX_OPCODE_0F,
 732                              bool rex_w = false, int vector_len = AVX_128bit);
 733 
 734   // Move/convert 32-bit integer value.
 735   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
 736                              VexSimdPrefix pre, bool no_mask_reg) {
 737     // It is OK to cast from Register to XMMRegister to pass argument here
 738     // since only encoding is used in simd_prefix_and_encode() and number of
 739     // Gen and Xmm registers are the same.
 740     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F);
 741   }
 742   int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
 743     return simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg);
 744   }
 745   int simd_prefix_and_encode(Register dst, XMMRegister src,
 746                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 747                              bool no_mask_reg = false) {
 748     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc);
 749   }
 750 
 751   // Move/convert 64-bit integer value.
 752   int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
 753                                VexSimdPrefix pre, bool no_mask_reg = false) {
 754     bool rex_w = true;
 755     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
 756   }
 757   int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
 758     return simd_prefix_and_encode_q(dst, xnoreg, src, pre, no_mask_reg);
 759   }
 760   int simd_prefix_and_encode_q(Register dst, XMMRegister src,
 761                                VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 762                                bool no_mask_reg = false) {
 763     bool rex_w = true;
 764     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc, rex_w);
 765   }
 766 
 767   // Helper functions for groups of instructions
 768   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 769 
 770   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 771   // Force generation of a 4 byte immediate value even if it fits into 8bit
 772   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 773   void emit_arith(int op1, int op2, Register dst, Register src);
 774 
 775   void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 776   void emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 777   void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 778   void emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
 779   void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 780   void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
 781   void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false, bool legacy_mode = false);
 782   void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
 783   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 784                       Address src, VexSimdPrefix pre, int vector_len,
 785                       bool no_mask_reg = false, bool legacy_mode = false);
 786   void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
 787                         Address src, VexSimdPrefix pre, int vector_len,
 788                         bool no_mask_reg = false);
 789   void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
 790                       XMMRegister src, VexSimdPrefix pre, int vector_len,
 791                       bool no_mask_reg = false, bool legacy_mode = false);
 792   void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
 793                         XMMRegister src, VexSimdPrefix pre, int vector_len,
 794                         bool no_mask_reg = false);
 795 
 796   bool emit_compressed_disp_byte(int &disp);
 797 
 798   void emit_operand(Register reg,
 799                     Register base, Register index, Address::ScaleFactor scale,
 800                     int disp,
 801                     RelocationHolder const& rspec,
 802                     int rip_relative_correction = 0);
 803 
 804   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 805 
 806   // operands that only take the original 32bit registers
 807   void emit_operand32(Register reg, Address adr);
 808 
 809   void emit_operand(XMMRegister reg,
 810                     Register base, Register index, Address::ScaleFactor scale,
 811                     int disp,
 812                     RelocationHolder const& rspec);
 813 
 814   void emit_operand(XMMRegister reg, Address adr);
 815 
 816   void emit_operand(MMXRegister reg, Address adr);
 817 
 818   // workaround gcc (3.2.1-7) bug
 819   void emit_operand(Address adr, MMXRegister reg);
 820 
 821 
 822   // Immediate-to-memory forms
 823   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 824 
 825   void emit_farith(int b1, int b2, int i);
 826 
 827 
 828  protected:
 829   #ifdef ASSERT
 830   void check_relocation(RelocationHolder const& rspec, int format);
 831   #endif
 832 
 833   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 834   void emit_data(jint data, RelocationHolder const& rspec, int format);
 835   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 836   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 837 
 838   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 839 
 840   // These are all easily abused and hence protected
 841 
 842   // 32BIT ONLY SECTION
 843 #ifndef _LP64
 844   // Make these disappear in 64bit mode since they would never be correct
 845   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 846   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 847 
 848   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 849   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 850 
 851   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 852 #else
 853   // 64BIT ONLY SECTION
 854   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 855 
 856   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 857   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 858 
 859   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 860   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 861 #endif // _LP64
 862 
 863   // These are unique in that we are ensured by the caller that the 32bit
 864   // relative in these instructions will always be able to reach the potentially
 865   // 64bit address described by entry. Since they can take a 64bit address they
 866   // don't have the 32 suffix like the other instructions in this class.
 867 
 868   void call_literal(address entry, RelocationHolder const& rspec);
 869   void jmp_literal(address entry, RelocationHolder const& rspec);
 870 
 871   // Avoid using directly section
 872   // Instructions in this section are actually usable by anyone without danger
 873   // of failure but have performance issues that are addressed my enhanced
 874   // instructions which will do the proper thing base on the particular cpu.
 875   // We protect them because we don't trust you...
 876 
 877   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 878   // could cause a partial flag stall since they don't set CF flag.
 879   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 880   // which call inc() & dec() or add() & sub() in accordance with
 881   // the product flag UseIncDec value.
 882 
 883   void decl(Register dst);
 884   void decl(Address dst);
 885   void decq(Register dst);
 886   void decq(Address dst);
 887 
 888   void incl(Register dst);
 889   void incl(Address dst);
 890   void incq(Register dst);
 891   void incq(Address dst);
 892 
 893   // New cpus require use of movsd and movss to avoid partial register stall
 894   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 895   // The selection is done in MacroAssembler::movdbl() and movflt().
 896 
 897   // Move Scalar Single-Precision Floating-Point Values
 898   void movss(XMMRegister dst, Address src);
 899   void movss(XMMRegister dst, XMMRegister src);
 900   void movss(Address dst, XMMRegister src);
 901 
 902   // Move Scalar Double-Precision Floating-Point Values
 903   void movsd(XMMRegister dst, Address src);
 904   void movsd(XMMRegister dst, XMMRegister src);
 905   void movsd(Address dst, XMMRegister src);
 906   void movlpd(XMMRegister dst, Address src);
 907 
 908   // New cpus require use of movaps and movapd to avoid partial register stall
 909   // when moving between registers.
 910   void movaps(XMMRegister dst, XMMRegister src);
 911   void movapd(XMMRegister dst, XMMRegister src);
 912 
 913   // End avoid using directly
 914 
 915 
 916   // Instruction prefixes
 917   void prefix(Prefix p);
 918 
 919   public:
 920 
 921   // Creation
 922   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 923     init_attributes();
 924   }
 925 
 926   // Decoding
 927   static address locate_operand(address inst, WhichOperand which);
 928   static address locate_next_instruction(address inst);
 929 
 930   // Utilities
 931   static bool is_polling_page_far() NOT_LP64({ return false;});
 932   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 933                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 934 
 935   // Generic instructions
 936   // Does 32bit or 64bit as needed for the platform. In some sense these
 937   // belong in macro assembler but there is no need for both varieties to exist
 938 
 939   void init_attributes(void) {
 940     evex_encoding = 0;
 941     input_size_in_bits = 0;
 942     avx_vector_len = AVX_NoVec;
 943     tuple_type = EVEX_ETUP;
 944     is_evex_instruction = false;
 945   }
 946 
 947   void lea(Register dst, Address src);
 948 
 949   void mov(Register dst, Register src);
 950 
 951   void pusha();
 952   void popa();
 953 
 954   void pushf();
 955   void popf();
 956 
 957   void push(int32_t imm32);
 958 
 959   void push(Register src);
 960 
 961   void pop(Register dst);
 962 
 963   // These are dummies to prevent surprise implicit conversions to Register
 964   void push(void* v);
 965   void pop(void* v);
 966 
 967   // These do register sized moves/scans
 968   void rep_mov();
 969   void rep_stos();
 970   void rep_stosb();
 971   void repne_scan();
 972 #ifdef _LP64
 973   void repne_scanl();
 974 #endif
 975 
 976   // Vanilla instructions in lexical order
 977 
 978   void adcl(Address dst, int32_t imm32);
 979   void adcl(Address dst, Register src);
 980   void adcl(Register dst, int32_t imm32);
 981   void adcl(Register dst, Address src);
 982   void adcl(Register dst, Register src);
 983 
 984   void adcq(Register dst, int32_t imm32);
 985   void adcq(Register dst, Address src);
 986   void adcq(Register dst, Register src);
 987 
 988   void addl(Address dst, int32_t imm32);
 989   void addl(Address dst, Register src);
 990   void addl(Register dst, int32_t imm32);
 991   void addl(Register dst, Address src);
 992   void addl(Register dst, Register src);
 993 
 994   void addq(Address dst, int32_t imm32);
 995   void addq(Address dst, Register src);
 996   void addq(Register dst, int32_t imm32);
 997   void addq(Register dst, Address src);
 998   void addq(Register dst, Register src);
 999 
1000 #ifdef _LP64
1001  //Add Unsigned Integers with Carry Flag
1002   void adcxq(Register dst, Register src);
1003 
1004  //Add Unsigned Integers with Overflow Flag
1005   void adoxq(Register dst, Register src);
1006 #endif
1007 
1008   void addr_nop_4();
1009   void addr_nop_5();
1010   void addr_nop_7();
1011   void addr_nop_8();
1012 
1013   // Add Scalar Double-Precision Floating-Point Values
1014   void addsd(XMMRegister dst, Address src);
1015   void addsd(XMMRegister dst, XMMRegister src);
1016 
1017   // Add Scalar Single-Precision Floating-Point Values
1018   void addss(XMMRegister dst, Address src);
1019   void addss(XMMRegister dst, XMMRegister src);
1020 
1021   // AES instructions
1022   void aesdec(XMMRegister dst, Address src);
1023   void aesdec(XMMRegister dst, XMMRegister src);
1024   void aesdeclast(XMMRegister dst, Address src);
1025   void aesdeclast(XMMRegister dst, XMMRegister src);
1026   void aesenc(XMMRegister dst, Address src);
1027   void aesenc(XMMRegister dst, XMMRegister src);
1028   void aesenclast(XMMRegister dst, Address src);
1029   void aesenclast(XMMRegister dst, XMMRegister src);
1030 
1031 
1032   void andl(Address  dst, int32_t imm32);
1033   void andl(Register dst, int32_t imm32);
1034   void andl(Register dst, Address src);
1035   void andl(Register dst, Register src);
1036 
1037   void andq(Address  dst, int32_t imm32);
1038   void andq(Register dst, int32_t imm32);
1039   void andq(Register dst, Address src);
1040   void andq(Register dst, Register src);
1041 
1042   // BMI instructions
1043   void andnl(Register dst, Register src1, Register src2);
1044   void andnl(Register dst, Register src1, Address src2);
1045   void andnq(Register dst, Register src1, Register src2);
1046   void andnq(Register dst, Register src1, Address src2);
1047 
1048   void blsil(Register dst, Register src);
1049   void blsil(Register dst, Address src);
1050   void blsiq(Register dst, Register src);
1051   void blsiq(Register dst, Address src);
1052 
1053   void blsmskl(Register dst, Register src);
1054   void blsmskl(Register dst, Address src);
1055   void blsmskq(Register dst, Register src);
1056   void blsmskq(Register dst, Address src);
1057 
1058   void blsrl(Register dst, Register src);
1059   void blsrl(Register dst, Address src);
1060   void blsrq(Register dst, Register src);
1061   void blsrq(Register dst, Address src);
1062 
1063   void bsfl(Register dst, Register src);
1064   void bsrl(Register dst, Register src);
1065 
1066 #ifdef _LP64
1067   void bsfq(Register dst, Register src);
1068   void bsrq(Register dst, Register src);
1069 #endif
1070 
1071   void bswapl(Register reg);
1072 
1073   void bswapq(Register reg);
1074 
1075   void call(Label& L, relocInfo::relocType rtype);
1076   void call(Register reg);  // push pc; pc <- reg
1077   void call(Address adr);   // push pc; pc <- adr
1078 
1079   void cdql();
1080 
1081   void cdqq();
1082 
1083   void cld();
1084 
1085   void clflush(Address adr);
1086 
1087   void cmovl(Condition cc, Register dst, Register src);
1088   void cmovl(Condition cc, Register dst, Address src);
1089 
1090   void cmovq(Condition cc, Register dst, Register src);
1091   void cmovq(Condition cc, Register dst, Address src);
1092 
1093 
1094   void cmpb(Address dst, int imm8);
1095 
1096   void cmpl(Address dst, int32_t imm32);
1097 
1098   void cmpl(Register dst, int32_t imm32);
1099   void cmpl(Register dst, Register src);
1100   void cmpl(Register dst, Address src);
1101 
1102   void cmpq(Address dst, int32_t imm32);
1103   void cmpq(Address dst, Register src);
1104 
1105   void cmpq(Register dst, int32_t imm32);
1106   void cmpq(Register dst, Register src);
1107   void cmpq(Register dst, Address src);
1108 
1109   // these are dummies used to catch attempting to convert NULL to Register
1110   void cmpl(Register dst, void* junk); // dummy
1111   void cmpq(Register dst, void* junk); // dummy
1112 
1113   void cmpw(Address dst, int imm16);
1114 
1115   void cmpxchg8 (Address adr);
1116 
1117   void cmpxchgb(Register reg, Address adr);
1118   void cmpxchgl(Register reg, Address adr);
1119 
1120   void cmpxchgq(Register reg, Address adr);
1121 
1122   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1123   void comisd(XMMRegister dst, Address src);
1124   void comisd(XMMRegister dst, XMMRegister src);
1125 
1126   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1127   void comiss(XMMRegister dst, Address src);
1128   void comiss(XMMRegister dst, XMMRegister src);
1129 
1130   // Identify processor type and features
1131   void cpuid();
1132 
1133   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1134   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1135   void cvtsd2ss(XMMRegister dst, Address src);
1136 
1137   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1138   void cvtsi2sdl(XMMRegister dst, Register src);
1139   void cvtsi2sdl(XMMRegister dst, Address src);
1140   void cvtsi2sdq(XMMRegister dst, Register src);
1141   void cvtsi2sdq(XMMRegister dst, Address src);
1142 
1143   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1144   void cvtsi2ssl(XMMRegister dst, Register src);
1145   void cvtsi2ssl(XMMRegister dst, Address src);
1146   void cvtsi2ssq(XMMRegister dst, Register src);
1147   void cvtsi2ssq(XMMRegister dst, Address src);
1148 
1149   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1150   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1151 
1152   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1153   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1154 
1155   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1156   void cvtss2sd(XMMRegister dst, XMMRegister src);
1157   void cvtss2sd(XMMRegister dst, Address src);
1158 
1159   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1160   void cvttsd2sil(Register dst, Address src);
1161   void cvttsd2sil(Register dst, XMMRegister src);
1162   void cvttsd2siq(Register dst, XMMRegister src);
1163 
1164   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1165   void cvttss2sil(Register dst, XMMRegister src);
1166   void cvttss2siq(Register dst, XMMRegister src);
1167 
1168   // Divide Scalar Double-Precision Floating-Point Values
1169   void divsd(XMMRegister dst, Address src);
1170   void divsd(XMMRegister dst, XMMRegister src);
1171 
1172   // Divide Scalar Single-Precision Floating-Point Values
1173   void divss(XMMRegister dst, Address src);
1174   void divss(XMMRegister dst, XMMRegister src);
1175 
1176   void emms();
1177 
1178   void fabs();
1179 
1180   void fadd(int i);
1181 
1182   void fadd_d(Address src);
1183   void fadd_s(Address src);
1184 
1185   // "Alternate" versions of x87 instructions place result down in FPU
1186   // stack instead of on TOS
1187 
1188   void fadda(int i); // "alternate" fadd
1189   void faddp(int i = 1);
1190 
1191   void fchs();
1192 
1193   void fcom(int i);
1194 
1195   void fcomp(int i = 1);
1196   void fcomp_d(Address src);
1197   void fcomp_s(Address src);
1198 
1199   void fcompp();
1200 
1201   void fcos();
1202 
1203   void fdecstp();
1204 
1205   void fdiv(int i);
1206   void fdiv_d(Address src);
1207   void fdivr_s(Address src);
1208   void fdiva(int i);  // "alternate" fdiv
1209   void fdivp(int i = 1);
1210 
1211   void fdivr(int i);
1212   void fdivr_d(Address src);
1213   void fdiv_s(Address src);
1214 
1215   void fdivra(int i); // "alternate" reversed fdiv
1216 
1217   void fdivrp(int i = 1);
1218 
1219   void ffree(int i = 0);
1220 
1221   void fild_d(Address adr);
1222   void fild_s(Address adr);
1223 
1224   void fincstp();
1225 
1226   void finit();
1227 
1228   void fist_s (Address adr);
1229   void fistp_d(Address adr);
1230   void fistp_s(Address adr);
1231 
1232   void fld1();
1233 
1234   void fld_d(Address adr);
1235   void fld_s(Address adr);
1236   void fld_s(int index);
1237   void fld_x(Address adr);  // extended-precision (80-bit) format
1238 
1239   void fldcw(Address src);
1240 
1241   void fldenv(Address src);
1242 
1243   void fldlg2();
1244 
1245   void fldln2();
1246 
1247   void fldz();
1248 
1249   void flog();
1250   void flog10();
1251 
1252   void fmul(int i);
1253 
1254   void fmul_d(Address src);
1255   void fmul_s(Address src);
1256 
1257   void fmula(int i);  // "alternate" fmul
1258 
1259   void fmulp(int i = 1);
1260 
1261   void fnsave(Address dst);
1262 
1263   void fnstcw(Address src);
1264 
1265   void fnstsw_ax();
1266 
1267   void fprem();
1268   void fprem1();
1269 
1270   void frstor(Address src);
1271 
1272   void fsin();
1273 
1274   void fsqrt();
1275 
1276   void fst_d(Address adr);
1277   void fst_s(Address adr);
1278 
1279   void fstp_d(Address adr);
1280   void fstp_d(int index);
1281   void fstp_s(Address adr);
1282   void fstp_x(Address adr); // extended-precision (80-bit) format
1283 
1284   void fsub(int i);
1285   void fsub_d(Address src);
1286   void fsub_s(Address src);
1287 
1288   void fsuba(int i);  // "alternate" fsub
1289 
1290   void fsubp(int i = 1);
1291 
1292   void fsubr(int i);
1293   void fsubr_d(Address src);
1294   void fsubr_s(Address src);
1295 
1296   void fsubra(int i); // "alternate" reversed fsub
1297 
1298   void fsubrp(int i = 1);
1299 
1300   void ftan();
1301 
1302   void ftst();
1303 
1304   void fucomi(int i = 1);
1305   void fucomip(int i = 1);
1306 
1307   void fwait();
1308 
1309   void fxch(int i = 1);
1310 
1311   void fxrstor(Address src);
1312 
1313   void fxsave(Address dst);
1314 
1315   void fyl2x();
1316   void frndint();
1317   void f2xm1();
1318   void fldl2e();
1319 
1320   void hlt();
1321 
1322   void idivl(Register src);
1323   void divl(Register src); // Unsigned division
1324 
1325 #ifdef _LP64
1326   void idivq(Register src);
1327 #endif
1328 
1329   void imull(Register dst, Register src);
1330   void imull(Register dst, Register src, int value);
1331   void imull(Register dst, Address src);
1332 
1333 #ifdef _LP64
1334   void imulq(Register dst, Register src);
1335   void imulq(Register dst, Register src, int value);
1336   void imulq(Register dst, Address src);
1337 #endif
1338 
1339   // jcc is the generic conditional branch generator to run-
1340   // time routines, jcc is used for branches to labels. jcc
1341   // takes a branch opcode (cc) and a label (L) and generates
1342   // either a backward branch or a forward branch and links it
1343   // to the label fixup chain. Usage:
1344   //
1345   // Label L;      // unbound label
1346   // jcc(cc, L);   // forward branch to unbound label
1347   // bind(L);      // bind label to the current pc
1348   // jcc(cc, L);   // backward branch to bound label
1349   // bind(L);      // illegal: a label may be bound only once
1350   //
1351   // Note: The same Label can be used for forward and backward branches
1352   // but it may be bound only once.
1353 
1354   void jcc(Condition cc, Label& L, bool maybe_short = true);
1355 
1356   // Conditional jump to a 8-bit offset to L.
1357   // WARNING: be very careful using this for forward jumps.  If the label is
1358   // not bound within an 8-bit offset of this instruction, a run-time error
1359   // will occur.
1360   void jccb(Condition cc, Label& L);
1361 
1362   void jmp(Address entry);    // pc <- entry
1363 
1364   // Label operations & relative jumps (PPUM Appendix D)
1365   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1366 
1367   void jmp(Register entry); // pc <- entry
1368 
1369   // Unconditional 8-bit offset jump to L.
1370   // WARNING: be very careful using this for forward jumps.  If the label is
1371   // not bound within an 8-bit offset of this instruction, a run-time error
1372   // will occur.
1373   void jmpb(Label& L);
1374 
1375   void ldmxcsr( Address src );
1376 
1377   void leal(Register dst, Address src);
1378 
1379   void leaq(Register dst, Address src);
1380 
1381   void lfence();
1382 
1383   void lock();
1384 
1385   void lzcntl(Register dst, Register src);
1386 
1387 #ifdef _LP64
1388   void lzcntq(Register dst, Register src);
1389 #endif
1390 
1391   enum Membar_mask_bits {
1392     StoreStore = 1 << 3,
1393     LoadStore  = 1 << 2,
1394     StoreLoad  = 1 << 1,
1395     LoadLoad   = 1 << 0
1396   };
1397 
1398   // Serializes memory and blows flags
1399   void membar(Membar_mask_bits order_constraint) {
1400     if (os::is_MP()) {
1401       // We only have to handle StoreLoad
1402       if (order_constraint & StoreLoad) {
1403         // All usable chips support "locked" instructions which suffice
1404         // as barriers, and are much faster than the alternative of
1405         // using cpuid instruction. We use here a locked add [esp-C],0.
1406         // This is conveniently otherwise a no-op except for blowing
1407         // flags, and introducing a false dependency on target memory
1408         // location. We can't do anything with flags, but we can avoid
1409         // memory dependencies in the current method by locked-adding
1410         // somewhere else on the stack. Doing [esp+C] will collide with
1411         // something on stack in current method, hence we go for [esp-C].
1412         // It is convenient since it is almost always in data cache, for
1413         // any small C.  We need to step back from SP to avoid data
1414         // dependencies with other things on below SP (callee-saves, for
1415         // example). Without a clear way to figure out the minimal safe
1416         // distance from SP, it makes sense to step back the complete
1417         // cache line, as this will also avoid possible second-order effects
1418         // with locked ops against the cache line. Our choice of offset
1419         // is bounded by x86 operand encoding, which should stay within
1420         // [-128; +127] to have the 8-byte displacement encoding.
1421         //
1422         // Any change to this code may need to revisit other places in
1423         // the code where this idiom is used, in particular the
1424         // orderAccess code.
1425 
1426         int offset = -VM_Version::L1_line_size();
1427         if (offset < -128) {
1428           offset = -128;
1429         }
1430 
1431         lock();
1432         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1433       }
1434     }
1435   }
1436 
1437   void mfence();
1438 
1439   // Moves
1440 
1441   void mov64(Register dst, int64_t imm64);
1442 
1443   void movb(Address dst, Register src);
1444   void movb(Address dst, int imm8);
1445   void movb(Register dst, Address src);
1446 
1447   void kmovq(KRegister dst, KRegister src);
1448   void kmovql(KRegister dst, Register src);
1449   void kmovdl(KRegister dst, Register src);
1450   void kmovq(Address dst, KRegister src);
1451   void kmovq(KRegister dst, Address src);
1452 
1453   void movdl(XMMRegister dst, Register src);
1454   void movdl(Register dst, XMMRegister src);
1455   void movdl(XMMRegister dst, Address src);
1456   void movdl(Address dst, XMMRegister src);
1457 
1458   // Move Double Quadword
1459   void movdq(XMMRegister dst, Register src);
1460   void movdq(Register dst, XMMRegister src);
1461 
1462   // Move Aligned Double Quadword
1463   void movdqa(XMMRegister dst, XMMRegister src);
1464   void movdqa(XMMRegister dst, Address src);
1465 
1466   // Move Unaligned Double Quadword
1467   void movdqu(Address     dst, XMMRegister src);
1468   void movdqu(XMMRegister dst, Address src);
1469   void movdqu(XMMRegister dst, XMMRegister src);
1470 
1471   // Move Unaligned 256bit Vector
1472   void vmovdqu(Address dst, XMMRegister src);
1473   void vmovdqu(XMMRegister dst, Address src);
1474   void vmovdqu(XMMRegister dst, XMMRegister src);
1475 
1476    // Move Unaligned 512bit Vector
1477   void evmovdqu(Address dst, XMMRegister src, int vector_len);
1478   void evmovdqu(XMMRegister dst, Address src, int vector_len);
1479   void evmovdqu(XMMRegister dst, XMMRegister src, int vector_len);
1480 
1481   // Move lower 64bit to high 64bit in 128bit register
1482   void movlhps(XMMRegister dst, XMMRegister src);
1483 
1484   void movl(Register dst, int32_t imm32);
1485   void movl(Address dst, int32_t imm32);
1486   void movl(Register dst, Register src);
1487   void movl(Register dst, Address src);
1488   void movl(Address dst, Register src);
1489 
1490   // These dummies prevent using movl from converting a zero (like NULL) into Register
1491   // by giving the compiler two choices it can't resolve
1492 
1493   void movl(Address  dst, void* junk);
1494   void movl(Register dst, void* junk);
1495 
1496 #ifdef _LP64
1497   void movq(Register dst, Register src);
1498   void movq(Register dst, Address src);
1499   void movq(Address  dst, Register src);
1500 #endif
1501 
1502   void movq(Address     dst, MMXRegister src );
1503   void movq(MMXRegister dst, Address src );
1504 
1505 #ifdef _LP64
1506   // These dummies prevent using movq from converting a zero (like NULL) into Register
1507   // by giving the compiler two choices it can't resolve
1508 
1509   void movq(Address  dst, void* dummy);
1510   void movq(Register dst, void* dummy);
1511 #endif
1512 
1513   // Move Quadword
1514   void movq(Address     dst, XMMRegister src);
1515   void movq(XMMRegister dst, Address src);
1516 
1517   void movsbl(Register dst, Address src);
1518   void movsbl(Register dst, Register src);
1519 
1520 #ifdef _LP64
1521   void movsbq(Register dst, Address src);
1522   void movsbq(Register dst, Register src);
1523 
1524   // Move signed 32bit immediate to 64bit extending sign
1525   void movslq(Address  dst, int32_t imm64);
1526   void movslq(Register dst, int32_t imm64);
1527 
1528   void movslq(Register dst, Address src);
1529   void movslq(Register dst, Register src);
1530   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1531 #endif
1532 
1533   void movswl(Register dst, Address src);
1534   void movswl(Register dst, Register src);
1535 
1536 #ifdef _LP64
1537   void movswq(Register dst, Address src);
1538   void movswq(Register dst, Register src);
1539 #endif
1540 
1541   void movw(Address dst, int imm16);
1542   void movw(Register dst, Address src);
1543   void movw(Address dst, Register src);
1544 
1545   void movzbl(Register dst, Address src);
1546   void movzbl(Register dst, Register src);
1547 
1548 #ifdef _LP64
1549   void movzbq(Register dst, Address src);
1550   void movzbq(Register dst, Register src);
1551 #endif
1552 
1553   void movzwl(Register dst, Address src);
1554   void movzwl(Register dst, Register src);
1555 
1556 #ifdef _LP64
1557   void movzwq(Register dst, Address src);
1558   void movzwq(Register dst, Register src);
1559 #endif
1560 
1561   // Unsigned multiply with RAX destination register
1562   void mull(Address src);
1563   void mull(Register src);
1564 
1565 #ifdef _LP64
1566   void mulq(Address src);
1567   void mulq(Register src);
1568   void mulxq(Register dst1, Register dst2, Register src);
1569 #endif
1570 
1571   // Multiply Scalar Double-Precision Floating-Point Values
1572   void mulsd(XMMRegister dst, Address src);
1573   void mulsd(XMMRegister dst, XMMRegister src);
1574 
1575   // Multiply Scalar Single-Precision Floating-Point Values
1576   void mulss(XMMRegister dst, Address src);
1577   void mulss(XMMRegister dst, XMMRegister src);
1578 
1579   void negl(Register dst);
1580 
1581 #ifdef _LP64
1582   void negq(Register dst);
1583 #endif
1584 
1585   void nop(int i = 1);
1586 
1587   void notl(Register dst);
1588 
1589 #ifdef _LP64
1590   void notq(Register dst);
1591 #endif
1592 
1593   void orl(Address dst, int32_t imm32);
1594   void orl(Register dst, int32_t imm32);
1595   void orl(Register dst, Address src);
1596   void orl(Register dst, Register src);
1597   void orl(Address dst, Register src);
1598 
1599   void orq(Address dst, int32_t imm32);
1600   void orq(Register dst, int32_t imm32);
1601   void orq(Register dst, Address src);
1602   void orq(Register dst, Register src);
1603 
1604   // Pack with unsigned saturation
1605   void packuswb(XMMRegister dst, XMMRegister src);
1606   void packuswb(XMMRegister dst, Address src);
1607   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1608 
1609   // Pemutation of 64bit words
1610   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1611 
1612   void pause();
1613 
1614   // SSE4.2 string instructions
1615   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1616   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1617 
1618   // SSE 4.1 extract
1619   void pextrd(Register dst, XMMRegister src, int imm8);
1620   void pextrq(Register dst, XMMRegister src, int imm8);
1621 
1622   // SSE 4.1 insert
1623   void pinsrd(XMMRegister dst, Register src, int imm8);
1624   void pinsrq(XMMRegister dst, Register src, int imm8);
1625 
1626   // SSE4.1 packed move
1627   void pmovzxbw(XMMRegister dst, XMMRegister src);
1628   void pmovzxbw(XMMRegister dst, Address src);
1629 
1630 #ifndef _LP64 // no 32bit push/pop on amd64
1631   void popl(Address dst);
1632 #endif
1633 
1634 #ifdef _LP64
1635   void popq(Address dst);
1636 #endif
1637 
1638   void popcntl(Register dst, Address src);
1639   void popcntl(Register dst, Register src);
1640 
1641 #ifdef _LP64
1642   void popcntq(Register dst, Address src);
1643   void popcntq(Register dst, Register src);
1644 #endif
1645 
1646   // Prefetches (SSE, SSE2, 3DNOW only)
1647 
1648   void prefetchnta(Address src);
1649   void prefetchr(Address src);
1650   void prefetcht0(Address src);
1651   void prefetcht1(Address src);
1652   void prefetcht2(Address src);
1653   void prefetchw(Address src);
1654 
1655   // Shuffle Bytes
1656   void pshufb(XMMRegister dst, XMMRegister src);
1657   void pshufb(XMMRegister dst, Address src);
1658 
1659   // Shuffle Packed Doublewords
1660   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1661   void pshufd(XMMRegister dst, Address src,     int mode);
1662 
1663   // Shuffle Packed Low Words
1664   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1665   void pshuflw(XMMRegister dst, Address src,     int mode);
1666 
1667   // Shift Right by bytes Logical DoubleQuadword Immediate
1668   void psrldq(XMMRegister dst, int shift);
1669   // Shift Left by bytes Logical DoubleQuadword Immediate
1670   void pslldq(XMMRegister dst, int shift);
1671 
1672   // Logical Compare 128bit
1673   void ptest(XMMRegister dst, XMMRegister src);
1674   void ptest(XMMRegister dst, Address src);
1675   // Logical Compare 256bit
1676   void vptest(XMMRegister dst, XMMRegister src);
1677   void vptest(XMMRegister dst, Address src);
1678 
1679   // Interleave Low Bytes
1680   void punpcklbw(XMMRegister dst, XMMRegister src);
1681   void punpcklbw(XMMRegister dst, Address src);
1682 
1683   // Interleave Low Doublewords
1684   void punpckldq(XMMRegister dst, XMMRegister src);
1685   void punpckldq(XMMRegister dst, Address src);
1686 
1687   // Interleave Low Quadwords
1688   void punpcklqdq(XMMRegister dst, XMMRegister src);
1689 
1690 #ifndef _LP64 // no 32bit push/pop on amd64
1691   void pushl(Address src);
1692 #endif
1693 
1694   void pushq(Address src);
1695 
1696   void rcll(Register dst, int imm8);
1697 
1698   void rclq(Register dst, int imm8);
1699 
1700   void rcrq(Register dst, int imm8);
1701 
1702   void rdtsc();
1703 
1704   void ret(int imm16);
1705 
1706 #ifdef _LP64
1707   void rorq(Register dst, int imm8);
1708   void rorxq(Register dst, Register src, int imm8);
1709 #endif
1710 
1711   void sahf();
1712 
1713   void sarl(Register dst, int imm8);
1714   void sarl(Register dst);
1715 
1716   void sarq(Register dst, int imm8);
1717   void sarq(Register dst);
1718 
1719   void sbbl(Address dst, int32_t imm32);
1720   void sbbl(Register dst, int32_t imm32);
1721   void sbbl(Register dst, Address src);
1722   void sbbl(Register dst, Register src);
1723 
1724   void sbbq(Address dst, int32_t imm32);
1725   void sbbq(Register dst, int32_t imm32);
1726   void sbbq(Register dst, Address src);
1727   void sbbq(Register dst, Register src);
1728 
1729   void setb(Condition cc, Register dst);
1730 
1731   void shldl(Register dst, Register src);
1732 
1733   void shll(Register dst, int imm8);
1734   void shll(Register dst);
1735 
1736   void shlq(Register dst, int imm8);
1737   void shlq(Register dst);
1738 
1739   void shrdl(Register dst, Register src);
1740 
1741   void shrl(Register dst, int imm8);
1742   void shrl(Register dst);
1743 
1744   void shrq(Register dst, int imm8);
1745   void shrq(Register dst);
1746 
1747   void smovl(); // QQQ generic?
1748 
1749   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1750   void sqrtsd(XMMRegister dst, Address src);
1751   void sqrtsd(XMMRegister dst, XMMRegister src);
1752 
1753   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1754   void sqrtss(XMMRegister dst, Address src);
1755   void sqrtss(XMMRegister dst, XMMRegister src);
1756 
1757   void std();
1758 
1759   void stmxcsr( Address dst );
1760 
1761   void subl(Address dst, int32_t imm32);
1762   void subl(Address dst, Register src);
1763   void subl(Register dst, int32_t imm32);
1764   void subl(Register dst, Address src);
1765   void subl(Register dst, Register src);
1766 
1767   void subq(Address dst, int32_t imm32);
1768   void subq(Address dst, Register src);
1769   void subq(Register dst, int32_t imm32);
1770   void subq(Register dst, Address src);
1771   void subq(Register dst, Register src);
1772 
1773   // Force generation of a 4 byte immediate value even if it fits into 8bit
1774   void subl_imm32(Register dst, int32_t imm32);
1775   void subq_imm32(Register dst, int32_t imm32);
1776 
1777   // Subtract Scalar Double-Precision Floating-Point Values
1778   void subsd(XMMRegister dst, Address src);
1779   void subsd(XMMRegister dst, XMMRegister src);
1780 
1781   // Subtract Scalar Single-Precision Floating-Point Values
1782   void subss(XMMRegister dst, Address src);
1783   void subss(XMMRegister dst, XMMRegister src);
1784 
1785   void testb(Register dst, int imm8);
1786 
1787   void testl(Register dst, int32_t imm32);
1788   void testl(Register dst, Register src);
1789   void testl(Register dst, Address src);
1790 
1791   void testq(Register dst, int32_t imm32);
1792   void testq(Register dst, Register src);
1793 
1794   // BMI - count trailing zeros
1795   void tzcntl(Register dst, Register src);
1796   void tzcntq(Register dst, Register src);
1797 
1798   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1799   void ucomisd(XMMRegister dst, Address src);
1800   void ucomisd(XMMRegister dst, XMMRegister src);
1801 
1802   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1803   void ucomiss(XMMRegister dst, Address src);
1804   void ucomiss(XMMRegister dst, XMMRegister src);
1805 
1806   void xabort(int8_t imm8);
1807 
1808   void xaddl(Address dst, Register src);
1809 
1810   void xaddq(Address dst, Register src);
1811 
1812   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1813 
1814   void xchgl(Register reg, Address adr);
1815   void xchgl(Register dst, Register src);
1816 
1817   void xchgq(Register reg, Address adr);
1818   void xchgq(Register dst, Register src);
1819 
1820   void xend();
1821 
1822   // Get Value of Extended Control Register
1823   void xgetbv();
1824 
1825   void xorl(Register dst, int32_t imm32);
1826   void xorl(Register dst, Address src);
1827   void xorl(Register dst, Register src);
1828 
1829   void xorq(Register dst, Address src);
1830   void xorq(Register dst, Register src);
1831 
1832   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1833 
1834   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1835 
1836   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1837   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1838   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1839   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1840   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1841   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1842   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1843   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1844   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1845   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1846   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1847   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1848   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1849   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1850   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1851   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1852 
1853 
1854   //====================VECTOR ARITHMETIC=====================================
1855 
1856   // Add Packed Floating-Point Values
1857   void addpd(XMMRegister dst, XMMRegister src);
1858   void addps(XMMRegister dst, XMMRegister src);
1859   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1860   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1861   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1862   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1863 
1864   // Subtract Packed Floating-Point Values
1865   void subpd(XMMRegister dst, XMMRegister src);
1866   void subps(XMMRegister dst, XMMRegister src);
1867   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1868   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1869   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1870   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1871 
1872   // Multiply Packed Floating-Point Values
1873   void mulpd(XMMRegister dst, XMMRegister src);
1874   void mulps(XMMRegister dst, XMMRegister src);
1875   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1876   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1877   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1878   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1879 
1880   // Divide Packed Floating-Point Values
1881   void divpd(XMMRegister dst, XMMRegister src);
1882   void divps(XMMRegister dst, XMMRegister src);
1883   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1884   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1885   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1886   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1887 
1888   // Bitwise Logical AND of Packed Floating-Point Values
1889   void andpd(XMMRegister dst, XMMRegister src);
1890   void andps(XMMRegister dst, XMMRegister src);
1891   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1892   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1893   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1894   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1895 
1896   // Bitwise Logical XOR of Packed Floating-Point Values
1897   void xorpd(XMMRegister dst, XMMRegister src);
1898   void xorps(XMMRegister dst, XMMRegister src);
1899   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1900   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1901   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1902   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1903 
1904   // Add horizontal packed integers
1905   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1906   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1907   void phaddw(XMMRegister dst, XMMRegister src);
1908   void phaddd(XMMRegister dst, XMMRegister src);
1909 
1910   // Add packed integers
1911   void paddb(XMMRegister dst, XMMRegister src);
1912   void paddw(XMMRegister dst, XMMRegister src);
1913   void paddd(XMMRegister dst, XMMRegister src);
1914   void paddq(XMMRegister dst, XMMRegister src);
1915   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1916   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1917   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1918   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1919   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1920   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1921   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1922   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1923 
1924   // Sub packed integers
1925   void psubb(XMMRegister dst, XMMRegister src);
1926   void psubw(XMMRegister dst, XMMRegister src);
1927   void psubd(XMMRegister dst, XMMRegister src);
1928   void psubq(XMMRegister dst, XMMRegister src);
1929   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1930   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1931   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1932   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1933   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1934   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1935   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1936   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1937 
1938   // Multiply packed integers (only shorts and ints)
1939   void pmullw(XMMRegister dst, XMMRegister src);
1940   void pmulld(XMMRegister dst, XMMRegister src);
1941   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1942   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1943   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1944   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1945   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1946   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1947 
1948   // Shift left packed integers
1949   void psllw(XMMRegister dst, int shift);
1950   void pslld(XMMRegister dst, int shift);
1951   void psllq(XMMRegister dst, int shift);
1952   void psllw(XMMRegister dst, XMMRegister shift);
1953   void pslld(XMMRegister dst, XMMRegister shift);
1954   void psllq(XMMRegister dst, XMMRegister shift);
1955   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1956   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1957   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1958   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1959   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1960   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1961 
1962   // Logical shift right packed integers
1963   void psrlw(XMMRegister dst, int shift);
1964   void psrld(XMMRegister dst, int shift);
1965   void psrlq(XMMRegister dst, int shift);
1966   void psrlw(XMMRegister dst, XMMRegister shift);
1967   void psrld(XMMRegister dst, XMMRegister shift);
1968   void psrlq(XMMRegister dst, XMMRegister shift);
1969   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1970   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1971   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1972   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1973   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1974   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1975 
1976   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1977   void psraw(XMMRegister dst, int shift);
1978   void psrad(XMMRegister dst, int shift);
1979   void psraw(XMMRegister dst, XMMRegister shift);
1980   void psrad(XMMRegister dst, XMMRegister shift);
1981   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1982   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1983   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1984   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1985 
1986   // And packed integers
1987   void pand(XMMRegister dst, XMMRegister src);
1988   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1989   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1990 
1991   // Or packed integers
1992   void por(XMMRegister dst, XMMRegister src);
1993   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1994   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1995 
1996   // Xor packed integers
1997   void pxor(XMMRegister dst, XMMRegister src);
1998   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1999   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2000 
2001   // Copy low 128bit into high 128bit of YMM registers.
2002   void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2003   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2004   void vextractf128h(XMMRegister dst, XMMRegister src);
2005   void vextracti128h(XMMRegister dst, XMMRegister src);
2006 
2007   // Load/store high 128bit of YMM registers which does not destroy other half.
2008   void vinsertf128h(XMMRegister dst, Address src);
2009   void vinserti128h(XMMRegister dst, Address src);
2010   void vextractf128h(Address dst, XMMRegister src);
2011   void vextracti128h(Address dst, XMMRegister src);
2012 
2013   // Copy low 256bit into high 256bit of ZMM registers.
2014   void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2015   void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2016   void vextracti64x4h(XMMRegister dst, XMMRegister src);
2017   void vextractf64x4h(XMMRegister dst, XMMRegister src);
2018   void vextractf64x4h(Address dst, XMMRegister src);
2019   void vinsertf64x4h(XMMRegister dst, Address src);
2020 
2021   // Copy targeted 128bit segments of the ZMM registers
2022   void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
2023   void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
2024   void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
2025 
2026   // duplicate 4-bytes integer data from src into 8 locations in dest
2027   void vpbroadcastd(XMMRegister dst, XMMRegister src);
2028 
2029   // duplicate 4-bytes integer data from src into vector_len locations in dest
2030   void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2031 
2032   // Carry-Less Multiplication Quadword
2033   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2034   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2035 
2036   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2037   // to avoid transaction penalty between AVX and SSE states. There is no
2038   // penalty if legacy SSE instructions are encoded using VEX prefix because
2039   // they always clear upper 128 bits. It should be used before calling
2040   // runtime code and native libraries.
2041   void vzeroupper();
2042 
2043  protected:
2044   // Next instructions require address alignment 16 bytes SSE mode.
2045   // They should be called only from corresponding MacroAssembler instructions.
2046   void andpd(XMMRegister dst, Address src);
2047   void andps(XMMRegister dst, Address src);
2048   void xorpd(XMMRegister dst, Address src);
2049   void xorps(XMMRegister dst, Address src);
2050 
2051 };
2052 
2053 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP
--- EOF ---