1 /*
   2  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright 2012, 2013 SAP AG. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
  27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 // Address is an abstraction used to represent a memory location
  32 // as used in assembler instructions.
  33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
  34 // So far we do not use this as simplification by this class is low
  35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
  36 // represent an offset.
  37 class Address VALUE_OBJ_CLASS_SPEC {
  38 };
  39 
  40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
  41  private:
  42   address          _address;
  43   RelocationHolder _rspec;
  44 
  45   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
  46     switch (rtype) {
  47     case relocInfo::external_word_type:
  48       return external_word_Relocation::spec(addr);
  49     case relocInfo::internal_word_type:
  50       return internal_word_Relocation::spec(addr);
  51     case relocInfo::opt_virtual_call_type:
  52       return opt_virtual_call_Relocation::spec();
  53     case relocInfo::static_call_type:
  54       return static_call_Relocation::spec();
  55     case relocInfo::runtime_call_type:
  56       return runtime_call_Relocation::spec();
  57     case relocInfo::none:
  58       return RelocationHolder();
  59     default:
  60       ShouldNotReachHere();
  61       return RelocationHolder();
  62     }
  63   }
  64 
  65  protected:
  66   // creation
  67   AddressLiteral() : _address(NULL), _rspec(NULL) {}
  68 
  69  public:
  70   AddressLiteral(address addr, RelocationHolder const& rspec)
  71     : _address(addr),
  72       _rspec(rspec) {}
  73 
  74   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
  75     : _address((address) addr),
  76       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
  77 
  78   AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
  79     : _address((address) addr),
  80       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
  81 
  82   intptr_t value() const { return (intptr_t) _address; }
  83 
  84   const RelocationHolder& rspec() const { return _rspec; }
  85 };
  86 
  87 // Argument is an abstraction used to represent an outgoing
  88 // actual argument or an incoming formal parameter, whether
  89 // it resides in memory or in a register, in a manner consistent
  90 // with the PPC Application Binary Interface, or ABI. This is
  91 // often referred to as the native or C calling convention.
  92 
  93 class Argument VALUE_OBJ_CLASS_SPEC {
  94  private:
  95   int _number;  // The number of the argument.
  96  public:
  97   enum {
  98     // Only 8 registers may contain integer parameters.
  99     n_register_parameters = 8,
 100     // Can have up to 8 floating registers.
 101     n_float_register_parameters = 8,
 102 
 103     // PPC C calling conventions.
 104     // The first eight arguments are passed in int regs if they are int.
 105     n_int_register_parameters_c = 8,
 106     // The first thirteen float arguments are passed in float regs.
 107     n_float_register_parameters_c = 13,
 108     // Only the first 8 parameters are not placed on the stack. Aix disassembly
 109     // shows that xlC places all float args after argument 8 on the stack AND
 110     // in a register. This is not documented, but we follow this convention, too.
 111     n_regs_not_on_stack_c = 8,
 112   };
 113   // creation
 114   Argument(int number) : _number(number) {}
 115 
 116   int  number() const { return _number; }
 117 
 118   // Locating register-based arguments:
 119   bool is_register() const { return _number < n_register_parameters; }
 120 
 121   Register as_register() const {
 122     assert(is_register(), "must be a register argument");
 123     return as_Register(number() + R3_ARG1->encoding());
 124   }
 125 };
 126 
 127 #if !defined(ABI_ELFv2)
 128 // A ppc64 function descriptor.
 129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
 130  private:
 131   address _entry;
 132   address _toc;
 133   address _env;
 134 
 135  public:
 136   inline address entry() const { return _entry; }
 137   inline address toc()   const { return _toc; }
 138   inline address env()   const { return _env; }
 139 
 140   inline void set_entry(address entry) { _entry = entry; }
 141   inline void set_toc(  address toc)   { _toc   = toc; }
 142   inline void set_env(  address env)   { _env   = env; }
 143 
 144   inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
 145   inline static ByteSize toc_offset()   { return byte_offset_of(FunctionDescriptor, _toc); }
 146   inline static ByteSize env_offset()   { return byte_offset_of(FunctionDescriptor, _env); }
 147 
 148   // Friend functions can be called without loading toc and env.
 149   enum {
 150     friend_toc = 0xcafe,
 151     friend_env = 0xc0de
 152   };
 153 
 154   inline bool is_friend_function() const {
 155     return (toc() == (address) friend_toc) && (env() == (address) friend_env);
 156   }
 157 
 158   // Constructor for stack-allocated instances.
 159   FunctionDescriptor() {
 160     _entry = (address) 0xbad;
 161     _toc   = (address) 0xbad;
 162     _env   = (address) 0xbad;
 163   }
 164 };
 165 #endif
 166 
 167 class Assembler : public AbstractAssembler {
 168  protected:
 169   // Displacement routines
 170   static void print_instruction(int inst);
 171   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 172   static int  branch_destination(int inst, int pos);
 173 
 174   friend class AbstractAssembler;
 175 
 176   // Code patchers need various routines like inv_wdisp()
 177   friend class NativeInstruction;
 178   friend class NativeGeneralJump;
 179   friend class Relocation;
 180 
 181  public:
 182 
 183   enum shifts {
 184     XO_21_29_SHIFT = 2,
 185     XO_21_30_SHIFT = 1,
 186     XO_27_29_SHIFT = 2,
 187     XO_30_31_SHIFT = 0,
 188     SPR_5_9_SHIFT  = 11u, // SPR_5_9 field in bits 11 -- 15
 189     SPR_0_4_SHIFT  = 16u, // SPR_0_4 field in bits 16 -- 20
 190     RS_SHIFT       = 21u, // RS field in bits 21 -- 25
 191     OPCODE_SHIFT   = 26u, // opcode in bits 26 -- 31
 192   };
 193 
 194   enum opcdxos_masks {
 195     XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
 196     ADDI_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 197     ADDIS_OPCODE_MASK   = (63u << OPCODE_SHIFT),
 198     BXX_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 199     BCXX_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 200     // trap instructions
 201     TDI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 202     TWI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 203     TD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
 204     TW_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
 205     LD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
 206     STD_OPCODE_MASK     = LD_OPCODE_MASK,
 207     STDU_OPCODE_MASK    = STD_OPCODE_MASK,
 208     STDX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
 209     STDUX_OPCODE_MASK   = STDX_OPCODE_MASK,
 210     STW_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 211     STWU_OPCODE_MASK    = STW_OPCODE_MASK,
 212     STWX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
 213     STWUX_OPCODE_MASK   = STWX_OPCODE_MASK,
 214     MTCTR_OPCODE_MASK   = ~(31u << RS_SHIFT),
 215     ORI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 216     ORIS_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 217     RLDICR_OPCODE_MASK  = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
 218   };
 219 
 220   enum opcdxos {
 221     ADD_OPCODE    = (31u << OPCODE_SHIFT | 266u << 1),
 222     ADDC_OPCODE   = (31u << OPCODE_SHIFT |  10u << 1),
 223     ADDI_OPCODE   = (14u << OPCODE_SHIFT),
 224     ADDIS_OPCODE  = (15u << OPCODE_SHIFT),
 225     ADDIC__OPCODE = (13u << OPCODE_SHIFT),
 226     ADDE_OPCODE   = (31u << OPCODE_SHIFT | 138u << 1),
 227     SUBF_OPCODE   = (31u << OPCODE_SHIFT |  40u << 1),
 228     SUBFC_OPCODE  = (31u << OPCODE_SHIFT |   8u << 1),
 229     SUBFE_OPCODE  = (31u << OPCODE_SHIFT | 136u << 1),
 230     SUBFIC_OPCODE = (8u  << OPCODE_SHIFT),
 231     SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
 232     DIVW_OPCODE   = (31u << OPCODE_SHIFT | 491u << 1),
 233     MULLW_OPCODE  = (31u << OPCODE_SHIFT | 235u << 1),
 234     MULHW_OPCODE  = (31u << OPCODE_SHIFT |  75u << 1),
 235     MULHWU_OPCODE = (31u << OPCODE_SHIFT |  11u << 1),
 236     MULLI_OPCODE  = (7u  << OPCODE_SHIFT),
 237     AND_OPCODE    = (31u << OPCODE_SHIFT |  28u << 1),
 238     ANDI_OPCODE   = (28u << OPCODE_SHIFT),
 239     ANDIS_OPCODE  = (29u << OPCODE_SHIFT),
 240     ANDC_OPCODE   = (31u << OPCODE_SHIFT |  60u << 1),
 241     ORC_OPCODE    = (31u << OPCODE_SHIFT | 412u << 1),
 242     OR_OPCODE     = (31u << OPCODE_SHIFT | 444u << 1),
 243     ORI_OPCODE    = (24u << OPCODE_SHIFT),
 244     ORIS_OPCODE   = (25u << OPCODE_SHIFT),
 245     XOR_OPCODE    = (31u << OPCODE_SHIFT | 316u << 1),
 246     XORI_OPCODE   = (26u << OPCODE_SHIFT),
 247     XORIS_OPCODE  = (27u << OPCODE_SHIFT),
 248 
 249     NEG_OPCODE    = (31u << OPCODE_SHIFT | 104u << 1),
 250 
 251     RLWINM_OPCODE = (21u << OPCODE_SHIFT),
 252     CLRRWI_OPCODE = RLWINM_OPCODE,
 253     CLRLWI_OPCODE = RLWINM_OPCODE,
 254 
 255     RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
 256 
 257     SLW_OPCODE    = (31u << OPCODE_SHIFT |  24u << 1),
 258     SLWI_OPCODE   = RLWINM_OPCODE,
 259     SRW_OPCODE    = (31u << OPCODE_SHIFT | 536u << 1),
 260     SRWI_OPCODE   = RLWINM_OPCODE,
 261     SRAW_OPCODE   = (31u << OPCODE_SHIFT | 792u << 1),
 262     SRAWI_OPCODE  = (31u << OPCODE_SHIFT | 824u << 1),
 263 
 264     CMP_OPCODE    = (31u << OPCODE_SHIFT |   0u << 1),
 265     CMPI_OPCODE   = (11u << OPCODE_SHIFT),
 266     CMPL_OPCODE   = (31u << OPCODE_SHIFT |  32u << 1),
 267     CMPLI_OPCODE  = (10u << OPCODE_SHIFT),
 268 
 269     ISEL_OPCODE   = (31u << OPCODE_SHIFT |  15u << 1),
 270 
 271     MTLR_OPCODE   = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT),
 272     MFLR_OPCODE   = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT),
 273 
 274     MTCRF_OPCODE  = (31u << OPCODE_SHIFT | 144u << 1),
 275     MFCR_OPCODE   = (31u << OPCODE_SHIFT | 19u << 1),
 276     MCRF_OPCODE   = (19u << OPCODE_SHIFT | 0u << 1),
 277 
 278     // condition register logic instructions
 279     CRAND_OPCODE  = (19u << OPCODE_SHIFT | 257u << 1),
 280     CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
 281     CROR_OPCODE   = (19u << OPCODE_SHIFT | 449u << 1),
 282     CRXOR_OPCODE  = (19u << OPCODE_SHIFT | 193u << 1),
 283     CRNOR_OPCODE  = (19u << OPCODE_SHIFT |  33u << 1),
 284     CREQV_OPCODE  = (19u << OPCODE_SHIFT | 289u << 1),
 285     CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
 286     CRORC_OPCODE  = (19u << OPCODE_SHIFT | 417u << 1),
 287 
 288     BCLR_OPCODE   = (19u << OPCODE_SHIFT | 16u << 1),
 289     BXX_OPCODE      = (18u << OPCODE_SHIFT),
 290     BCXX_OPCODE     = (16u << OPCODE_SHIFT),
 291 
 292     // CTR-related opcodes
 293     BCCTR_OPCODE  = (19u << OPCODE_SHIFT | 528u << 1),
 294     MTCTR_OPCODE  = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
 295     MFCTR_OPCODE  = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
 296 
 297 
 298     LWZ_OPCODE   = (32u << OPCODE_SHIFT),
 299     LWZX_OPCODE  = (31u << OPCODE_SHIFT |  23u << 1),
 300     LWZU_OPCODE  = (33u << OPCODE_SHIFT),
 301 
 302     LHA_OPCODE   = (42u << OPCODE_SHIFT),
 303     LHAX_OPCODE  = (31u << OPCODE_SHIFT | 343u << 1),
 304     LHAU_OPCODE  = (43u << OPCODE_SHIFT),
 305 
 306     LHZ_OPCODE   = (40u << OPCODE_SHIFT),
 307     LHZX_OPCODE  = (31u << OPCODE_SHIFT | 279u << 1),
 308     LHZU_OPCODE  = (41u << OPCODE_SHIFT),
 309 
 310     LBZ_OPCODE   = (34u << OPCODE_SHIFT),
 311     LBZX_OPCODE  = (31u << OPCODE_SHIFT |  87u << 1),
 312     LBZU_OPCODE  = (35u << OPCODE_SHIFT),
 313 
 314     STW_OPCODE   = (36u << OPCODE_SHIFT),
 315     STWX_OPCODE  = (31u << OPCODE_SHIFT | 151u << 1),
 316     STWU_OPCODE  = (37u << OPCODE_SHIFT),
 317     STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
 318 
 319     STH_OPCODE   = (44u << OPCODE_SHIFT),
 320     STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
 321     STHU_OPCODE  = (45u << OPCODE_SHIFT),
 322 
 323     STB_OPCODE   = (38u << OPCODE_SHIFT),
 324     STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
 325     STBU_OPCODE  = (39u << OPCODE_SHIFT),
 326 
 327     EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
 328     EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
 329     EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM
 330 
 331     // 32 bit opcode encodings
 332 
 333     LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM
 334     LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
 335 
 336     CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM
 337 
 338     // 64 bit opcode encodings
 339 
 340     LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 341     LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 342     LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
 343 
 344     STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 345     STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 346     STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),                  // X-FORM
 347     STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
 348 
 349     RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
 350     RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
 351     RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM
 352     RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM
 353 
 354     SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
 355 
 356     SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM
 357     SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM
 358     SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM
 359 
 360     MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM
 361     MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM
 362     MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM
 363     DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM
 364 
 365     CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM
 366     NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
 367     NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
 368 
 369 
 370     // opcodes only used for floating arithmetic
 371     FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),
 372     FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),
 373     FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),
 374     FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),
 375     FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),
 376     FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),
 377     // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
 378     // on Power7.  Do not use.
 379     // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),
 380     // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),
 381     CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),
 382     POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),
 383     POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),
 384     POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),
 385     FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),
 386     FNABS_OPCODE   = (63u << OPCODE_SHIFT |  136u << 1),
 387     FMUL_OPCODE    = (63u << OPCODE_SHIFT |   25u << 1),
 388     FMULS_OPCODE   = (59u << OPCODE_SHIFT |   25u << 1),
 389     FNEG_OPCODE    = (63u << OPCODE_SHIFT |   40u << 1),
 390     FSUB_OPCODE    = (63u << OPCODE_SHIFT |   20u << 1),
 391     FSUBS_OPCODE   = (59u << OPCODE_SHIFT |   20u << 1),
 392 
 393     // PPC64-internal FPU conversion opcodes
 394     FCFID_OPCODE   = (63u << OPCODE_SHIFT |  846u << 1),
 395     FCFIDS_OPCODE  = (59u << OPCODE_SHIFT |  846u << 1),
 396     FCTID_OPCODE   = (63u << OPCODE_SHIFT |  814u << 1),
 397     FCTIDZ_OPCODE  = (63u << OPCODE_SHIFT |  815u << 1),
 398     FCTIW_OPCODE   = (63u << OPCODE_SHIFT |   14u << 1),
 399     FCTIWZ_OPCODE  = (63u << OPCODE_SHIFT |   15u << 1),
 400     FRSP_OPCODE    = (63u << OPCODE_SHIFT |   12u << 1),
 401 
 402     // WARNING: using fmadd results in a non-compliant vm. Some floating
 403     // point tck tests will fail.
 404     FMADD_OPCODE   = (59u << OPCODE_SHIFT |   29u << 1),
 405     DMADD_OPCODE   = (63u << OPCODE_SHIFT |   29u << 1),
 406     FMSUB_OPCODE   = (59u << OPCODE_SHIFT |   28u << 1),
 407     DMSUB_OPCODE   = (63u << OPCODE_SHIFT |   28u << 1),
 408     FNMADD_OPCODE  = (59u << OPCODE_SHIFT |   31u << 1),
 409     DNMADD_OPCODE  = (63u << OPCODE_SHIFT |   31u << 1),
 410     FNMSUB_OPCODE  = (59u << OPCODE_SHIFT |   30u << 1),
 411     DNMSUB_OPCODE  = (63u << OPCODE_SHIFT |   30u << 1),
 412 
 413     LFD_OPCODE     = (50u << OPCODE_SHIFT |   00u << 1),
 414     LFDU_OPCODE    = (51u << OPCODE_SHIFT |   00u << 1),
 415     LFDX_OPCODE    = (31u << OPCODE_SHIFT |  599u << 1),
 416     LFS_OPCODE     = (48u << OPCODE_SHIFT |   00u << 1),
 417     LFSU_OPCODE    = (49u << OPCODE_SHIFT |   00u << 1),
 418     LFSX_OPCODE    = (31u << OPCODE_SHIFT |  535u << 1),
 419 
 420     STFD_OPCODE    = (54u << OPCODE_SHIFT |   00u << 1),
 421     STFDU_OPCODE   = (55u << OPCODE_SHIFT |   00u << 1),
 422     STFDX_OPCODE   = (31u << OPCODE_SHIFT |  727u << 1),
 423     STFS_OPCODE    = (52u << OPCODE_SHIFT |   00u << 1),
 424     STFSU_OPCODE   = (53u << OPCODE_SHIFT |   00u << 1),
 425     STFSX_OPCODE   = (31u << OPCODE_SHIFT |  663u << 1),
 426 
 427     FSQRT_OPCODE   = (63u << OPCODE_SHIFT |   22u << 1),            // A-FORM
 428     FSQRTS_OPCODE  = (59u << OPCODE_SHIFT |   22u << 1),            // A-FORM
 429 
 430     // Vector instruction support for >= Power6
 431     // Vector Storage Access
 432     LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),
 433     LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),
 434     LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),
 435     LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),
 436     LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),
 437     STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),
 438     STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),
 439     STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),
 440     STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),
 441     STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),
 442     LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),
 443     LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
 444 
 445     // Vector Permute and Formatting
 446     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
 447     VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
 448     VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
 449     VPKSHUS_OPCODE = (4u  << OPCODE_SHIFT |  270u     ),
 450     VPKSWUS_OPCODE = (4u  << OPCODE_SHIFT |  334u     ),
 451     VPKUHUM_OPCODE = (4u  << OPCODE_SHIFT |   14u     ),
 452     VPKUWUM_OPCODE = (4u  << OPCODE_SHIFT |   78u     ),
 453     VPKUHUS_OPCODE = (4u  << OPCODE_SHIFT |  142u     ),
 454     VPKUWUS_OPCODE = (4u  << OPCODE_SHIFT |  206u     ),
 455     VUPKHPX_OPCODE = (4u  << OPCODE_SHIFT |  846u     ),
 456     VUPKHSB_OPCODE = (4u  << OPCODE_SHIFT |  526u     ),
 457     VUPKHSH_OPCODE = (4u  << OPCODE_SHIFT |  590u     ),
 458     VUPKLPX_OPCODE = (4u  << OPCODE_SHIFT |  974u     ),
 459     VUPKLSB_OPCODE = (4u  << OPCODE_SHIFT |  654u     ),
 460     VUPKLSH_OPCODE = (4u  << OPCODE_SHIFT |  718u     ),
 461 
 462     VMRGHB_OPCODE  = (4u  << OPCODE_SHIFT |   12u     ),
 463     VMRGHW_OPCODE  = (4u  << OPCODE_SHIFT |  140u     ),
 464     VMRGHH_OPCODE  = (4u  << OPCODE_SHIFT |   76u     ),
 465     VMRGLB_OPCODE  = (4u  << OPCODE_SHIFT |  268u     ),
 466     VMRGLW_OPCODE  = (4u  << OPCODE_SHIFT |  396u     ),
 467     VMRGLH_OPCODE  = (4u  << OPCODE_SHIFT |  332u     ),
 468 
 469     VSPLT_OPCODE   = (4u  << OPCODE_SHIFT |  524u     ),
 470     VSPLTH_OPCODE  = (4u  << OPCODE_SHIFT |  588u     ),
 471     VSPLTW_OPCODE  = (4u  << OPCODE_SHIFT |  652u     ),
 472     VSPLTISB_OPCODE= (4u  << OPCODE_SHIFT |  780u     ),
 473     VSPLTISH_OPCODE= (4u  << OPCODE_SHIFT |  844u     ),
 474     VSPLTISW_OPCODE= (4u  << OPCODE_SHIFT |  908u     ),
 475 
 476     VPERM_OPCODE   = (4u  << OPCODE_SHIFT |   43u     ),
 477     VSEL_OPCODE    = (4u  << OPCODE_SHIFT |   42u     ),
 478 
 479     VSL_OPCODE     = (4u  << OPCODE_SHIFT |  452u     ),
 480     VSLDOI_OPCODE  = (4u  << OPCODE_SHIFT |   44u     ),
 481     VSLO_OPCODE    = (4u  << OPCODE_SHIFT | 1036u     ),
 482     VSR_OPCODE     = (4u  << OPCODE_SHIFT |  708u     ),
 483     VSRO_OPCODE    = (4u  << OPCODE_SHIFT | 1100u     ),
 484 
 485     // Vector Integer
 486     VADDCUW_OPCODE = (4u  << OPCODE_SHIFT |  384u     ),
 487     VADDSHS_OPCODE = (4u  << OPCODE_SHIFT |  832u     ),
 488     VADDSBS_OPCODE = (4u  << OPCODE_SHIFT |  768u     ),
 489     VADDSWS_OPCODE = (4u  << OPCODE_SHIFT |  896u     ),
 490     VADDUBM_OPCODE = (4u  << OPCODE_SHIFT |    0u     ),
 491     VADDUWM_OPCODE = (4u  << OPCODE_SHIFT |  128u     ),
 492     VADDUHM_OPCODE = (4u  << OPCODE_SHIFT |   64u     ),
 493     VADDUBS_OPCODE = (4u  << OPCODE_SHIFT |  512u     ),
 494     VADDUWS_OPCODE = (4u  << OPCODE_SHIFT |  640u     ),
 495     VADDUHS_OPCODE = (4u  << OPCODE_SHIFT |  576u     ),
 496     VSUBCUW_OPCODE = (4u  << OPCODE_SHIFT | 1408u     ),
 497     VSUBSHS_OPCODE = (4u  << OPCODE_SHIFT | 1856u     ),
 498     VSUBSBS_OPCODE = (4u  << OPCODE_SHIFT | 1792u     ),
 499     VSUBSWS_OPCODE = (4u  << OPCODE_SHIFT | 1920u     ),
 500     VSUBUBM_OPCODE = (4u  << OPCODE_SHIFT | 1024u     ),
 501     VSUBUWM_OPCODE = (4u  << OPCODE_SHIFT | 1152u     ),
 502     VSUBUHM_OPCODE = (4u  << OPCODE_SHIFT | 1088u     ),
 503     VSUBUBS_OPCODE = (4u  << OPCODE_SHIFT | 1536u     ),
 504     VSUBUWS_OPCODE = (4u  << OPCODE_SHIFT | 1664u     ),
 505     VSUBUHS_OPCODE = (4u  << OPCODE_SHIFT | 1600u     ),
 506 
 507     VMULESB_OPCODE = (4u  << OPCODE_SHIFT |  776u     ),
 508     VMULEUB_OPCODE = (4u  << OPCODE_SHIFT |  520u     ),
 509     VMULESH_OPCODE = (4u  << OPCODE_SHIFT |  840u     ),
 510     VMULEUH_OPCODE = (4u  << OPCODE_SHIFT |  584u     ),
 511     VMULOSB_OPCODE = (4u  << OPCODE_SHIFT |  264u     ),
 512     VMULOUB_OPCODE = (4u  << OPCODE_SHIFT |    8u     ),
 513     VMULOSH_OPCODE = (4u  << OPCODE_SHIFT |  328u     ),
 514     VMULOUH_OPCODE = (4u  << OPCODE_SHIFT |   72u     ),
 515     VMHADDSHS_OPCODE=(4u  << OPCODE_SHIFT |   32u     ),
 516     VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT |   33u     ),
 517     VMLADDUHM_OPCODE=(4u  << OPCODE_SHIFT |   34u     ),
 518     VMSUBUHM_OPCODE= (4u  << OPCODE_SHIFT |   36u     ),
 519     VMSUMMBM_OPCODE= (4u  << OPCODE_SHIFT |   37u     ),
 520     VMSUMSHM_OPCODE= (4u  << OPCODE_SHIFT |   40u     ),
 521     VMSUMSHS_OPCODE= (4u  << OPCODE_SHIFT |   41u     ),
 522     VMSUMUHM_OPCODE= (4u  << OPCODE_SHIFT |   38u     ),
 523     VMSUMUHS_OPCODE= (4u  << OPCODE_SHIFT |   39u     ),
 524 
 525     VSUMSWS_OPCODE = (4u  << OPCODE_SHIFT | 1928u     ),
 526     VSUM2SWS_OPCODE= (4u  << OPCODE_SHIFT | 1672u     ),
 527     VSUM4SBS_OPCODE= (4u  << OPCODE_SHIFT | 1800u     ),
 528     VSUM4UBS_OPCODE= (4u  << OPCODE_SHIFT | 1544u     ),
 529     VSUM4SHS_OPCODE= (4u  << OPCODE_SHIFT | 1608u     ),
 530 
 531     VAVGSB_OPCODE  = (4u  << OPCODE_SHIFT | 1282u     ),
 532     VAVGSW_OPCODE  = (4u  << OPCODE_SHIFT | 1410u     ),
 533     VAVGSH_OPCODE  = (4u  << OPCODE_SHIFT | 1346u     ),
 534     VAVGUB_OPCODE  = (4u  << OPCODE_SHIFT | 1026u     ),
 535     VAVGUW_OPCODE  = (4u  << OPCODE_SHIFT | 1154u     ),
 536     VAVGUH_OPCODE  = (4u  << OPCODE_SHIFT | 1090u     ),
 537 
 538     VMAXSB_OPCODE  = (4u  << OPCODE_SHIFT |  258u     ),
 539     VMAXSW_OPCODE  = (4u  << OPCODE_SHIFT |  386u     ),
 540     VMAXSH_OPCODE  = (4u  << OPCODE_SHIFT |  322u     ),
 541     VMAXUB_OPCODE  = (4u  << OPCODE_SHIFT |    2u     ),
 542     VMAXUW_OPCODE  = (4u  << OPCODE_SHIFT |  130u     ),
 543     VMAXUH_OPCODE  = (4u  << OPCODE_SHIFT |   66u     ),
 544     VMINSB_OPCODE  = (4u  << OPCODE_SHIFT |  770u     ),
 545     VMINSW_OPCODE  = (4u  << OPCODE_SHIFT |  898u     ),
 546     VMINSH_OPCODE  = (4u  << OPCODE_SHIFT |  834u     ),
 547     VMINUB_OPCODE  = (4u  << OPCODE_SHIFT |  514u     ),
 548     VMINUW_OPCODE  = (4u  << OPCODE_SHIFT |  642u     ),
 549     VMINUH_OPCODE  = (4u  << OPCODE_SHIFT |  578u     ),
 550 
 551     VCMPEQUB_OPCODE= (4u  << OPCODE_SHIFT |    6u     ),
 552     VCMPEQUH_OPCODE= (4u  << OPCODE_SHIFT |   70u     ),
 553     VCMPEQUW_OPCODE= (4u  << OPCODE_SHIFT |  134u     ),
 554     VCMPGTSH_OPCODE= (4u  << OPCODE_SHIFT |  838u     ),
 555     VCMPGTSB_OPCODE= (4u  << OPCODE_SHIFT |  774u     ),
 556     VCMPGTSW_OPCODE= (4u  << OPCODE_SHIFT |  902u     ),
 557     VCMPGTUB_OPCODE= (4u  << OPCODE_SHIFT |  518u     ),
 558     VCMPGTUH_OPCODE= (4u  << OPCODE_SHIFT |  582u     ),
 559     VCMPGTUW_OPCODE= (4u  << OPCODE_SHIFT |  646u     ),
 560 
 561     VAND_OPCODE    = (4u  << OPCODE_SHIFT | 1028u     ),
 562     VANDC_OPCODE   = (4u  << OPCODE_SHIFT | 1092u     ),
 563     VNOR_OPCODE    = (4u  << OPCODE_SHIFT | 1284u     ),
 564     VOR_OPCODE     = (4u  << OPCODE_SHIFT | 1156u     ),
 565     VXOR_OPCODE    = (4u  << OPCODE_SHIFT | 1220u     ),
 566     VRLB_OPCODE    = (4u  << OPCODE_SHIFT |    4u     ),
 567     VRLW_OPCODE    = (4u  << OPCODE_SHIFT |  132u     ),
 568     VRLH_OPCODE    = (4u  << OPCODE_SHIFT |   68u     ),
 569     VSLB_OPCODE    = (4u  << OPCODE_SHIFT |  260u     ),
 570     VSKW_OPCODE    = (4u  << OPCODE_SHIFT |  388u     ),
 571     VSLH_OPCODE    = (4u  << OPCODE_SHIFT |  324u     ),
 572     VSRB_OPCODE    = (4u  << OPCODE_SHIFT |  516u     ),
 573     VSRW_OPCODE    = (4u  << OPCODE_SHIFT |  644u     ),
 574     VSRH_OPCODE    = (4u  << OPCODE_SHIFT |  580u     ),
 575     VSRAB_OPCODE   = (4u  << OPCODE_SHIFT |  772u     ),
 576     VSRAW_OPCODE   = (4u  << OPCODE_SHIFT |  900u     ),
 577     VSRAH_OPCODE   = (4u  << OPCODE_SHIFT |  836u     ),
 578 
 579     // Vector Floating-Point
 580     // not implemented yet
 581 
 582     // Vector Status and Control
 583     MTVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1604u     ),
 584     MFVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1540u     ),
 585 
 586     // Icache and dcache related instructions
 587     DCBA_OPCODE    = (31u << OPCODE_SHIFT |  758u << 1),
 588     DCBZ_OPCODE    = (31u << OPCODE_SHIFT | 1014u << 1),
 589     DCBST_OPCODE   = (31u << OPCODE_SHIFT |   54u << 1),
 590     DCBF_OPCODE    = (31u << OPCODE_SHIFT |   86u << 1),
 591 
 592     DCBT_OPCODE    = (31u << OPCODE_SHIFT |  278u << 1),
 593     DCBTST_OPCODE  = (31u << OPCODE_SHIFT |  246u << 1),
 594     ICBI_OPCODE    = (31u << OPCODE_SHIFT |  982u << 1),
 595 
 596     // Instruction synchronization
 597     ISYNC_OPCODE   = (19u << OPCODE_SHIFT |  150u << 1),
 598     // Memory barriers
 599     SYNC_OPCODE    = (31u << OPCODE_SHIFT |  598u << 1),
 600     EIEIO_OPCODE   = (31u << OPCODE_SHIFT |  854u << 1),
 601 
 602     // Trap instructions
 603     TDI_OPCODE     = (2u  << OPCODE_SHIFT),
 604     TWI_OPCODE     = (3u  << OPCODE_SHIFT),
 605     TD_OPCODE      = (31u << OPCODE_SHIFT |   68u << 1),
 606     TW_OPCODE      = (31u << OPCODE_SHIFT |    4u << 1),
 607 
 608     // Atomics.
 609     LWARX_OPCODE   = (31u << OPCODE_SHIFT |   20u << 1),
 610     LDARX_OPCODE   = (31u << OPCODE_SHIFT |   84u << 1),
 611     STWCX_OPCODE   = (31u << OPCODE_SHIFT |  150u << 1),
 612     STDCX_OPCODE   = (31u << OPCODE_SHIFT |  214u << 1)
 613 
 614   };
 615 
 616   // Trap instructions TO bits
 617   enum trap_to_bits {
 618     // single bits
 619     traptoLessThanSigned      = 1 << 4, // 0, left end
 620     traptoGreaterThanSigned   = 1 << 3,
 621     traptoEqual               = 1 << 2,
 622     traptoLessThanUnsigned    = 1 << 1,
 623     traptoGreaterThanUnsigned = 1 << 0, // 4, right end
 624 
 625     // compound ones
 626     traptoUnconditional       = (traptoLessThanSigned |
 627                                  traptoGreaterThanSigned |
 628                                  traptoEqual |
 629                                  traptoLessThanUnsigned |
 630                                  traptoGreaterThanUnsigned)
 631   };
 632 
 633   // Branch hints BH field
 634   enum branch_hint_bh {
 635     // bclr cases:
 636     bhintbhBCLRisReturn            = 0,
 637     bhintbhBCLRisNotReturnButSame  = 1,
 638     bhintbhBCLRisNotPredictable    = 3,
 639 
 640     // bcctr cases:
 641     bhintbhBCCTRisNotReturnButSame = 0,
 642     bhintbhBCCTRisNotPredictable   = 3
 643   };
 644 
 645   // Branch prediction hints AT field
 646   enum branch_hint_at {
 647     bhintatNoHint     = 0,  // at=00
 648     bhintatIsNotTaken = 2,  // at=10
 649     bhintatIsTaken    = 3   // at=11
 650   };
 651 
 652   // Branch prediction hints
 653   enum branch_hint_concept {
 654     // Use the same encoding as branch_hint_at to simply code.
 655     bhintNoHint       = bhintatNoHint,
 656     bhintIsNotTaken   = bhintatIsNotTaken,
 657     bhintIsTaken      = bhintatIsTaken
 658   };
 659 
 660   // Used in BO field of branch instruction.
 661   enum branch_condition {
 662     bcondCRbiIs0      =  4, // bo=001at
 663     bcondCRbiIs1      = 12, // bo=011at
 664     bcondAlways       = 20  // bo=10100
 665   };
 666 
 667   // Branch condition with combined prediction hints.
 668   enum branch_condition_with_hint {
 669     bcondCRbiIs0_bhintNoHint     = bcondCRbiIs0 | bhintatNoHint,
 670     bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
 671     bcondCRbiIs0_bhintIsTaken    = bcondCRbiIs0 | bhintatIsTaken,
 672     bcondCRbiIs1_bhintNoHint     = bcondCRbiIs1 | bhintatNoHint,
 673     bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
 674     bcondCRbiIs1_bhintIsTaken    = bcondCRbiIs1 | bhintatIsTaken,
 675   };
 676 
 677   // Elemental Memory Barriers (>=Power 8)
 678   enum Elemental_Membar_mask_bits {
 679     StoreStore = 1 << 0,
 680     StoreLoad  = 1 << 1,
 681     LoadStore  = 1 << 2,
 682     LoadLoad   = 1 << 3
 683   };
 684 
 685   // Branch prediction hints.
 686   inline static int add_bhint_to_boint(const int bhint, const int boint) {
 687     switch (boint) {
 688       case bcondCRbiIs0:
 689       case bcondCRbiIs1:
 690         // branch_hint and branch_hint_at have same encodings
 691         assert(   (int)bhintNoHint     == (int)bhintatNoHint
 692                && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
 693                && (int)bhintIsTaken    == (int)bhintatIsTaken,
 694                "wrong encodings");
 695         assert((bhint & 0x03) == bhint, "wrong encodings");
 696         return (boint & ~0x03) | bhint;
 697       case bcondAlways:
 698         // no branch_hint
 699         return boint;
 700       default:
 701         ShouldNotReachHere();
 702         return 0;
 703     }
 704   }
 705 
 706   // Extract bcond from boint.
 707   inline static int inv_boint_bcond(const int boint) {
 708     int r_bcond = boint & ~0x03;
 709     assert(r_bcond == bcondCRbiIs0 ||
 710            r_bcond == bcondCRbiIs1 ||
 711            r_bcond == bcondAlways,
 712            "bad branch condition");
 713     return r_bcond;
 714   }
 715 
 716   // Extract bhint from boint.
 717   inline static int inv_boint_bhint(const int boint) {
 718     int r_bhint = boint & 0x03;
 719     assert(r_bhint == bhintatNoHint ||
 720            r_bhint == bhintatIsNotTaken ||
 721            r_bhint == bhintatIsTaken,
 722            "bad branch hint");
 723     return r_bhint;
 724   }
 725 
 726   // Calculate opposite of given bcond.
 727   inline static int opposite_bcond(const int bcond) {
 728     switch (bcond) {
 729       case bcondCRbiIs0:
 730         return bcondCRbiIs1;
 731       case bcondCRbiIs1:
 732         return bcondCRbiIs0;
 733       default:
 734         ShouldNotReachHere();
 735         return 0;
 736     }
 737   }
 738 
 739   // Calculate opposite of given bhint.
 740   inline static int opposite_bhint(const int bhint) {
 741     switch (bhint) {
 742       case bhintatNoHint:
 743         return bhintatNoHint;
 744       case bhintatIsNotTaken:
 745         return bhintatIsTaken;
 746       case bhintatIsTaken:
 747         return bhintatIsNotTaken;
 748       default:
 749         ShouldNotReachHere();
 750         return 0;
 751     }
 752   }
 753 
 754   // PPC branch instructions
 755   enum ppcops {
 756     b_op    = 18,
 757     bc_op   = 16,
 758     bcr_op  = 19
 759   };
 760 
 761   enum Condition {
 762     negative         = 0,
 763     less             = 0,
 764     positive         = 1,
 765     greater          = 1,
 766     zero             = 2,
 767     equal            = 2,
 768     summary_overflow = 3,
 769   };
 770 
 771  public:
 772   // Helper functions for groups of instructions
 773 
 774   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 775 
 776   // instruction must start at passed address
 777   static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
 778 
 779   // instruction must be left-justified in argument
 780   static int instr_len(unsigned long instr)  { return BytesPerInstWord; }
 781 
 782   // longest instructions
 783   static int instr_maxlen() { return BytesPerInstWord; }
 784 
 785   // Test if x is within signed immediate range for nbits.
 786   static bool is_simm(int x, unsigned int nbits) {
 787     assert(0 < nbits && nbits < 32, "out of bounds");
 788     const int   min      = -( ((int)1) << nbits-1 );
 789     const int   maxplus1 =  ( ((int)1) << nbits-1 );
 790     return min <= x && x < maxplus1;
 791   }
 792 
 793   static bool is_simm(jlong x, unsigned int nbits) {
 794     assert(0 < nbits && nbits < 64, "out of bounds");
 795     const jlong min      = -( ((jlong)1) << nbits-1 );
 796     const jlong maxplus1 =  ( ((jlong)1) << nbits-1 );
 797     return min <= x && x < maxplus1;
 798   }
 799 
 800   // Test if x is within unsigned immediate range for nbits
 801   static bool is_uimm(int x, unsigned int nbits) {
 802     assert(0 < nbits && nbits < 32, "out of bounds");
 803     const int   maxplus1 = ( ((int)1) << nbits );
 804     return 0 <= x && x < maxplus1;
 805   }
 806 
 807   static bool is_uimm(jlong x, unsigned int nbits) {
 808     assert(0 < nbits && nbits < 64, "out of bounds");
 809     const jlong maxplus1 =  ( ((jlong)1) << nbits );
 810     return 0 <= x && x < maxplus1;
 811   }
 812 
 813  protected:
 814   // helpers
 815 
 816   // X is supposed to fit in a field "nbits" wide
 817   // and be sign-extended. Check the range.
 818   static void assert_signed_range(intptr_t x, int nbits) {
 819     assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
 820            "value out of range");
 821   }
 822 
 823   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 824     assert((x & 3) == 0, "not word aligned");
 825     assert_signed_range(x, nbits + 2);
 826   }
 827 
 828   static void assert_unsigned_const(int x, int nbits) {
 829     assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
 830   }
 831 
 832   static int fmask(juint hi_bit, juint lo_bit) {
 833     assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
 834     return (1 << ( hi_bit-lo_bit + 1 )) - 1;
 835   }
 836 
 837   // inverse of u_field
 838   static int inv_u_field(int x, int hi_bit, int lo_bit) {
 839     juint r = juint(x) >> lo_bit;
 840     r &= fmask(hi_bit, lo_bit);
 841     return int(r);
 842   }
 843 
 844   // signed version: extract from field and sign-extend
 845   static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
 846     x = x << (31-hi_bit);
 847     x = x >> (31-hi_bit+lo_bit);
 848     return x;
 849   }
 850 
 851   static int u_field(int x, int hi_bit, int lo_bit) {
 852     assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
 853     int r = x << lo_bit;
 854     assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 855     return r;
 856   }
 857 
 858   // Same as u_field for signed values
 859   static int s_field(int x, int hi_bit, int lo_bit) {
 860     int nbits = hi_bit - lo_bit + 1;
 861     assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
 862       "value out of range");
 863     x &= fmask(hi_bit, lo_bit);
 864     int r = x << lo_bit;
 865     return r;
 866   }
 867 
 868   // inv_op for ppc instructions
 869   static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
 870 
 871   // Determine target address from li, bd field of branch instruction.
 872   static intptr_t inv_li_field(int x) {
 873     intptr_t r = inv_s_field_ppc(x, 25, 2);
 874     r = (r << 2);
 875     return r;
 876   }
 877   static intptr_t inv_bd_field(int x, intptr_t pos) {
 878     intptr_t r = inv_s_field_ppc(x, 15, 2);
 879     r = (r << 2) + pos;
 880     return r;
 881   }
 882 
 883   #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
 884   #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
 885   // Extract instruction fields from instruction words.
 886  public:
 887   static int inv_ra_field(int x)  { return inv_opp_u_field(x, 15, 11); }
 888   static int inv_rb_field(int x)  { return inv_opp_u_field(x, 20, 16); }
 889   static int inv_rt_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 890   static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
 891   static int inv_rs_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 892   // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
 893   // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
 894   static int inv_ds_field(int x)  { return inv_opp_s_field(x, 29, 16) << 2; }
 895   static int inv_d1_field(int x)  { return inv_opp_s_field(x, 31, 16); }
 896   static int inv_si_field(int x)  { return inv_opp_s_field(x, 31, 16); }
 897   static int inv_to_field(int x)  { return inv_opp_u_field(x, 10, 6);  }
 898   static int inv_lk_field(int x)  { return inv_opp_u_field(x, 31, 31); }
 899   static int inv_bo_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 900   static int inv_bi_field(int x)  { return inv_opp_u_field(x, 15, 11); }
 901 
 902   #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
 903   #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
 904 
 905   // instruction fields
 906   static int aa(       int         x)  { return  opp_u_field(x,             30, 30); }
 907   static int ba(       int         x)  { return  opp_u_field(x,             15, 11); }
 908   static int bb(       int         x)  { return  opp_u_field(x,             20, 16); }
 909   static int bc(       int         x)  { return  opp_u_field(x,             25, 21); }
 910   static int bd(       int         x)  { return  opp_s_field(x,             29, 16); }
 911   static int bf( ConditionRegister cr) { return  bf(cr->encoding()); }
 912   static int bf(       int         x)  { return  opp_u_field(x,              8,  6); }
 913   static int bfa(ConditionRegister cr) { return  bfa(cr->encoding()); }
 914   static int bfa(      int         x)  { return  opp_u_field(x,             13, 11); }
 915   static int bh(       int         x)  { return  opp_u_field(x,             20, 19); }
 916   static int bi(       int         x)  { return  opp_u_field(x,             15, 11); }
 917   static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
 918   static int bo(       int         x)  { return  opp_u_field(x,             10,  6); }
 919   static int bt(       int         x)  { return  opp_u_field(x,             10,  6); }
 920   static int d1(       int         x)  { return  opp_s_field(x,             31, 16); }
 921   static int ds(       int         x)  { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
 922   static int eh(       int         x)  { return  opp_u_field(x,             31, 31); }
 923   static int flm(      int         x)  { return  opp_u_field(x,             14,  7); }
 924   static int fra(    FloatRegister r)  { return  fra(r->encoding());}
 925   static int frb(    FloatRegister r)  { return  frb(r->encoding());}
 926   static int frc(    FloatRegister r)  { return  frc(r->encoding());}
 927   static int frs(    FloatRegister r)  { return  frs(r->encoding());}
 928   static int frt(    FloatRegister r)  { return  frt(r->encoding());}
 929   static int fra(      int         x)  { return  opp_u_field(x,             15, 11); }
 930   static int frb(      int         x)  { return  opp_u_field(x,             20, 16); }
 931   static int frc(      int         x)  { return  opp_u_field(x,             25, 21); }
 932   static int frs(      int         x)  { return  opp_u_field(x,             10,  6); }
 933   static int frt(      int         x)  { return  opp_u_field(x,             10,  6); }
 934   static int fxm(      int         x)  { return  opp_u_field(x,             19, 12); }
 935   static int l10(      int         x)  { return  opp_u_field(x,             10, 10); }
 936   static int l15(      int         x)  { return  opp_u_field(x,             15, 15); }
 937   static int l910(     int         x)  { return  opp_u_field(x,             10,  9); }
 938   static int e1215(    int         x)  { return  opp_u_field(x,             15, 12); }
 939   static int lev(      int         x)  { return  opp_u_field(x,             26, 20); }
 940   static int li(       int         x)  { return  opp_s_field(x,             29,  6); }
 941   static int lk(       int         x)  { return  opp_u_field(x,             31, 31); }
 942   static int mb2125(   int         x)  { return  opp_u_field(x,             25, 21); }
 943   static int me2630(   int         x)  { return  opp_u_field(x,             30, 26); }
 944   static int mb2126(   int         x)  { return  opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
 945   static int me2126(   int         x)  { return  mb2126(x); }
 946   static int nb(       int         x)  { return  opp_u_field(x,             20, 16); }
 947   //static int opcd(   int         x)  { return  opp_u_field(x,              5,  0); } // is contained in our opcodes
 948   static int oe(       int         x)  { return  opp_u_field(x,             21, 21); }
 949   static int ra(       Register    r)  { return  ra(r->encoding()); }
 950   static int ra(       int         x)  { return  opp_u_field(x,             15, 11); }
 951   static int rb(       Register    r)  { return  rb(r->encoding()); }
 952   static int rb(       int         x)  { return  opp_u_field(x,             20, 16); }
 953   static int rc(       int         x)  { return  opp_u_field(x,             31, 31); }
 954   static int rs(       Register    r)  { return  rs(r->encoding()); }
 955   static int rs(       int         x)  { return  opp_u_field(x,             10,  6); }
 956   // we don't want to use R0 in memory accesses, because it has value `0' then
 957   static int ra0mem(   Register    r)  { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
 958   static int ra0mem(   int         x)  { assert(x != 0,  "cannot use register 0 in memory access");  return ra(x); }
 959 
 960   // register r is target
 961   static int rt(       Register    r)  { return rs(r); }
 962   static int rt(       int         x)  { return rs(x); }
 963   static int rta(      Register    r)  { return ra(r); }
 964   static int rta0mem(  Register    r)  { rta(r); return ra0mem(r); }
 965 
 966   static int sh1620(   int         x)  { return  opp_u_field(x,             20, 16); }
 967   static int sh30(     int         x)  { return  opp_u_field(x,             30, 30); }
 968   static int sh162030( int         x)  { return  sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
 969   static int si(       int         x)  { return  opp_s_field(x,             31, 16); }
 970   static int spr(      int         x)  { return  opp_u_field(x,             20, 11); }
 971   static int sr(       int         x)  { return  opp_u_field(x,             15, 12); }
 972   static int tbr(      int         x)  { return  opp_u_field(x,             20, 11); }
 973   static int th(       int         x)  { return  opp_u_field(x,             10,  7); }
 974   static int thct(     int         x)  { assert((x&8) == 0, "must be valid cache specification");  return th(x); }
 975   static int thds(     int         x)  { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
 976   static int to(       int         x)  { return  opp_u_field(x,             10,  6); }
 977   static int u(        int         x)  { return  opp_u_field(x,             19, 16); }
 978   static int ui(       int         x)  { return  opp_u_field(x,             31, 16); }
 979 
 980   // Support vector instructions for >= Power6.
 981   static int vra(      int         x)  { return  opp_u_field(x,             15, 11); }
 982   static int vrb(      int         x)  { return  opp_u_field(x,             20, 16); }
 983   static int vrc(      int         x)  { return  opp_u_field(x,             25, 21); }
 984   static int vrs(      int         x)  { return  opp_u_field(x,             10,  6); }
 985   static int vrt(      int         x)  { return  opp_u_field(x,             10,  6); }
 986 
 987   static int vra(   VectorRegister r)  { return  vra(r->encoding());}
 988   static int vrb(   VectorRegister r)  { return  vrb(r->encoding());}
 989   static int vrc(   VectorRegister r)  { return  vrc(r->encoding());}
 990   static int vrs(   VectorRegister r)  { return  vrs(r->encoding());}
 991   static int vrt(   VectorRegister r)  { return  vrt(r->encoding());}
 992 
 993   static int vsplt_uim( int        x)  { return  opp_u_field(x,             15, 12); } // for vsplt* instructions
 994   static int vsplti_sim(int        x)  { return  opp_u_field(x,             15, 11); } // for vsplti* instructions
 995   static int vsldoi_shb(int        x)  { return  opp_u_field(x,             25, 22); } // for vsldoi instruction
 996   static int vcmp_rc(   int        x)  { return  opp_u_field(x,             21, 21); } // for vcmp* instructions
 997 
 998   //static int xo1(     int        x)  { return  opp_u_field(x,             29, 21); }// is contained in our opcodes
 999   //static int xo2(     int        x)  { return  opp_u_field(x,             30, 21); }// is contained in our opcodes
1000   //static int xo3(     int        x)  { return  opp_u_field(x,             30, 22); }// is contained in our opcodes
1001   //static int xo4(     int        x)  { return  opp_u_field(x,             30, 26); }// is contained in our opcodes
1002   //static int xo5(     int        x)  { return  opp_u_field(x,             29, 27); }// is contained in our opcodes
1003   //static int xo6(     int        x)  { return  opp_u_field(x,             30, 27); }// is contained in our opcodes
1004   //static int xo7(     int        x)  { return  opp_u_field(x,             31, 30); }// is contained in our opcodes
1005 
1006  protected:
1007   // Compute relative address for branch.
1008   static intptr_t disp(intptr_t x, intptr_t off) {
1009     int xx = x - off;
1010     xx = xx >> 2;
1011     return xx;
1012   }
1013 
1014  public:
1015   // signed immediate, in low bits, nbits long
1016   static int simm(int x, int nbits) {
1017     assert_signed_range(x, nbits);
1018     return x & ((1 << nbits) - 1);
1019   }
1020 
1021   // unsigned immediate, in low bits, nbits long
1022   static int uimm(int x, int nbits) {
1023     assert_unsigned_const(x, nbits);
1024     return x & ((1 << nbits) - 1);
1025   }
1026 
1027   static void set_imm(int* instr, short s) {
1028     // imm is always in the lower 16 bits of the instruction,
1029     // so this is endian-neutral. Same for the get_imm below.
1030     uint32_t w = *(uint32_t *)instr;
1031     *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1032   }
1033 
1034   static int get_imm(address a, int instruction_number) {
1035     return (short)((int *)a)[instruction_number];
1036   }
1037 
1038   static inline int hi16_signed(  int x) { return (int)(int16_t)(x >> 16); }
1039   static inline int lo16_unsigned(int x) { return x & 0xffff; }
1040 
1041  protected:
1042 
1043   // Extract the top 32 bits in a 64 bit word.
1044   static int32_t hi32(int64_t x) {
1045     int32_t r = int32_t((uint64_t)x >> 32);
1046     return r;
1047   }
1048 
1049  public:
1050 
1051   static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1052     return ((addr + (a - 1)) & ~(a - 1));
1053   }
1054 
1055   static inline bool is_aligned(unsigned int addr, unsigned int a) {
1056     return (0 == addr % a);
1057   }
1058 
1059   void flush() {
1060     AbstractAssembler::flush();
1061   }
1062 
1063   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
1064   inline void emit_data(int);
1065   inline void emit_data(int, RelocationHolder const&);
1066   inline void emit_data(int, relocInfo::relocType rtype);
1067 
1068   // Emit an address.
1069   inline address emit_addr(const address addr = NULL);
1070 
1071 #if !defined(ABI_ELFv2)
1072   // Emit a function descriptor with the specified entry point, TOC,
1073   // and ENV. If the entry point is NULL, the descriptor will point
1074   // just past the descriptor.
1075   // Use values from friend functions as defaults.
1076   inline address emit_fd(address entry = NULL,
1077                          address toc = (address) FunctionDescriptor::friend_toc,
1078                          address env = (address) FunctionDescriptor::friend_env);
1079 #endif
1080 
1081   /////////////////////////////////////////////////////////////////////////////////////
1082   // PPC instructions
1083   /////////////////////////////////////////////////////////////////////////////////////
1084 
1085   // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1086   // immediates. The normal instruction encoders enforce that r0 is not
1087   // passed to them. Use either extended mnemonics encoders or the special ra0
1088   // versions.
1089 
1090   // Issue an illegal instruction.
1091   inline void illtrap();
1092   static inline bool is_illtrap(int x);
1093 
1094   // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1095   inline void addi( Register d, Register a, int si16);
1096   inline void addis(Register d, Register a, int si16);
1097  private:
1098   inline void addi_r0ok( Register d, Register a, int si16);
1099   inline void addis_r0ok(Register d, Register a, int si16);
1100  public:
1101   inline void addic_( Register d, Register a, int si16);
1102   inline void subfic( Register d, Register a, int si16);
1103   inline void add(    Register d, Register a, Register b);
1104   inline void add_(   Register d, Register a, Register b);
1105   inline void subf(   Register d, Register a, Register b);  // d = b - a    "Sub_from", as in ppc spec.
1106   inline void sub(    Register d, Register a, Register b);  // d = a - b    Swap operands of subf for readability.
1107   inline void subf_(  Register d, Register a, Register b);
1108   inline void addc(   Register d, Register a, Register b);
1109   inline void addc_(  Register d, Register a, Register b);
1110   inline void subfc(  Register d, Register a, Register b);
1111   inline void subfc_( Register d, Register a, Register b);
1112   inline void adde(   Register d, Register a, Register b);
1113   inline void adde_(  Register d, Register a, Register b);
1114   inline void subfe(  Register d, Register a, Register b);
1115   inline void subfe_( Register d, Register a, Register b);
1116   inline void neg(    Register d, Register a);
1117   inline void neg_(   Register d, Register a);
1118   inline void mulli(  Register d, Register a, int si16);
1119   inline void mulld(  Register d, Register a, Register b);
1120   inline void mulld_( Register d, Register a, Register b);
1121   inline void mullw(  Register d, Register a, Register b);
1122   inline void mullw_( Register d, Register a, Register b);
1123   inline void mulhw(  Register d, Register a, Register b);
1124   inline void mulhw_( Register d, Register a, Register b);
1125   inline void mulhd(  Register d, Register a, Register b);
1126   inline void mulhd_( Register d, Register a, Register b);
1127   inline void mulhdu( Register d, Register a, Register b);
1128   inline void mulhdu_(Register d, Register a, Register b);
1129   inline void divd(   Register d, Register a, Register b);
1130   inline void divd_(  Register d, Register a, Register b);
1131   inline void divw(   Register d, Register a, Register b);
1132   inline void divw_(  Register d, Register a, Register b);
1133 
1134   // extended mnemonics
1135   inline void li(   Register d, int si16);
1136   inline void lis(  Register d, int si16);
1137   inline void addir(Register d, int si16, Register a);
1138 
1139   static bool is_addi(int x) {
1140      return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1141   }
1142   static bool is_addis(int x) {
1143      return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1144   }
1145   static bool is_bxx(int x) {
1146      return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1147   }
1148   static bool is_b(int x) {
1149      return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1150   }
1151   static bool is_bl(int x) {
1152      return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1153   }
1154   static bool is_bcxx(int x) {
1155      return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1156   }
1157   static bool is_bxx_or_bcxx(int x) {
1158      return is_bxx(x) || is_bcxx(x);
1159   }
1160   static bool is_bctrl(int x) {
1161      return x == 0x4e800421;
1162   }
1163   static bool is_bctr(int x) {
1164      return x == 0x4e800420;
1165   }
1166   static bool is_bclr(int x) {
1167      return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1168   }
1169   static bool is_li(int x) {
1170      return is_addi(x) && inv_ra_field(x)==0;
1171   }
1172   static bool is_lis(int x) {
1173      return is_addis(x) && inv_ra_field(x)==0;
1174   }
1175   static bool is_mtctr(int x) {
1176      return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1177   }
1178   static bool is_ld(int x) {
1179      return LD_OPCODE == (x & LD_OPCODE_MASK);
1180   }
1181   static bool is_std(int x) {
1182      return STD_OPCODE == (x & STD_OPCODE_MASK);
1183   }
1184   static bool is_stdu(int x) {
1185      return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1186   }
1187   static bool is_stdx(int x) {
1188      return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1189   }
1190   static bool is_stdux(int x) {
1191      return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1192   }
1193   static bool is_stwx(int x) {
1194      return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1195   }
1196   static bool is_stwux(int x) {
1197      return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1198   }
1199   static bool is_stw(int x) {
1200      return STW_OPCODE == (x & STW_OPCODE_MASK);
1201   }
1202   static bool is_stwu(int x) {
1203      return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1204   }
1205   static bool is_ori(int x) {
1206      return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1207   };
1208   static bool is_oris(int x) {
1209      return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1210   };
1211   static bool is_rldicr(int x) {
1212      return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1213   };
1214   static bool is_nop(int x) {
1215     return x == 0x60000000;
1216   }
1217   // endgroup opcode for Power6
1218   static bool is_endgroup(int x) {
1219     return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1220   }
1221 
1222 
1223  private:
1224   // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1225   inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1226   inline void cmp(  ConditionRegister bf, int l, Register a, Register b);
1227   inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1228   inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1229 
1230  public:
1231   // extended mnemonics of Compare Instructions
1232   inline void cmpwi( ConditionRegister crx, Register a, int si16);
1233   inline void cmpdi( ConditionRegister crx, Register a, int si16);
1234   inline void cmpw(  ConditionRegister crx, Register a, Register b);
1235   inline void cmpd(  ConditionRegister crx, Register a, Register b);
1236   inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1237   inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1238   inline void cmplw( ConditionRegister crx, Register a, Register b);
1239   inline void cmpld( ConditionRegister crx, Register a, Register b);
1240 
1241   inline void isel(   Register d, Register a, Register b, int bc);
1242   // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1243   inline void isel(   Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1244   // Set d = 0 if (cr.cc) equals 1, otherwise b.
1245   inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1246 
1247   // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1248          void andi(   Register a, Register s, int ui16);   // optimized version
1249   inline void andi_(  Register a, Register s, int ui16);
1250   inline void andis_( Register a, Register s, int ui16);
1251   inline void ori(    Register a, Register s, int ui16);
1252   inline void oris(   Register a, Register s, int ui16);
1253   inline void xori(   Register a, Register s, int ui16);
1254   inline void xoris(  Register a, Register s, int ui16);
1255   inline void andr(   Register a, Register s, Register b);  // suffixed by 'r' as 'and' is C++ keyword
1256   inline void and_(   Register a, Register s, Register b);
1257   // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1258   // SMT-priority change instruction (see SMT instructions below).
1259   inline void or_unchecked(Register a, Register s, Register b);
1260   inline void orr(    Register a, Register s, Register b);  // suffixed by 'r' as 'or' is C++ keyword
1261   inline void or_(    Register a, Register s, Register b);
1262   inline void xorr(   Register a, Register s, Register b);  // suffixed by 'r' as 'xor' is C++ keyword
1263   inline void xor_(   Register a, Register s, Register b);
1264   inline void nand(   Register a, Register s, Register b);
1265   inline void nand_(  Register a, Register s, Register b);
1266   inline void nor(    Register a, Register s, Register b);
1267   inline void nor_(   Register a, Register s, Register b);
1268   inline void andc(   Register a, Register s, Register b);
1269   inline void andc_(  Register a, Register s, Register b);
1270   inline void orc(    Register a, Register s, Register b);
1271   inline void orc_(   Register a, Register s, Register b);
1272   inline void extsb(  Register a, Register s);
1273   inline void extsh(  Register a, Register s);
1274   inline void extsw(  Register a, Register s);
1275 
1276   // extended mnemonics
1277   inline void nop();
1278   // NOP for FP and BR units (different versions to allow them to be in one group)
1279   inline void fpnop0();
1280   inline void fpnop1();
1281   inline void brnop0();
1282   inline void brnop1();
1283   inline void brnop2();
1284 
1285   inline void mr(      Register d, Register s);
1286   inline void ori_opt( Register d, int ui16);
1287   inline void oris_opt(Register d, int ui16);
1288 
1289   // endgroup opcode for Power6
1290   inline void endgroup();
1291 
1292   // count instructions
1293   inline void cntlzw(  Register a, Register s);
1294   inline void cntlzw_( Register a, Register s);
1295   inline void cntlzd(  Register a, Register s);
1296   inline void cntlzd_( Register a, Register s);
1297 
1298   // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1299   inline void sld(     Register a, Register s, Register b);
1300   inline void sld_(    Register a, Register s, Register b);
1301   inline void slw(     Register a, Register s, Register b);
1302   inline void slw_(    Register a, Register s, Register b);
1303   inline void srd(     Register a, Register s, Register b);
1304   inline void srd_(    Register a, Register s, Register b);
1305   inline void srw(     Register a, Register s, Register b);
1306   inline void srw_(    Register a, Register s, Register b);
1307   inline void srad(    Register a, Register s, Register b);
1308   inline void srad_(   Register a, Register s, Register b);
1309   inline void sraw(    Register a, Register s, Register b);
1310   inline void sraw_(   Register a, Register s, Register b);
1311   inline void sradi(   Register a, Register s, int sh6);
1312   inline void sradi_(  Register a, Register s, int sh6);
1313   inline void srawi(   Register a, Register s, int sh5);
1314   inline void srawi_(  Register a, Register s, int sh5);
1315 
1316   // extended mnemonics for Shift Instructions
1317   inline void sldi(    Register a, Register s, int sh6);
1318   inline void sldi_(   Register a, Register s, int sh6);
1319   inline void slwi(    Register a, Register s, int sh5);
1320   inline void slwi_(   Register a, Register s, int sh5);
1321   inline void srdi(    Register a, Register s, int sh6);
1322   inline void srdi_(   Register a, Register s, int sh6);
1323   inline void srwi(    Register a, Register s, int sh5);
1324   inline void srwi_(   Register a, Register s, int sh5);
1325 
1326   inline void clrrdi(  Register a, Register s, int ui6);
1327   inline void clrrdi_( Register a, Register s, int ui6);
1328   inline void clrldi(  Register a, Register s, int ui6);
1329   inline void clrldi_( Register a, Register s, int ui6);
1330   inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1331   inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1332   inline void extrdi(  Register a, Register s, int n, int b);
1333   // testbit with condition register
1334   inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1335 
1336   // rotate instructions
1337   inline void rotldi(  Register a, Register s, int n);
1338   inline void rotrdi(  Register a, Register s, int n);
1339   inline void rotlwi(  Register a, Register s, int n);
1340   inline void rotrwi(  Register a, Register s, int n);
1341 
1342   // Rotate Instructions
1343   inline void rldic(   Register a, Register s, int sh6, int mb6);
1344   inline void rldic_(  Register a, Register s, int sh6, int mb6);
1345   inline void rldicr(  Register a, Register s, int sh6, int mb6);
1346   inline void rldicr_( Register a, Register s, int sh6, int mb6);
1347   inline void rldicl(  Register a, Register s, int sh6, int mb6);
1348   inline void rldicl_( Register a, Register s, int sh6, int mb6);
1349   inline void rlwinm(  Register a, Register s, int sh5, int mb5, int me5);
1350   inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1351   inline void rldimi(  Register a, Register s, int sh6, int mb6);
1352   inline void rldimi_( Register a, Register s, int sh6, int mb6);
1353   inline void rlwimi(  Register a, Register s, int sh5, int mb5, int me5);
1354   inline void insrdi(  Register a, Register s, int n,   int b);
1355   inline void insrwi(  Register a, Register s, int n,   int b);
1356 
1357   // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1358   // 4 bytes
1359   inline void lwzx( Register d, Register s1, Register s2);
1360   inline void lwz(  Register d, int si16,    Register s1);
1361   inline void lwzu( Register d, int si16,    Register s1);
1362 
1363   // 4 bytes
1364   inline void lwax( Register d, Register s1, Register s2);
1365   inline void lwa(  Register d, int si16,    Register s1);
1366 
1367   // 2 bytes
1368   inline void lhzx( Register d, Register s1, Register s2);
1369   inline void lhz(  Register d, int si16,    Register s1);
1370   inline void lhzu( Register d, int si16,    Register s1);
1371 
1372   // 2 bytes
1373   inline void lhax( Register d, Register s1, Register s2);
1374   inline void lha(  Register d, int si16,    Register s1);
1375   inline void lhau( Register d, int si16,    Register s1);
1376 
1377   // 1 byte
1378   inline void lbzx( Register d, Register s1, Register s2);
1379   inline void lbz(  Register d, int si16,    Register s1);
1380   inline void lbzu( Register d, int si16,    Register s1);
1381 
1382   // 8 bytes
1383   inline void ldx(  Register d, Register s1, Register s2);
1384   inline void ld(   Register d, int si16,    Register s1);
1385   inline void ldu(  Register d, int si16,    Register s1);
1386 
1387   //  PPC 1, section 3.3.3 Fixed-Point Store Instructions
1388   inline void stwx( Register d, Register s1, Register s2);
1389   inline void stw(  Register d, int si16,    Register s1);
1390   inline void stwu( Register d, int si16,    Register s1);
1391 
1392   inline void sthx( Register d, Register s1, Register s2);
1393   inline void sth(  Register d, int si16,    Register s1);
1394   inline void sthu( Register d, int si16,    Register s1);
1395 
1396   inline void stbx( Register d, Register s1, Register s2);
1397   inline void stb(  Register d, int si16,    Register s1);
1398   inline void stbu( Register d, int si16,    Register s1);
1399 
1400   inline void stdx( Register d, Register s1, Register s2);
1401   inline void std(  Register d, int si16,    Register s1);
1402   inline void stdu( Register d, int si16,    Register s1);
1403   inline void stdux(Register s, Register a,  Register b);
1404 
1405   // PPC 1, section 3.3.13 Move To/From System Register Instructions
1406   inline void mtlr( Register s1);
1407   inline void mflr( Register d);
1408   inline void mtctr(Register s1);
1409   inline void mfctr(Register d);
1410   inline void mtcrf(int fxm, Register s);
1411   inline void mfcr( Register d);
1412   inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1413   inline void mtcr( Register s);
1414 
1415   // PPC 1, section 2.4.1 Branch Instructions
1416   inline void b(  address a, relocInfo::relocType rt = relocInfo::none);
1417   inline void b(  Label& L);
1418   inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1419   inline void bl( Label& L);
1420   inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1421   inline void bc( int boint, int biint, Label& L);
1422   inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1423   inline void bcl(int boint, int biint, Label& L);
1424 
1425   inline void bclr(  int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1426   inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1427   inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1428                          relocInfo::relocType rt = relocInfo::none);
1429   inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1430                          relocInfo::relocType rt = relocInfo::none);
1431 
1432   // helper function for b, bcxx
1433   inline bool is_within_range_of_b(address a, address pc);
1434   inline bool is_within_range_of_bcxx(address a, address pc);
1435 
1436   // get the destination of a bxx branch (b, bl, ba, bla)
1437   static inline address  bxx_destination(address baddr);
1438   static inline address  bxx_destination(int instr, address pc);
1439   static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1440 
1441   // extended mnemonics for branch instructions
1442   inline void blt(ConditionRegister crx, Label& L);
1443   inline void bgt(ConditionRegister crx, Label& L);
1444   inline void beq(ConditionRegister crx, Label& L);
1445   inline void bso(ConditionRegister crx, Label& L);
1446   inline void bge(ConditionRegister crx, Label& L);
1447   inline void ble(ConditionRegister crx, Label& L);
1448   inline void bne(ConditionRegister crx, Label& L);
1449   inline void bns(ConditionRegister crx, Label& L);
1450 
1451   // Branch instructions with static prediction hints.
1452   inline void blt_predict_taken(    ConditionRegister crx, Label& L);
1453   inline void bgt_predict_taken(    ConditionRegister crx, Label& L);
1454   inline void beq_predict_taken(    ConditionRegister crx, Label& L);
1455   inline void bso_predict_taken(    ConditionRegister crx, Label& L);
1456   inline void bge_predict_taken(    ConditionRegister crx, Label& L);
1457   inline void ble_predict_taken(    ConditionRegister crx, Label& L);
1458   inline void bne_predict_taken(    ConditionRegister crx, Label& L);
1459   inline void bns_predict_taken(    ConditionRegister crx, Label& L);
1460   inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1461   inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1462   inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1463   inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1464   inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1465   inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1466   inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1467   inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1468 
1469   // for use in conjunction with testbitdi:
1470   inline void btrue( ConditionRegister crx, Label& L);
1471   inline void bfalse(ConditionRegister crx, Label& L);
1472 
1473   inline void bltl(ConditionRegister crx, Label& L);
1474   inline void bgtl(ConditionRegister crx, Label& L);
1475   inline void beql(ConditionRegister crx, Label& L);
1476   inline void bsol(ConditionRegister crx, Label& L);
1477   inline void bgel(ConditionRegister crx, Label& L);
1478   inline void blel(ConditionRegister crx, Label& L);
1479   inline void bnel(ConditionRegister crx, Label& L);
1480   inline void bnsl(ConditionRegister crx, Label& L);
1481 
1482   // extended mnemonics for Branch Instructions via LR
1483   // We use `blr' for returns.
1484   inline void blr(relocInfo::relocType rt = relocInfo::none);
1485 
1486   // extended mnemonics for Branch Instructions with CTR
1487   // bdnz means `decrement CTR and jump to L if CTR is not zero'
1488   inline void bdnz(Label& L);
1489   // Decrement and branch if result is zero.
1490   inline void bdz(Label& L);
1491   // we use `bctr[l]' for jumps/calls in function descriptor glue
1492   // code, e.g. calls to runtime functions
1493   inline void bctr( relocInfo::relocType rt = relocInfo::none);
1494   inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1495   // conditional jumps/branches via CTR
1496   inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1497   inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1498   inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1499   inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1500 
1501   // condition register logic instructions
1502   inline void crand( int d, int s1, int s2);
1503   inline void crnand(int d, int s1, int s2);
1504   inline void cror(  int d, int s1, int s2);
1505   inline void crxor( int d, int s1, int s2);
1506   inline void crnor( int d, int s1, int s2);
1507   inline void creqv( int d, int s1, int s2);
1508   inline void crandc(int d, int s1, int s2);
1509   inline void crorc( int d, int s1, int s2);
1510 
1511   // icache and dcache related instructions
1512   inline void icbi(  Register s1, Register s2);
1513   //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1514   inline void dcbz(  Register s1, Register s2);
1515   inline void dcbst( Register s1, Register s2);
1516   inline void dcbf(  Register s1, Register s2);
1517 
1518   enum ct_cache_specification {
1519     ct_primary_cache   = 0,
1520     ct_secondary_cache = 2
1521   };
1522   // dcache read hint
1523   inline void dcbt(    Register s1, Register s2);
1524   inline void dcbtct(  Register s1, Register s2, int ct);
1525   inline void dcbtds(  Register s1, Register s2, int ds);
1526   // dcache write hint
1527   inline void dcbtst(  Register s1, Register s2);
1528   inline void dcbtstct(Register s1, Register s2, int ct);
1529 
1530   //  machine barrier instructions:
1531   //
1532   //  - sync    two-way memory barrier, aka fence
1533   //  - lwsync  orders  Store|Store,
1534   //                     Load|Store,
1535   //                     Load|Load,
1536   //            but not Store|Load
1537   //  - eieio   orders memory accesses for device memory (only)
1538   //  - isync   invalidates speculatively executed instructions
1539   //            From the Power ISA 2.06 documentation:
1540   //             "[...] an isync instruction prevents the execution of
1541   //            instructions following the isync until instructions
1542   //            preceding the isync have completed, [...]"
1543   //            From IBM's AIX assembler reference:
1544   //             "The isync [...] instructions causes the processor to
1545   //            refetch any instructions that might have been fetched
1546   //            prior to the isync instruction. The instruction isync
1547   //            causes the processor to wait for all previous instructions
1548   //            to complete. Then any instructions already fetched are
1549   //            discarded and instruction processing continues in the
1550   //            environment established by the previous instructions."
1551   //
1552   //  semantic barrier instructions:
1553   //  (as defined in orderAccess.hpp)
1554   //
1555   //  - release  orders Store|Store,       (maps to lwsync)
1556   //                     Load|Store
1557   //  - acquire  orders  Load|Store,       (maps to lwsync)
1558   //                     Load|Load
1559   //  - fence    orders Store|Store,       (maps to sync)
1560   //                     Load|Store,
1561   //                     Load|Load,
1562   //                    Store|Load
1563   //
1564  private:
1565   inline void sync(int l);
1566  public:
1567   inline void sync();
1568   inline void lwsync();
1569   inline void ptesync();
1570   inline void eieio();
1571   inline void isync();
1572   inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1573 
1574   // atomics
1575   inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1576   inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1577   inline bool lxarx_hint_exclusive_access();
1578   inline void lwarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
1579   inline void ldarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
1580   inline void stwcx_( Register s, Register a, Register b);
1581   inline void stdcx_( Register s, Register a, Register b);
1582 
1583   // Instructions for adjusting thread priority for simultaneous
1584   // multithreading (SMT) on Power5.
1585  private:
1586   inline void smt_prio_very_low();
1587   inline void smt_prio_medium_high();
1588   inline void smt_prio_high();
1589 
1590  public:
1591   inline void smt_prio_low();
1592   inline void smt_prio_medium_low();
1593   inline void smt_prio_medium();
1594 
1595   // trap instructions
1596   inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1597   // NOT FOR DIRECT USE!!
1598  protected:
1599   inline void tdi_unchecked(int tobits, Register a, int si16);
1600   inline void twi_unchecked(int tobits, Register a, int si16);
1601   inline void tdi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
1602   inline void twi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
1603   inline void td(           int tobits, Register a, Register b); // asserts UseSIGTRAP
1604   inline void tw(           int tobits, Register a, Register b); // asserts UseSIGTRAP
1605 
1606   static bool is_tdi(int x, int tobits, int ra, int si16) {
1607      return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1608          && (tobits == inv_to_field(x))
1609          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1610          && (si16 == inv_si_field(x));
1611   }
1612 
1613   static bool is_twi(int x, int tobits, int ra, int si16) {
1614      return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1615          && (tobits == inv_to_field(x))
1616          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1617          && (si16 == inv_si_field(x));
1618   }
1619 
1620   static bool is_twi(int x, int tobits, int ra) {
1621      return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1622          && (tobits == inv_to_field(x))
1623          && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1624   }
1625 
1626   static bool is_td(int x, int tobits, int ra, int rb) {
1627      return (TD_OPCODE == (x & TD_OPCODE_MASK))
1628          && (tobits == inv_to_field(x))
1629          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1630          && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1631   }
1632 
1633   static bool is_tw(int x, int tobits, int ra, int rb) {
1634      return (TW_OPCODE == (x & TW_OPCODE_MASK))
1635          && (tobits == inv_to_field(x))
1636          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1637          && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1638   }
1639 
1640  public:
1641   // PPC floating point instructions
1642   // PPC 1, section 4.6.2 Floating-Point Load Instructions
1643   inline void lfs(  FloatRegister d, int si16,   Register a);
1644   inline void lfsu( FloatRegister d, int si16,   Register a);
1645   inline void lfsx( FloatRegister d, Register a, Register b);
1646   inline void lfd(  FloatRegister d, int si16,   Register a);
1647   inline void lfdu( FloatRegister d, int si16,   Register a);
1648   inline void lfdx( FloatRegister d, Register a, Register b);
1649 
1650   // PPC 1, section 4.6.3 Floating-Point Store Instructions
1651   inline void stfs(  FloatRegister s, int si16,   Register a);
1652   inline void stfsu( FloatRegister s, int si16,   Register a);
1653   inline void stfsx( FloatRegister s, Register a, Register b);
1654   inline void stfd(  FloatRegister s, int si16,   Register a);
1655   inline void stfdu( FloatRegister s, int si16,   Register a);
1656   inline void stfdx( FloatRegister s, Register a, Register b);
1657 
1658   // PPC 1, section 4.6.4 Floating-Point Move Instructions
1659   inline void fmr(  FloatRegister d, FloatRegister b);
1660   inline void fmr_( FloatRegister d, FloatRegister b);
1661 
1662   //  inline void mffgpr( FloatRegister d, Register b);
1663   //  inline void mftgpr( Register d, FloatRegister b);
1664   inline void cmpb(   Register a, Register s, Register b);
1665   inline void popcntb(Register a, Register s);
1666   inline void popcntw(Register a, Register s);
1667   inline void popcntd(Register a, Register s);
1668 
1669   inline void fneg(  FloatRegister d, FloatRegister b);
1670   inline void fneg_( FloatRegister d, FloatRegister b);
1671   inline void fabs(  FloatRegister d, FloatRegister b);
1672   inline void fabs_( FloatRegister d, FloatRegister b);
1673   inline void fnabs( FloatRegister d, FloatRegister b);
1674   inline void fnabs_(FloatRegister d, FloatRegister b);
1675 
1676   // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1677   inline void fadd(  FloatRegister d, FloatRegister a, FloatRegister b);
1678   inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1679   inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1680   inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1681   inline void fsub(  FloatRegister d, FloatRegister a, FloatRegister b);
1682   inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1683   inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1684   inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1685   inline void fmul(  FloatRegister d, FloatRegister a, FloatRegister c);
1686   inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1687   inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1688   inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1689   inline void fdiv(  FloatRegister d, FloatRegister a, FloatRegister b);
1690   inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1691   inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1692   inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1693 
1694   // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1695   inline void frsp(  FloatRegister d, FloatRegister b);
1696   inline void fctid( FloatRegister d, FloatRegister b);
1697   inline void fctidz(FloatRegister d, FloatRegister b);
1698   inline void fctiw( FloatRegister d, FloatRegister b);
1699   inline void fctiwz(FloatRegister d, FloatRegister b);
1700   inline void fcfid( FloatRegister d, FloatRegister b);
1701   inline void fcfids(FloatRegister d, FloatRegister b);
1702 
1703   // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1704   inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1705 
1706   inline void fsqrt( FloatRegister d, FloatRegister b);
1707   inline void fsqrts(FloatRegister d, FloatRegister b);
1708 
1709   // Vector instructions for >= Power6.
1710   inline void lvebx(    VectorRegister d, Register s1, Register s2);
1711   inline void lvehx(    VectorRegister d, Register s1, Register s2);
1712   inline void lvewx(    VectorRegister d, Register s1, Register s2);
1713   inline void lvx(      VectorRegister d, Register s1, Register s2);
1714   inline void lvxl(     VectorRegister d, Register s1, Register s2);
1715   inline void stvebx(   VectorRegister d, Register s1, Register s2);
1716   inline void stvehx(   VectorRegister d, Register s1, Register s2);
1717   inline void stvewx(   VectorRegister d, Register s1, Register s2);
1718   inline void stvx(     VectorRegister d, Register s1, Register s2);
1719   inline void stvxl(    VectorRegister d, Register s1, Register s2);
1720   inline void lvsl(     VectorRegister d, Register s1, Register s2);
1721   inline void lvsr(     VectorRegister d, Register s1, Register s2);
1722   inline void vpkpx(    VectorRegister d, VectorRegister a, VectorRegister b);
1723   inline void vpkshss(  VectorRegister d, VectorRegister a, VectorRegister b);
1724   inline void vpkswss(  VectorRegister d, VectorRegister a, VectorRegister b);
1725   inline void vpkshus(  VectorRegister d, VectorRegister a, VectorRegister b);
1726   inline void vpkswus(  VectorRegister d, VectorRegister a, VectorRegister b);
1727   inline void vpkuhum(  VectorRegister d, VectorRegister a, VectorRegister b);
1728   inline void vpkuwum(  VectorRegister d, VectorRegister a, VectorRegister b);
1729   inline void vpkuhus(  VectorRegister d, VectorRegister a, VectorRegister b);
1730   inline void vpkuwus(  VectorRegister d, VectorRegister a, VectorRegister b);
1731   inline void vupkhpx(  VectorRegister d, VectorRegister b);
1732   inline void vupkhsb(  VectorRegister d, VectorRegister b);
1733   inline void vupkhsh(  VectorRegister d, VectorRegister b);
1734   inline void vupklpx(  VectorRegister d, VectorRegister b);
1735   inline void vupklsb(  VectorRegister d, VectorRegister b);
1736   inline void vupklsh(  VectorRegister d, VectorRegister b);
1737   inline void vmrghb(   VectorRegister d, VectorRegister a, VectorRegister b);
1738   inline void vmrghw(   VectorRegister d, VectorRegister a, VectorRegister b);
1739   inline void vmrghh(   VectorRegister d, VectorRegister a, VectorRegister b);
1740   inline void vmrglb(   VectorRegister d, VectorRegister a, VectorRegister b);
1741   inline void vmrglw(   VectorRegister d, VectorRegister a, VectorRegister b);
1742   inline void vmrglh(   VectorRegister d, VectorRegister a, VectorRegister b);
1743   inline void vsplt(    VectorRegister d, int ui4,          VectorRegister b);
1744   inline void vsplth(   VectorRegister d, int ui3,          VectorRegister b);
1745   inline void vspltw(   VectorRegister d, int ui2,          VectorRegister b);
1746   inline void vspltisb( VectorRegister d, int si5);
1747   inline void vspltish( VectorRegister d, int si5);
1748   inline void vspltisw( VectorRegister d, int si5);
1749   inline void vperm(    VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1750   inline void vsel(     VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1751   inline void vsl(      VectorRegister d, VectorRegister a, VectorRegister b);
1752   inline void vsldoi(   VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1753   inline void vslo(     VectorRegister d, VectorRegister a, VectorRegister b);
1754   inline void vsr(      VectorRegister d, VectorRegister a, VectorRegister b);
1755   inline void vsro(     VectorRegister d, VectorRegister a, VectorRegister b);
1756   inline void vaddcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
1757   inline void vaddshs(  VectorRegister d, VectorRegister a, VectorRegister b);
1758   inline void vaddsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
1759   inline void vaddsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1760   inline void vaddubm(  VectorRegister d, VectorRegister a, VectorRegister b);
1761   inline void vadduwm(  VectorRegister d, VectorRegister a, VectorRegister b);
1762   inline void vadduhm(  VectorRegister d, VectorRegister a, VectorRegister b);
1763   inline void vaddubs(  VectorRegister d, VectorRegister a, VectorRegister b);
1764   inline void vadduws(  VectorRegister d, VectorRegister a, VectorRegister b);
1765   inline void vadduhs(  VectorRegister d, VectorRegister a, VectorRegister b);
1766   inline void vsubcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
1767   inline void vsubshs(  VectorRegister d, VectorRegister a, VectorRegister b);
1768   inline void vsubsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
1769   inline void vsubsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1770   inline void vsububm(  VectorRegister d, VectorRegister a, VectorRegister b);
1771   inline void vsubuwm(  VectorRegister d, VectorRegister a, VectorRegister b);
1772   inline void vsubuhm(  VectorRegister d, VectorRegister a, VectorRegister b);
1773   inline void vsububs(  VectorRegister d, VectorRegister a, VectorRegister b);
1774   inline void vsubuws(  VectorRegister d, VectorRegister a, VectorRegister b);
1775   inline void vsubuhs(  VectorRegister d, VectorRegister a, VectorRegister b);
1776   inline void vmulesb(  VectorRegister d, VectorRegister a, VectorRegister b);
1777   inline void vmuleub(  VectorRegister d, VectorRegister a, VectorRegister b);
1778   inline void vmulesh(  VectorRegister d, VectorRegister a, VectorRegister b);
1779   inline void vmuleuh(  VectorRegister d, VectorRegister a, VectorRegister b);
1780   inline void vmulosb(  VectorRegister d, VectorRegister a, VectorRegister b);
1781   inline void vmuloub(  VectorRegister d, VectorRegister a, VectorRegister b);
1782   inline void vmulosh(  VectorRegister d, VectorRegister a, VectorRegister b);
1783   inline void vmulouh(  VectorRegister d, VectorRegister a, VectorRegister b);
1784   inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1785   inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1786   inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1787   inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1788   inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1789   inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1790   inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1791   inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1792   inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1793   inline void vsumsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1794   inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1795   inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1796   inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1797   inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1798   inline void vavgsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1799   inline void vavgsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1800   inline void vavgsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1801   inline void vavgub(   VectorRegister d, VectorRegister a, VectorRegister b);
1802   inline void vavguw(   VectorRegister d, VectorRegister a, VectorRegister b);
1803   inline void vavguh(   VectorRegister d, VectorRegister a, VectorRegister b);
1804   inline void vmaxsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1805   inline void vmaxsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1806   inline void vmaxsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1807   inline void vmaxub(   VectorRegister d, VectorRegister a, VectorRegister b);
1808   inline void vmaxuw(   VectorRegister d, VectorRegister a, VectorRegister b);
1809   inline void vmaxuh(   VectorRegister d, VectorRegister a, VectorRegister b);
1810   inline void vminsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1811   inline void vminsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1812   inline void vminsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1813   inline void vminub(   VectorRegister d, VectorRegister a, VectorRegister b);
1814   inline void vminuw(   VectorRegister d, VectorRegister a, VectorRegister b);
1815   inline void vminuh(   VectorRegister d, VectorRegister a, VectorRegister b);
1816   inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1817   inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1818   inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1819   inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1820   inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1821   inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1822   inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1823   inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
1824   inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
1825   inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
1826   inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
1827   inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
1828   inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
1829   inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
1830   inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
1831   inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
1832   inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
1833   inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
1834   inline void vand(     VectorRegister d, VectorRegister a, VectorRegister b);
1835   inline void vandc(    VectorRegister d, VectorRegister a, VectorRegister b);
1836   inline void vnor(     VectorRegister d, VectorRegister a, VectorRegister b);
1837   inline void vor(      VectorRegister d, VectorRegister a, VectorRegister b);
1838   inline void vxor(     VectorRegister d, VectorRegister a, VectorRegister b);
1839   inline void vrlb(     VectorRegister d, VectorRegister a, VectorRegister b);
1840   inline void vrlw(     VectorRegister d, VectorRegister a, VectorRegister b);
1841   inline void vrlh(     VectorRegister d, VectorRegister a, VectorRegister b);
1842   inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
1843   inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);
1844   inline void vslh(     VectorRegister d, VectorRegister a, VectorRegister b);
1845   inline void vsrb(     VectorRegister d, VectorRegister a, VectorRegister b);
1846   inline void vsrw(     VectorRegister d, VectorRegister a, VectorRegister b);
1847   inline void vsrh(     VectorRegister d, VectorRegister a, VectorRegister b);
1848   inline void vsrab(    VectorRegister d, VectorRegister a, VectorRegister b);
1849   inline void vsraw(    VectorRegister d, VectorRegister a, VectorRegister b);
1850   inline void vsrah(    VectorRegister d, VectorRegister a, VectorRegister b);
1851   // Vector Floating-Point not implemented yet
1852   inline void mtvscr(   VectorRegister b);
1853   inline void mfvscr(   VectorRegister d);
1854 
1855   // The following encoders use r0 as second operand. These instructions
1856   // read r0 as '0'.
1857   inline void lwzx( Register d, Register s2);
1858   inline void lwz(  Register d, int si16);
1859   inline void lwax( Register d, Register s2);
1860   inline void lwa(  Register d, int si16);
1861   inline void lhzx( Register d, Register s2);
1862   inline void lhz(  Register d, int si16);
1863   inline void lhax( Register d, Register s2);
1864   inline void lha(  Register d, int si16);
1865   inline void lbzx( Register d, Register s2);
1866   inline void lbz(  Register d, int si16);
1867   inline void ldx(  Register d, Register s2);
1868   inline void ld(   Register d, int si16);
1869   inline void stwx( Register d, Register s2);
1870   inline void stw(  Register d, int si16);
1871   inline void sthx( Register d, Register s2);
1872   inline void sth(  Register d, int si16);
1873   inline void stbx( Register d, Register s2);
1874   inline void stb(  Register d, int si16);
1875   inline void stdx( Register d, Register s2);
1876   inline void std(  Register d, int si16);
1877 
1878   // PPC 2, section 3.2.1 Instruction Cache Instructions
1879   inline void icbi(    Register s2);
1880   // PPC 2, section 3.2.2 Data Cache Instructions
1881   //inlinevoid dcba(   Register s2); // Instruction for embedded processor only.
1882   inline void dcbz(    Register s2);
1883   inline void dcbst(   Register s2);
1884   inline void dcbf(    Register s2);
1885   // dcache read hint
1886   inline void dcbt(    Register s2);
1887   inline void dcbtct(  Register s2, int ct);
1888   inline void dcbtds(  Register s2, int ds);
1889   // dcache write hint
1890   inline void dcbtst(  Register s2);
1891   inline void dcbtstct(Register s2, int ct);
1892 
1893   // Atomics: use ra0mem to disallow R0 as base.
1894   inline void lwarx_unchecked(Register d, Register b, int eh1);
1895   inline void ldarx_unchecked(Register d, Register b, int eh1);
1896   inline void lwarx( Register d, Register b, bool hint_exclusive_access);
1897   inline void ldarx( Register d, Register b, bool hint_exclusive_access);
1898   inline void stwcx_(Register s, Register b);
1899   inline void stdcx_(Register s, Register b);
1900   inline void lfs(   FloatRegister d, int si16);
1901   inline void lfsx(  FloatRegister d, Register b);
1902   inline void lfd(   FloatRegister d, int si16);
1903   inline void lfdx(  FloatRegister d, Register b);
1904   inline void stfs(  FloatRegister s, int si16);
1905   inline void stfsx( FloatRegister s, Register b);
1906   inline void stfd(  FloatRegister s, int si16);
1907   inline void stfdx( FloatRegister s, Register b);
1908   inline void lvebx( VectorRegister d, Register s2);
1909   inline void lvehx( VectorRegister d, Register s2);
1910   inline void lvewx( VectorRegister d, Register s2);
1911   inline void lvx(   VectorRegister d, Register s2);
1912   inline void lvxl(  VectorRegister d, Register s2);
1913   inline void stvebx(VectorRegister d, Register s2);
1914   inline void stvehx(VectorRegister d, Register s2);
1915   inline void stvewx(VectorRegister d, Register s2);
1916   inline void stvx(  VectorRegister d, Register s2);
1917   inline void stvxl( VectorRegister d, Register s2);
1918   inline void lvsl(  VectorRegister d, Register s2);
1919   inline void lvsr(  VectorRegister d, Register s2);
1920 
1921   // RegisterOrConstant versions.
1922   // These emitters choose between the versions using two registers and
1923   // those with register and immediate, depending on the content of roc.
1924   // If the constant is not encodable as immediate, instructions to
1925   // load the constant are emitted beforehand. Store instructions need a
1926   // tmp reg if the constant is not encodable as immediate.
1927   // Size unpredictable.
1928   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
1929   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
1930   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1931   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
1932   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1933   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1934   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1935   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1936   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1937   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1938   void add( Register d, RegisterOrConstant roc, Register s1);
1939   void subf(Register d, RegisterOrConstant roc, Register s1);
1940   void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
1941 
1942 
1943   // Emit several instructions to load a 64 bit constant. This issues a fixed
1944   // instruction pattern so that the constant can be patched later on.
1945   enum {
1946     load_const_size = 5 * BytesPerInstWord
1947   };
1948          void load_const(Register d, long a,            Register tmp = noreg);
1949   inline void load_const(Register d, void* a,           Register tmp = noreg);
1950   inline void load_const(Register d, Label& L,          Register tmp = noreg);
1951   inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
1952 
1953   // Load a 64 bit constant, optimized, not identifyable.
1954   // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
1955   // 16 bit immediate offset. This is useful if the offset can be encoded in
1956   // a succeeding instruction.
1957          int load_const_optimized(Register d, long a,  Register tmp = noreg, bool return_simm16_rest = false);
1958   inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
1959     return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
1960   }
1961 
1962   // Creation
1963   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1964 #ifdef CHECK_DELAY
1965     delay_state = no_delay;
1966 #endif
1967   }
1968 
1969   // Testing
1970 #ifndef PRODUCT
1971   void test_asm();
1972 #endif
1973 };
1974 
1975 
1976 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP