281 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
282 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
283 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
284 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
285 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
286 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
287
288 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
289 BXX_OPCODE = (18u << OPCODE_SHIFT),
290 BCXX_OPCODE = (16u << OPCODE_SHIFT),
291
292 // CTR-related opcodes
293 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
294 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
295 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
296
297
298 LWZ_OPCODE = (32u << OPCODE_SHIFT),
299 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
300 LWZU_OPCODE = (33u << OPCODE_SHIFT),
301
302 LHA_OPCODE = (42u << OPCODE_SHIFT),
303 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
304 LHAU_OPCODE = (43u << OPCODE_SHIFT),
305
306 LHZ_OPCODE = (40u << OPCODE_SHIFT),
307 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
308 LHZU_OPCODE = (41u << OPCODE_SHIFT),
309
310 LBZ_OPCODE = (34u << OPCODE_SHIFT),
311 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
312 LBZU_OPCODE = (35u << OPCODE_SHIFT),
313
314 STW_OPCODE = (36u << OPCODE_SHIFT),
315 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
316 STWU_OPCODE = (37u << OPCODE_SHIFT),
317 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
318
319 STH_OPCODE = (44u << OPCODE_SHIFT),
320 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
321 STHU_OPCODE = (45u << OPCODE_SHIFT),
322
323 STB_OPCODE = (38u << OPCODE_SHIFT),
324 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
325 STBU_OPCODE = (39u << OPCODE_SHIFT),
326
327 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
328 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
1347 inline void rldicl( Register a, Register s, int sh6, int mb6);
1348 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1349 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1350 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1351 inline void rldimi( Register a, Register s, int sh6, int mb6);
1352 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1353 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1354 inline void insrdi( Register a, Register s, int n, int b);
1355 inline void insrwi( Register a, Register s, int n, int b);
1356
1357 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1358 // 4 bytes
1359 inline void lwzx( Register d, Register s1, Register s2);
1360 inline void lwz( Register d, int si16, Register s1);
1361 inline void lwzu( Register d, int si16, Register s1);
1362
1363 // 4 bytes
1364 inline void lwax( Register d, Register s1, Register s2);
1365 inline void lwa( Register d, int si16, Register s1);
1366
1367 // 2 bytes
1368 inline void lhzx( Register d, Register s1, Register s2);
1369 inline void lhz( Register d, int si16, Register s1);
1370 inline void lhzu( Register d, int si16, Register s1);
1371
1372 // 2 bytes
1373 inline void lhax( Register d, Register s1, Register s2);
1374 inline void lha( Register d, int si16, Register s1);
1375 inline void lhau( Register d, int si16, Register s1);
1376
1377 // 1 byte
1378 inline void lbzx( Register d, Register s1, Register s2);
1379 inline void lbz( Register d, int si16, Register s1);
1380 inline void lbzu( Register d, int si16, Register s1);
1381
1382 // 8 bytes
1383 inline void ldx( Register d, Register s1, Register s2);
1384 inline void ld( Register d, int si16, Register s1);
1385 inline void ldu( Register d, int si16, Register s1);
1386
1387 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1388 inline void stwx( Register d, Register s1, Register s2);
1389 inline void stw( Register d, int si16, Register s1);
1390 inline void stwu( Register d, int si16, Register s1);
1391
1841 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1842 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1843 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1844 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1845 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1846 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1847 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1848 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1849 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1850 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1851 // Vector Floating-Point not implemented yet
1852 inline void mtvscr( VectorRegister b);
1853 inline void mfvscr( VectorRegister d);
1854
1855 // The following encoders use r0 as second operand. These instructions
1856 // read r0 as '0'.
1857 inline void lwzx( Register d, Register s2);
1858 inline void lwz( Register d, int si16);
1859 inline void lwax( Register d, Register s2);
1860 inline void lwa( Register d, int si16);
1861 inline void lhzx( Register d, Register s2);
1862 inline void lhz( Register d, int si16);
1863 inline void lhax( Register d, Register s2);
1864 inline void lha( Register d, int si16);
1865 inline void lbzx( Register d, Register s2);
1866 inline void lbz( Register d, int si16);
1867 inline void ldx( Register d, Register s2);
1868 inline void ld( Register d, int si16);
1869 inline void stwx( Register d, Register s2);
1870 inline void stw( Register d, int si16);
1871 inline void sthx( Register d, Register s2);
1872 inline void sth( Register d, int si16);
1873 inline void stbx( Register d, Register s2);
1874 inline void stb( Register d, int si16);
1875 inline void stdx( Register d, Register s2);
1876 inline void std( Register d, int si16);
1877
1878 // PPC 2, section 3.2.1 Instruction Cache Instructions
1879 inline void icbi( Register s2);
1880 // PPC 2, section 3.2.2 Data Cache Instructions
1881 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
1882 inline void dcbz( Register s2);
1883 inline void dcbst( Register s2);
1884 inline void dcbf( Register s2);
|
281 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
282 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
283 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
284 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
285 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
286 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
287
288 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
289 BXX_OPCODE = (18u << OPCODE_SHIFT),
290 BCXX_OPCODE = (16u << OPCODE_SHIFT),
291
292 // CTR-related opcodes
293 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
294 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
295 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
296
297
298 LWZ_OPCODE = (32u << OPCODE_SHIFT),
299 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
300 LWZU_OPCODE = (33u << OPCODE_SHIFT),
301 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
302
303 LHA_OPCODE = (42u << OPCODE_SHIFT),
304 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
305 LHAU_OPCODE = (43u << OPCODE_SHIFT),
306
307 LHZ_OPCODE = (40u << OPCODE_SHIFT),
308 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
309 LHZU_OPCODE = (41u << OPCODE_SHIFT),
310 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
311
312 LBZ_OPCODE = (34u << OPCODE_SHIFT),
313 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
314 LBZU_OPCODE = (35u << OPCODE_SHIFT),
315
316 STW_OPCODE = (36u << OPCODE_SHIFT),
317 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
318 STWU_OPCODE = (37u << OPCODE_SHIFT),
319 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
320
321 STH_OPCODE = (44u << OPCODE_SHIFT),
322 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
323 STHU_OPCODE = (45u << OPCODE_SHIFT),
324
325 STB_OPCODE = (38u << OPCODE_SHIFT),
326 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
327 STBU_OPCODE = (39u << OPCODE_SHIFT),
328
329 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
330 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
1349 inline void rldicl( Register a, Register s, int sh6, int mb6);
1350 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1351 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1352 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1353 inline void rldimi( Register a, Register s, int sh6, int mb6);
1354 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1355 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1356 inline void insrdi( Register a, Register s, int n, int b);
1357 inline void insrwi( Register a, Register s, int n, int b);
1358
1359 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1360 // 4 bytes
1361 inline void lwzx( Register d, Register s1, Register s2);
1362 inline void lwz( Register d, int si16, Register s1);
1363 inline void lwzu( Register d, int si16, Register s1);
1364
1365 // 4 bytes
1366 inline void lwax( Register d, Register s1, Register s2);
1367 inline void lwa( Register d, int si16, Register s1);
1368
1369 // 4 bytes reversed
1370 inline void lwbrx( Register d, Register s1, Register s2);
1371
1372 // 2 bytes
1373 inline void lhzx( Register d, Register s1, Register s2);
1374 inline void lhz( Register d, int si16, Register s1);
1375 inline void lhzu( Register d, int si16, Register s1);
1376
1377 // 2 bytes reversed
1378 inline void lhbrx( Register d, Register s1, Register s2);
1379
1380 // 2 bytes
1381 inline void lhax( Register d, Register s1, Register s2);
1382 inline void lha( Register d, int si16, Register s1);
1383 inline void lhau( Register d, int si16, Register s1);
1384
1385 // 1 byte
1386 inline void lbzx( Register d, Register s1, Register s2);
1387 inline void lbz( Register d, int si16, Register s1);
1388 inline void lbzu( Register d, int si16, Register s1);
1389
1390 // 8 bytes
1391 inline void ldx( Register d, Register s1, Register s2);
1392 inline void ld( Register d, int si16, Register s1);
1393 inline void ldu( Register d, int si16, Register s1);
1394
1395 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1396 inline void stwx( Register d, Register s1, Register s2);
1397 inline void stw( Register d, int si16, Register s1);
1398 inline void stwu( Register d, int si16, Register s1);
1399
1849 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1850 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1851 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1852 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1853 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1854 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1855 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1856 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1857 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1858 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1859 // Vector Floating-Point not implemented yet
1860 inline void mtvscr( VectorRegister b);
1861 inline void mfvscr( VectorRegister d);
1862
1863 // The following encoders use r0 as second operand. These instructions
1864 // read r0 as '0'.
1865 inline void lwzx( Register d, Register s2);
1866 inline void lwz( Register d, int si16);
1867 inline void lwax( Register d, Register s2);
1868 inline void lwa( Register d, int si16);
1869 inline void lwbrx(Register d, Register s2);
1870 inline void lhzx( Register d, Register s2);
1871 inline void lhz( Register d, int si16);
1872 inline void lhax( Register d, Register s2);
1873 inline void lha( Register d, int si16);
1874 inline void lhbrx(Register d, Register s2);
1875 inline void lbzx( Register d, Register s2);
1876 inline void lbz( Register d, int si16);
1877 inline void ldx( Register d, Register s2);
1878 inline void ld( Register d, int si16);
1879 inline void stwx( Register d, Register s2);
1880 inline void stw( Register d, int si16);
1881 inline void sthx( Register d, Register s2);
1882 inline void sth( Register d, int si16);
1883 inline void stbx( Register d, Register s2);
1884 inline void stb( Register d, int si16);
1885 inline void stdx( Register d, Register s2);
1886 inline void std( Register d, int si16);
1887
1888 // PPC 2, section 3.2.1 Instruction Cache Instructions
1889 inline void icbi( Register s2);
1890 // PPC 2, section 3.2.2 Data Cache Instructions
1891 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
1892 inline void dcbz( Register s2);
1893 inline void dcbst( Register s2);
1894 inline void dcbf( Register s2);
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