1 /*
   2  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright 2012, 2013 SAP AG. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
  27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 // Address is an abstraction used to represent a memory location
  32 // as used in assembler instructions.
  33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
  34 // So far we do not use this as simplification by this class is low
  35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
  36 // represent an offset.
  37 class Address VALUE_OBJ_CLASS_SPEC {
  38 };
  39 
  40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
  41  private:
  42   address          _address;
  43   RelocationHolder _rspec;
  44 
  45   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
  46     switch (rtype) {
  47     case relocInfo::external_word_type:
  48       return external_word_Relocation::spec(addr);
  49     case relocInfo::internal_word_type:
  50       return internal_word_Relocation::spec(addr);
  51     case relocInfo::opt_virtual_call_type:
  52       return opt_virtual_call_Relocation::spec();
  53     case relocInfo::static_call_type:
  54       return static_call_Relocation::spec();
  55     case relocInfo::runtime_call_type:
  56       return runtime_call_Relocation::spec();
  57     case relocInfo::none:
  58       return RelocationHolder();
  59     default:
  60       ShouldNotReachHere();
  61       return RelocationHolder();
  62     }
  63   }
  64 
  65  protected:
  66   // creation
  67   AddressLiteral() : _address(NULL), _rspec(NULL) {}
  68 
  69  public:
  70   AddressLiteral(address addr, RelocationHolder const& rspec)
  71     : _address(addr),
  72       _rspec(rspec) {}
  73 
  74   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
  75     : _address((address) addr),
  76       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
  77 
  78   AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
  79     : _address((address) addr),
  80       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
  81 
  82   intptr_t value() const { return (intptr_t) _address; }
  83 
  84   const RelocationHolder& rspec() const { return _rspec; }
  85 };
  86 
  87 // Argument is an abstraction used to represent an outgoing
  88 // actual argument or an incoming formal parameter, whether
  89 // it resides in memory or in a register, in a manner consistent
  90 // with the PPC Application Binary Interface, or ABI. This is
  91 // often referred to as the native or C calling convention.
  92 
  93 class Argument VALUE_OBJ_CLASS_SPEC {
  94  private:
  95   int _number;  // The number of the argument.
  96  public:
  97   enum {
  98     // Only 8 registers may contain integer parameters.
  99     n_register_parameters = 8,
 100     // Can have up to 8 floating registers.
 101     n_float_register_parameters = 8,
 102 
 103     // PPC C calling conventions.
 104     // The first eight arguments are passed in int regs if they are int.
 105     n_int_register_parameters_c = 8,
 106     // The first thirteen float arguments are passed in float regs.
 107     n_float_register_parameters_c = 13,
 108     // Only the first 8 parameters are not placed on the stack. Aix disassembly
 109     // shows that xlC places all float args after argument 8 on the stack AND
 110     // in a register. This is not documented, but we follow this convention, too.
 111     n_regs_not_on_stack_c = 8,
 112   };
 113   // creation
 114   Argument(int number) : _number(number) {}
 115 
 116   int  number() const { return _number; }
 117 
 118   // Locating register-based arguments:
 119   bool is_register() const { return _number < n_register_parameters; }
 120 
 121   Register as_register() const {
 122     assert(is_register(), "must be a register argument");
 123     return as_Register(number() + R3_ARG1->encoding());
 124   }
 125 };
 126 
 127 #if !defined(ABI_ELFv2)
 128 // A ppc64 function descriptor.
 129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
 130  private:
 131   address _entry;
 132   address _toc;
 133   address _env;
 134 
 135  public:
 136   inline address entry() const { return _entry; }
 137   inline address toc()   const { return _toc; }
 138   inline address env()   const { return _env; }
 139 
 140   inline void set_entry(address entry) { _entry = entry; }
 141   inline void set_toc(  address toc)   { _toc   = toc; }
 142   inline void set_env(  address env)   { _env   = env; }
 143 
 144   inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
 145   inline static ByteSize toc_offset()   { return byte_offset_of(FunctionDescriptor, _toc); }
 146   inline static ByteSize env_offset()   { return byte_offset_of(FunctionDescriptor, _env); }
 147 
 148   // Friend functions can be called without loading toc and env.
 149   enum {
 150     friend_toc = 0xcafe,
 151     friend_env = 0xc0de
 152   };
 153 
 154   inline bool is_friend_function() const {
 155     return (toc() == (address) friend_toc) && (env() == (address) friend_env);
 156   }
 157 
 158   // Constructor for stack-allocated instances.
 159   FunctionDescriptor() {
 160     _entry = (address) 0xbad;
 161     _toc   = (address) 0xbad;
 162     _env   = (address) 0xbad;
 163   }
 164 };
 165 #endif
 166 
 167 class Assembler : public AbstractAssembler {
 168  protected:
 169   // Displacement routines
 170   static void print_instruction(int inst);
 171   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 172   static int  branch_destination(int inst, int pos);
 173 
 174   friend class AbstractAssembler;
 175 
 176   // Code patchers need various routines like inv_wdisp()
 177   friend class NativeInstruction;
 178   friend class NativeGeneralJump;
 179   friend class Relocation;
 180 
 181  public:
 182 
 183   enum shifts {
 184     XO_21_29_SHIFT = 2,
 185     XO_21_30_SHIFT = 1,
 186     XO_27_29_SHIFT = 2,
 187     XO_30_31_SHIFT = 0,
 188     SPR_5_9_SHIFT  = 11u, // SPR_5_9 field in bits 11 -- 15
 189     SPR_0_4_SHIFT  = 16u, // SPR_0_4 field in bits 16 -- 20
 190     RS_SHIFT       = 21u, // RS field in bits 21 -- 25
 191     OPCODE_SHIFT   = 26u, // opcode in bits 26 -- 31
 192   };
 193 
 194   enum opcdxos_masks {
 195     XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
 196     ADDI_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 197     ADDIS_OPCODE_MASK   = (63u << OPCODE_SHIFT),
 198     BXX_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 199     BCXX_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 200     // trap instructions
 201     TDI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 202     TWI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 203     TD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
 204     TW_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
 205     LD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
 206     STD_OPCODE_MASK     = LD_OPCODE_MASK,
 207     STDU_OPCODE_MASK    = STD_OPCODE_MASK,
 208     STDX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
 209     STDUX_OPCODE_MASK   = STDX_OPCODE_MASK,
 210     STW_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 211     STWU_OPCODE_MASK    = STW_OPCODE_MASK,
 212     STWX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
 213     STWUX_OPCODE_MASK   = STWX_OPCODE_MASK,
 214     MTCTR_OPCODE_MASK   = ~(31u << RS_SHIFT),
 215     ORI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
 216     ORIS_OPCODE_MASK    = (63u << OPCODE_SHIFT),
 217     RLDICR_OPCODE_MASK  = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
 218   };
 219 
 220   enum opcdxos {
 221     ADD_OPCODE    = (31u << OPCODE_SHIFT | 266u << 1),
 222     ADDC_OPCODE   = (31u << OPCODE_SHIFT |  10u << 1),
 223     ADDI_OPCODE   = (14u << OPCODE_SHIFT),
 224     ADDIS_OPCODE  = (15u << OPCODE_SHIFT),
 225     ADDIC__OPCODE = (13u << OPCODE_SHIFT),
 226     ADDE_OPCODE   = (31u << OPCODE_SHIFT | 138u << 1),
 227     SUBF_OPCODE   = (31u << OPCODE_SHIFT |  40u << 1),
 228     SUBFC_OPCODE  = (31u << OPCODE_SHIFT |   8u << 1),
 229     SUBFE_OPCODE  = (31u << OPCODE_SHIFT | 136u << 1),
 230     SUBFIC_OPCODE = (8u  << OPCODE_SHIFT),
 231     SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
 232     DIVW_OPCODE   = (31u << OPCODE_SHIFT | 491u << 1),
 233     MULLW_OPCODE  = (31u << OPCODE_SHIFT | 235u << 1),
 234     MULHW_OPCODE  = (31u << OPCODE_SHIFT |  75u << 1),
 235     MULHWU_OPCODE = (31u << OPCODE_SHIFT |  11u << 1),
 236     MULLI_OPCODE  = (7u  << OPCODE_SHIFT),
 237     AND_OPCODE    = (31u << OPCODE_SHIFT |  28u << 1),
 238     ANDI_OPCODE   = (28u << OPCODE_SHIFT),
 239     ANDIS_OPCODE  = (29u << OPCODE_SHIFT),
 240     ANDC_OPCODE   = (31u << OPCODE_SHIFT |  60u << 1),
 241     ORC_OPCODE    = (31u << OPCODE_SHIFT | 412u << 1),
 242     OR_OPCODE     = (31u << OPCODE_SHIFT | 444u << 1),
 243     ORI_OPCODE    = (24u << OPCODE_SHIFT),
 244     ORIS_OPCODE   = (25u << OPCODE_SHIFT),
 245     XOR_OPCODE    = (31u << OPCODE_SHIFT | 316u << 1),
 246     XORI_OPCODE   = (26u << OPCODE_SHIFT),
 247     XORIS_OPCODE  = (27u << OPCODE_SHIFT),
 248 
 249     NEG_OPCODE    = (31u << OPCODE_SHIFT | 104u << 1),
 250 
 251     RLWINM_OPCODE = (21u << OPCODE_SHIFT),
 252     CLRRWI_OPCODE = RLWINM_OPCODE,
 253     CLRLWI_OPCODE = RLWINM_OPCODE,
 254 
 255     RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
 256 
 257     SLW_OPCODE    = (31u << OPCODE_SHIFT |  24u << 1),
 258     SLWI_OPCODE   = RLWINM_OPCODE,
 259     SRW_OPCODE    = (31u << OPCODE_SHIFT | 536u << 1),
 260     SRWI_OPCODE   = RLWINM_OPCODE,
 261     SRAW_OPCODE   = (31u << OPCODE_SHIFT | 792u << 1),
 262     SRAWI_OPCODE  = (31u << OPCODE_SHIFT | 824u << 1),
 263 
 264     CMP_OPCODE    = (31u << OPCODE_SHIFT |   0u << 1),
 265     CMPI_OPCODE   = (11u << OPCODE_SHIFT),
 266     CMPL_OPCODE   = (31u << OPCODE_SHIFT |  32u << 1),
 267     CMPLI_OPCODE  = (10u << OPCODE_SHIFT),
 268 
 269     ISEL_OPCODE   = (31u << OPCODE_SHIFT |  15u << 1),
 270 
 271     // Special purpose registers
 272     MTSPR_OPCODE  = (31u << OPCODE_SHIFT | 467u << 1),
 273     MFSPR_OPCODE  = (31u << OPCODE_SHIFT | 339u << 1),
 274 
 275     MTXER_OPCODE  = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
 276     MFXER_OPCODE  = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
 277 
 278     MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
 279     MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
 280 
 281     MTLR_OPCODE   = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
 282     MFLR_OPCODE   = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
 283 
 284     MTCTR_OPCODE  = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
 285     MFCTR_OPCODE  = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
 286 
 287     MTTFHAR_OPCODE   = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT),
 288     MFTFHAR_OPCODE   = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT),
 289     MTTFIAR_OPCODE   = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT),
 290     MFTFIAR_OPCODE   = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT),
 291     MTTEXASR_OPCODE  = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT),
 292     MFTEXASR_OPCODE  = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT),
 293     MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT),
 294     MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT),
 295 
 296     MTVRSAVE_OPCODE  = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT),
 297     MFVRSAVE_OPCODE  = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT),
 298 
 299     MFTB_OPCODE   = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT),
 300 
 301     MTCRF_OPCODE  = (31u << OPCODE_SHIFT | 144u << 1),
 302     MFCR_OPCODE   = (31u << OPCODE_SHIFT | 19u << 1),
 303     MCRF_OPCODE   = (19u << OPCODE_SHIFT | 0u << 1),
 304 
 305     // condition register logic instructions
 306     CRAND_OPCODE  = (19u << OPCODE_SHIFT | 257u << 1),
 307     CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
 308     CROR_OPCODE   = (19u << OPCODE_SHIFT | 449u << 1),
 309     CRXOR_OPCODE  = (19u << OPCODE_SHIFT | 193u << 1),
 310     CRNOR_OPCODE  = (19u << OPCODE_SHIFT |  33u << 1),
 311     CREQV_OPCODE  = (19u << OPCODE_SHIFT | 289u << 1),
 312     CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
 313     CRORC_OPCODE  = (19u << OPCODE_SHIFT | 417u << 1),
 314 
 315     BCLR_OPCODE   = (19u << OPCODE_SHIFT | 16u << 1),
 316     BXX_OPCODE      = (18u << OPCODE_SHIFT),
 317     BCXX_OPCODE     = (16u << OPCODE_SHIFT),
 318 
 319     // CTR-related opcodes
 320     BCCTR_OPCODE  = (19u << OPCODE_SHIFT | 528u << 1),
 321 
 322     LWZ_OPCODE   = (32u << OPCODE_SHIFT),
 323     LWZX_OPCODE  = (31u << OPCODE_SHIFT |  23u << 1),
 324     LWZU_OPCODE  = (33u << OPCODE_SHIFT),
 325     LWBRX_OPCODE = (31u << OPCODE_SHIFT |  534 << 1),
 326 
 327     LHA_OPCODE   = (42u << OPCODE_SHIFT),
 328     LHAX_OPCODE  = (31u << OPCODE_SHIFT | 343u << 1),
 329     LHAU_OPCODE  = (43u << OPCODE_SHIFT),
 330 
 331     LHZ_OPCODE   = (40u << OPCODE_SHIFT),
 332     LHZX_OPCODE  = (31u << OPCODE_SHIFT | 279u << 1),
 333     LHZU_OPCODE  = (41u << OPCODE_SHIFT),
 334     LHBRX_OPCODE = (31u << OPCODE_SHIFT |  790 << 1),
 335 
 336     LBZ_OPCODE   = (34u << OPCODE_SHIFT),
 337     LBZX_OPCODE  = (31u << OPCODE_SHIFT |  87u << 1),
 338     LBZU_OPCODE  = (35u << OPCODE_SHIFT),
 339 
 340     STW_OPCODE   = (36u << OPCODE_SHIFT),
 341     STWX_OPCODE  = (31u << OPCODE_SHIFT | 151u << 1),
 342     STWU_OPCODE  = (37u << OPCODE_SHIFT),
 343     STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
 344 
 345     STH_OPCODE   = (44u << OPCODE_SHIFT),
 346     STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
 347     STHU_OPCODE  = (45u << OPCODE_SHIFT),
 348 
 349     STB_OPCODE   = (38u << OPCODE_SHIFT),
 350     STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
 351     STBU_OPCODE  = (39u << OPCODE_SHIFT),
 352 
 353     EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
 354     EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
 355     EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM
 356 
 357     // 32 bit opcode encodings
 358 
 359     LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM
 360     LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
 361 
 362     CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM
 363 
 364     // 64 bit opcode encodings
 365 
 366     LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 367     LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 368     LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
 369 
 370     STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 371     STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 372     STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),                  // X-FORM
 373     STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
 374 
 375     RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
 376     RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
 377     RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM
 378     RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM
 379 
 380     SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
 381 
 382     SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM
 383     SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM
 384     SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM
 385 
 386     MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM
 387     MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM
 388     MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM
 389     DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM
 390 
 391     CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM
 392     NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
 393     NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
 394 
 395 
 396     // opcodes only used for floating arithmetic
 397     FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),
 398     FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),
 399     FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),
 400     FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),
 401     FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),
 402     FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),
 403     // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
 404     // on Power7.  Do not use.
 405     // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),
 406     // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),
 407     CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),
 408     POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),
 409     POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),
 410     POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),
 411     FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),
 412     FNABS_OPCODE   = (63u << OPCODE_SHIFT |  136u << 1),
 413     FMUL_OPCODE    = (63u << OPCODE_SHIFT |   25u << 1),
 414     FMULS_OPCODE   = (59u << OPCODE_SHIFT |   25u << 1),
 415     FNEG_OPCODE    = (63u << OPCODE_SHIFT |   40u << 1),
 416     FSUB_OPCODE    = (63u << OPCODE_SHIFT |   20u << 1),
 417     FSUBS_OPCODE   = (59u << OPCODE_SHIFT |   20u << 1),
 418 
 419     // PPC64-internal FPU conversion opcodes
 420     FCFID_OPCODE   = (63u << OPCODE_SHIFT |  846u << 1),
 421     FCFIDS_OPCODE  = (59u << OPCODE_SHIFT |  846u << 1),
 422     FCTID_OPCODE   = (63u << OPCODE_SHIFT |  814u << 1),
 423     FCTIDZ_OPCODE  = (63u << OPCODE_SHIFT |  815u << 1),
 424     FCTIW_OPCODE   = (63u << OPCODE_SHIFT |   14u << 1),
 425     FCTIWZ_OPCODE  = (63u << OPCODE_SHIFT |   15u << 1),
 426     FRSP_OPCODE    = (63u << OPCODE_SHIFT |   12u << 1),
 427 
 428     // WARNING: using fmadd results in a non-compliant vm. Some floating
 429     // point tck tests will fail.
 430     FMADD_OPCODE   = (59u << OPCODE_SHIFT |   29u << 1),
 431     DMADD_OPCODE   = (63u << OPCODE_SHIFT |   29u << 1),
 432     FMSUB_OPCODE   = (59u << OPCODE_SHIFT |   28u << 1),
 433     DMSUB_OPCODE   = (63u << OPCODE_SHIFT |   28u << 1),
 434     FNMADD_OPCODE  = (59u << OPCODE_SHIFT |   31u << 1),
 435     DNMADD_OPCODE  = (63u << OPCODE_SHIFT |   31u << 1),
 436     FNMSUB_OPCODE  = (59u << OPCODE_SHIFT |   30u << 1),
 437     DNMSUB_OPCODE  = (63u << OPCODE_SHIFT |   30u << 1),
 438 
 439     LFD_OPCODE     = (50u << OPCODE_SHIFT |   00u << 1),
 440     LFDU_OPCODE    = (51u << OPCODE_SHIFT |   00u << 1),
 441     LFDX_OPCODE    = (31u << OPCODE_SHIFT |  599u << 1),
 442     LFS_OPCODE     = (48u << OPCODE_SHIFT |   00u << 1),
 443     LFSU_OPCODE    = (49u << OPCODE_SHIFT |   00u << 1),
 444     LFSX_OPCODE    = (31u << OPCODE_SHIFT |  535u << 1),
 445 
 446     STFD_OPCODE    = (54u << OPCODE_SHIFT |   00u << 1),
 447     STFDU_OPCODE   = (55u << OPCODE_SHIFT |   00u << 1),
 448     STFDX_OPCODE   = (31u << OPCODE_SHIFT |  727u << 1),
 449     STFS_OPCODE    = (52u << OPCODE_SHIFT |   00u << 1),
 450     STFSU_OPCODE   = (53u << OPCODE_SHIFT |   00u << 1),
 451     STFSX_OPCODE   = (31u << OPCODE_SHIFT |  663u << 1),
 452 
 453     FSQRT_OPCODE   = (63u << OPCODE_SHIFT |   22u << 1),            // A-FORM
 454     FSQRTS_OPCODE  = (59u << OPCODE_SHIFT |   22u << 1),            // A-FORM
 455 
 456     // Vector instruction support for >= Power6
 457     // Vector Storage Access
 458     LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),
 459     LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),
 460     LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),
 461     LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),
 462     LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),
 463     STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),
 464     STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),
 465     STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),
 466     STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),
 467     STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),
 468     LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),
 469     LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
 470 
 471     // Vector Permute and Formatting
 472     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
 473     VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
 474     VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
 475     VPKSHUS_OPCODE = (4u  << OPCODE_SHIFT |  270u     ),
 476     VPKSWUS_OPCODE = (4u  << OPCODE_SHIFT |  334u     ),
 477     VPKUHUM_OPCODE = (4u  << OPCODE_SHIFT |   14u     ),
 478     VPKUWUM_OPCODE = (4u  << OPCODE_SHIFT |   78u     ),
 479     VPKUHUS_OPCODE = (4u  << OPCODE_SHIFT |  142u     ),
 480     VPKUWUS_OPCODE = (4u  << OPCODE_SHIFT |  206u     ),
 481     VUPKHPX_OPCODE = (4u  << OPCODE_SHIFT |  846u     ),
 482     VUPKHSB_OPCODE = (4u  << OPCODE_SHIFT |  526u     ),
 483     VUPKHSH_OPCODE = (4u  << OPCODE_SHIFT |  590u     ),
 484     VUPKLPX_OPCODE = (4u  << OPCODE_SHIFT |  974u     ),
 485     VUPKLSB_OPCODE = (4u  << OPCODE_SHIFT |  654u     ),
 486     VUPKLSH_OPCODE = (4u  << OPCODE_SHIFT |  718u     ),
 487 
 488     VMRGHB_OPCODE  = (4u  << OPCODE_SHIFT |   12u     ),
 489     VMRGHW_OPCODE  = (4u  << OPCODE_SHIFT |  140u     ),
 490     VMRGHH_OPCODE  = (4u  << OPCODE_SHIFT |   76u     ),
 491     VMRGLB_OPCODE  = (4u  << OPCODE_SHIFT |  268u     ),
 492     VMRGLW_OPCODE  = (4u  << OPCODE_SHIFT |  396u     ),
 493     VMRGLH_OPCODE  = (4u  << OPCODE_SHIFT |  332u     ),
 494 
 495     VSPLT_OPCODE   = (4u  << OPCODE_SHIFT |  524u     ),
 496     VSPLTH_OPCODE  = (4u  << OPCODE_SHIFT |  588u     ),
 497     VSPLTW_OPCODE  = (4u  << OPCODE_SHIFT |  652u     ),
 498     VSPLTISB_OPCODE= (4u  << OPCODE_SHIFT |  780u     ),
 499     VSPLTISH_OPCODE= (4u  << OPCODE_SHIFT |  844u     ),
 500     VSPLTISW_OPCODE= (4u  << OPCODE_SHIFT |  908u     ),
 501 
 502     VPERM_OPCODE   = (4u  << OPCODE_SHIFT |   43u     ),
 503     VSEL_OPCODE    = (4u  << OPCODE_SHIFT |   42u     ),
 504 
 505     VSL_OPCODE     = (4u  << OPCODE_SHIFT |  452u     ),
 506     VSLDOI_OPCODE  = (4u  << OPCODE_SHIFT |   44u     ),
 507     VSLO_OPCODE    = (4u  << OPCODE_SHIFT | 1036u     ),
 508     VSR_OPCODE     = (4u  << OPCODE_SHIFT |  708u     ),
 509     VSRO_OPCODE    = (4u  << OPCODE_SHIFT | 1100u     ),
 510 
 511     // Vector Integer
 512     VADDCUW_OPCODE = (4u  << OPCODE_SHIFT |  384u     ),
 513     VADDSHS_OPCODE = (4u  << OPCODE_SHIFT |  832u     ),
 514     VADDSBS_OPCODE = (4u  << OPCODE_SHIFT |  768u     ),
 515     VADDSWS_OPCODE = (4u  << OPCODE_SHIFT |  896u     ),
 516     VADDUBM_OPCODE = (4u  << OPCODE_SHIFT |    0u     ),
 517     VADDUWM_OPCODE = (4u  << OPCODE_SHIFT |  128u     ),
 518     VADDUHM_OPCODE = (4u  << OPCODE_SHIFT |   64u     ),
 519     VADDUBS_OPCODE = (4u  << OPCODE_SHIFT |  512u     ),
 520     VADDUWS_OPCODE = (4u  << OPCODE_SHIFT |  640u     ),
 521     VADDUHS_OPCODE = (4u  << OPCODE_SHIFT |  576u     ),
 522     VSUBCUW_OPCODE = (4u  << OPCODE_SHIFT | 1408u     ),
 523     VSUBSHS_OPCODE = (4u  << OPCODE_SHIFT | 1856u     ),
 524     VSUBSBS_OPCODE = (4u  << OPCODE_SHIFT | 1792u     ),
 525     VSUBSWS_OPCODE = (4u  << OPCODE_SHIFT | 1920u     ),
 526     VSUBUBM_OPCODE = (4u  << OPCODE_SHIFT | 1024u     ),
 527     VSUBUWM_OPCODE = (4u  << OPCODE_SHIFT | 1152u     ),
 528     VSUBUHM_OPCODE = (4u  << OPCODE_SHIFT | 1088u     ),
 529     VSUBUBS_OPCODE = (4u  << OPCODE_SHIFT | 1536u     ),
 530     VSUBUWS_OPCODE = (4u  << OPCODE_SHIFT | 1664u     ),
 531     VSUBUHS_OPCODE = (4u  << OPCODE_SHIFT | 1600u     ),
 532 
 533     VMULESB_OPCODE = (4u  << OPCODE_SHIFT |  776u     ),
 534     VMULEUB_OPCODE = (4u  << OPCODE_SHIFT |  520u     ),
 535     VMULESH_OPCODE = (4u  << OPCODE_SHIFT |  840u     ),
 536     VMULEUH_OPCODE = (4u  << OPCODE_SHIFT |  584u     ),
 537     VMULOSB_OPCODE = (4u  << OPCODE_SHIFT |  264u     ),
 538     VMULOUB_OPCODE = (4u  << OPCODE_SHIFT |    8u     ),
 539     VMULOSH_OPCODE = (4u  << OPCODE_SHIFT |  328u     ),
 540     VMULOUH_OPCODE = (4u  << OPCODE_SHIFT |   72u     ),
 541     VMHADDSHS_OPCODE=(4u  << OPCODE_SHIFT |   32u     ),
 542     VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT |   33u     ),
 543     VMLADDUHM_OPCODE=(4u  << OPCODE_SHIFT |   34u     ),
 544     VMSUBUHM_OPCODE= (4u  << OPCODE_SHIFT |   36u     ),
 545     VMSUMMBM_OPCODE= (4u  << OPCODE_SHIFT |   37u     ),
 546     VMSUMSHM_OPCODE= (4u  << OPCODE_SHIFT |   40u     ),
 547     VMSUMSHS_OPCODE= (4u  << OPCODE_SHIFT |   41u     ),
 548     VMSUMUHM_OPCODE= (4u  << OPCODE_SHIFT |   38u     ),
 549     VMSUMUHS_OPCODE= (4u  << OPCODE_SHIFT |   39u     ),
 550 
 551     VSUMSWS_OPCODE = (4u  << OPCODE_SHIFT | 1928u     ),
 552     VSUM2SWS_OPCODE= (4u  << OPCODE_SHIFT | 1672u     ),
 553     VSUM4SBS_OPCODE= (4u  << OPCODE_SHIFT | 1800u     ),
 554     VSUM4UBS_OPCODE= (4u  << OPCODE_SHIFT | 1544u     ),
 555     VSUM4SHS_OPCODE= (4u  << OPCODE_SHIFT | 1608u     ),
 556 
 557     VAVGSB_OPCODE  = (4u  << OPCODE_SHIFT | 1282u     ),
 558     VAVGSW_OPCODE  = (4u  << OPCODE_SHIFT | 1410u     ),
 559     VAVGSH_OPCODE  = (4u  << OPCODE_SHIFT | 1346u     ),
 560     VAVGUB_OPCODE  = (4u  << OPCODE_SHIFT | 1026u     ),
 561     VAVGUW_OPCODE  = (4u  << OPCODE_SHIFT | 1154u     ),
 562     VAVGUH_OPCODE  = (4u  << OPCODE_SHIFT | 1090u     ),
 563 
 564     VMAXSB_OPCODE  = (4u  << OPCODE_SHIFT |  258u     ),
 565     VMAXSW_OPCODE  = (4u  << OPCODE_SHIFT |  386u     ),
 566     VMAXSH_OPCODE  = (4u  << OPCODE_SHIFT |  322u     ),
 567     VMAXUB_OPCODE  = (4u  << OPCODE_SHIFT |    2u     ),
 568     VMAXUW_OPCODE  = (4u  << OPCODE_SHIFT |  130u     ),
 569     VMAXUH_OPCODE  = (4u  << OPCODE_SHIFT |   66u     ),
 570     VMINSB_OPCODE  = (4u  << OPCODE_SHIFT |  770u     ),
 571     VMINSW_OPCODE  = (4u  << OPCODE_SHIFT |  898u     ),
 572     VMINSH_OPCODE  = (4u  << OPCODE_SHIFT |  834u     ),
 573     VMINUB_OPCODE  = (4u  << OPCODE_SHIFT |  514u     ),
 574     VMINUW_OPCODE  = (4u  << OPCODE_SHIFT |  642u     ),
 575     VMINUH_OPCODE  = (4u  << OPCODE_SHIFT |  578u     ),
 576 
 577     VCMPEQUB_OPCODE= (4u  << OPCODE_SHIFT |    6u     ),
 578     VCMPEQUH_OPCODE= (4u  << OPCODE_SHIFT |   70u     ),
 579     VCMPEQUW_OPCODE= (4u  << OPCODE_SHIFT |  134u     ),
 580     VCMPGTSH_OPCODE= (4u  << OPCODE_SHIFT |  838u     ),
 581     VCMPGTSB_OPCODE= (4u  << OPCODE_SHIFT |  774u     ),
 582     VCMPGTSW_OPCODE= (4u  << OPCODE_SHIFT |  902u     ),
 583     VCMPGTUB_OPCODE= (4u  << OPCODE_SHIFT |  518u     ),
 584     VCMPGTUH_OPCODE= (4u  << OPCODE_SHIFT |  582u     ),
 585     VCMPGTUW_OPCODE= (4u  << OPCODE_SHIFT |  646u     ),
 586 
 587     VAND_OPCODE    = (4u  << OPCODE_SHIFT | 1028u     ),
 588     VANDC_OPCODE   = (4u  << OPCODE_SHIFT | 1092u     ),
 589     VNOR_OPCODE    = (4u  << OPCODE_SHIFT | 1284u     ),
 590     VOR_OPCODE     = (4u  << OPCODE_SHIFT | 1156u     ),
 591     VXOR_OPCODE    = (4u  << OPCODE_SHIFT | 1220u     ),
 592     VRLB_OPCODE    = (4u  << OPCODE_SHIFT |    4u     ),
 593     VRLW_OPCODE    = (4u  << OPCODE_SHIFT |  132u     ),
 594     VRLH_OPCODE    = (4u  << OPCODE_SHIFT |   68u     ),
 595     VSLB_OPCODE    = (4u  << OPCODE_SHIFT |  260u     ),
 596     VSKW_OPCODE    = (4u  << OPCODE_SHIFT |  388u     ),
 597     VSLH_OPCODE    = (4u  << OPCODE_SHIFT |  324u     ),
 598     VSRB_OPCODE    = (4u  << OPCODE_SHIFT |  516u     ),
 599     VSRW_OPCODE    = (4u  << OPCODE_SHIFT |  644u     ),
 600     VSRH_OPCODE    = (4u  << OPCODE_SHIFT |  580u     ),
 601     VSRAB_OPCODE   = (4u  << OPCODE_SHIFT |  772u     ),
 602     VSRAW_OPCODE   = (4u  << OPCODE_SHIFT |  900u     ),
 603     VSRAH_OPCODE   = (4u  << OPCODE_SHIFT |  836u     ),
 604 
 605     // Vector Floating-Point
 606     // not implemented yet
 607 
 608     // Vector Status and Control
 609     MTVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1604u     ),
 610     MFVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1540u     ),
 611 
 612     // AES (introduced with Power 8)
 613     VCIPHER_OPCODE      = (4u  << OPCODE_SHIFT | 1288u),
 614     VCIPHERLAST_OPCODE  = (4u  << OPCODE_SHIFT | 1289u),
 615     VNCIPHER_OPCODE     = (4u  << OPCODE_SHIFT | 1352u),
 616     VNCIPHERLAST_OPCODE = (4u  << OPCODE_SHIFT | 1353u),
 617     VSBOX_OPCODE        = (4u  << OPCODE_SHIFT | 1480u),
 618 
 619     // SHA (introduced with Power 8)
 620     VSHASIGMAD_OPCODE   = (4u  << OPCODE_SHIFT | 1730u),
 621     VSHASIGMAW_OPCODE   = (4u  << OPCODE_SHIFT | 1666u),
 622 
 623     // Vector Binary Polynomial Multiplication (introduced with Power 8)
 624     VPMSUMB_OPCODE      = (4u  << OPCODE_SHIFT | 1032u),
 625     VPMSUMD_OPCODE      = (4u  << OPCODE_SHIFT | 1224u),
 626     VPMSUMH_OPCODE      = (4u  << OPCODE_SHIFT | 1096u),
 627     VPMSUMW_OPCODE      = (4u  << OPCODE_SHIFT | 1160u),
 628 
 629     // Vector Permute and Xor (introduced with Power 8)
 630     VPERMXOR_OPCODE     = (4u  << OPCODE_SHIFT |   45u),
 631 
 632     // Transactional Memory instructions (introduced with Power 8)
 633     TBEGIN_OPCODE    = (31u << OPCODE_SHIFT |  654u << 1),
 634     TEND_OPCODE      = (31u << OPCODE_SHIFT |  686u << 1),
 635     TABORT_OPCODE    = (31u << OPCODE_SHIFT |  910u << 1),
 636     TABORTWC_OPCODE  = (31u << OPCODE_SHIFT |  782u << 1),
 637     TABORTWCI_OPCODE = (31u << OPCODE_SHIFT |  846u << 1),
 638     TABORTDC_OPCODE  = (31u << OPCODE_SHIFT |  814u << 1),
 639     TABORTDCI_OPCODE = (31u << OPCODE_SHIFT |  878u << 1),
 640     TSR_OPCODE       = (31u << OPCODE_SHIFT |  750u << 1),
 641     TCHECK_OPCODE    = (31u << OPCODE_SHIFT |  718u << 1),
 642 
 643     // Icache and dcache related instructions
 644     DCBA_OPCODE    = (31u << OPCODE_SHIFT |  758u << 1),
 645     DCBZ_OPCODE    = (31u << OPCODE_SHIFT | 1014u << 1),
 646     DCBST_OPCODE   = (31u << OPCODE_SHIFT |   54u << 1),
 647     DCBF_OPCODE    = (31u << OPCODE_SHIFT |   86u << 1),
 648 
 649     DCBT_OPCODE    = (31u << OPCODE_SHIFT |  278u << 1),
 650     DCBTST_OPCODE  = (31u << OPCODE_SHIFT |  246u << 1),
 651     ICBI_OPCODE    = (31u << OPCODE_SHIFT |  982u << 1),
 652 
 653     // Instruction synchronization
 654     ISYNC_OPCODE   = (19u << OPCODE_SHIFT |  150u << 1),
 655     // Memory barriers
 656     SYNC_OPCODE    = (31u << OPCODE_SHIFT |  598u << 1),
 657     EIEIO_OPCODE   = (31u << OPCODE_SHIFT |  854u << 1),
 658 
 659     // Trap instructions
 660     TDI_OPCODE     = (2u  << OPCODE_SHIFT),
 661     TWI_OPCODE     = (3u  << OPCODE_SHIFT),
 662     TD_OPCODE      = (31u << OPCODE_SHIFT |   68u << 1),
 663     TW_OPCODE      = (31u << OPCODE_SHIFT |    4u << 1),
 664 
 665     // Atomics.
 666     LWARX_OPCODE   = (31u << OPCODE_SHIFT |   20u << 1),
 667     LDARX_OPCODE   = (31u << OPCODE_SHIFT |   84u << 1),
 668     STWCX_OPCODE   = (31u << OPCODE_SHIFT |  150u << 1),
 669     STDCX_OPCODE   = (31u << OPCODE_SHIFT |  214u << 1)
 670 
 671   };
 672 
 673   // Trap instructions TO bits
 674   enum trap_to_bits {
 675     // single bits
 676     traptoLessThanSigned      = 1 << 4, // 0, left end
 677     traptoGreaterThanSigned   = 1 << 3,
 678     traptoEqual               = 1 << 2,
 679     traptoLessThanUnsigned    = 1 << 1,
 680     traptoGreaterThanUnsigned = 1 << 0, // 4, right end
 681 
 682     // compound ones
 683     traptoUnconditional       = (traptoLessThanSigned |
 684                                  traptoGreaterThanSigned |
 685                                  traptoEqual |
 686                                  traptoLessThanUnsigned |
 687                                  traptoGreaterThanUnsigned)
 688   };
 689 
 690   // Branch hints BH field
 691   enum branch_hint_bh {
 692     // bclr cases:
 693     bhintbhBCLRisReturn            = 0,
 694     bhintbhBCLRisNotReturnButSame  = 1,
 695     bhintbhBCLRisNotPredictable    = 3,
 696 
 697     // bcctr cases:
 698     bhintbhBCCTRisNotReturnButSame = 0,
 699     bhintbhBCCTRisNotPredictable   = 3
 700   };
 701 
 702   // Branch prediction hints AT field
 703   enum branch_hint_at {
 704     bhintatNoHint     = 0,  // at=00
 705     bhintatIsNotTaken = 2,  // at=10
 706     bhintatIsTaken    = 3   // at=11
 707   };
 708 
 709   // Branch prediction hints
 710   enum branch_hint_concept {
 711     // Use the same encoding as branch_hint_at to simply code.
 712     bhintNoHint       = bhintatNoHint,
 713     bhintIsNotTaken   = bhintatIsNotTaken,
 714     bhintIsTaken      = bhintatIsTaken
 715   };
 716 
 717   // Used in BO field of branch instruction.
 718   enum branch_condition {
 719     bcondCRbiIs0      =  4, // bo=001at
 720     bcondCRbiIs1      = 12, // bo=011at
 721     bcondAlways       = 20  // bo=10100
 722   };
 723 
 724   // Branch condition with combined prediction hints.
 725   enum branch_condition_with_hint {
 726     bcondCRbiIs0_bhintNoHint     = bcondCRbiIs0 | bhintatNoHint,
 727     bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
 728     bcondCRbiIs0_bhintIsTaken    = bcondCRbiIs0 | bhintatIsTaken,
 729     bcondCRbiIs1_bhintNoHint     = bcondCRbiIs1 | bhintatNoHint,
 730     bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
 731     bcondCRbiIs1_bhintIsTaken    = bcondCRbiIs1 | bhintatIsTaken,
 732   };
 733 
 734   // Elemental Memory Barriers (>=Power 8)
 735   enum Elemental_Membar_mask_bits {
 736     StoreStore = 1 << 0,
 737     StoreLoad  = 1 << 1,
 738     LoadStore  = 1 << 2,
 739     LoadLoad   = 1 << 3
 740   };
 741 
 742   // Branch prediction hints.
 743   inline static int add_bhint_to_boint(const int bhint, const int boint) {
 744     switch (boint) {
 745       case bcondCRbiIs0:
 746       case bcondCRbiIs1:
 747         // branch_hint and branch_hint_at have same encodings
 748         assert(   (int)bhintNoHint     == (int)bhintatNoHint
 749                && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
 750                && (int)bhintIsTaken    == (int)bhintatIsTaken,
 751                "wrong encodings");
 752         assert((bhint & 0x03) == bhint, "wrong encodings");
 753         return (boint & ~0x03) | bhint;
 754       case bcondAlways:
 755         // no branch_hint
 756         return boint;
 757       default:
 758         ShouldNotReachHere();
 759         return 0;
 760     }
 761   }
 762 
 763   // Extract bcond from boint.
 764   inline static int inv_boint_bcond(const int boint) {
 765     int r_bcond = boint & ~0x03;
 766     assert(r_bcond == bcondCRbiIs0 ||
 767            r_bcond == bcondCRbiIs1 ||
 768            r_bcond == bcondAlways,
 769            "bad branch condition");
 770     return r_bcond;
 771   }
 772 
 773   // Extract bhint from boint.
 774   inline static int inv_boint_bhint(const int boint) {
 775     int r_bhint = boint & 0x03;
 776     assert(r_bhint == bhintatNoHint ||
 777            r_bhint == bhintatIsNotTaken ||
 778            r_bhint == bhintatIsTaken,
 779            "bad branch hint");
 780     return r_bhint;
 781   }
 782 
 783   // Calculate opposite of given bcond.
 784   inline static int opposite_bcond(const int bcond) {
 785     switch (bcond) {
 786       case bcondCRbiIs0:
 787         return bcondCRbiIs1;
 788       case bcondCRbiIs1:
 789         return bcondCRbiIs0;
 790       default:
 791         ShouldNotReachHere();
 792         return 0;
 793     }
 794   }
 795 
 796   // Calculate opposite of given bhint.
 797   inline static int opposite_bhint(const int bhint) {
 798     switch (bhint) {
 799       case bhintatNoHint:
 800         return bhintatNoHint;
 801       case bhintatIsNotTaken:
 802         return bhintatIsTaken;
 803       case bhintatIsTaken:
 804         return bhintatIsNotTaken;
 805       default:
 806         ShouldNotReachHere();
 807         return 0;
 808     }
 809   }
 810 
 811   // PPC branch instructions
 812   enum ppcops {
 813     b_op    = 18,
 814     bc_op   = 16,
 815     bcr_op  = 19
 816   };
 817 
 818   enum Condition {
 819     negative         = 0,
 820     less             = 0,
 821     positive         = 1,
 822     greater          = 1,
 823     zero             = 2,
 824     equal            = 2,
 825     summary_overflow = 3,
 826   };
 827 
 828  public:
 829   // Helper functions for groups of instructions
 830 
 831   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 832 
 833   // instruction must start at passed address
 834   static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
 835 
 836   // instruction must be left-justified in argument
 837   static int instr_len(unsigned long instr)  { return BytesPerInstWord; }
 838 
 839   // longest instructions
 840   static int instr_maxlen() { return BytesPerInstWord; }
 841 
 842   // Test if x is within signed immediate range for nbits.
 843   static bool is_simm(int x, unsigned int nbits) {
 844     assert(0 < nbits && nbits < 32, "out of bounds");
 845     const int   min      = -( ((int)1) << nbits-1 );
 846     const int   maxplus1 =  ( ((int)1) << nbits-1 );
 847     return min <= x && x < maxplus1;
 848   }
 849 
 850   static bool is_simm(jlong x, unsigned int nbits) {
 851     assert(0 < nbits && nbits < 64, "out of bounds");
 852     const jlong min      = -( ((jlong)1) << nbits-1 );
 853     const jlong maxplus1 =  ( ((jlong)1) << nbits-1 );
 854     return min <= x && x < maxplus1;
 855   }
 856 
 857   // Test if x is within unsigned immediate range for nbits
 858   static bool is_uimm(int x, unsigned int nbits) {
 859     assert(0 < nbits && nbits < 32, "out of bounds");
 860     const int   maxplus1 = ( ((int)1) << nbits );
 861     return 0 <= x && x < maxplus1;
 862   }
 863 
 864   static bool is_uimm(jlong x, unsigned int nbits) {
 865     assert(0 < nbits && nbits < 64, "out of bounds");
 866     const jlong maxplus1 =  ( ((jlong)1) << nbits );
 867     return 0 <= x && x < maxplus1;
 868   }
 869 
 870  protected:
 871   // helpers
 872 
 873   // X is supposed to fit in a field "nbits" wide
 874   // and be sign-extended. Check the range.
 875   static void assert_signed_range(intptr_t x, int nbits) {
 876     assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
 877            "value out of range");
 878   }
 879 
 880   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 881     assert((x & 3) == 0, "not word aligned");
 882     assert_signed_range(x, nbits + 2);
 883   }
 884 
 885   static void assert_unsigned_const(int x, int nbits) {
 886     assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
 887   }
 888 
 889   static int fmask(juint hi_bit, juint lo_bit) {
 890     assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
 891     return (1 << ( hi_bit-lo_bit + 1 )) - 1;
 892   }
 893 
 894   // inverse of u_field
 895   static int inv_u_field(int x, int hi_bit, int lo_bit) {
 896     juint r = juint(x) >> lo_bit;
 897     r &= fmask(hi_bit, lo_bit);
 898     return int(r);
 899   }
 900 
 901   // signed version: extract from field and sign-extend
 902   static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
 903     x = x << (31-hi_bit);
 904     x = x >> (31-hi_bit+lo_bit);
 905     return x;
 906   }
 907 
 908   static int u_field(int x, int hi_bit, int lo_bit) {
 909     assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
 910     int r = x << lo_bit;
 911     assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 912     return r;
 913   }
 914 
 915   // Same as u_field for signed values
 916   static int s_field(int x, int hi_bit, int lo_bit) {
 917     int nbits = hi_bit - lo_bit + 1;
 918     assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
 919       "value out of range");
 920     x &= fmask(hi_bit, lo_bit);
 921     int r = x << lo_bit;
 922     return r;
 923   }
 924 
 925   // inv_op for ppc instructions
 926   static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
 927 
 928   // Determine target address from li, bd field of branch instruction.
 929   static intptr_t inv_li_field(int x) {
 930     intptr_t r = inv_s_field_ppc(x, 25, 2);
 931     r = (r << 2);
 932     return r;
 933   }
 934   static intptr_t inv_bd_field(int x, intptr_t pos) {
 935     intptr_t r = inv_s_field_ppc(x, 15, 2);
 936     r = (r << 2) + pos;
 937     return r;
 938   }
 939 
 940   #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
 941   #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
 942   // Extract instruction fields from instruction words.
 943  public:
 944   static int inv_ra_field(int x)  { return inv_opp_u_field(x, 15, 11); }
 945   static int inv_rb_field(int x)  { return inv_opp_u_field(x, 20, 16); }
 946   static int inv_rt_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 947   static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
 948   static int inv_rs_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 949   // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
 950   // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
 951   static int inv_ds_field(int x)  { return inv_opp_s_field(x, 29, 16) << 2; }
 952   static int inv_d1_field(int x)  { return inv_opp_s_field(x, 31, 16); }
 953   static int inv_si_field(int x)  { return inv_opp_s_field(x, 31, 16); }
 954   static int inv_to_field(int x)  { return inv_opp_u_field(x, 10, 6);  }
 955   static int inv_lk_field(int x)  { return inv_opp_u_field(x, 31, 31); }
 956   static int inv_bo_field(int x)  { return inv_opp_u_field(x, 10,  6); }
 957   static int inv_bi_field(int x)  { return inv_opp_u_field(x, 15, 11); }
 958 
 959   #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
 960   #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
 961 
 962   // instruction fields
 963   static int aa(       int         x)  { return  opp_u_field(x,             30, 30); }
 964   static int ba(       int         x)  { return  opp_u_field(x,             15, 11); }
 965   static int bb(       int         x)  { return  opp_u_field(x,             20, 16); }
 966   static int bc(       int         x)  { return  opp_u_field(x,             25, 21); }
 967   static int bd(       int         x)  { return  opp_s_field(x,             29, 16); }
 968   static int bf( ConditionRegister cr) { return  bf(cr->encoding()); }
 969   static int bf(       int         x)  { return  opp_u_field(x,              8,  6); }
 970   static int bfa(ConditionRegister cr) { return  bfa(cr->encoding()); }
 971   static int bfa(      int         x)  { return  opp_u_field(x,             13, 11); }
 972   static int bh(       int         x)  { return  opp_u_field(x,             20, 19); }
 973   static int bi(       int         x)  { return  opp_u_field(x,             15, 11); }
 974   static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
 975   static int bo(       int         x)  { return  opp_u_field(x,             10,  6); }
 976   static int bt(       int         x)  { return  opp_u_field(x,             10,  6); }
 977   static int d1(       int         x)  { return  opp_s_field(x,             31, 16); }
 978   static int ds(       int         x)  { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
 979   static int eh(       int         x)  { return  opp_u_field(x,             31, 31); }
 980   static int flm(      int         x)  { return  opp_u_field(x,             14,  7); }
 981   static int fra(    FloatRegister r)  { return  fra(r->encoding());}
 982   static int frb(    FloatRegister r)  { return  frb(r->encoding());}
 983   static int frc(    FloatRegister r)  { return  frc(r->encoding());}
 984   static int frs(    FloatRegister r)  { return  frs(r->encoding());}
 985   static int frt(    FloatRegister r)  { return  frt(r->encoding());}
 986   static int fra(      int         x)  { return  opp_u_field(x,             15, 11); }
 987   static int frb(      int         x)  { return  opp_u_field(x,             20, 16); }
 988   static int frc(      int         x)  { return  opp_u_field(x,             25, 21); }
 989   static int frs(      int         x)  { return  opp_u_field(x,             10,  6); }
 990   static int frt(      int         x)  { return  opp_u_field(x,             10,  6); }
 991   static int fxm(      int         x)  { return  opp_u_field(x,             19, 12); }
 992   static int l10(      int         x)  { return  opp_u_field(x,             10, 10); }
 993   static int l15(      int         x)  { return  opp_u_field(x,             15, 15); }
 994   static int l910(     int         x)  { return  opp_u_field(x,             10,  9); }
 995   static int e1215(    int         x)  { return  opp_u_field(x,             15, 12); }
 996   static int lev(      int         x)  { return  opp_u_field(x,             26, 20); }
 997   static int li(       int         x)  { return  opp_s_field(x,             29,  6); }
 998   static int lk(       int         x)  { return  opp_u_field(x,             31, 31); }
 999   static int mb2125(   int         x)  { return  opp_u_field(x,             25, 21); }
1000   static int me2630(   int         x)  { return  opp_u_field(x,             30, 26); }
1001   static int mb2126(   int         x)  { return  opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1002   static int me2126(   int         x)  { return  mb2126(x); }
1003   static int nb(       int         x)  { return  opp_u_field(x,             20, 16); }
1004   //static int opcd(   int         x)  { return  opp_u_field(x,              5,  0); } // is contained in our opcodes
1005   static int oe(       int         x)  { return  opp_u_field(x,             21, 21); }
1006   static int ra(       Register    r)  { return  ra(r->encoding()); }
1007   static int ra(       int         x)  { return  opp_u_field(x,             15, 11); }
1008   static int rb(       Register    r)  { return  rb(r->encoding()); }
1009   static int rb(       int         x)  { return  opp_u_field(x,             20, 16); }
1010   static int rc(       int         x)  { return  opp_u_field(x,             31, 31); }
1011   static int rs(       Register    r)  { return  rs(r->encoding()); }
1012   static int rs(       int         x)  { return  opp_u_field(x,             10,  6); }
1013   // we don't want to use R0 in memory accesses, because it has value `0' then
1014   static int ra0mem(   Register    r)  { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
1015   static int ra0mem(   int         x)  { assert(x != 0,  "cannot use register 0 in memory access");  return ra(x); }
1016 
1017   // register r is target
1018   static int rt(       Register    r)  { return rs(r); }
1019   static int rt(       int         x)  { return rs(x); }
1020   static int rta(      Register    r)  { return ra(r); }
1021   static int rta0mem(  Register    r)  { rta(r); return ra0mem(r); }
1022 
1023   static int sh1620(   int         x)  { return  opp_u_field(x,             20, 16); }
1024   static int sh30(     int         x)  { return  opp_u_field(x,             30, 30); }
1025   static int sh162030( int         x)  { return  sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
1026   static int si(       int         x)  { return  opp_s_field(x,             31, 16); }
1027   static int spr(      int         x)  { return  opp_u_field(x,             20, 11); }
1028   static int sr(       int         x)  { return  opp_u_field(x,             15, 12); }
1029   static int tbr(      int         x)  { return  opp_u_field(x,             20, 11); }
1030   static int th(       int         x)  { return  opp_u_field(x,             10,  7); }
1031   static int thct(     int         x)  { assert((x&8) == 0, "must be valid cache specification");  return th(x); }
1032   static int thds(     int         x)  { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1033   static int to(       int         x)  { return  opp_u_field(x,             10,  6); }
1034   static int u(        int         x)  { return  opp_u_field(x,             19, 16); }
1035   static int ui(       int         x)  { return  opp_u_field(x,             31, 16); }
1036 
1037   // Support vector instructions for >= Power6.
1038   static int vra(      int         x)  { return  opp_u_field(x,             15, 11); }
1039   static int vrb(      int         x)  { return  opp_u_field(x,             20, 16); }
1040   static int vrc(      int         x)  { return  opp_u_field(x,             25, 21); }
1041   static int vrs(      int         x)  { return  opp_u_field(x,             10,  6); }
1042   static int vrt(      int         x)  { return  opp_u_field(x,             10,  6); }
1043 
1044   static int vra(   VectorRegister r)  { return  vra(r->encoding());}
1045   static int vrb(   VectorRegister r)  { return  vrb(r->encoding());}
1046   static int vrc(   VectorRegister r)  { return  vrc(r->encoding());}
1047   static int vrs(   VectorRegister r)  { return  vrs(r->encoding());}
1048   static int vrt(   VectorRegister r)  { return  vrt(r->encoding());}
1049 
1050   static int vsplt_uim( int        x)  { return  opp_u_field(x,             15, 12); } // for vsplt* instructions
1051   static int vsplti_sim(int        x)  { return  opp_u_field(x,             15, 11); } // for vsplti* instructions
1052   static int vsldoi_shb(int        x)  { return  opp_u_field(x,             25, 22); } // for vsldoi instruction
1053   static int vcmp_rc(   int        x)  { return  opp_u_field(x,             21, 21); } // for vcmp* instructions
1054 
1055   //static int xo1(     int        x)  { return  opp_u_field(x,             29, 21); }// is contained in our opcodes
1056   //static int xo2(     int        x)  { return  opp_u_field(x,             30, 21); }// is contained in our opcodes
1057   //static int xo3(     int        x)  { return  opp_u_field(x,             30, 22); }// is contained in our opcodes
1058   //static int xo4(     int        x)  { return  opp_u_field(x,             30, 26); }// is contained in our opcodes
1059   //static int xo5(     int        x)  { return  opp_u_field(x,             29, 27); }// is contained in our opcodes
1060   //static int xo6(     int        x)  { return  opp_u_field(x,             30, 27); }// is contained in our opcodes
1061   //static int xo7(     int        x)  { return  opp_u_field(x,             31, 30); }// is contained in our opcodes
1062 
1063  protected:
1064   // Compute relative address for branch.
1065   static intptr_t disp(intptr_t x, intptr_t off) {
1066     int xx = x - off;
1067     xx = xx >> 2;
1068     return xx;
1069   }
1070 
1071  public:
1072   // signed immediate, in low bits, nbits long
1073   static int simm(int x, int nbits) {
1074     assert_signed_range(x, nbits);
1075     return x & ((1 << nbits) - 1);
1076   }
1077 
1078   // unsigned immediate, in low bits, nbits long
1079   static int uimm(int x, int nbits) {
1080     assert_unsigned_const(x, nbits);
1081     return x & ((1 << nbits) - 1);
1082   }
1083 
1084   static void set_imm(int* instr, short s) {
1085     // imm is always in the lower 16 bits of the instruction,
1086     // so this is endian-neutral. Same for the get_imm below.
1087     uint32_t w = *(uint32_t *)instr;
1088     *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1089   }
1090 
1091   static int get_imm(address a, int instruction_number) {
1092     return (short)((int *)a)[instruction_number];
1093   }
1094 
1095   static inline int hi16_signed(  int x) { return (int)(int16_t)(x >> 16); }
1096   static inline int lo16_unsigned(int x) { return x & 0xffff; }
1097 
1098  protected:
1099 
1100   // Extract the top 32 bits in a 64 bit word.
1101   static int32_t hi32(int64_t x) {
1102     int32_t r = int32_t((uint64_t)x >> 32);
1103     return r;
1104   }
1105 
1106  public:
1107 
1108   static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1109     return ((addr + (a - 1)) & ~(a - 1));
1110   }
1111 
1112   static inline bool is_aligned(unsigned int addr, unsigned int a) {
1113     return (0 == addr % a);
1114   }
1115 
1116   void flush() {
1117     AbstractAssembler::flush();
1118   }
1119 
1120   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
1121   inline void emit_data(int);
1122   inline void emit_data(int, RelocationHolder const&);
1123   inline void emit_data(int, relocInfo::relocType rtype);
1124 
1125   // Emit an address.
1126   inline address emit_addr(const address addr = NULL);
1127 
1128   // Emit a function descriptor.
1129   // If we are running in a little-endian environment (i.e. if ABI_ELFv2 is
1130   // defined) this function will emit no code and simply return the current PC)
1131   inline address emit_fd();
1132 
1133   /////////////////////////////////////////////////////////////////////////////////////
1134   // PPC instructions
1135   /////////////////////////////////////////////////////////////////////////////////////
1136 
1137   // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1138   // immediates. The normal instruction encoders enforce that r0 is not
1139   // passed to them. Use either extended mnemonics encoders or the special ra0
1140   // versions.
1141 
1142   // Issue an illegal instruction.
1143   inline void illtrap();
1144   static inline bool is_illtrap(int x);
1145 
1146   // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1147   inline void addi( Register d, Register a, int si16);
1148   inline void addis(Register d, Register a, int si16);
1149  private:
1150   inline void addi_r0ok( Register d, Register a, int si16);
1151   inline void addis_r0ok(Register d, Register a, int si16);
1152  public:
1153   inline void addic_( Register d, Register a, int si16);
1154   inline void subfic( Register d, Register a, int si16);
1155   inline void add(    Register d, Register a, Register b);
1156   inline void add_(   Register d, Register a, Register b);
1157   inline void subf(   Register d, Register a, Register b);  // d = b - a    "Sub_from", as in ppc spec.
1158   inline void sub(    Register d, Register a, Register b);  // d = a - b    Swap operands of subf for readability.
1159   inline void subf_(  Register d, Register a, Register b);
1160   inline void addc(   Register d, Register a, Register b);
1161   inline void addc_(  Register d, Register a, Register b);
1162   inline void subfc(  Register d, Register a, Register b);
1163   inline void subfc_( Register d, Register a, Register b);
1164   inline void adde(   Register d, Register a, Register b);
1165   inline void adde_(  Register d, Register a, Register b);
1166   inline void subfe(  Register d, Register a, Register b);
1167   inline void subfe_( Register d, Register a, Register b);
1168   inline void neg(    Register d, Register a);
1169   inline void neg_(   Register d, Register a);
1170   inline void mulli(  Register d, Register a, int si16);
1171   inline void mulld(  Register d, Register a, Register b);
1172   inline void mulld_( Register d, Register a, Register b);
1173   inline void mullw(  Register d, Register a, Register b);
1174   inline void mullw_( Register d, Register a, Register b);
1175   inline void mulhw(  Register d, Register a, Register b);
1176   inline void mulhw_( Register d, Register a, Register b);
1177   inline void mulhd(  Register d, Register a, Register b);
1178   inline void mulhd_( Register d, Register a, Register b);
1179   inline void mulhdu( Register d, Register a, Register b);
1180   inline void mulhdu_(Register d, Register a, Register b);
1181   inline void divd(   Register d, Register a, Register b);
1182   inline void divd_(  Register d, Register a, Register b);
1183   inline void divw(   Register d, Register a, Register b);
1184   inline void divw_(  Register d, Register a, Register b);
1185 
1186   // extended mnemonics
1187   inline void li(   Register d, int si16);
1188   inline void lis(  Register d, int si16);
1189   inline void addir(Register d, int si16, Register a);
1190 
1191   static bool is_addi(int x) {
1192      return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1193   }
1194   static bool is_addis(int x) {
1195      return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1196   }
1197   static bool is_bxx(int x) {
1198      return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1199   }
1200   static bool is_b(int x) {
1201      return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1202   }
1203   static bool is_bl(int x) {
1204      return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1205   }
1206   static bool is_bcxx(int x) {
1207      return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1208   }
1209   static bool is_bxx_or_bcxx(int x) {
1210      return is_bxx(x) || is_bcxx(x);
1211   }
1212   static bool is_bctrl(int x) {
1213      return x == 0x4e800421;
1214   }
1215   static bool is_bctr(int x) {
1216      return x == 0x4e800420;
1217   }
1218   static bool is_bclr(int x) {
1219      return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1220   }
1221   static bool is_li(int x) {
1222      return is_addi(x) && inv_ra_field(x)==0;
1223   }
1224   static bool is_lis(int x) {
1225      return is_addis(x) && inv_ra_field(x)==0;
1226   }
1227   static bool is_mtctr(int x) {
1228      return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1229   }
1230   static bool is_ld(int x) {
1231      return LD_OPCODE == (x & LD_OPCODE_MASK);
1232   }
1233   static bool is_std(int x) {
1234      return STD_OPCODE == (x & STD_OPCODE_MASK);
1235   }
1236   static bool is_stdu(int x) {
1237      return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1238   }
1239   static bool is_stdx(int x) {
1240      return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1241   }
1242   static bool is_stdux(int x) {
1243      return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1244   }
1245   static bool is_stwx(int x) {
1246      return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1247   }
1248   static bool is_stwux(int x) {
1249      return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1250   }
1251   static bool is_stw(int x) {
1252      return STW_OPCODE == (x & STW_OPCODE_MASK);
1253   }
1254   static bool is_stwu(int x) {
1255      return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1256   }
1257   static bool is_ori(int x) {
1258      return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1259   };
1260   static bool is_oris(int x) {
1261      return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1262   };
1263   static bool is_rldicr(int x) {
1264      return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1265   };
1266   static bool is_nop(int x) {
1267     return x == 0x60000000;
1268   }
1269   // endgroup opcode for Power6
1270   static bool is_endgroup(int x) {
1271     return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1272   }
1273 
1274 
1275  private:
1276   // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1277   inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1278   inline void cmp(  ConditionRegister bf, int l, Register a, Register b);
1279   inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1280   inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1281 
1282  public:
1283   // extended mnemonics of Compare Instructions
1284   inline void cmpwi( ConditionRegister crx, Register a, int si16);
1285   inline void cmpdi( ConditionRegister crx, Register a, int si16);
1286   inline void cmpw(  ConditionRegister crx, Register a, Register b);
1287   inline void cmpd(  ConditionRegister crx, Register a, Register b);
1288   inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1289   inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1290   inline void cmplw( ConditionRegister crx, Register a, Register b);
1291   inline void cmpld( ConditionRegister crx, Register a, Register b);
1292 
1293   inline void isel(   Register d, Register a, Register b, int bc);
1294   // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1295   inline void isel(   Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1296   // Set d = 0 if (cr.cc) equals 1, otherwise b.
1297   inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1298 
1299   // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1300          void andi(   Register a, Register s, int ui16);   // optimized version
1301   inline void andi_(  Register a, Register s, int ui16);
1302   inline void andis_( Register a, Register s, int ui16);
1303   inline void ori(    Register a, Register s, int ui16);
1304   inline void oris(   Register a, Register s, int ui16);
1305   inline void xori(   Register a, Register s, int ui16);
1306   inline void xoris(  Register a, Register s, int ui16);
1307   inline void andr(   Register a, Register s, Register b);  // suffixed by 'r' as 'and' is C++ keyword
1308   inline void and_(   Register a, Register s, Register b);
1309   // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1310   // SMT-priority change instruction (see SMT instructions below).
1311   inline void or_unchecked(Register a, Register s, Register b);
1312   inline void orr(    Register a, Register s, Register b);  // suffixed by 'r' as 'or' is C++ keyword
1313   inline void or_(    Register a, Register s, Register b);
1314   inline void xorr(   Register a, Register s, Register b);  // suffixed by 'r' as 'xor' is C++ keyword
1315   inline void xor_(   Register a, Register s, Register b);
1316   inline void nand(   Register a, Register s, Register b);
1317   inline void nand_(  Register a, Register s, Register b);
1318   inline void nor(    Register a, Register s, Register b);
1319   inline void nor_(   Register a, Register s, Register b);
1320   inline void andc(   Register a, Register s, Register b);
1321   inline void andc_(  Register a, Register s, Register b);
1322   inline void orc(    Register a, Register s, Register b);
1323   inline void orc_(   Register a, Register s, Register b);
1324   inline void extsb(  Register a, Register s);
1325   inline void extsh(  Register a, Register s);
1326   inline void extsw(  Register a, Register s);
1327 
1328   // extended mnemonics
1329   inline void nop();
1330   // NOP for FP and BR units (different versions to allow them to be in one group)
1331   inline void fpnop0();
1332   inline void fpnop1();
1333   inline void brnop0();
1334   inline void brnop1();
1335   inline void brnop2();
1336 
1337   inline void mr(      Register d, Register s);
1338   inline void ori_opt( Register d, int ui16);
1339   inline void oris_opt(Register d, int ui16);
1340 
1341   // endgroup opcode for Power6
1342   inline void endgroup();
1343 
1344   // count instructions
1345   inline void cntlzw(  Register a, Register s);
1346   inline void cntlzw_( Register a, Register s);
1347   inline void cntlzd(  Register a, Register s);
1348   inline void cntlzd_( Register a, Register s);
1349 
1350   // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1351   inline void sld(     Register a, Register s, Register b);
1352   inline void sld_(    Register a, Register s, Register b);
1353   inline void slw(     Register a, Register s, Register b);
1354   inline void slw_(    Register a, Register s, Register b);
1355   inline void srd(     Register a, Register s, Register b);
1356   inline void srd_(    Register a, Register s, Register b);
1357   inline void srw(     Register a, Register s, Register b);
1358   inline void srw_(    Register a, Register s, Register b);
1359   inline void srad(    Register a, Register s, Register b);
1360   inline void srad_(   Register a, Register s, Register b);
1361   inline void sraw(    Register a, Register s, Register b);
1362   inline void sraw_(   Register a, Register s, Register b);
1363   inline void sradi(   Register a, Register s, int sh6);
1364   inline void sradi_(  Register a, Register s, int sh6);
1365   inline void srawi(   Register a, Register s, int sh5);
1366   inline void srawi_(  Register a, Register s, int sh5);
1367 
1368   // extended mnemonics for Shift Instructions
1369   inline void sldi(    Register a, Register s, int sh6);
1370   inline void sldi_(   Register a, Register s, int sh6);
1371   inline void slwi(    Register a, Register s, int sh5);
1372   inline void slwi_(   Register a, Register s, int sh5);
1373   inline void srdi(    Register a, Register s, int sh6);
1374   inline void srdi_(   Register a, Register s, int sh6);
1375   inline void srwi(    Register a, Register s, int sh5);
1376   inline void srwi_(   Register a, Register s, int sh5);
1377 
1378   inline void clrrdi(  Register a, Register s, int ui6);
1379   inline void clrrdi_( Register a, Register s, int ui6);
1380   inline void clrldi(  Register a, Register s, int ui6);
1381   inline void clrldi_( Register a, Register s, int ui6);
1382   inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1383   inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1384   inline void extrdi(  Register a, Register s, int n, int b);
1385   // testbit with condition register
1386   inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1387 
1388   // rotate instructions
1389   inline void rotldi(  Register a, Register s, int n);
1390   inline void rotrdi(  Register a, Register s, int n);
1391   inline void rotlwi(  Register a, Register s, int n);
1392   inline void rotrwi(  Register a, Register s, int n);
1393 
1394   // Rotate Instructions
1395   inline void rldic(   Register a, Register s, int sh6, int mb6);
1396   inline void rldic_(  Register a, Register s, int sh6, int mb6);
1397   inline void rldicr(  Register a, Register s, int sh6, int mb6);
1398   inline void rldicr_( Register a, Register s, int sh6, int mb6);
1399   inline void rldicl(  Register a, Register s, int sh6, int mb6);
1400   inline void rldicl_( Register a, Register s, int sh6, int mb6);
1401   inline void rlwinm(  Register a, Register s, int sh5, int mb5, int me5);
1402   inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1403   inline void rldimi(  Register a, Register s, int sh6, int mb6);
1404   inline void rldimi_( Register a, Register s, int sh6, int mb6);
1405   inline void rlwimi(  Register a, Register s, int sh5, int mb5, int me5);
1406   inline void insrdi(  Register a, Register s, int n,   int b);
1407   inline void insrwi(  Register a, Register s, int n,   int b);
1408 
1409   // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1410   // 4 bytes
1411   inline void lwzx( Register d, Register s1, Register s2);
1412   inline void lwz(  Register d, int si16,    Register s1);
1413   inline void lwzu( Register d, int si16,    Register s1);
1414 
1415   // 4 bytes
1416   inline void lwax( Register d, Register s1, Register s2);
1417   inline void lwa(  Register d, int si16,    Register s1);
1418 
1419   // 4 bytes reversed
1420   inline void lwbrx( Register d, Register s1, Register s2);
1421 
1422   // 2 bytes
1423   inline void lhzx( Register d, Register s1, Register s2);
1424   inline void lhz(  Register d, int si16,    Register s1);
1425   inline void lhzu( Register d, int si16,    Register s1);
1426 
1427   // 2 bytes reversed
1428   inline void lhbrx( Register d, Register s1, Register s2);
1429 
1430   // 2 bytes
1431   inline void lhax( Register d, Register s1, Register s2);
1432   inline void lha(  Register d, int si16,    Register s1);
1433   inline void lhau( Register d, int si16,    Register s1);
1434 
1435   // 1 byte
1436   inline void lbzx( Register d, Register s1, Register s2);
1437   inline void lbz(  Register d, int si16,    Register s1);
1438   inline void lbzu( Register d, int si16,    Register s1);
1439 
1440   // 8 bytes
1441   inline void ldx(  Register d, Register s1, Register s2);
1442   inline void ld(   Register d, int si16,    Register s1);
1443   inline void ldu(  Register d, int si16,    Register s1);
1444 
1445   //  PPC 1, section 3.3.3 Fixed-Point Store Instructions
1446   inline void stwx( Register d, Register s1, Register s2);
1447   inline void stw(  Register d, int si16,    Register s1);
1448   inline void stwu( Register d, int si16,    Register s1);
1449 
1450   inline void sthx( Register d, Register s1, Register s2);
1451   inline void sth(  Register d, int si16,    Register s1);
1452   inline void sthu( Register d, int si16,    Register s1);
1453 
1454   inline void stbx( Register d, Register s1, Register s2);
1455   inline void stb(  Register d, int si16,    Register s1);
1456   inline void stbu( Register d, int si16,    Register s1);
1457 
1458   inline void stdx( Register d, Register s1, Register s2);
1459   inline void std(  Register d, int si16,    Register s1);
1460   inline void stdu( Register d, int si16,    Register s1);
1461   inline void stdux(Register s, Register a,  Register b);
1462 
1463   // PPC 1, section 3.3.13 Move To/From System Register Instructions
1464   inline void mtlr( Register s1);
1465   inline void mflr( Register d);
1466   inline void mtctr(Register s1);
1467   inline void mfctr(Register d);
1468   inline void mtcrf(int fxm, Register s);
1469   inline void mfcr( Register d);
1470   inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1471   inline void mtcr( Register s);
1472 
1473   // Special purpose registers
1474   // Exception Register
1475   inline void mtxer(Register s1);
1476   inline void mfxer(Register d);
1477   // Vector Register Save Register
1478   inline void mtvrsave(Register s1);
1479   inline void mfvrsave(Register d);
1480   // Timebase
1481   inline void mftb(Register d);
1482   // Introduced with Power 8:
1483   // Data Stream Control Register
1484   inline void mtdscr(Register s1);
1485   inline void mfdscr(Register d );
1486   // Transactional Memory Registers
1487   inline void mftfhar(Register d);
1488   inline void mftfiar(Register d);
1489   inline void mftexasr(Register d);
1490   inline void mftexasru(Register d);
1491 
1492   // PPC 1, section 2.4.1 Branch Instructions
1493   inline void b(  address a, relocInfo::relocType rt = relocInfo::none);
1494   inline void b(  Label& L);
1495   inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1496   inline void bl( Label& L);
1497   inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1498   inline void bc( int boint, int biint, Label& L);
1499   inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1500   inline void bcl(int boint, int biint, Label& L);
1501 
1502   inline void bclr(  int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1503   inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1504   inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1505                          relocInfo::relocType rt = relocInfo::none);
1506   inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1507                          relocInfo::relocType rt = relocInfo::none);
1508 
1509   // helper function for b, bcxx
1510   inline bool is_within_range_of_b(address a, address pc);
1511   inline bool is_within_range_of_bcxx(address a, address pc);
1512 
1513   // get the destination of a bxx branch (b, bl, ba, bla)
1514   static inline address  bxx_destination(address baddr);
1515   static inline address  bxx_destination(int instr, address pc);
1516   static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1517 
1518   // extended mnemonics for branch instructions
1519   inline void blt(ConditionRegister crx, Label& L);
1520   inline void bgt(ConditionRegister crx, Label& L);
1521   inline void beq(ConditionRegister crx, Label& L);
1522   inline void bso(ConditionRegister crx, Label& L);
1523   inline void bge(ConditionRegister crx, Label& L);
1524   inline void ble(ConditionRegister crx, Label& L);
1525   inline void bne(ConditionRegister crx, Label& L);
1526   inline void bns(ConditionRegister crx, Label& L);
1527 
1528   // Branch instructions with static prediction hints.
1529   inline void blt_predict_taken(    ConditionRegister crx, Label& L);
1530   inline void bgt_predict_taken(    ConditionRegister crx, Label& L);
1531   inline void beq_predict_taken(    ConditionRegister crx, Label& L);
1532   inline void bso_predict_taken(    ConditionRegister crx, Label& L);
1533   inline void bge_predict_taken(    ConditionRegister crx, Label& L);
1534   inline void ble_predict_taken(    ConditionRegister crx, Label& L);
1535   inline void bne_predict_taken(    ConditionRegister crx, Label& L);
1536   inline void bns_predict_taken(    ConditionRegister crx, Label& L);
1537   inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1538   inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1539   inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1540   inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1541   inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1542   inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1543   inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1544   inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1545 
1546   // for use in conjunction with testbitdi:
1547   inline void btrue( ConditionRegister crx, Label& L);
1548   inline void bfalse(ConditionRegister crx, Label& L);
1549 
1550   inline void bltl(ConditionRegister crx, Label& L);
1551   inline void bgtl(ConditionRegister crx, Label& L);
1552   inline void beql(ConditionRegister crx, Label& L);
1553   inline void bsol(ConditionRegister crx, Label& L);
1554   inline void bgel(ConditionRegister crx, Label& L);
1555   inline void blel(ConditionRegister crx, Label& L);
1556   inline void bnel(ConditionRegister crx, Label& L);
1557   inline void bnsl(ConditionRegister crx, Label& L);
1558 
1559   // extended mnemonics for Branch Instructions via LR
1560   // We use `blr' for returns.
1561   inline void blr(relocInfo::relocType rt = relocInfo::none);
1562 
1563   // extended mnemonics for Branch Instructions with CTR
1564   // bdnz means `decrement CTR and jump to L if CTR is not zero'
1565   inline void bdnz(Label& L);
1566   // Decrement and branch if result is zero.
1567   inline void bdz(Label& L);
1568   // we use `bctr[l]' for jumps/calls in function descriptor glue
1569   // code, e.g. calls to runtime functions
1570   inline void bctr( relocInfo::relocType rt = relocInfo::none);
1571   inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1572   // conditional jumps/branches via CTR
1573   inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1574   inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1575   inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1576   inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1577 
1578   // condition register logic instructions
1579   inline void crand( int d, int s1, int s2);
1580   inline void crnand(int d, int s1, int s2);
1581   inline void cror(  int d, int s1, int s2);
1582   inline void crxor( int d, int s1, int s2);
1583   inline void crnor( int d, int s1, int s2);
1584   inline void creqv( int d, int s1, int s2);
1585   inline void crandc(int d, int s1, int s2);
1586   inline void crorc( int d, int s1, int s2);
1587 
1588   // icache and dcache related instructions
1589   inline void icbi(  Register s1, Register s2);
1590   //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1591   inline void dcbz(  Register s1, Register s2);
1592   inline void dcbst( Register s1, Register s2);
1593   inline void dcbf(  Register s1, Register s2);
1594 
1595   enum ct_cache_specification {
1596     ct_primary_cache   = 0,
1597     ct_secondary_cache = 2
1598   };
1599   // dcache read hint
1600   inline void dcbt(    Register s1, Register s2);
1601   inline void dcbtct(  Register s1, Register s2, int ct);
1602   inline void dcbtds(  Register s1, Register s2, int ds);
1603   // dcache write hint
1604   inline void dcbtst(  Register s1, Register s2);
1605   inline void dcbtstct(Register s1, Register s2, int ct);
1606 
1607   //  machine barrier instructions:
1608   //
1609   //  - sync    two-way memory barrier, aka fence
1610   //  - lwsync  orders  Store|Store,
1611   //                     Load|Store,
1612   //                     Load|Load,
1613   //            but not Store|Load
1614   //  - eieio   orders memory accesses for device memory (only)
1615   //  - isync   invalidates speculatively executed instructions
1616   //            From the Power ISA 2.06 documentation:
1617   //             "[...] an isync instruction prevents the execution of
1618   //            instructions following the isync until instructions
1619   //            preceding the isync have completed, [...]"
1620   //            From IBM's AIX assembler reference:
1621   //             "The isync [...] instructions causes the processor to
1622   //            refetch any instructions that might have been fetched
1623   //            prior to the isync instruction. The instruction isync
1624   //            causes the processor to wait for all previous instructions
1625   //            to complete. Then any instructions already fetched are
1626   //            discarded and instruction processing continues in the
1627   //            environment established by the previous instructions."
1628   //
1629   //  semantic barrier instructions:
1630   //  (as defined in orderAccess.hpp)
1631   //
1632   //  - release  orders Store|Store,       (maps to lwsync)
1633   //                     Load|Store
1634   //  - acquire  orders  Load|Store,       (maps to lwsync)
1635   //                     Load|Load
1636   //  - fence    orders Store|Store,       (maps to sync)
1637   //                     Load|Store,
1638   //                     Load|Load,
1639   //                    Store|Load
1640   //
1641  private:
1642   inline void sync(int l);
1643  public:
1644   inline void sync();
1645   inline void lwsync();
1646   inline void ptesync();
1647   inline void eieio();
1648   inline void isync();
1649   inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1650 
1651   // atomics
1652   inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1653   inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1654   inline bool lxarx_hint_exclusive_access();
1655   inline void lwarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
1656   inline void ldarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
1657   inline void stwcx_( Register s, Register a, Register b);
1658   inline void stdcx_( Register s, Register a, Register b);
1659 
1660   // Instructions for adjusting thread priority for simultaneous
1661   // multithreading (SMT) on Power5.
1662  private:
1663   inline void smt_prio_very_low();
1664   inline void smt_prio_medium_high();
1665   inline void smt_prio_high();
1666 
1667  public:
1668   inline void smt_prio_low();
1669   inline void smt_prio_medium_low();
1670   inline void smt_prio_medium();
1671 
1672   // trap instructions
1673   inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1674   // NOT FOR DIRECT USE!!
1675  protected:
1676   inline void tdi_unchecked(int tobits, Register a, int si16);
1677   inline void twi_unchecked(int tobits, Register a, int si16);
1678   inline void tdi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
1679   inline void twi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
1680   inline void td(           int tobits, Register a, Register b); // asserts UseSIGTRAP
1681   inline void tw(           int tobits, Register a, Register b); // asserts UseSIGTRAP
1682 
1683   static bool is_tdi(int x, int tobits, int ra, int si16) {
1684      return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1685          && (tobits == inv_to_field(x))
1686          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1687          && (si16 == inv_si_field(x));
1688   }
1689 
1690   static bool is_twi(int x, int tobits, int ra, int si16) {
1691      return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1692          && (tobits == inv_to_field(x))
1693          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1694          && (si16 == inv_si_field(x));
1695   }
1696 
1697   static bool is_twi(int x, int tobits, int ra) {
1698      return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1699          && (tobits == inv_to_field(x))
1700          && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1701   }
1702 
1703   static bool is_td(int x, int tobits, int ra, int rb) {
1704      return (TD_OPCODE == (x & TD_OPCODE_MASK))
1705          && (tobits == inv_to_field(x))
1706          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1707          && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1708   }
1709 
1710   static bool is_tw(int x, int tobits, int ra, int rb) {
1711      return (TW_OPCODE == (x & TW_OPCODE_MASK))
1712          && (tobits == inv_to_field(x))
1713          && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1714          && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1715   }
1716 
1717  public:
1718   // PPC floating point instructions
1719   // PPC 1, section 4.6.2 Floating-Point Load Instructions
1720   inline void lfs(  FloatRegister d, int si16,   Register a);
1721   inline void lfsu( FloatRegister d, int si16,   Register a);
1722   inline void lfsx( FloatRegister d, Register a, Register b);
1723   inline void lfd(  FloatRegister d, int si16,   Register a);
1724   inline void lfdu( FloatRegister d, int si16,   Register a);
1725   inline void lfdx( FloatRegister d, Register a, Register b);
1726 
1727   // PPC 1, section 4.6.3 Floating-Point Store Instructions
1728   inline void stfs(  FloatRegister s, int si16,   Register a);
1729   inline void stfsu( FloatRegister s, int si16,   Register a);
1730   inline void stfsx( FloatRegister s, Register a, Register b);
1731   inline void stfd(  FloatRegister s, int si16,   Register a);
1732   inline void stfdu( FloatRegister s, int si16,   Register a);
1733   inline void stfdx( FloatRegister s, Register a, Register b);
1734 
1735   // PPC 1, section 4.6.4 Floating-Point Move Instructions
1736   inline void fmr(  FloatRegister d, FloatRegister b);
1737   inline void fmr_( FloatRegister d, FloatRegister b);
1738 
1739   //  inline void mffgpr( FloatRegister d, Register b);
1740   //  inline void mftgpr( Register d, FloatRegister b);
1741   inline void cmpb(   Register a, Register s, Register b);
1742   inline void popcntb(Register a, Register s);
1743   inline void popcntw(Register a, Register s);
1744   inline void popcntd(Register a, Register s);
1745 
1746   inline void fneg(  FloatRegister d, FloatRegister b);
1747   inline void fneg_( FloatRegister d, FloatRegister b);
1748   inline void fabs(  FloatRegister d, FloatRegister b);
1749   inline void fabs_( FloatRegister d, FloatRegister b);
1750   inline void fnabs( FloatRegister d, FloatRegister b);
1751   inline void fnabs_(FloatRegister d, FloatRegister b);
1752 
1753   // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1754   inline void fadd(  FloatRegister d, FloatRegister a, FloatRegister b);
1755   inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1756   inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1757   inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1758   inline void fsub(  FloatRegister d, FloatRegister a, FloatRegister b);
1759   inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1760   inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1761   inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1762   inline void fmul(  FloatRegister d, FloatRegister a, FloatRegister c);
1763   inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1764   inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1765   inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1766   inline void fdiv(  FloatRegister d, FloatRegister a, FloatRegister b);
1767   inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1768   inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1769   inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1770 
1771   // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1772   inline void frsp(  FloatRegister d, FloatRegister b);
1773   inline void fctid( FloatRegister d, FloatRegister b);
1774   inline void fctidz(FloatRegister d, FloatRegister b);
1775   inline void fctiw( FloatRegister d, FloatRegister b);
1776   inline void fctiwz(FloatRegister d, FloatRegister b);
1777   inline void fcfid( FloatRegister d, FloatRegister b);
1778   inline void fcfids(FloatRegister d, FloatRegister b);
1779 
1780   // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1781   inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1782 
1783   inline void fsqrt( FloatRegister d, FloatRegister b);
1784   inline void fsqrts(FloatRegister d, FloatRegister b);
1785 
1786   // Vector instructions for >= Power6.
1787   inline void lvebx(    VectorRegister d, Register s1, Register s2);
1788   inline void lvehx(    VectorRegister d, Register s1, Register s2);
1789   inline void lvewx(    VectorRegister d, Register s1, Register s2);
1790   inline void lvx(      VectorRegister d, Register s1, Register s2);
1791   inline void lvxl(     VectorRegister d, Register s1, Register s2);
1792   inline void stvebx(   VectorRegister d, Register s1, Register s2);
1793   inline void stvehx(   VectorRegister d, Register s1, Register s2);
1794   inline void stvewx(   VectorRegister d, Register s1, Register s2);
1795   inline void stvx(     VectorRegister d, Register s1, Register s2);
1796   inline void stvxl(    VectorRegister d, Register s1, Register s2);
1797   inline void lvsl(     VectorRegister d, Register s1, Register s2);
1798   inline void lvsr(     VectorRegister d, Register s1, Register s2);
1799   inline void vpkpx(    VectorRegister d, VectorRegister a, VectorRegister b);
1800   inline void vpkshss(  VectorRegister d, VectorRegister a, VectorRegister b);
1801   inline void vpkswss(  VectorRegister d, VectorRegister a, VectorRegister b);
1802   inline void vpkshus(  VectorRegister d, VectorRegister a, VectorRegister b);
1803   inline void vpkswus(  VectorRegister d, VectorRegister a, VectorRegister b);
1804   inline void vpkuhum(  VectorRegister d, VectorRegister a, VectorRegister b);
1805   inline void vpkuwum(  VectorRegister d, VectorRegister a, VectorRegister b);
1806   inline void vpkuhus(  VectorRegister d, VectorRegister a, VectorRegister b);
1807   inline void vpkuwus(  VectorRegister d, VectorRegister a, VectorRegister b);
1808   inline void vupkhpx(  VectorRegister d, VectorRegister b);
1809   inline void vupkhsb(  VectorRegister d, VectorRegister b);
1810   inline void vupkhsh(  VectorRegister d, VectorRegister b);
1811   inline void vupklpx(  VectorRegister d, VectorRegister b);
1812   inline void vupklsb(  VectorRegister d, VectorRegister b);
1813   inline void vupklsh(  VectorRegister d, VectorRegister b);
1814   inline void vmrghb(   VectorRegister d, VectorRegister a, VectorRegister b);
1815   inline void vmrghw(   VectorRegister d, VectorRegister a, VectorRegister b);
1816   inline void vmrghh(   VectorRegister d, VectorRegister a, VectorRegister b);
1817   inline void vmrglb(   VectorRegister d, VectorRegister a, VectorRegister b);
1818   inline void vmrglw(   VectorRegister d, VectorRegister a, VectorRegister b);
1819   inline void vmrglh(   VectorRegister d, VectorRegister a, VectorRegister b);
1820   inline void vsplt(    VectorRegister d, int ui4,          VectorRegister b);
1821   inline void vsplth(   VectorRegister d, int ui3,          VectorRegister b);
1822   inline void vspltw(   VectorRegister d, int ui2,          VectorRegister b);
1823   inline void vspltisb( VectorRegister d, int si5);
1824   inline void vspltish( VectorRegister d, int si5);
1825   inline void vspltisw( VectorRegister d, int si5);
1826   inline void vperm(    VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1827   inline void vsel(     VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1828   inline void vsl(      VectorRegister d, VectorRegister a, VectorRegister b);
1829   inline void vsldoi(   VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1830   inline void vslo(     VectorRegister d, VectorRegister a, VectorRegister b);
1831   inline void vsr(      VectorRegister d, VectorRegister a, VectorRegister b);
1832   inline void vsro(     VectorRegister d, VectorRegister a, VectorRegister b);
1833   inline void vaddcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
1834   inline void vaddshs(  VectorRegister d, VectorRegister a, VectorRegister b);
1835   inline void vaddsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
1836   inline void vaddsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1837   inline void vaddubm(  VectorRegister d, VectorRegister a, VectorRegister b);
1838   inline void vadduwm(  VectorRegister d, VectorRegister a, VectorRegister b);
1839   inline void vadduhm(  VectorRegister d, VectorRegister a, VectorRegister b);
1840   inline void vaddubs(  VectorRegister d, VectorRegister a, VectorRegister b);
1841   inline void vadduws(  VectorRegister d, VectorRegister a, VectorRegister b);
1842   inline void vadduhs(  VectorRegister d, VectorRegister a, VectorRegister b);
1843   inline void vsubcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
1844   inline void vsubshs(  VectorRegister d, VectorRegister a, VectorRegister b);
1845   inline void vsubsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
1846   inline void vsubsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1847   inline void vsububm(  VectorRegister d, VectorRegister a, VectorRegister b);
1848   inline void vsubuwm(  VectorRegister d, VectorRegister a, VectorRegister b);
1849   inline void vsubuhm(  VectorRegister d, VectorRegister a, VectorRegister b);
1850   inline void vsububs(  VectorRegister d, VectorRegister a, VectorRegister b);
1851   inline void vsubuws(  VectorRegister d, VectorRegister a, VectorRegister b);
1852   inline void vsubuhs(  VectorRegister d, VectorRegister a, VectorRegister b);
1853   inline void vmulesb(  VectorRegister d, VectorRegister a, VectorRegister b);
1854   inline void vmuleub(  VectorRegister d, VectorRegister a, VectorRegister b);
1855   inline void vmulesh(  VectorRegister d, VectorRegister a, VectorRegister b);
1856   inline void vmuleuh(  VectorRegister d, VectorRegister a, VectorRegister b);
1857   inline void vmulosb(  VectorRegister d, VectorRegister a, VectorRegister b);
1858   inline void vmuloub(  VectorRegister d, VectorRegister a, VectorRegister b);
1859   inline void vmulosh(  VectorRegister d, VectorRegister a, VectorRegister b);
1860   inline void vmulouh(  VectorRegister d, VectorRegister a, VectorRegister b);
1861   inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1862   inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1863   inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1864   inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1865   inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1866   inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1867   inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1868   inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1869   inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1870   inline void vsumsws(  VectorRegister d, VectorRegister a, VectorRegister b);
1871   inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1872   inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1873   inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1874   inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1875   inline void vavgsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1876   inline void vavgsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1877   inline void vavgsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1878   inline void vavgub(   VectorRegister d, VectorRegister a, VectorRegister b);
1879   inline void vavguw(   VectorRegister d, VectorRegister a, VectorRegister b);
1880   inline void vavguh(   VectorRegister d, VectorRegister a, VectorRegister b);
1881   inline void vmaxsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1882   inline void vmaxsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1883   inline void vmaxsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1884   inline void vmaxub(   VectorRegister d, VectorRegister a, VectorRegister b);
1885   inline void vmaxuw(   VectorRegister d, VectorRegister a, VectorRegister b);
1886   inline void vmaxuh(   VectorRegister d, VectorRegister a, VectorRegister b);
1887   inline void vminsb(   VectorRegister d, VectorRegister a, VectorRegister b);
1888   inline void vminsw(   VectorRegister d, VectorRegister a, VectorRegister b);
1889   inline void vminsh(   VectorRegister d, VectorRegister a, VectorRegister b);
1890   inline void vminub(   VectorRegister d, VectorRegister a, VectorRegister b);
1891   inline void vminuw(   VectorRegister d, VectorRegister a, VectorRegister b);
1892   inline void vminuh(   VectorRegister d, VectorRegister a, VectorRegister b);
1893   inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1894   inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1895   inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1896   inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1897   inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1898   inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1899   inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1900   inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
1901   inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
1902   inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
1903   inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
1904   inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
1905   inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
1906   inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
1907   inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
1908   inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
1909   inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
1910   inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
1911   inline void vand(     VectorRegister d, VectorRegister a, VectorRegister b);
1912   inline void vandc(    VectorRegister d, VectorRegister a, VectorRegister b);
1913   inline void vnor(     VectorRegister d, VectorRegister a, VectorRegister b);
1914   inline void vor(      VectorRegister d, VectorRegister a, VectorRegister b);
1915   inline void vxor(     VectorRegister d, VectorRegister a, VectorRegister b);
1916   inline void vrlb(     VectorRegister d, VectorRegister a, VectorRegister b);
1917   inline void vrlw(     VectorRegister d, VectorRegister a, VectorRegister b);
1918   inline void vrlh(     VectorRegister d, VectorRegister a, VectorRegister b);
1919   inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
1920   inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);
1921   inline void vslh(     VectorRegister d, VectorRegister a, VectorRegister b);
1922   inline void vsrb(     VectorRegister d, VectorRegister a, VectorRegister b);
1923   inline void vsrw(     VectorRegister d, VectorRegister a, VectorRegister b);
1924   inline void vsrh(     VectorRegister d, VectorRegister a, VectorRegister b);
1925   inline void vsrab(    VectorRegister d, VectorRegister a, VectorRegister b);
1926   inline void vsraw(    VectorRegister d, VectorRegister a, VectorRegister b);
1927   inline void vsrah(    VectorRegister d, VectorRegister a, VectorRegister b);
1928   // Vector Floating-Point not implemented yet
1929   inline void mtvscr(   VectorRegister b);
1930   inline void mfvscr(   VectorRegister d);
1931 
1932   // AES (introduced with Power 8)
1933   inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
1934   inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1935   inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);
1936   inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1937   inline void vsbox(       VectorRegister d, VectorRegister a);
1938 
1939   // SHA (introduced with Power 8)
1940   // Not yet implemented.
1941 
1942   // Vector Binary Polynomial Multiplication (introduced with Power 8)
1943   inline void vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b);
1944   inline void vpmsumd(  VectorRegister d, VectorRegister a, VectorRegister b);
1945   inline void vpmsumh(  VectorRegister d, VectorRegister a, VectorRegister b);
1946   inline void vpmsumw(  VectorRegister d, VectorRegister a, VectorRegister b);
1947 
1948   // Vector Permute and Xor (introduced with Power 8)
1949   inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1950 
1951   // Transactional Memory instructions (introduced with Power 8)
1952   inline void tbegin_();    // R=0
1953   inline void tbeginrot_(); // R=1 Rollback-Only Transaction
1954   inline void tend_();    // A=0
1955   inline void tendall_(); // A=1
1956   inline void tabort_(Register a);
1957   inline void tabortwc_(int t, Register a, Register b);
1958   inline void tabortwci_(int t, Register a, int si);
1959   inline void tabortdc_(int t, Register a, Register b);
1960   inline void tabortdci_(int t, Register a, int si);
1961   inline void tsuspend_(); // tsr with L=0
1962   inline void tresume_();  // tsr with L=1
1963   inline void tcheck(int f);
1964 
1965   // The following encoders use r0 as second operand. These instructions
1966   // read r0 as '0'.
1967   inline void lwzx( Register d, Register s2);
1968   inline void lwz(  Register d, int si16);
1969   inline void lwax( Register d, Register s2);
1970   inline void lwa(  Register d, int si16);
1971   inline void lwbrx(Register d, Register s2);
1972   inline void lhzx( Register d, Register s2);
1973   inline void lhz(  Register d, int si16);
1974   inline void lhax( Register d, Register s2);
1975   inline void lha(  Register d, int si16);
1976   inline void lhbrx(Register d, Register s2);
1977   inline void lbzx( Register d, Register s2);
1978   inline void lbz(  Register d, int si16);
1979   inline void ldx(  Register d, Register s2);
1980   inline void ld(   Register d, int si16);
1981   inline void stwx( Register d, Register s2);
1982   inline void stw(  Register d, int si16);
1983   inline void sthx( Register d, Register s2);
1984   inline void sth(  Register d, int si16);
1985   inline void stbx( Register d, Register s2);
1986   inline void stb(  Register d, int si16);
1987   inline void stdx( Register d, Register s2);
1988   inline void std(  Register d, int si16);
1989 
1990   // PPC 2, section 3.2.1 Instruction Cache Instructions
1991   inline void icbi(    Register s2);
1992   // PPC 2, section 3.2.2 Data Cache Instructions
1993   //inlinevoid dcba(   Register s2); // Instruction for embedded processor only.
1994   inline void dcbz(    Register s2);
1995   inline void dcbst(   Register s2);
1996   inline void dcbf(    Register s2);
1997   // dcache read hint
1998   inline void dcbt(    Register s2);
1999   inline void dcbtct(  Register s2, int ct);
2000   inline void dcbtds(  Register s2, int ds);
2001   // dcache write hint
2002   inline void dcbtst(  Register s2);
2003   inline void dcbtstct(Register s2, int ct);
2004 
2005   // Atomics: use ra0mem to disallow R0 as base.
2006   inline void lwarx_unchecked(Register d, Register b, int eh1);
2007   inline void ldarx_unchecked(Register d, Register b, int eh1);
2008   inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2009   inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2010   inline void stwcx_(Register s, Register b);
2011   inline void stdcx_(Register s, Register b);
2012   inline void lfs(   FloatRegister d, int si16);
2013   inline void lfsx(  FloatRegister d, Register b);
2014   inline void lfd(   FloatRegister d, int si16);
2015   inline void lfdx(  FloatRegister d, Register b);
2016   inline void stfs(  FloatRegister s, int si16);
2017   inline void stfsx( FloatRegister s, Register b);
2018   inline void stfd(  FloatRegister s, int si16);
2019   inline void stfdx( FloatRegister s, Register b);
2020   inline void lvebx( VectorRegister d, Register s2);
2021   inline void lvehx( VectorRegister d, Register s2);
2022   inline void lvewx( VectorRegister d, Register s2);
2023   inline void lvx(   VectorRegister d, Register s2);
2024   inline void lvxl(  VectorRegister d, Register s2);
2025   inline void stvebx(VectorRegister d, Register s2);
2026   inline void stvehx(VectorRegister d, Register s2);
2027   inline void stvewx(VectorRegister d, Register s2);
2028   inline void stvx(  VectorRegister d, Register s2);
2029   inline void stvxl( VectorRegister d, Register s2);
2030   inline void lvsl(  VectorRegister d, Register s2);
2031   inline void lvsr(  VectorRegister d, Register s2);
2032 
2033   // RegisterOrConstant versions.
2034   // These emitters choose between the versions using two registers and
2035   // those with register and immediate, depending on the content of roc.
2036   // If the constant is not encodable as immediate, instructions to
2037   // load the constant are emitted beforehand. Store instructions need a
2038   // tmp reg if the constant is not encodable as immediate.
2039   // Size unpredictable.
2040   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2041   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2042   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2043   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2044   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2045   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2046   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2047   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2048   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2049   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2050   void add( Register d, RegisterOrConstant roc, Register s1);
2051   void subf(Register d, RegisterOrConstant roc, Register s1);
2052   void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
2053 
2054 
2055   // Emit several instructions to load a 64 bit constant. This issues a fixed
2056   // instruction pattern so that the constant can be patched later on.
2057   enum {
2058     load_const_size = 5 * BytesPerInstWord
2059   };
2060          void load_const(Register d, long a,            Register tmp = noreg);
2061   inline void load_const(Register d, void* a,           Register tmp = noreg);
2062   inline void load_const(Register d, Label& L,          Register tmp = noreg);
2063   inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
2064 
2065   // Load a 64 bit constant, optimized, not identifyable.
2066   // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
2067   // 16 bit immediate offset. This is useful if the offset can be encoded in
2068   // a succeeding instruction.
2069          int load_const_optimized(Register d, long a,  Register tmp = noreg, bool return_simm16_rest = false);
2070   inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
2071     return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
2072   }
2073 
2074   // Creation
2075   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2076 #ifdef CHECK_DELAY
2077     delay_state = no_delay;
2078 #endif
2079   }
2080 
2081   // Testing
2082 #ifndef PRODUCT
2083   void test_asm();
2084 #endif
2085 };
2086 
2087 
2088 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP