1 /*
   2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "asm/macroAssembler.hpp"
  29 #include "ci/ciEnv.hpp"
  30 #include "code/nativeInst.hpp"
  31 #include "compiler/disassembler.hpp"
  32 #include "gc/shared/barrierSet.hpp"
  33 #include "gc/shared/cardTable.hpp"
  34 #include "gc/shared/barrierSetAssembler.hpp"
  35 #include "gc/shared/cardTableBarrierSet.hpp"
  36 #include "gc/shared/collectedHeap.inline.hpp"
  37 #include "interpreter/interpreter.hpp"
  38 #include "memory/resourceArea.hpp"
  39 #include "oops/accessDecorators.hpp"
  40 #include "oops/klass.inline.hpp"
  41 #include "prims/methodHandles.hpp"
  42 #include "runtime/biasedLocking.hpp"
  43 #include "runtime/interfaceSupport.inline.hpp"
  44 #include "runtime/objectMonitor.hpp"
  45 #include "runtime/os.hpp"
  46 #include "runtime/sharedRuntime.hpp"
  47 #include "runtime/stubRoutines.hpp"
  48 #include "utilities/macros.hpp"
  49 
  50 // Implementation of AddressLiteral
  51 
  52 void AddressLiteral::set_rspec(relocInfo::relocType rtype) {
  53   switch (rtype) {
  54   case relocInfo::oop_type:
  55     // Oops are a special case. Normally they would be their own section
  56     // but in cases like icBuffer they are literals in the code stream that
  57     // we don't have a section for. We use none so that we get a literal address
  58     // which is always patchable.
  59     break;
  60   case relocInfo::external_word_type:
  61     _rspec = external_word_Relocation::spec(_target);
  62     break;
  63   case relocInfo::internal_word_type:
  64     _rspec = internal_word_Relocation::spec(_target);
  65     break;
  66   case relocInfo::opt_virtual_call_type:
  67     _rspec = opt_virtual_call_Relocation::spec();
  68     break;
  69   case relocInfo::static_call_type:
  70     _rspec = static_call_Relocation::spec();
  71     break;
  72   case relocInfo::runtime_call_type:
  73     _rspec = runtime_call_Relocation::spec();
  74     break;
  75   case relocInfo::poll_type:
  76   case relocInfo::poll_return_type:
  77     _rspec = Relocation::spec_simple(rtype);
  78     break;
  79   case relocInfo::none:
  80     break;
  81   default:
  82     ShouldNotReachHere();
  83     break;
  84   }
  85 }
  86 
  87 // Initially added to the Assembler interface as a pure virtual:
  88 //   RegisterConstant delayed_value(..)
  89 // for:
  90 //   6812678 macro assembler needs delayed binding of a few constants (for 6655638)
  91 // this was subsequently modified to its present name and return type
  92 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
  93                                                       Register tmp,
  94                                                       int offset) {
  95   ShouldNotReachHere();
  96   return RegisterOrConstant(-1);
  97 }
  98 
  99 
 100 #ifdef AARCH64
 101 // Note: ARM32 version is OS dependent
 102 void MacroAssembler::breakpoint(AsmCondition cond) {
 103   if (cond == al) {
 104     brk();
 105   } else {
 106     Label L;
 107     b(L, inverse(cond));
 108     brk();
 109     bind(L);
 110   }
 111 }
 112 #endif // AARCH64
 113 
 114 
 115 // virtual method calling
 116 void MacroAssembler::lookup_virtual_method(Register recv_klass,
 117                                            Register vtable_index,
 118                                            Register method_result) {
 119   const int base_offset = in_bytes(Klass::vtable_start_offset()) + vtableEntry::method_offset_in_bytes();
 120   assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
 121   add(recv_klass, recv_klass, AsmOperand(vtable_index, lsl, LogBytesPerWord));
 122   ldr(method_result, Address(recv_klass, base_offset));
 123 }
 124 
 125 
 126 // Simplified, combined version, good for typical uses.
 127 // Falls through on failure.
 128 void MacroAssembler::check_klass_subtype(Register sub_klass,
 129                                          Register super_klass,
 130                                          Register temp_reg,
 131                                          Register temp_reg2,
 132                                          Register temp_reg3,
 133                                          Label& L_success) {
 134   Label L_failure;
 135   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, temp_reg2, &L_success, &L_failure, NULL);
 136   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, temp_reg2, temp_reg3, &L_success, NULL);
 137   bind(L_failure);
 138 };
 139 
 140 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
 141                                                    Register super_klass,
 142                                                    Register temp_reg,
 143                                                    Register temp_reg2,
 144                                                    Label* L_success,
 145                                                    Label* L_failure,
 146                                                    Label* L_slow_path) {
 147 
 148   assert_different_registers(sub_klass, super_klass, temp_reg, temp_reg2, noreg);
 149   const Register super_check_offset = temp_reg2;
 150 
 151   Label L_fallthrough;
 152   int label_nulls = 0;
 153   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
 154   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
 155   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
 156   assert(label_nulls <= 1, "at most one NULL in the batch");
 157 
 158   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
 159   int sco_offset = in_bytes(Klass::super_check_offset_offset());
 160   Address super_check_offset_addr(super_klass, sco_offset);
 161 
 162   // If the pointers are equal, we are done (e.g., String[] elements).
 163   // This self-check enables sharing of secondary supertype arrays among
 164   // non-primary types such as array-of-interface.  Otherwise, each such
 165   // type would need its own customized SSA.
 166   // We move this check to the front of the fast path because many
 167   // type checks are in fact trivially successful in this manner,
 168   // so we get a nicely predicted branch right at the start of the check.
 169   cmp(sub_klass, super_klass);
 170   b(*L_success, eq);
 171 
 172   // Check the supertype display:
 173   ldr_u32(super_check_offset, super_check_offset_addr);
 174 
 175   Address super_check_addr(sub_klass, super_check_offset);
 176   ldr(temp_reg, super_check_addr);
 177   cmp(super_klass, temp_reg); // load displayed supertype
 178 
 179   // This check has worked decisively for primary supers.
 180   // Secondary supers are sought in the super_cache ('super_cache_addr').
 181   // (Secondary supers are interfaces and very deeply nested subtypes.)
 182   // This works in the same check above because of a tricky aliasing
 183   // between the super_cache and the primary super display elements.
 184   // (The 'super_check_addr' can address either, as the case requires.)
 185   // Note that the cache is updated below if it does not help us find
 186   // what we need immediately.
 187   // So if it was a primary super, we can just fail immediately.
 188   // Otherwise, it's the slow path for us (no success at this point).
 189 
 190   b(*L_success, eq);
 191   cmp_32(super_check_offset, sc_offset);
 192   if (L_failure == &L_fallthrough) {
 193     b(*L_slow_path, eq);
 194   } else {
 195     b(*L_failure, ne);
 196     if (L_slow_path != &L_fallthrough) {
 197       b(*L_slow_path);
 198     }
 199   }
 200 
 201   bind(L_fallthrough);
 202 }
 203 
 204 
 205 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
 206                                                    Register super_klass,
 207                                                    Register temp_reg,
 208                                                    Register temp2_reg,
 209                                                    Register temp3_reg,
 210                                                    Label* L_success,
 211                                                    Label* L_failure,
 212                                                    bool set_cond_codes) {
 213 #ifdef AARCH64
 214   NOT_IMPLEMENTED();
 215 #else
 216   // Note: if used by code that expects a register to be 0 on success,
 217   // this register must be temp_reg and set_cond_codes must be true
 218 
 219   Register saved_reg = noreg;
 220 
 221   // get additional tmp registers
 222   if (temp3_reg == noreg) {
 223     saved_reg = temp3_reg = LR;
 224     push(saved_reg);
 225   }
 226 
 227   assert(temp2_reg != noreg, "need all the temporary registers");
 228   assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg);
 229 
 230   Register cmp_temp = temp_reg;
 231   Register scan_temp = temp3_reg;
 232   Register count_temp = temp2_reg;
 233 
 234   Label L_fallthrough;
 235   int label_nulls = 0;
 236   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
 237   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
 238   assert(label_nulls <= 1, "at most one NULL in the batch");
 239 
 240   // a couple of useful fields in sub_klass:
 241   int ss_offset = in_bytes(Klass::secondary_supers_offset());
 242   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
 243   Address secondary_supers_addr(sub_klass, ss_offset);
 244   Address super_cache_addr(     sub_klass, sc_offset);
 245 
 246 #ifndef PRODUCT
 247   inc_counter((address)&SharedRuntime::_partial_subtype_ctr, scan_temp, count_temp);
 248 #endif
 249 
 250   // We will consult the secondary-super array.
 251   ldr(scan_temp, Address(sub_klass, ss_offset));
 252 
 253   assert(! UseCompressedOops, "search_key must be the compressed super_klass");
 254   // else search_key is the
 255   Register search_key = super_klass;
 256 
 257   // Load the array length.
 258   ldr(count_temp, Address(scan_temp, Array<Klass*>::length_offset_in_bytes()));
 259   add(scan_temp, scan_temp, Array<Klass*>::base_offset_in_bytes());
 260 
 261   add(count_temp, count_temp, 1);
 262 
 263   Label L_loop, L_setnz_and_fail, L_fail;
 264 
 265   // Top of search loop
 266   bind(L_loop);
 267   // Notes:
 268   //  scan_temp starts at the array elements
 269   //  count_temp is 1+size
 270   subs(count_temp, count_temp, 1);
 271   if ((L_failure != &L_fallthrough) && (! set_cond_codes) && (saved_reg == noreg)) {
 272     // direct jump to L_failure if failed and no cleanup needed
 273     b(*L_failure, eq); // not found and
 274   } else {
 275     b(L_fail, eq); // not found in the array
 276   }
 277 
 278   // Load next super to check
 279   // In the array of super classes elements are pointer sized.
 280   int element_size = wordSize;
 281   ldr(cmp_temp, Address(scan_temp, element_size, post_indexed));
 282 
 283   // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
 284   subs(cmp_temp, cmp_temp, search_key);
 285 
 286   // A miss means we are NOT a subtype and need to keep looping
 287   b(L_loop, ne);
 288 
 289   // Falling out the bottom means we found a hit; we ARE a subtype
 290 
 291   // Note: temp_reg/cmp_temp is already 0 and flag Z is set
 292 
 293   // Success.  Cache the super we found and proceed in triumph.
 294   str(super_klass, Address(sub_klass, sc_offset));
 295 
 296   if (saved_reg != noreg) {
 297     // Return success
 298     pop(saved_reg);
 299   }
 300 
 301   b(*L_success);
 302 
 303   bind(L_fail);
 304   // Note1: check "b(*L_failure, eq)" above if adding extra instructions here
 305   if (set_cond_codes) {
 306     movs(temp_reg, sub_klass); // clears Z and sets temp_reg to non-0 if needed
 307   }
 308   if (saved_reg != noreg) {
 309     pop(saved_reg);
 310   }
 311   if (L_failure != &L_fallthrough) {
 312     b(*L_failure);
 313   }
 314 
 315   bind(L_fallthrough);
 316 #endif
 317 }
 318 
 319 // Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.
 320 Address MacroAssembler::receiver_argument_address(Register params_base, Register params_count, Register tmp) {
 321   assert_different_registers(params_base, params_count);
 322   add(tmp, params_base, AsmOperand(params_count, lsl, Interpreter::logStackElementSize));
 323   return Address(tmp, -Interpreter::stackElementSize);
 324 }
 325 
 326 
 327 void MacroAssembler::align(int modulus) {
 328   while (offset() % modulus != 0) {
 329     nop();
 330   }
 331 }
 332 
 333 int MacroAssembler::set_last_Java_frame(Register last_java_sp,
 334                                         Register last_java_fp,
 335                                         bool save_last_java_pc,
 336                                         Register tmp) {
 337   int pc_offset;
 338   if (last_java_fp != noreg) {
 339     // optional
 340     str(last_java_fp, Address(Rthread, JavaThread::last_Java_fp_offset()));
 341     _fp_saved = true;
 342   } else {
 343     _fp_saved = false;
 344   }
 345   if (AARCH64_ONLY(true) NOT_AARCH64(save_last_java_pc)) { // optional on 32-bit ARM
 346 #ifdef AARCH64
 347     pc_offset = mov_pc_to(tmp);
 348     str(tmp, Address(Rthread, JavaThread::last_Java_pc_offset()));
 349 #else
 350     str(PC, Address(Rthread, JavaThread::last_Java_pc_offset()));
 351     pc_offset = offset() + VM_Version::stored_pc_adjustment();
 352 #endif
 353     _pc_saved = true;
 354   } else {
 355     _pc_saved = false;
 356     pc_offset = -1;
 357   }
 358   // According to comment in javaFrameAnchorm SP must be saved last, so that other
 359   // entries are valid when SP is set.
 360 
 361   // However, this is probably not a strong constrainst since for instance PC is
 362   // sometimes read from the stack at SP... but is pushed later (by the call). Hence,
 363   // we now write the fields in the expected order but we have not added a StoreStore
 364   // barrier.
 365 
 366   // XXX: if the ordering is really important, PC should always be saved (without forgetting
 367   // to update oop_map offsets) and a StoreStore barrier might be needed.
 368 
 369   if (last_java_sp == noreg) {
 370     last_java_sp = SP; // always saved
 371   }
 372 #ifdef AARCH64
 373   if (last_java_sp == SP) {
 374     mov(tmp, SP);
 375     str(tmp, Address(Rthread, JavaThread::last_Java_sp_offset()));
 376   } else {
 377     str(last_java_sp, Address(Rthread, JavaThread::last_Java_sp_offset()));
 378   }
 379 #else
 380   str(last_java_sp, Address(Rthread, JavaThread::last_Java_sp_offset()));
 381 #endif
 382 
 383   return pc_offset; // for oopmaps
 384 }
 385 
 386 void MacroAssembler::reset_last_Java_frame(Register tmp) {
 387   const Register Rzero = zero_register(tmp);
 388   str(Rzero, Address(Rthread, JavaThread::last_Java_sp_offset()));
 389   if (_fp_saved) {
 390     str(Rzero, Address(Rthread, JavaThread::last_Java_fp_offset()));
 391   }
 392   if (_pc_saved) {
 393     str(Rzero, Address(Rthread, JavaThread::last_Java_pc_offset()));
 394   }
 395 }
 396 
 397 
 398 // Implementation of call_VM versions
 399 
 400 void MacroAssembler::call_VM_leaf_helper(address entry_point, int number_of_arguments) {
 401   assert(number_of_arguments >= 0, "cannot have negative number of arguments");
 402   assert(number_of_arguments <= 4, "cannot have more than 4 arguments");
 403 
 404 #ifndef AARCH64
 405   // Safer to save R9 here since callers may have been written
 406   // assuming R9 survives. This is suboptimal but is not worth
 407   // optimizing for the few platforms where R9 is scratched.
 408   push(RegisterSet(R4) | R9ifScratched);
 409   mov(R4, SP);
 410   bic(SP, SP, StackAlignmentInBytes - 1);
 411 #endif // AARCH64
 412   call(entry_point, relocInfo::runtime_call_type);
 413 #ifndef AARCH64
 414   mov(SP, R4);
 415   pop(RegisterSet(R4) | R9ifScratched);
 416 #endif // AARCH64
 417 }
 418 
 419 
 420 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
 421   assert(number_of_arguments >= 0, "cannot have negative number of arguments");
 422   assert(number_of_arguments <= 3, "cannot have more than 3 arguments");
 423 
 424   const Register tmp = Rtemp;
 425   assert_different_registers(oop_result, tmp);
 426 
 427   set_last_Java_frame(SP, FP, true, tmp);
 428 
 429 #ifdef ASSERT
 430   AARCH64_ONLY(if (UseCompressedOops || UseCompressedClassPointers) { verify_heapbase("call_VM_helper: heap base corrupted?"); });
 431 #endif // ASSERT
 432 
 433 #ifndef AARCH64
 434 #if R9_IS_SCRATCHED
 435   // Safer to save R9 here since callers may have been written
 436   // assuming R9 survives. This is suboptimal but is not worth
 437   // optimizing for the few platforms where R9 is scratched.
 438 
 439   // Note: cannot save R9 above the saved SP (some calls expect for
 440   // instance the Java stack top at the saved SP)
 441   // => once saved (with set_last_Java_frame), decrease SP before rounding to
 442   // ensure the slot at SP will be free for R9).
 443   sub(SP, SP, 4);
 444   bic(SP, SP, StackAlignmentInBytes - 1);
 445   str(R9, Address(SP, 0));
 446 #else
 447   bic(SP, SP, StackAlignmentInBytes - 1);
 448 #endif // R9_IS_SCRATCHED
 449 #endif
 450 
 451   mov(R0, Rthread);
 452   call(entry_point, relocInfo::runtime_call_type);
 453 
 454 #ifndef AARCH64
 455 #if R9_IS_SCRATCHED
 456   ldr(R9, Address(SP, 0));
 457 #endif
 458   ldr(SP, Address(Rthread, JavaThread::last_Java_sp_offset()));
 459 #endif
 460 
 461   reset_last_Java_frame(tmp);
 462 
 463   // C++ interp handles this in the interpreter
 464   check_and_handle_popframe();
 465   check_and_handle_earlyret();
 466 
 467   if (check_exceptions) {
 468     // check for pending exceptions
 469     ldr(tmp, Address(Rthread, Thread::pending_exception_offset()));
 470 #ifdef AARCH64
 471     Label L;
 472     cbz(tmp, L);
 473     mov_pc_to(Rexception_pc);
 474     b(StubRoutines::forward_exception_entry());
 475     bind(L);
 476 #else
 477     cmp(tmp, 0);
 478     mov(Rexception_pc, PC, ne);
 479     b(StubRoutines::forward_exception_entry(), ne);
 480 #endif // AARCH64
 481   }
 482 
 483   // get oop result if there is one and reset the value in the thread
 484   if (oop_result->is_valid()) {
 485     get_vm_result(oop_result, tmp);
 486   }
 487 }
 488 
 489 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
 490   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
 491 }
 492 
 493 
 494 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
 495   assert (arg_1 == R1, "fixed register for arg_1");
 496   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
 497 }
 498 
 499 
 500 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
 501   assert (arg_1 == R1, "fixed register for arg_1");
 502   assert (arg_2 == R2, "fixed register for arg_2");
 503   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
 504 }
 505 
 506 
 507 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
 508   assert (arg_1 == R1, "fixed register for arg_1");
 509   assert (arg_2 == R2, "fixed register for arg_2");
 510   assert (arg_3 == R3, "fixed register for arg_3");
 511   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
 512 }
 513 
 514 
 515 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
 516   // Not used on ARM
 517   Unimplemented();
 518 }
 519 
 520 
 521 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
 522   // Not used on ARM
 523   Unimplemented();
 524 }
 525 
 526 
 527 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
 528 // Not used on ARM
 529   Unimplemented();
 530 }
 531 
 532 
 533 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
 534   // Not used on ARM
 535   Unimplemented();
 536 }
 537 
 538 // Raw call, without saving/restoring registers, exception handling, etc.
 539 // Mainly used from various stubs.
 540 void MacroAssembler::call_VM(address entry_point, bool save_R9_if_scratched) {
 541   const Register tmp = Rtemp; // Rtemp free since scratched by call
 542   set_last_Java_frame(SP, FP, true, tmp);
 543 #if R9_IS_SCRATCHED
 544   if (save_R9_if_scratched) {
 545     // Note: Saving also R10 for alignment.
 546     push(RegisterSet(R9, R10));
 547   }
 548 #endif
 549   mov(R0, Rthread);
 550   call(entry_point, relocInfo::runtime_call_type);
 551 #if R9_IS_SCRATCHED
 552   if (save_R9_if_scratched) {
 553     pop(RegisterSet(R9, R10));
 554   }
 555 #endif
 556   reset_last_Java_frame(tmp);
 557 }
 558 
 559 void MacroAssembler::call_VM_leaf(address entry_point) {
 560   call_VM_leaf_helper(entry_point, 0);
 561 }
 562 
 563 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
 564   assert (arg_1 == R0, "fixed register for arg_1");
 565   call_VM_leaf_helper(entry_point, 1);
 566 }
 567 
 568 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
 569   assert (arg_1 == R0, "fixed register for arg_1");
 570   assert (arg_2 == R1, "fixed register for arg_2");
 571   call_VM_leaf_helper(entry_point, 2);
 572 }
 573 
 574 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
 575   assert (arg_1 == R0, "fixed register for arg_1");
 576   assert (arg_2 == R1, "fixed register for arg_2");
 577   assert (arg_3 == R2, "fixed register for arg_3");
 578   call_VM_leaf_helper(entry_point, 3);
 579 }
 580 
 581 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4) {
 582   assert (arg_1 == R0, "fixed register for arg_1");
 583   assert (arg_2 == R1, "fixed register for arg_2");
 584   assert (arg_3 == R2, "fixed register for arg_3");
 585   assert (arg_4 == R3, "fixed register for arg_4");
 586   call_VM_leaf_helper(entry_point, 4);
 587 }
 588 
 589 void MacroAssembler::get_vm_result(Register oop_result, Register tmp) {
 590   assert_different_registers(oop_result, tmp);
 591   ldr(oop_result, Address(Rthread, JavaThread::vm_result_offset()));
 592   str(zero_register(tmp), Address(Rthread, JavaThread::vm_result_offset()));
 593   verify_oop(oop_result);
 594 }
 595 
 596 void MacroAssembler::get_vm_result_2(Register metadata_result, Register tmp) {
 597   assert_different_registers(metadata_result, tmp);
 598   ldr(metadata_result, Address(Rthread, JavaThread::vm_result_2_offset()));
 599   str(zero_register(tmp), Address(Rthread, JavaThread::vm_result_2_offset()));
 600 }
 601 
 602 void MacroAssembler::add_rc(Register dst, Register arg1, RegisterOrConstant arg2) {
 603   if (arg2.is_register()) {
 604     add(dst, arg1, arg2.as_register());
 605   } else {
 606     add(dst, arg1, arg2.as_constant());
 607   }
 608 }
 609 
 610 void MacroAssembler::add_slow(Register rd, Register rn, int c) {
 611 #ifdef AARCH64
 612   if (c == 0) {
 613     if (rd != rn) {
 614       mov(rd, rn);
 615     }
 616     return;
 617   }
 618   if (c < 0) {
 619     sub_slow(rd, rn, -c);
 620     return;
 621   }
 622   if (c > right_n_bits(24)) {
 623     guarantee(rd != rn, "no large add_slow with only one register");
 624     mov_slow(rd, c);
 625     add(rd, rn, rd);
 626   } else {
 627     int lo = c & right_n_bits(12);
 628     int hi = (c >> 12) & right_n_bits(12);
 629     if (lo != 0) {
 630       add(rd, rn, lo, lsl0);
 631     }
 632     if (hi != 0) {
 633       add(rd, (lo == 0) ? rn : rd, hi, lsl12);
 634     }
 635   }
 636 #else
 637   // This function is used in compiler for handling large frame offsets
 638   if ((c < 0) && (((-c) & ~0x3fc) == 0)) {
 639     return sub(rd, rn, (-c));
 640   }
 641   int low = c & 0x3fc;
 642   if (low != 0) {
 643     add(rd, rn, low);
 644     rn = rd;
 645   }
 646   if (c & ~0x3fc) {
 647     assert(AsmOperand::is_rotated_imm(c & ~0x3fc), "unsupported add_slow offset %d", c);
 648     add(rd, rn, c & ~0x3fc);
 649   } else if (rd != rn) {
 650     assert(c == 0, "");
 651     mov(rd, rn); // need to generate at least one move!
 652   }
 653 #endif // AARCH64
 654 }
 655 
 656 void MacroAssembler::sub_slow(Register rd, Register rn, int c) {
 657 #ifdef AARCH64
 658   if (c <= 0) {
 659     add_slow(rd, rn, -c);
 660     return;
 661   }
 662   if (c > right_n_bits(24)) {
 663     guarantee(rd != rn, "no large sub_slow with only one register");
 664     mov_slow(rd, c);
 665     sub(rd, rn, rd);
 666   } else {
 667     int lo = c & right_n_bits(12);
 668     int hi = (c >> 12) & right_n_bits(12);
 669     if (lo != 0) {
 670       sub(rd, rn, lo, lsl0);
 671     }
 672     if (hi != 0) {
 673       sub(rd, (lo == 0) ? rn : rd, hi, lsl12);
 674     }
 675   }
 676 #else
 677   // This function is used in compiler for handling large frame offsets
 678   if ((c < 0) && (((-c) & ~0x3fc) == 0)) {
 679     return add(rd, rn, (-c));
 680   }
 681   int low = c & 0x3fc;
 682   if (low != 0) {
 683     sub(rd, rn, low);
 684     rn = rd;
 685   }
 686   if (c & ~0x3fc) {
 687     assert(AsmOperand::is_rotated_imm(c & ~0x3fc), "unsupported sub_slow offset %d", c);
 688     sub(rd, rn, c & ~0x3fc);
 689   } else if (rd != rn) {
 690     assert(c == 0, "");
 691     mov(rd, rn); // need to generate at least one move!
 692   }
 693 #endif // AARCH64
 694 }
 695 
 696 void MacroAssembler::mov_slow(Register rd, address addr) {
 697   // do *not* call the non relocated mov_related_address
 698   mov_slow(rd, (intptr_t)addr);
 699 }
 700 
 701 void MacroAssembler::mov_slow(Register rd, const char *str) {
 702   mov_slow(rd, (intptr_t)str);
 703 }
 704 
 705 #ifdef AARCH64
 706 
 707 // Common code for mov_slow and instr_count_for_mov_slow.
 708 // Returns number of instructions of mov_slow pattern,
 709 // generating it if non-null MacroAssembler is given.
 710 int MacroAssembler::mov_slow_helper(Register rd, intptr_t c, MacroAssembler* masm) {
 711   // This code pattern is matched in NativeIntruction::is_mov_slow.
 712   // Update it at modifications.
 713 
 714   const intx mask = right_n_bits(16);
 715   // 1 movz instruction
 716   for (int base_shift = 0; base_shift < 64; base_shift += 16) {
 717     if ((c & ~(mask << base_shift)) == 0) {
 718       if (masm != NULL) {
 719         masm->movz(rd, ((uintx)c) >> base_shift, base_shift);
 720       }
 721       return 1;
 722     }
 723   }
 724   // 1 movn instruction
 725   for (int base_shift = 0; base_shift < 64; base_shift += 16) {
 726     if (((~c) & ~(mask << base_shift)) == 0) {
 727       if (masm != NULL) {
 728         masm->movn(rd, ((uintx)(~c)) >> base_shift, base_shift);
 729       }
 730       return 1;
 731     }
 732   }
 733   // 1 orr instruction
 734   {
 735     LogicalImmediate imm(c, false);
 736     if (imm.is_encoded()) {
 737       if (masm != NULL) {
 738         masm->orr(rd, ZR, imm);
 739       }
 740       return 1;
 741     }
 742   }
 743   // 1 movz/movn + up to 3 movk instructions
 744   int zeroes = 0;
 745   int ones = 0;
 746   for (int base_shift = 0; base_shift < 64; base_shift += 16) {
 747     int part = (c >> base_shift) & mask;
 748     if (part == 0) {
 749       ++zeroes;
 750     } else if (part == mask) {
 751       ++ones;
 752     }
 753   }
 754   int def_bits = 0;
 755   if (ones > zeroes) {
 756     def_bits = mask;
 757   }
 758   int inst_count = 0;
 759   for (int base_shift = 0; base_shift < 64; base_shift += 16) {
 760     int part = (c >> base_shift) & mask;
 761     if (part != def_bits) {
 762       if (masm != NULL) {
 763         if (inst_count > 0) {
 764           masm->movk(rd, part, base_shift);
 765         } else {
 766           if (def_bits == 0) {
 767             masm->movz(rd, part, base_shift);
 768           } else {
 769             masm->movn(rd, ~part & mask, base_shift);
 770           }
 771         }
 772       }
 773       inst_count++;
 774     }
 775   }
 776   assert((1 <= inst_count) && (inst_count <= 4), "incorrect number of instructions");
 777   return inst_count;
 778 }
 779 
 780 void MacroAssembler::mov_slow(Register rd, intptr_t c) {
 781 #ifdef ASSERT
 782   int off = offset();
 783 #endif
 784   (void) mov_slow_helper(rd, c, this);
 785   assert(offset() - off == instr_count_for_mov_slow(c) * InstructionSize, "size mismatch");
 786 }
 787 
 788 // Counts instructions generated by mov_slow(rd, c).
 789 int MacroAssembler::instr_count_for_mov_slow(intptr_t c) {
 790   return mov_slow_helper(noreg, c, NULL);
 791 }
 792 
 793 int MacroAssembler::instr_count_for_mov_slow(address c) {
 794   return mov_slow_helper(noreg, (intptr_t)c, NULL);
 795 }
 796 
 797 #else
 798 
 799 void MacroAssembler::mov_slow(Register rd, intptr_t c, AsmCondition cond) {
 800   if (AsmOperand::is_rotated_imm(c)) {
 801     mov(rd, c, cond);
 802   } else if (AsmOperand::is_rotated_imm(~c)) {
 803     mvn(rd, ~c, cond);
 804   } else if (VM_Version::supports_movw()) {
 805     movw(rd, c & 0xffff, cond);
 806     if ((unsigned int)c >> 16) {
 807       movt(rd, (unsigned int)c >> 16, cond);
 808     }
 809   } else {
 810     // Find first non-zero bit
 811     int shift = 0;
 812     while ((c & (3 << shift)) == 0) {
 813       shift += 2;
 814     }
 815     // Put the least significant part of the constant
 816     int mask = 0xff << shift;
 817     mov(rd, c & mask, cond);
 818     // Add up to 3 other parts of the constant;
 819     // each of them can be represented as rotated_imm
 820     if (c & (mask << 8)) {
 821       orr(rd, rd, c & (mask << 8), cond);
 822     }
 823     if (c & (mask << 16)) {
 824       orr(rd, rd, c & (mask << 16), cond);
 825     }
 826     if (c & (mask << 24)) {
 827       orr(rd, rd, c & (mask << 24), cond);
 828     }
 829   }
 830 }
 831 
 832 #endif // AARCH64
 833 
 834 void MacroAssembler::mov_oop(Register rd, jobject o, int oop_index,
 835 #ifdef AARCH64
 836                              bool patchable
 837 #else
 838                              AsmCondition cond
 839 #endif
 840                              ) {
 841 
 842   if (o == NULL) {
 843 #ifdef AARCH64
 844     if (patchable) {
 845       nop();
 846     }
 847     mov(rd, ZR);
 848 #else
 849     mov(rd, 0, cond);
 850 #endif
 851     return;
 852   }
 853 
 854   if (oop_index == 0) {
 855     oop_index = oop_recorder()->allocate_oop_index(o);
 856   }
 857   relocate(oop_Relocation::spec(oop_index));
 858 
 859 #ifdef AARCH64
 860   if (patchable) {
 861     nop();
 862   }
 863   ldr(rd, pc());
 864 #else
 865   if (VM_Version::supports_movw()) {
 866     movw(rd, 0, cond);
 867     movt(rd, 0, cond);
 868   } else {
 869     ldr(rd, Address(PC), cond);
 870     // Extra nop to handle case of large offset of oop placeholder (see NativeMovConstReg::set_data).
 871     nop();
 872   }
 873 #endif
 874 }
 875 
 876 void MacroAssembler::mov_metadata(Register rd, Metadata* o, int metadata_index AARCH64_ONLY_ARG(bool patchable)) {
 877   if (o == NULL) {
 878 #ifdef AARCH64
 879     if (patchable) {
 880       nop();
 881     }
 882 #endif
 883     mov(rd, 0);
 884     return;
 885   }
 886 
 887   if (metadata_index == 0) {
 888     metadata_index = oop_recorder()->allocate_metadata_index(o);
 889   }
 890   relocate(metadata_Relocation::spec(metadata_index));
 891 
 892 #ifdef AARCH64
 893   if (patchable) {
 894     nop();
 895   }
 896 #ifdef COMPILER2
 897   if (!patchable && VM_Version::prefer_moves_over_load_literal()) {
 898     mov_slow(rd, (address)o);
 899     return;
 900   }
 901 #endif
 902   ldr(rd, pc());
 903 #else
 904   if (VM_Version::supports_movw()) {
 905     movw(rd, ((int)o) & 0xffff);
 906     movt(rd, (unsigned int)o >> 16);
 907   } else {
 908     ldr(rd, Address(PC));
 909     // Extra nop to handle case of large offset of metadata placeholder (see NativeMovConstReg::set_data).
 910     nop();
 911   }
 912 #endif // AARCH64
 913 }
 914 
 915 void MacroAssembler::mov_float(FloatRegister fd, jfloat c NOT_AARCH64_ARG(AsmCondition cond)) {
 916   Label skip_constant;
 917   union {
 918     jfloat f;
 919     jint i;
 920   } accessor;
 921   accessor.f = c;
 922 
 923 #ifdef AARCH64
 924   // TODO-AARCH64 - try to optimize loading of float constants with fmov and/or mov_slow
 925   Label L;
 926   ldr_s(fd, target(L));
 927   b(skip_constant);
 928   bind(L);
 929   emit_int32(accessor.i);
 930   bind(skip_constant);
 931 #else
 932   flds(fd, Address(PC), cond);
 933   b(skip_constant);
 934   emit_int32(accessor.i);
 935   bind(skip_constant);
 936 #endif // AARCH64
 937 }
 938 
 939 void MacroAssembler::mov_double(FloatRegister fd, jdouble c NOT_AARCH64_ARG(AsmCondition cond)) {
 940   Label skip_constant;
 941   union {
 942     jdouble d;
 943     jint i[2];
 944   } accessor;
 945   accessor.d = c;
 946 
 947 #ifdef AARCH64
 948   // TODO-AARCH64 - try to optimize loading of double constants with fmov
 949   Label L;
 950   ldr_d(fd, target(L));
 951   b(skip_constant);
 952   align(wordSize);
 953   bind(L);
 954   emit_int32(accessor.i[0]);
 955   emit_int32(accessor.i[1]);
 956   bind(skip_constant);
 957 #else
 958   fldd(fd, Address(PC), cond);
 959   b(skip_constant);
 960   emit_int32(accessor.i[0]);
 961   emit_int32(accessor.i[1]);
 962   bind(skip_constant);
 963 #endif // AARCH64
 964 }
 965 
 966 void MacroAssembler::ldr_global_s32(Register reg, address address_of_global) {
 967   intptr_t addr = (intptr_t) address_of_global;
 968 #ifdef AARCH64
 969   assert((addr & 0x3) == 0, "address should be aligned");
 970 
 971   // FIXME: TODO
 972   if (false && page_reachable_from_cache(address_of_global)) {
 973     assert(false,"TODO: relocate");
 974     //relocate();
 975     adrp(reg, address_of_global);
 976     ldrsw(reg, Address(reg, addr & 0xfff));
 977   } else {
 978     mov_slow(reg, addr & ~0x3fff);
 979     ldrsw(reg, Address(reg, addr & 0x3fff));
 980   }
 981 #else
 982   mov_slow(reg, addr & ~0xfff);
 983   ldr(reg, Address(reg, addr & 0xfff));
 984 #endif
 985 }
 986 
 987 void MacroAssembler::ldr_global_ptr(Register reg, address address_of_global) {
 988 #ifdef AARCH64
 989   intptr_t addr = (intptr_t) address_of_global;
 990   assert ((addr & 0x7) == 0, "address should be aligned");
 991   mov_slow(reg, addr & ~0x7fff);
 992   ldr(reg, Address(reg, addr & 0x7fff));
 993 #else
 994   ldr_global_s32(reg, address_of_global);
 995 #endif
 996 }
 997 
 998 void MacroAssembler::ldrb_global(Register reg, address address_of_global) {
 999   intptr_t addr = (intptr_t) address_of_global;
1000   mov_slow(reg, addr & ~0xfff);
1001   ldrb(reg, Address(reg, addr & 0xfff));
1002 }
1003 
1004 void MacroAssembler::zero_extend(Register rd, Register rn, int bits) {
1005 #ifdef AARCH64
1006   switch (bits) {
1007     case  8: uxtb(rd, rn); break;
1008     case 16: uxth(rd, rn); break;
1009     case 32: mov_w(rd, rn); break;
1010     default: ShouldNotReachHere();
1011   }
1012 #else
1013   if (bits <= 8) {
1014     andr(rd, rn, (1 << bits) - 1);
1015   } else if (bits >= 24) {
1016     bic(rd, rn, -1 << bits);
1017   } else {
1018     mov(rd, AsmOperand(rn, lsl, 32 - bits));
1019     mov(rd, AsmOperand(rd, lsr, 32 - bits));
1020   }
1021 #endif
1022 }
1023 
1024 void MacroAssembler::sign_extend(Register rd, Register rn, int bits) {
1025 #ifdef AARCH64
1026   switch (bits) {
1027     case  8: sxtb(rd, rn); break;
1028     case 16: sxth(rd, rn); break;
1029     case 32: sxtw(rd, rn); break;
1030     default: ShouldNotReachHere();
1031   }
1032 #else
1033   mov(rd, AsmOperand(rn, lsl, 32 - bits));
1034   mov(rd, AsmOperand(rd, asr, 32 - bits));
1035 #endif
1036 }
1037 
1038 #ifndef AARCH64
1039 
1040 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
1041   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1042   bs->obj_equals(this, obj1, obj2);
1043 }
1044 
1045 void MacroAssembler::long_move(Register rd_lo, Register rd_hi,
1046                                Register rn_lo, Register rn_hi,
1047                                AsmCondition cond) {
1048   if (rd_lo != rn_hi) {
1049     if (rd_lo != rn_lo) { mov(rd_lo, rn_lo, cond); }
1050     if (rd_hi != rn_hi) { mov(rd_hi, rn_hi, cond); }
1051   } else if (rd_hi != rn_lo) {
1052     if (rd_hi != rn_hi) { mov(rd_hi, rn_hi, cond); }
1053     if (rd_lo != rn_lo) { mov(rd_lo, rn_lo, cond); }
1054   } else {
1055     eor(rd_lo, rd_hi, rd_lo, cond);
1056     eor(rd_hi, rd_lo, rd_hi, cond);
1057     eor(rd_lo, rd_hi, rd_lo, cond);
1058   }
1059 }
1060 
1061 void MacroAssembler::long_shift(Register rd_lo, Register rd_hi,
1062                                 Register rn_lo, Register rn_hi,
1063                                 AsmShift shift, Register count) {
1064   Register tmp;
1065   if (rd_lo != rn_lo && rd_lo != rn_hi && rd_lo != count) {
1066     tmp = rd_lo;
1067   } else {
1068     tmp = rd_hi;
1069   }
1070   assert_different_registers(tmp, count, rn_lo, rn_hi);
1071 
1072   subs(tmp, count, 32);
1073   if (shift == lsl) {
1074     assert_different_registers(rd_hi, rn_lo);
1075     assert_different_registers(count, rd_hi);
1076     mov(rd_hi, AsmOperand(rn_lo, shift, tmp), pl);
1077     rsb(tmp, count, 32, mi);
1078     if (rd_hi == rn_hi) {
1079       mov(rd_hi, AsmOperand(rn_hi, lsl, count), mi);
1080       orr(rd_hi, rd_hi, AsmOperand(rn_lo, lsr, tmp), mi);
1081     } else {
1082       mov(rd_hi, AsmOperand(rn_lo, lsr, tmp), mi);
1083       orr(rd_hi, rd_hi, AsmOperand(rn_hi, lsl, count), mi);
1084     }
1085     mov(rd_lo, AsmOperand(rn_lo, shift, count));
1086   } else {
1087     assert_different_registers(rd_lo, rn_hi);
1088     assert_different_registers(rd_lo, count);
1089     mov(rd_lo, AsmOperand(rn_hi, shift, tmp), pl);
1090     rsb(tmp, count, 32, mi);
1091     if (rd_lo == rn_lo) {
1092       mov(rd_lo, AsmOperand(rn_lo, lsr, count), mi);
1093       orr(rd_lo, rd_lo, AsmOperand(rn_hi, lsl, tmp), mi);
1094     } else {
1095       mov(rd_lo, AsmOperand(rn_hi, lsl, tmp), mi);
1096       orr(rd_lo, rd_lo, AsmOperand(rn_lo, lsr, count), mi);
1097     }
1098     mov(rd_hi, AsmOperand(rn_hi, shift, count));
1099   }
1100 }
1101 
1102 void MacroAssembler::long_shift(Register rd_lo, Register rd_hi,
1103                                 Register rn_lo, Register rn_hi,
1104                                 AsmShift shift, int count) {
1105   assert(count != 0 && (count & ~63) == 0, "must be");
1106 
1107   if (shift == lsl) {
1108     assert_different_registers(rd_hi, rn_lo);
1109     if (count >= 32) {
1110       mov(rd_hi, AsmOperand(rn_lo, lsl, count - 32));
1111       mov(rd_lo, 0);
1112     } else {
1113       mov(rd_hi, AsmOperand(rn_hi, lsl, count));
1114       orr(rd_hi, rd_hi, AsmOperand(rn_lo, lsr, 32 - count));
1115       mov(rd_lo, AsmOperand(rn_lo, lsl, count));
1116     }
1117   } else {
1118     assert_different_registers(rd_lo, rn_hi);
1119     if (count >= 32) {
1120       if (count == 32) {
1121         mov(rd_lo, rn_hi);
1122       } else {
1123         mov(rd_lo, AsmOperand(rn_hi, shift, count - 32));
1124       }
1125       if (shift == asr) {
1126         mov(rd_hi, AsmOperand(rn_hi, asr, 0));
1127       } else {
1128         mov(rd_hi, 0);
1129       }
1130     } else {
1131       mov(rd_lo, AsmOperand(rn_lo, lsr, count));
1132       orr(rd_lo, rd_lo, AsmOperand(rn_hi, lsl, 32 - count));
1133       mov(rd_hi, AsmOperand(rn_hi, shift, count));
1134     }
1135   }
1136 }
1137 #endif // !AARCH64
1138 
1139 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1140   // This code pattern is matched in NativeIntruction::skip_verify_oop.
1141   // Update it at modifications.
1142   if (!VerifyOops) return;
1143 
1144   char buffer[64];
1145 #ifdef COMPILER1
1146   if (CommentedAssembly) {
1147     snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1148     block_comment(buffer);
1149   }
1150 #endif
1151   const char* msg_buffer = NULL;
1152   {
1153     ResourceMark rm;
1154     stringStream ss;
1155     ss.print("%s at offset %d (%s:%d)", s, offset(), file, line);
1156     msg_buffer = code_string(ss.as_string());
1157   }
1158 
1159   save_all_registers();
1160 
1161   if (reg != R2) {
1162       mov(R2, reg);                              // oop to verify
1163   }
1164   mov(R1, SP);                                   // register save area
1165 
1166   Label done;
1167   InlinedString Lmsg(msg_buffer);
1168   ldr_literal(R0, Lmsg);                         // message
1169 
1170   // call indirectly to solve generation ordering problem
1171   ldr_global_ptr(Rtemp, StubRoutines::verify_oop_subroutine_entry_address());
1172   call(Rtemp);
1173 
1174   restore_all_registers();
1175 
1176   b(done);
1177 #ifdef COMPILER2
1178   int off = offset();
1179 #endif
1180   bind_literal(Lmsg);
1181 #ifdef COMPILER2
1182   if (offset() - off == 1 * wordSize) {
1183     // no padding, so insert nop for worst-case sizing
1184     nop();
1185   }
1186 #endif
1187   bind(done);
1188 }
1189 
1190 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1191   if (!VerifyOops) return;
1192 
1193   const char* msg_buffer = NULL;
1194   {
1195     ResourceMark rm;
1196     stringStream ss;
1197     if ((addr.base() == SP) && (addr.index()==noreg)) {
1198       ss.print("verify_oop_addr SP[%d]: %s", (int)addr.disp(), s);
1199     } else {
1200       ss.print("verify_oop_addr: %s", s);
1201     }
1202     ss.print(" (%s:%d)", file, line);
1203     msg_buffer = code_string(ss.as_string());
1204   }
1205 
1206   int push_size = save_all_registers();
1207 
1208   if (addr.base() == SP) {
1209     // computes an addr that takes into account the push
1210     if (addr.index() != noreg) {
1211       Register new_base = addr.index() == R2 ? R1 : R2; // avoid corrupting the index
1212       add(new_base, SP, push_size);
1213       addr = addr.rebase(new_base);
1214     } else {
1215       addr = addr.plus_disp(push_size);
1216     }
1217   }
1218 
1219   ldr(R2, addr);                                 // oop to verify
1220   mov(R1, SP);                                   // register save area
1221 
1222   Label done;
1223   InlinedString Lmsg(msg_buffer);
1224   ldr_literal(R0, Lmsg);                         // message
1225 
1226   // call indirectly to solve generation ordering problem
1227   ldr_global_ptr(Rtemp, StubRoutines::verify_oop_subroutine_entry_address());
1228   call(Rtemp);
1229 
1230   restore_all_registers();
1231 
1232   b(done);
1233   bind_literal(Lmsg);
1234   bind(done);
1235 }
1236 
1237 void MacroAssembler::null_check(Register reg, Register tmp, int offset) {
1238   if (needs_explicit_null_check(offset)) {
1239 #ifdef AARCH64
1240     ldr(ZR, Address(reg));
1241 #else
1242     assert_different_registers(reg, tmp);
1243     if (tmp == noreg) {
1244       tmp = Rtemp;
1245       assert((! Thread::current()->is_Compiler_thread()) ||
1246              (! (ciEnv::current()->task() == NULL)) ||
1247              (! (ciEnv::current()->comp_level() == CompLevel_full_optimization)),
1248              "Rtemp not available in C2"); // explicit tmp register required
1249       // XXX: could we mark the code buffer as not compatible with C2 ?
1250     }
1251     ldr(tmp, Address(reg));
1252 #endif
1253   }
1254 }
1255 
1256 // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.
1257 void MacroAssembler::eden_allocate(Register obj, Register obj_end, Register tmp1, Register tmp2,
1258                                  RegisterOrConstant size_expression, Label& slow_case) {
1259   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
1260   bs->eden_allocate(this, obj, obj_end, tmp1, tmp2, size_expression, slow_case);
1261 }
1262 
1263 // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.
1264 void MacroAssembler::tlab_allocate(Register obj, Register obj_end, Register tmp1,
1265                                  RegisterOrConstant size_expression, Label& slow_case) {
1266   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
1267   bs->tlab_allocate(this, obj, obj_end, tmp1, size_expression, slow_case);
1268 }
1269 
1270 // Fills memory regions [start..end] with zeroes. Clobbers `start` and `tmp` registers.
1271 void MacroAssembler::zero_memory(Register start, Register end, Register tmp) {
1272   Label loop;
1273   const Register ptr = start;
1274 
1275 #ifdef AARCH64
1276   // TODO-AARCH64 - compare performance of 2x word zeroing with simple 1x
1277   const Register size = tmp;
1278   Label remaining, done;
1279 
1280   sub(size, end, start);
1281 
1282 #ifdef ASSERT
1283   { Label L;
1284     tst(size, wordSize - 1);
1285     b(L, eq);
1286     stop("size is not a multiple of wordSize");
1287     bind(L);
1288   }
1289 #endif // ASSERT
1290 
1291   subs(size, size, wordSize);
1292   b(remaining, le);
1293 
1294   // Zero by 2 words per iteration.
1295   bind(loop);
1296   subs(size, size, 2*wordSize);
1297   stp(ZR, ZR, Address(ptr, 2*wordSize, post_indexed));
1298   b(loop, gt);
1299 
1300   bind(remaining);
1301   b(done, ne);
1302   str(ZR, Address(ptr));
1303   bind(done);
1304 #else
1305   mov(tmp, 0);
1306   bind(loop);
1307   cmp(ptr, end);
1308   str(tmp, Address(ptr, wordSize, post_indexed), lo);
1309   b(loop, lo);
1310 #endif // AARCH64
1311 }
1312 
1313 void MacroAssembler::arm_stack_overflow_check(int frame_size_in_bytes, Register tmp) {
1314   // Version of AbstractAssembler::generate_stack_overflow_check optimized for ARM
1315   if (UseStackBanging) {
1316     const int page_size = os::vm_page_size();
1317 
1318     sub_slow(tmp, SP, JavaThread::stack_shadow_zone_size());
1319     strb(R0, Address(tmp));
1320 #ifdef AARCH64
1321     for (; frame_size_in_bytes >= page_size; frame_size_in_bytes -= page_size) {
1322       sub(tmp, tmp, page_size);
1323       strb(R0, Address(tmp));
1324     }
1325 #else
1326     for (; frame_size_in_bytes >= page_size; frame_size_in_bytes -= 0xff0) {
1327       strb(R0, Address(tmp, -0xff0, pre_indexed));
1328     }
1329 #endif // AARCH64
1330   }
1331 }
1332 
1333 void MacroAssembler::arm_stack_overflow_check(Register Rsize, Register tmp) {
1334   if (UseStackBanging) {
1335     Label loop;
1336 
1337     mov(tmp, SP);
1338     add_slow(Rsize, Rsize, JavaThread::stack_shadow_zone_size() - os::vm_page_size());
1339 #ifdef AARCH64
1340     sub(tmp, tmp, Rsize);
1341     bind(loop);
1342     subs(Rsize, Rsize, os::vm_page_size());
1343     strb(ZR, Address(tmp, Rsize));
1344 #else
1345     bind(loop);
1346     subs(Rsize, Rsize, 0xff0);
1347     strb(R0, Address(tmp, -0xff0, pre_indexed));
1348 #endif // AARCH64
1349     b(loop, hi);
1350   }
1351 }
1352 
1353 void MacroAssembler::stop(const char* msg) {
1354   // This code pattern is matched in NativeIntruction::is_stop.
1355   // Update it at modifications.
1356 #ifdef COMPILER1
1357   if (CommentedAssembly) {
1358     block_comment("stop");
1359   }
1360 #endif
1361 
1362   InlinedAddress Ldebug(CAST_FROM_FN_PTR(address, MacroAssembler::debug));
1363   InlinedString Lmsg(msg);
1364 
1365   // save all registers for further inspection
1366   save_all_registers();
1367 
1368   ldr_literal(R0, Lmsg);                     // message
1369   mov(R1, SP);                               // register save area
1370 
1371 #ifdef AARCH64
1372   ldr_literal(Rtemp, Ldebug);
1373   br(Rtemp);
1374 #else
1375   ldr_literal(PC, Ldebug);                   // call MacroAssembler::debug
1376 #endif // AARCH64
1377 
1378 #if defined(COMPILER2) && defined(AARCH64)
1379   int off = offset();
1380 #endif
1381   bind_literal(Lmsg);
1382   bind_literal(Ldebug);
1383 #if defined(COMPILER2) && defined(AARCH64)
1384   if (offset() - off == 2 * wordSize) {
1385     // no padding, so insert nop for worst-case sizing
1386     nop();
1387   }
1388 #endif
1389 }
1390 
1391 void MacroAssembler::warn(const char* msg) {
1392 #ifdef COMPILER1
1393   if (CommentedAssembly) {
1394     block_comment("warn");
1395   }
1396 #endif
1397 
1398   InlinedAddress Lwarn(CAST_FROM_FN_PTR(address, warning));
1399   InlinedString Lmsg(msg);
1400   Label done;
1401 
1402   int push_size = save_caller_save_registers();
1403 
1404 #ifdef AARCH64
1405   // TODO-AARCH64 - get rid of extra debug parameters
1406   mov(R1, LR);
1407   mov(R2, FP);
1408   add(R3, SP, push_size);
1409 #endif
1410 
1411   ldr_literal(R0, Lmsg);                    // message
1412   ldr_literal(LR, Lwarn);                   // call warning
1413 
1414   call(LR);
1415 
1416   restore_caller_save_registers();
1417 
1418   b(done);
1419   bind_literal(Lmsg);
1420   bind_literal(Lwarn);
1421   bind(done);
1422 }
1423 
1424 
1425 int MacroAssembler::save_all_registers() {
1426   // This code pattern is matched in NativeIntruction::is_save_all_registers.
1427   // Update it at modifications.
1428 #ifdef AARCH64
1429   const Register tmp = Rtemp;
1430   raw_push(R30, ZR);
1431   for (int i = 28; i >= 0; i -= 2) {
1432       raw_push(as_Register(i), as_Register(i+1));
1433   }
1434   mov_pc_to(tmp);
1435   str(tmp, Address(SP, 31*wordSize));
1436   ldr(tmp, Address(SP, tmp->encoding()*wordSize));
1437   return 32*wordSize;
1438 #else
1439   push(RegisterSet(R0, R12) | RegisterSet(LR) | RegisterSet(PC));
1440   return 15*wordSize;
1441 #endif // AARCH64
1442 }
1443 
1444 void MacroAssembler::restore_all_registers() {
1445 #ifdef AARCH64
1446   for (int i = 0; i <= 28; i += 2) {
1447     raw_pop(as_Register(i), as_Register(i+1));
1448   }
1449   raw_pop(R30, ZR);
1450 #else
1451   pop(RegisterSet(R0, R12) | RegisterSet(LR));   // restore registers
1452   add(SP, SP, wordSize);                         // discard saved PC
1453 #endif // AARCH64
1454 }
1455 
1456 int MacroAssembler::save_caller_save_registers() {
1457 #ifdef AARCH64
1458   for (int i = 0; i <= 16; i += 2) {
1459     raw_push(as_Register(i), as_Register(i+1));
1460   }
1461   raw_push(R18, LR);
1462   return 20*wordSize;
1463 #else
1464 #if R9_IS_SCRATCHED
1465   // Save also R10 to preserve alignment
1466   push(RegisterSet(R0, R3) | RegisterSet(R12) | RegisterSet(LR) | RegisterSet(R9,R10));
1467   return 8*wordSize;
1468 #else
1469   push(RegisterSet(R0, R3) | RegisterSet(R12) | RegisterSet(LR));
1470   return 6*wordSize;
1471 #endif
1472 #endif // AARCH64
1473 }
1474 
1475 void MacroAssembler::restore_caller_save_registers() {
1476 #ifdef AARCH64
1477   raw_pop(R18, LR);
1478   for (int i = 16; i >= 0; i -= 2) {
1479     raw_pop(as_Register(i), as_Register(i+1));
1480   }
1481 #else
1482 #if R9_IS_SCRATCHED
1483   pop(RegisterSet(R0, R3) | RegisterSet(R12) | RegisterSet(LR) | RegisterSet(R9,R10));
1484 #else
1485   pop(RegisterSet(R0, R3) | RegisterSet(R12) | RegisterSet(LR));
1486 #endif
1487 #endif // AARCH64
1488 }
1489 
1490 void MacroAssembler::debug(const char* msg, const intx* registers) {
1491   // In order to get locks to work, we need to fake a in_VM state
1492   JavaThread* thread = JavaThread::current();
1493   thread->set_thread_state(_thread_in_vm);
1494 
1495   if (ShowMessageBoxOnError) {
1496     ttyLocker ttyl;
1497     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1498       BytecodeCounter::print();
1499     }
1500     if (os::message_box(msg, "Execution stopped, print registers?")) {
1501 #ifdef AARCH64
1502       // saved registers: R0-R30, PC
1503       const int nregs = 32;
1504 #else
1505       // saved registers: R0-R12, LR, PC
1506       const int nregs = 15;
1507       const Register regs[nregs] = {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, PC};
1508 #endif // AARCH64
1509 
1510       for (int i = 0; i < nregs AARCH64_ONLY(-1); i++) {
1511         tty->print_cr("%s = " INTPTR_FORMAT, AARCH64_ONLY(as_Register(i)) NOT_AARCH64(regs[i])->name(), registers[i]);
1512       }
1513 
1514 #ifdef AARCH64
1515       tty->print_cr("pc = " INTPTR_FORMAT, registers[nregs-1]);
1516 #endif // AARCH64
1517 
1518       // derive original SP value from the address of register save area
1519       tty->print_cr("%s = " INTPTR_FORMAT, SP->name(), p2i(&registers[nregs]));
1520     }
1521     BREAKPOINT;
1522   } else {
1523     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
1524   }
1525   assert(false, "DEBUG MESSAGE: %s", msg);
1526   fatal("%s", msg); // returning from MacroAssembler::debug is not supported
1527 }
1528 
1529 void MacroAssembler::unimplemented(const char* what) {
1530   const char* buf = NULL;
1531   {
1532     ResourceMark rm;
1533     stringStream ss;
1534     ss.print("unimplemented: %s", what);
1535     buf = code_string(ss.as_string());
1536   }
1537   stop(buf);
1538 }
1539 
1540 
1541 // Implementation of FixedSizeCodeBlock
1542 
1543 FixedSizeCodeBlock::FixedSizeCodeBlock(MacroAssembler* masm, int size_in_instrs, bool enabled) :
1544 _masm(masm), _start(masm->pc()), _size_in_instrs(size_in_instrs), _enabled(enabled) {
1545 }
1546 
1547 FixedSizeCodeBlock::~FixedSizeCodeBlock() {
1548   if (_enabled) {
1549     address curr_pc = _masm->pc();
1550 
1551     assert(_start < curr_pc, "invalid current pc");
1552     guarantee(curr_pc <= _start + _size_in_instrs * Assembler::InstructionSize, "code block is too long");
1553 
1554     int nops_count = (_start - curr_pc) / Assembler::InstructionSize + _size_in_instrs;
1555     for (int i = 0; i < nops_count; i++) {
1556       _masm->nop();
1557     }
1558   }
1559 }
1560 
1561 #ifdef AARCH64
1562 
1563 // Serializes memory.
1564 // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM
1565 void MacroAssembler::membar(Membar_mask_bits order_constraint, Register tmp) {
1566   if (!os::is_MP()) return;
1567 
1568   // TODO-AARCH64 investigate dsb vs dmb effects
1569   if (order_constraint == StoreStore) {
1570     dmb(DMB_st);
1571   } else if ((order_constraint & ~(LoadLoad | LoadStore)) == 0) {
1572     dmb(DMB_ld);
1573   } else {
1574     dmb(DMB_all);
1575   }
1576 }
1577 
1578 #else
1579 
1580 // Serializes memory. Potentially blows flags and reg.
1581 // tmp is a scratch for v6 co-processor write op (could be noreg for other architecure versions)
1582 // preserve_flags takes a longer path in LoadStore case (dmb rather then control dependency) to preserve status flags. Optional.
1583 // load_tgt is an ordered load target in a LoadStore case only, to create dependency between the load operation and conditional branch. Optional.
1584 void MacroAssembler::membar(Membar_mask_bits order_constraint,
1585                             Register tmp,
1586                             bool preserve_flags,
1587                             Register load_tgt) {
1588   if (!os::is_MP()) return;
1589 
1590   if (order_constraint == StoreStore) {
1591     dmb(DMB_st, tmp);
1592   } else if ((order_constraint & StoreLoad)  ||
1593              (order_constraint & LoadLoad)   ||
1594              (order_constraint & StoreStore) ||
1595              (load_tgt == noreg)             ||
1596              preserve_flags) {
1597     dmb(DMB_all, tmp);
1598   } else {
1599     // LoadStore: speculative stores reordeing is prohibited
1600 
1601     // By providing an ordered load target register, we avoid an extra memory load reference
1602     Label not_taken;
1603     bind(not_taken);
1604     cmp(load_tgt, load_tgt);
1605     b(not_taken, ne);
1606   }
1607 }
1608 
1609 #endif // AARCH64
1610 
1611 // If "allow_fallthrough_on_failure" is false, we always branch to "slow_case"
1612 // on failure, so fall-through can only mean success.
1613 // "one_shot" controls whether we loop and retry to mitigate spurious failures.
1614 // This is only needed for C2, which for some reason does not rety,
1615 // while C1/interpreter does.
1616 // TODO: measure if it makes a difference
1617 
1618 void MacroAssembler::cas_for_lock_acquire(Register oldval, Register newval,
1619   Register base, Register tmp, Label &slow_case,
1620   bool allow_fallthrough_on_failure, bool one_shot)
1621 {
1622 
1623   bool fallthrough_is_success = false;
1624 
1625   // ARM Litmus Test example does prefetching here.
1626   // TODO: investigate if it helps performance
1627 
1628   // The last store was to the displaced header, so to prevent
1629   // reordering we must issue a StoreStore or Release barrier before
1630   // the CAS store.
1631 
1632 #ifdef AARCH64
1633 
1634   Register Rscratch = tmp;
1635   Register Roop = base;
1636   Register mark = oldval;
1637   Register Rbox = newval;
1638   Label loop;
1639 
1640   assert(oopDesc::mark_offset_in_bytes() == 0, "must be");
1641 
1642   // Instead of StoreStore here, we use store-release-exclusive below
1643 
1644   bind(loop);
1645 
1646   ldaxr(tmp, base);  // acquire
1647   cmp(tmp, oldval);
1648   b(slow_case, ne);
1649   stlxr(tmp, newval, base); // release
1650   if (one_shot) {
1651     cmp_w(tmp, 0);
1652   } else {
1653     cbnz_w(tmp, loop);
1654     fallthrough_is_success = true;
1655   }
1656 
1657   // MemBarAcquireLock would normally go here, but
1658   // we already do ldaxr+stlxr above, which has
1659   // Sequential Consistency
1660 
1661 #else
1662   membar(MacroAssembler::StoreStore, noreg);
1663 
1664   if (one_shot) {
1665     ldrex(tmp, Address(base, oopDesc::mark_offset_in_bytes()));
1666     cmp(tmp, oldval);
1667     strex(tmp, newval, Address(base, oopDesc::mark_offset_in_bytes()), eq);
1668     cmp(tmp, 0, eq);
1669   } else {
1670     atomic_cas_bool(oldval, newval, base, oopDesc::mark_offset_in_bytes(), tmp);
1671   }
1672 
1673   // MemBarAcquireLock barrier
1674   // According to JSR-133 Cookbook, this should be LoadLoad | LoadStore,
1675   // but that doesn't prevent a load or store from floating up between
1676   // the load and store in the CAS sequence, so play it safe and
1677   // do a full fence.
1678   membar(Membar_mask_bits(LoadLoad | LoadStore | StoreStore | StoreLoad), noreg);
1679 #endif
1680   if (!fallthrough_is_success && !allow_fallthrough_on_failure) {
1681     b(slow_case, ne);
1682   }
1683 }
1684 
1685 void MacroAssembler::cas_for_lock_release(Register oldval, Register newval,
1686   Register base, Register tmp, Label &slow_case,
1687   bool allow_fallthrough_on_failure, bool one_shot)
1688 {
1689 
1690   bool fallthrough_is_success = false;
1691 
1692   assert_different_registers(oldval,newval,base,tmp);
1693 
1694 #ifdef AARCH64
1695   Label loop;
1696 
1697   assert(oopDesc::mark_offset_in_bytes() == 0, "must be");
1698 
1699   bind(loop);
1700   ldxr(tmp, base);
1701   cmp(tmp, oldval);
1702   b(slow_case, ne);
1703   // MemBarReleaseLock barrier
1704   stlxr(tmp, newval, base);
1705   if (one_shot) {
1706     cmp_w(tmp, 0);
1707   } else {
1708     cbnz_w(tmp, loop);
1709     fallthrough_is_success = true;
1710   }
1711 #else
1712   // MemBarReleaseLock barrier
1713   // According to JSR-133 Cookbook, this should be StoreStore | LoadStore,
1714   // but that doesn't prevent a load or store from floating down between
1715   // the load and store in the CAS sequence, so play it safe and
1716   // do a full fence.
1717   membar(Membar_mask_bits(LoadLoad | LoadStore | StoreStore | StoreLoad), tmp);
1718 
1719   if (one_shot) {
1720     ldrex(tmp, Address(base, oopDesc::mark_offset_in_bytes()));
1721     cmp(tmp, oldval);
1722     strex(tmp, newval, Address(base, oopDesc::mark_offset_in_bytes()), eq);
1723     cmp(tmp, 0, eq);
1724   } else {
1725     atomic_cas_bool(oldval, newval, base, oopDesc::mark_offset_in_bytes(), tmp);
1726   }
1727 #endif
1728   if (!fallthrough_is_success && !allow_fallthrough_on_failure) {
1729     b(slow_case, ne);
1730   }
1731 
1732   // ExitEnter
1733   // According to JSR-133 Cookbook, this should be StoreLoad, the same
1734   // barrier that follows volatile store.
1735   // TODO: Should be able to remove on armv8 if volatile loads
1736   // use the load-acquire instruction.
1737   membar(StoreLoad, noreg);
1738 }
1739 
1740 #ifndef PRODUCT
1741 
1742 // Preserves flags and all registers.
1743 // On SMP the updated value might not be visible to external observers without a sychronization barrier
1744 void MacroAssembler::cond_atomic_inc32(AsmCondition cond, int* counter_addr) {
1745   if (counter_addr != NULL) {
1746     InlinedAddress counter_addr_literal((address)counter_addr);
1747     Label done, retry;
1748     if (cond != al) {
1749       b(done, inverse(cond));
1750     }
1751 
1752 #ifdef AARCH64
1753     raw_push(R0, R1);
1754     raw_push(R2, ZR);
1755 
1756     ldr_literal(R0, counter_addr_literal);
1757 
1758     bind(retry);
1759     ldxr_w(R1, R0);
1760     add_w(R1, R1, 1);
1761     stxr_w(R2, R1, R0);
1762     cbnz_w(R2, retry);
1763 
1764     raw_pop(R2, ZR);
1765     raw_pop(R0, R1);
1766 #else
1767     push(RegisterSet(R0, R3) | RegisterSet(Rtemp));
1768     ldr_literal(R0, counter_addr_literal);
1769 
1770     mrs(CPSR, Rtemp);
1771 
1772     bind(retry);
1773     ldr_s32(R1, Address(R0));
1774     add(R2, R1, 1);
1775     atomic_cas_bool(R1, R2, R0, 0, R3);
1776     b(retry, ne);
1777 
1778     msr(CPSR_fsxc, Rtemp);
1779 
1780     pop(RegisterSet(R0, R3) | RegisterSet(Rtemp));
1781 #endif // AARCH64
1782 
1783     b(done);
1784     bind_literal(counter_addr_literal);
1785 
1786     bind(done);
1787   }
1788 }
1789 
1790 #endif // !PRODUCT
1791 
1792 
1793 // Building block for CAS cases of biased locking: makes CAS and records statistics.
1794 // The slow_case label is used to transfer control if CAS fails. Otherwise leaves condition codes set.
1795 void MacroAssembler::biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
1796                                                  Register tmp, Label& slow_case, int* counter_addr) {
1797 
1798   cas_for_lock_acquire(old_mark_reg, new_mark_reg, obj_reg, tmp, slow_case);
1799 #ifdef ASSERT
1800   breakpoint(ne); // Fallthrough only on success
1801 #endif
1802 #ifndef PRODUCT
1803   if (counter_addr != NULL) {
1804     cond_atomic_inc32(al, counter_addr);
1805   }
1806 #endif // !PRODUCT
1807 }
1808 
1809 int MacroAssembler::biased_locking_enter(Register obj_reg, Register swap_reg, Register tmp_reg,
1810                                          bool swap_reg_contains_mark,
1811                                          Register tmp2,
1812                                          Label& done, Label& slow_case,
1813                                          BiasedLockingCounters* counters) {
1814   // obj_reg must be preserved (at least) if the bias locking fails
1815   // tmp_reg is a temporary register
1816   // swap_reg was used as a temporary but contained a value
1817   //   that was used afterwards in some call pathes. Callers
1818   //   have been fixed so that swap_reg no longer needs to be
1819   //   saved.
1820   // Rtemp in no longer scratched
1821 
1822   assert(UseBiasedLocking, "why call this otherwise?");
1823   assert_different_registers(obj_reg, swap_reg, tmp_reg, tmp2);
1824   guarantee(swap_reg!=tmp_reg, "invariant");
1825   assert(tmp_reg != noreg, "must supply tmp_reg");
1826 
1827 #ifndef PRODUCT
1828   if (PrintBiasedLockingStatistics && (counters == NULL)) {
1829     counters = BiasedLocking::counters();
1830   }
1831 #endif
1832 
1833   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1834   Address mark_addr(obj_reg, oopDesc::mark_offset_in_bytes());
1835 
1836   // Biased locking
1837   // See whether the lock is currently biased toward our thread and
1838   // whether the epoch is still valid
1839   // Note that the runtime guarantees sufficient alignment of JavaThread
1840   // pointers to allow age to be placed into low bits
1841   // First check to see whether biasing is even enabled for this object
1842   Label cas_label;
1843 
1844   // The null check applies to the mark loading, if we need to load it.
1845   // If the mark has already been loaded in swap_reg then it has already
1846   // been performed and the offset is irrelevant.
1847   int null_check_offset = offset();
1848   if (!swap_reg_contains_mark) {
1849     ldr(swap_reg, mark_addr);
1850   }
1851 
1852   // On MP platform loads could return 'stale' values in some cases.
1853   // That is acceptable since either CAS or slow case path is taken in the worst case.
1854 
1855   andr(tmp_reg, swap_reg, (uintx)markOopDesc::biased_lock_mask_in_place);
1856   cmp(tmp_reg, markOopDesc::biased_lock_pattern);
1857 
1858   b(cas_label, ne);
1859 
1860   // The bias pattern is present in the object's header. Need to check
1861   // whether the bias owner and the epoch are both still current.
1862   load_klass(tmp_reg, obj_reg);
1863   ldr(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset()));
1864   orr(tmp_reg, tmp_reg, Rthread);
1865   eor(tmp_reg, tmp_reg, swap_reg);
1866 
1867 #ifdef AARCH64
1868   ands(tmp_reg, tmp_reg, ~((uintx) markOopDesc::age_mask_in_place));
1869 #else
1870   bics(tmp_reg, tmp_reg, ((int) markOopDesc::age_mask_in_place));
1871 #endif // AARCH64
1872 
1873 #ifndef PRODUCT
1874   if (counters != NULL) {
1875     cond_atomic_inc32(eq, counters->biased_lock_entry_count_addr());
1876   }
1877 #endif // !PRODUCT
1878 
1879   b(done, eq);
1880 
1881   Label try_revoke_bias;
1882   Label try_rebias;
1883 
1884   // At this point we know that the header has the bias pattern and
1885   // that we are not the bias owner in the current epoch. We need to
1886   // figure out more details about the state of the header in order to
1887   // know what operations can be legally performed on the object's
1888   // header.
1889 
1890   // If the low three bits in the xor result aren't clear, that means
1891   // the prototype header is no longer biased and we have to revoke
1892   // the bias on this object.
1893   tst(tmp_reg, (uintx)markOopDesc::biased_lock_mask_in_place);
1894   b(try_revoke_bias, ne);
1895 
1896   // Biasing is still enabled for this data type. See whether the
1897   // epoch of the current bias is still valid, meaning that the epoch
1898   // bits of the mark word are equal to the epoch bits of the
1899   // prototype header. (Note that the prototype header's epoch bits
1900   // only change at a safepoint.) If not, attempt to rebias the object
1901   // toward the current thread. Note that we must be absolutely sure
1902   // that the current epoch is invalid in order to do this because
1903   // otherwise the manipulations it performs on the mark word are
1904   // illegal.
1905   tst(tmp_reg, (uintx)markOopDesc::epoch_mask_in_place);
1906   b(try_rebias, ne);
1907 
1908   // tmp_reg has the age, epoch and pattern bits cleared
1909   // The remaining (owner) bits are (Thread ^ current_owner)
1910 
1911   // The epoch of the current bias is still valid but we know nothing
1912   // about the owner; it might be set or it might be clear. Try to
1913   // acquire the bias of the object using an atomic operation. If this
1914   // fails we will go in to the runtime to revoke the object's bias.
1915   // Note that we first construct the presumed unbiased header so we
1916   // don't accidentally blow away another thread's valid bias.
1917 
1918   // Note that we know the owner is not ourself. Hence, success can
1919   // only happen when the owner bits is 0
1920 
1921 #ifdef AARCH64
1922   // Bit mask biased_lock + age + epoch is not a valid AArch64 logical immediate, as it has
1923   // cleared bit in the middle (cms bit). So it is loaded with separate instruction.
1924   mov(tmp2, (markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place));
1925   andr(swap_reg, swap_reg, tmp2);
1926 #else
1927   // until the assembler can be made smarter, we need to make some assumptions about the values
1928   // so we can optimize this:
1929   assert((markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place) == 0x1ff, "biased bitmasks changed");
1930 
1931   mov(swap_reg, AsmOperand(swap_reg, lsl, 23));
1932   mov(swap_reg, AsmOperand(swap_reg, lsr, 23)); // markOop with thread bits cleared (for CAS)
1933 #endif // AARCH64
1934 
1935   orr(tmp_reg, swap_reg, Rthread); // new mark
1936 
1937   biased_locking_enter_with_cas(obj_reg, swap_reg, tmp_reg, tmp2, slow_case,
1938         (counters != NULL) ? counters->anonymously_biased_lock_entry_count_addr() : NULL);
1939 
1940   // If the biasing toward our thread failed, this means that
1941   // another thread succeeded in biasing it toward itself and we
1942   // need to revoke that bias. The revocation will occur in the
1943   // interpreter runtime in the slow case.
1944 
1945   b(done);
1946 
1947   bind(try_rebias);
1948 
1949   // At this point we know the epoch has expired, meaning that the
1950   // current "bias owner", if any, is actually invalid. Under these
1951   // circumstances _only_, we are allowed to use the current header's
1952   // value as the comparison value when doing the cas to acquire the
1953   // bias in the current epoch. In other words, we allow transfer of
1954   // the bias from one thread to another directly in this situation.
1955 
1956   // tmp_reg low (not owner) bits are (age: 0 | pattern&epoch: prototype^swap_reg)
1957 
1958   eor(tmp_reg, tmp_reg, swap_reg); // OK except for owner bits (age preserved !)
1959 
1960   // owner bits 'random'. Set them to Rthread.
1961 #ifdef AARCH64
1962   mov(tmp2, (markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place));
1963   andr(tmp_reg, tmp_reg, tmp2);
1964 #else
1965   mov(tmp_reg, AsmOperand(tmp_reg, lsl, 23));
1966   mov(tmp_reg, AsmOperand(tmp_reg, lsr, 23));
1967 #endif // AARCH64
1968 
1969   orr(tmp_reg, tmp_reg, Rthread); // new mark
1970 
1971   biased_locking_enter_with_cas(obj_reg, swap_reg, tmp_reg, tmp2, slow_case,
1972         (counters != NULL) ? counters->rebiased_lock_entry_count_addr() : NULL);
1973 
1974   // If the biasing toward our thread failed, then another thread
1975   // succeeded in biasing it toward itself and we need to revoke that
1976   // bias. The revocation will occur in the runtime in the slow case.
1977 
1978   b(done);
1979 
1980   bind(try_revoke_bias);
1981 
1982   // The prototype mark in the klass doesn't have the bias bit set any
1983   // more, indicating that objects of this data type are not supposed
1984   // to be biased any more. We are going to try to reset the mark of
1985   // this object to the prototype value and fall through to the
1986   // CAS-based locking scheme. Note that if our CAS fails, it means
1987   // that another thread raced us for the privilege of revoking the
1988   // bias of this particular object, so it's okay to continue in the
1989   // normal locking code.
1990 
1991   // tmp_reg low (not owner) bits are (age: 0 | pattern&epoch: prototype^swap_reg)
1992 
1993   eor(tmp_reg, tmp_reg, swap_reg); // OK except for owner bits (age preserved !)
1994 
1995   // owner bits 'random'. Clear them
1996 #ifdef AARCH64
1997   mov(tmp2, (markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place));
1998   andr(tmp_reg, tmp_reg, tmp2);
1999 #else
2000   mov(tmp_reg, AsmOperand(tmp_reg, lsl, 23));
2001   mov(tmp_reg, AsmOperand(tmp_reg, lsr, 23));
2002 #endif // AARCH64
2003 
2004   biased_locking_enter_with_cas(obj_reg, swap_reg, tmp_reg, tmp2, cas_label,
2005         (counters != NULL) ? counters->revoked_lock_entry_count_addr() : NULL);
2006 
2007   // Fall through to the normal CAS-based lock, because no matter what
2008   // the result of the above CAS, some thread must have succeeded in
2009   // removing the bias bit from the object's header.
2010 
2011   bind(cas_label);
2012 
2013   return null_check_offset;
2014 }
2015 
2016 
2017 void MacroAssembler::biased_locking_exit(Register obj_reg, Register tmp_reg, Label& done) {
2018   assert(UseBiasedLocking, "why call this otherwise?");
2019 
2020   // Check for biased locking unlock case, which is a no-op
2021   // Note: we do not have to check the thread ID for two reasons.
2022   // First, the interpreter checks for IllegalMonitorStateException at
2023   // a higher level. Second, if the bias was revoked while we held the
2024   // lock, the object could not be rebiased toward another thread, so
2025   // the bias bit would be clear.
2026   ldr(tmp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2027 
2028   andr(tmp_reg, tmp_reg, (uintx)markOopDesc::biased_lock_mask_in_place);
2029   cmp(tmp_reg, markOopDesc::biased_lock_pattern);
2030   b(done, eq);
2031 }
2032 
2033 
2034 void MacroAssembler::resolve_jobject(Register value,
2035                                      Register tmp1,
2036                                      Register tmp2) {
2037   assert_different_registers(value, tmp1, tmp2);
2038   Label done, not_weak;
2039   cbz(value, done);             // Use NULL as-is.
2040   STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u);
2041   tbz(value, 0, not_weak);      // Test for jweak tag.
2042 
2043   // Resolve jweak.
2044   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
2045                  Address(value, -JNIHandles::weak_tag_value), value, tmp1, tmp2, noreg);
2046   b(done);
2047   bind(not_weak);
2048   // Resolve (untagged) jobject.
2049   access_load_at(T_OBJECT, IN_NATIVE,
2050                  Address(value, 0), value, tmp1, tmp2, noreg);
2051   verify_oop(value);
2052   bind(done);
2053 }
2054 
2055 
2056 //////////////////////////////////////////////////////////////////////////////////
2057 
2058 #ifdef AARCH64
2059 
2060 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2061   switch (size_in_bytes) {
2062     case  8: ldr(dst, src); break;
2063     case  4: is_signed ? ldr_s32(dst, src) : ldr_u32(dst, src); break;
2064     case  2: is_signed ? ldrsh(dst, src) : ldrh(dst, src); break;
2065     case  1: is_signed ? ldrsb(dst, src) : ldrb(dst, src); break;
2066     default: ShouldNotReachHere();
2067   }
2068 }
2069 
2070 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
2071   switch (size_in_bytes) {
2072     case  8: str(src, dst);    break;
2073     case  4: str_32(src, dst); break;
2074     case  2: strh(src, dst);   break;
2075     case  1: strb(src, dst);   break;
2076     default: ShouldNotReachHere();
2077   }
2078 }
2079 
2080 #else
2081 
2082 void MacroAssembler::load_sized_value(Register dst, Address src,
2083                                     size_t size_in_bytes, bool is_signed, AsmCondition cond) {
2084   switch (size_in_bytes) {
2085     case  4: ldr(dst, src, cond); break;
2086     case  2: is_signed ? ldrsh(dst, src, cond) : ldrh(dst, src, cond); break;
2087     case  1: is_signed ? ldrsb(dst, src, cond) : ldrb(dst, src, cond); break;
2088     default: ShouldNotReachHere();
2089   }
2090 }
2091 
2092 
2093 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes, AsmCondition cond) {
2094   switch (size_in_bytes) {
2095     case  4: str(src, dst, cond); break;
2096     case  2: strh(src, dst, cond);   break;
2097     case  1: strb(src, dst, cond);   break;
2098     default: ShouldNotReachHere();
2099   }
2100 }
2101 #endif // AARCH64
2102 
2103 // Look up the method for a megamorphic invokeinterface call.
2104 // The target method is determined by <Rinterf, Rindex>.
2105 // The receiver klass is in Rklass.
2106 // On success, the result will be in method_result, and execution falls through.
2107 // On failure, execution transfers to the given label.
2108 void MacroAssembler::lookup_interface_method(Register Rklass,
2109                                              Register Rintf,
2110                                              RegisterOrConstant itable_index,
2111                                              Register method_result,
2112                                              Register Rscan,
2113                                              Register Rtmp,
2114                                              Label& L_no_such_interface) {
2115 
2116   assert_different_registers(Rklass, Rintf, Rscan, Rtmp);
2117 
2118   const int entry_size = itableOffsetEntry::size() * HeapWordSize;
2119   assert(itableOffsetEntry::interface_offset_in_bytes() == 0, "not added for convenience");
2120 
2121   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2122   const int base = in_bytes(Klass::vtable_start_offset());
2123   const int scale = exact_log2(vtableEntry::size_in_bytes());
2124   ldr_s32(Rtmp, Address(Rklass, Klass::vtable_length_offset())); // Get length of vtable
2125   add(Rscan, Rklass, base);
2126   add(Rscan, Rscan, AsmOperand(Rtmp, lsl, scale));
2127 
2128   // Search through the itable for an interface equal to incoming Rintf
2129   // itable looks like [intface][offset][intface][offset][intface][offset]
2130 
2131   Label loop;
2132   bind(loop);
2133   ldr(Rtmp, Address(Rscan, entry_size, post_indexed));
2134 #ifdef AARCH64
2135   Label found;
2136   cmp(Rtmp, Rintf);
2137   b(found, eq);
2138   cbnz(Rtmp, loop);
2139 #else
2140   cmp(Rtmp, Rintf);  // set ZF and CF if interface is found
2141   cmn(Rtmp, 0, ne);  // check if tmp == 0 and clear CF if it is
2142   b(loop, ne);
2143 #endif // AARCH64
2144 
2145 #ifdef AARCH64
2146   b(L_no_such_interface);
2147   bind(found);
2148 #else
2149   // CF == 0 means we reached the end of itable without finding icklass
2150   b(L_no_such_interface, cc);
2151 #endif // !AARCH64
2152 
2153   if (method_result != noreg) {
2154     // Interface found at previous position of Rscan, now load the method
2155     ldr_s32(Rtmp, Address(Rscan, itableOffsetEntry::offset_offset_in_bytes() - entry_size));
2156     if (itable_index.is_register()) {
2157       add(Rtmp, Rtmp, Rklass); // Add offset to Klass*
2158       assert(itableMethodEntry::size() * HeapWordSize == wordSize, "adjust the scaling in the code below");
2159       assert(itableMethodEntry::method_offset_in_bytes() == 0, "adjust the offset in the code below");
2160       ldr(method_result, Address::indexed_ptr(Rtmp, itable_index.as_register()));
2161     } else {
2162       int method_offset = itableMethodEntry::size() * HeapWordSize * itable_index.as_constant() +
2163                           itableMethodEntry::method_offset_in_bytes();
2164       add_slow(method_result, Rklass, method_offset);
2165       ldr(method_result, Address(method_result, Rtmp));
2166     }
2167   }
2168 }
2169 
2170 #ifdef COMPILER2
2171 // TODO: 8 bytes at a time? pre-fetch?
2172 // Compare char[] arrays aligned to 4 bytes.
2173 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
2174                                         Register limit, Register result,
2175                                       Register chr1, Register chr2, Label& Ldone) {
2176   Label Lvector, Lloop;
2177 
2178   // if (ary1 == ary2)
2179   //     return true; 
2180   cmpoop(ary1, ary2);
2181   b(Ldone, eq);
2182 
2183   // Note: limit contains number of bytes (2*char_elements) != 0.
2184   tst(limit, 0x2); // trailing character ?
2185   b(Lvector, eq);
2186 
2187   // compare the trailing char
2188   sub(limit, limit, sizeof(jchar));
2189   ldrh(chr1, Address(ary1, limit));
2190   ldrh(chr2, Address(ary2, limit));
2191   cmp(chr1, chr2);
2192   mov(result, 0, ne);     // not equal
2193   b(Ldone, ne);
2194 
2195   // only one char ?
2196   tst(limit, limit);
2197   mov(result, 1, eq);
2198   b(Ldone, eq);
2199 
2200   // word by word compare, dont't need alignment check
2201   bind(Lvector);
2202 
2203   // Shift ary1 and ary2 to the end of the arrays, negate limit
2204   add(ary1, limit, ary1);
2205   add(ary2, limit, ary2);
2206   neg(limit, limit);
2207 
2208   bind(Lloop);
2209   ldr_u32(chr1, Address(ary1, limit));
2210   ldr_u32(chr2, Address(ary2, limit));
2211   cmp_32(chr1, chr2);
2212   mov(result, 0, ne);     // not equal
2213   b(Ldone, ne);
2214   adds(limit, limit, 2*sizeof(jchar));
2215   b(Lloop, ne);
2216 
2217   // Caller should set it:
2218   // mov(result_reg, 1);  //equal
2219 }
2220 #endif
2221 
2222 void MacroAssembler::inc_counter(address counter_addr, Register tmpreg1, Register tmpreg2) {
2223   mov_slow(tmpreg1, counter_addr);
2224   ldr_s32(tmpreg2, tmpreg1);
2225   add_32(tmpreg2, tmpreg2, 1);
2226   str_32(tmpreg2, tmpreg1);
2227 }
2228 
2229 void MacroAssembler::floating_cmp(Register dst) {
2230 #ifdef AARCH64
2231   NOT_TESTED();
2232   cset(dst, gt);            // 1 if '>', else 0
2233   csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
2234 #else
2235   vmrs(dst, FPSCR);
2236   orr(dst, dst, 0x08000000);
2237   eor(dst, dst, AsmOperand(dst, lsl, 3));
2238   mov(dst, AsmOperand(dst, asr, 30));
2239 #endif
2240 }
2241 
2242 void MacroAssembler::restore_default_fp_mode() {
2243 #ifdef AARCH64
2244   msr(SysReg_FPCR, ZR);
2245 #else
2246 #ifndef __SOFTFP__
2247   // Round to Near mode, IEEE compatible, masked exceptions
2248   mov(Rtemp, 0);
2249   vmsr(FPSCR, Rtemp);
2250 #endif // !__SOFTFP__
2251 #endif // AARCH64
2252 }
2253 
2254 #ifndef AARCH64
2255 // 24-bit word range == 26-bit byte range
2256 bool check26(int offset) {
2257   // this could be simplified, but it mimics encoding and decoding
2258   // an actual branch insrtuction
2259   int off1 = offset << 6 >> 8;
2260   int encoded = off1 & ((1<<24)-1);
2261   int decoded = encoded << 8 >> 6;
2262   return offset == decoded;
2263 }
2264 #endif // !AARCH64
2265 
2266 // Perform some slight adjustments so the default 32MB code cache
2267 // is fully reachable.
2268 static inline address first_cache_address() {
2269   return CodeCache::low_bound() + sizeof(HeapBlock::Header);
2270 }
2271 static inline address last_cache_address() {
2272   return CodeCache::high_bound() - Assembler::InstructionSize;
2273 }
2274 
2275 #ifdef AARCH64
2276 // Can we reach target using ADRP?
2277 bool MacroAssembler::page_reachable_from_cache(address target) {
2278   intptr_t cl = (intptr_t)first_cache_address() & ~0xfff;
2279   intptr_t ch = (intptr_t)last_cache_address() & ~0xfff;
2280   intptr_t addr = (intptr_t)target & ~0xfff;
2281 
2282   intptr_t loffset = addr - cl;
2283   intptr_t hoffset = addr - ch;
2284   return is_imm_in_range(loffset >> 12, 21, 0) && is_imm_in_range(hoffset >> 12, 21, 0);
2285 }
2286 #endif
2287 
2288 // Can we reach target using unconditional branch or call from anywhere
2289 // in the code cache (because code can be relocated)?
2290 bool MacroAssembler::_reachable_from_cache(address target) {
2291 #ifdef __thumb__
2292   if ((1 & (intptr_t)target) != 0) {
2293     // Return false to avoid 'b' if we need switching to THUMB mode.
2294     return false;
2295   }
2296 #endif
2297 
2298   address cl = first_cache_address();
2299   address ch = last_cache_address();
2300 
2301   if (ForceUnreachable) {
2302     // Only addresses from CodeCache can be treated as reachable.
2303     if (target < CodeCache::low_bound() || CodeCache::high_bound() < target) {
2304       return false;
2305     }
2306   }
2307 
2308   intptr_t loffset = (intptr_t)target - (intptr_t)cl;
2309   intptr_t hoffset = (intptr_t)target - (intptr_t)ch;
2310 
2311 #ifdef AARCH64
2312   return is_offset_in_range(loffset, 26) && is_offset_in_range(hoffset, 26);
2313 #else
2314   return check26(loffset - 8) && check26(hoffset - 8);
2315 #endif
2316 }
2317 
2318 bool MacroAssembler::reachable_from_cache(address target) {
2319   assert(CodeCache::contains(pc()), "not supported");
2320   return _reachable_from_cache(target);
2321 }
2322 
2323 // Can we reach the entire code cache from anywhere else in the code cache?
2324 bool MacroAssembler::_cache_fully_reachable() {
2325   address cl = first_cache_address();
2326   address ch = last_cache_address();
2327   return _reachable_from_cache(cl) && _reachable_from_cache(ch);
2328 }
2329 
2330 bool MacroAssembler::cache_fully_reachable() {
2331   assert(CodeCache::contains(pc()), "not supported");
2332   return _cache_fully_reachable();
2333 }
2334 
2335 void MacroAssembler::jump(address target, relocInfo::relocType rtype, Register scratch NOT_AARCH64_ARG(AsmCondition cond)) {
2336   assert((rtype == relocInfo::runtime_call_type) || (rtype == relocInfo::none), "not supported");
2337   if (reachable_from_cache(target)) {
2338     relocate(rtype);
2339     b(target NOT_AARCH64_ARG(cond));
2340     return;
2341   }
2342 
2343   // Note: relocate is not needed for the code below,
2344   // encoding targets in absolute format.
2345   if (ignore_non_patchable_relocations()) {
2346     rtype = relocInfo::none;
2347   }
2348 
2349 #ifdef AARCH64
2350   assert (scratch != noreg, "should be specified");
2351   InlinedAddress address_literal(target, rtype);
2352   ldr_literal(scratch, address_literal);
2353   br(scratch);
2354   int off = offset();
2355   bind_literal(address_literal);
2356 #ifdef COMPILER2
2357   if (offset() - off == wordSize) {
2358     // no padding, so insert nop for worst-case sizing
2359     nop();
2360   }
2361 #endif
2362 #else
2363   if (VM_Version::supports_movw() && (scratch != noreg) && (rtype == relocInfo::none)) {
2364     // Note: this version cannot be (atomically) patched
2365     mov_slow(scratch, (intptr_t)target, cond);
2366     bx(scratch, cond);
2367   } else {
2368     Label skip;
2369     InlinedAddress address_literal(target);
2370     if (cond != al) {
2371       b(skip, inverse(cond));
2372     }
2373     relocate(rtype);
2374     ldr_literal(PC, address_literal);
2375     bind_literal(address_literal);
2376     bind(skip);
2377   }
2378 #endif // AARCH64
2379 }
2380 
2381 // Similar to jump except that:
2382 // - near calls are valid only if any destination in the cache is near
2383 // - no movt/movw (not atomically patchable)
2384 void MacroAssembler::patchable_jump(address target, relocInfo::relocType rtype, Register scratch NOT_AARCH64_ARG(AsmCondition cond)) {
2385   assert((rtype == relocInfo::runtime_call_type) || (rtype == relocInfo::none), "not supported");
2386   if (cache_fully_reachable()) {
2387     // Note: this assumes that all possible targets (the initial one
2388     // and the addressed patched to) are all in the code cache.
2389     assert(CodeCache::contains(target), "target might be too far");
2390     relocate(rtype);
2391     b(target NOT_AARCH64_ARG(cond));
2392     return;
2393   }
2394 
2395   // Discard the relocation information if not needed for CacheCompiledCode
2396   // since the next encodings are all in absolute format.
2397   if (ignore_non_patchable_relocations()) {
2398     rtype = relocInfo::none;
2399   }
2400 
2401 #ifdef AARCH64
2402   assert (scratch != noreg, "should be specified");
2403   InlinedAddress address_literal(target);
2404   relocate(rtype);
2405   ldr_literal(scratch, address_literal);
2406   br(scratch);
2407   int off = offset();
2408   bind_literal(address_literal);
2409 #ifdef COMPILER2
2410   if (offset() - off == wordSize) {
2411     // no padding, so insert nop for worst-case sizing
2412     nop();
2413   }
2414 #endif
2415 #else
2416   {
2417     Label skip;
2418     InlinedAddress address_literal(target);
2419     if (cond != al) {
2420       b(skip, inverse(cond));
2421     }
2422     relocate(rtype);
2423     ldr_literal(PC, address_literal);
2424     bind_literal(address_literal);
2425     bind(skip);
2426   }
2427 #endif // AARCH64
2428 }
2429 
2430 void MacroAssembler::call(address target, RelocationHolder rspec NOT_AARCH64_ARG(AsmCondition cond)) {
2431   Register scratch = LR;
2432   assert(rspec.type() == relocInfo::runtime_call_type || rspec.type() == relocInfo::none, "not supported");
2433   if (reachable_from_cache(target)) {
2434     relocate(rspec);
2435     bl(target NOT_AARCH64_ARG(cond));
2436     return;
2437   }
2438 
2439   // Note: relocate is not needed for the code below,
2440   // encoding targets in absolute format.
2441   if (ignore_non_patchable_relocations()) {
2442     // This assumes the information was needed only for relocating the code.
2443     rspec = RelocationHolder::none;
2444   }
2445 
2446 #ifndef AARCH64
2447   if (VM_Version::supports_movw() && (rspec.type() == relocInfo::none)) {
2448     // Note: this version cannot be (atomically) patched
2449     mov_slow(scratch, (intptr_t)target, cond);
2450     blx(scratch, cond);
2451     return;
2452   }
2453 #endif
2454 
2455   {
2456     Label ret_addr;
2457 #ifndef AARCH64
2458     if (cond != al) {
2459       b(ret_addr, inverse(cond));
2460     }
2461 #endif
2462 
2463 
2464 #ifdef AARCH64
2465     // TODO-AARCH64: make more optimal implementation
2466     // [ Keep in sync with MacroAssembler::call_size ]
2467     assert(rspec.type() == relocInfo::none, "call reloc not implemented");
2468     mov_slow(scratch, target);
2469     blr(scratch);
2470 #else
2471     InlinedAddress address_literal(target);
2472     relocate(rspec);
2473     adr(LR, ret_addr);
2474     ldr_literal(PC, address_literal);
2475 
2476     bind_literal(address_literal);
2477     bind(ret_addr);
2478 #endif
2479   }
2480 }
2481 
2482 #if defined(AARCH64) && defined(COMPILER2)
2483 int MacroAssembler::call_size(address target, bool far, bool patchable) {
2484   // FIXME: mov_slow is variable-length
2485   if (!far) return 1; // bl
2486   if (patchable) return 2;  // ldr; blr
2487   return instr_count_for_mov_slow((intptr_t)target) + 1;
2488 }
2489 #endif
2490 
2491 int MacroAssembler::patchable_call(address target, RelocationHolder const& rspec, bool c2) {
2492   assert(rspec.type() == relocInfo::static_call_type ||
2493          rspec.type() == relocInfo::none ||
2494          rspec.type() == relocInfo::opt_virtual_call_type, "not supported");
2495 
2496   // Always generate the relocation information, needed for patching
2497   relocate(rspec); // used by NativeCall::is_call_before()
2498   if (cache_fully_reachable()) {
2499     // Note: this assumes that all possible targets (the initial one
2500     // and the addresses patched to) are all in the code cache.
2501     assert(CodeCache::contains(target), "target might be too far");
2502     bl(target);
2503   } else {
2504 #if defined(AARCH64) && defined(COMPILER2)
2505     if (c2) {
2506       // return address needs to match call_size().
2507       // no need to trash Rtemp
2508       int off = offset();
2509       Label skip_literal;
2510       InlinedAddress address_literal(target);
2511       ldr_literal(LR, address_literal);
2512       blr(LR);
2513       int ret_addr_offset = offset();
2514       assert(offset() - off == call_size(target, true, true) * InstructionSize, "need to fix call_size()");
2515       b(skip_literal);
2516       int off2 = offset();
2517       bind_literal(address_literal);
2518       if (offset() - off2 == wordSize) {
2519         // no padding, so insert nop for worst-case sizing
2520         nop();
2521       }
2522       bind(skip_literal);
2523       return ret_addr_offset;
2524     }
2525 #endif
2526     Label ret_addr;
2527     InlinedAddress address_literal(target);
2528 #ifdef AARCH64
2529     ldr_literal(Rtemp, address_literal);
2530     adr(LR, ret_addr);
2531     br(Rtemp);
2532 #else
2533     adr(LR, ret_addr);
2534     ldr_literal(PC, address_literal);
2535 #endif
2536     bind_literal(address_literal);
2537     bind(ret_addr);
2538   }
2539   return offset();
2540 }
2541 
2542 // ((OopHandle)result).resolve();
2543 void MacroAssembler::resolve_oop_handle(Register result) {
2544   // OopHandle::resolve is an indirection.
2545   ldr(result, Address(result, 0));
2546 }
2547 
2548 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
2549   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
2550   ldr(tmp, Address(method, Method::const_offset()));
2551   ldr(tmp, Address(tmp,  ConstMethod::constants_offset()));
2552   ldr(tmp, Address(tmp, ConstantPool::pool_holder_offset_in_bytes()));
2553   ldr(mirror, Address(tmp, mirror_offset));
2554   resolve_oop_handle(mirror);
2555 }
2556 
2557 
2558 ///////////////////////////////////////////////////////////////////////////////
2559 
2560 // Compressed pointers
2561 
2562 #ifdef AARCH64
2563 
2564 void MacroAssembler::load_klass(Register dst_klass, Register src_oop) {
2565   if (UseCompressedClassPointers) {
2566     ldr_w(dst_klass, Address(src_oop, oopDesc::klass_offset_in_bytes()));
2567     decode_klass_not_null(dst_klass);
2568   } else {
2569     ldr(dst_klass, Address(src_oop, oopDesc::klass_offset_in_bytes()));
2570   }
2571 }
2572 
2573 #else
2574 
2575 void MacroAssembler::load_klass(Register dst_klass, Register src_oop, AsmCondition cond) {
2576   ldr(dst_klass, Address(src_oop, oopDesc::klass_offset_in_bytes()), cond);
2577 }
2578 
2579 #endif // AARCH64
2580 
2581 // Blows src_klass.
2582 void MacroAssembler::store_klass(Register src_klass, Register dst_oop) {
2583 #ifdef AARCH64
2584   if (UseCompressedClassPointers) {
2585     assert(src_klass != dst_oop, "not enough registers");
2586     encode_klass_not_null(src_klass);
2587     str_w(src_klass, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
2588     return;
2589   }
2590 #endif // AARCH64
2591   str(src_klass, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
2592 }
2593 
2594 #ifdef AARCH64
2595 
2596 void MacroAssembler::store_klass_gap(Register dst) {
2597   if (UseCompressedClassPointers) {
2598     str_w(ZR, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
2599   }
2600 }
2601 
2602 #endif // AARCH64
2603 
2604 
2605 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, Register tmp2, Register tmp3, DecoratorSet decorators) {
2606   access_load_at(T_OBJECT, IN_HEAP | decorators, src, dst, tmp1, tmp2, tmp3);
2607 }
2608 
2609 // Blows src and flags.
2610 void MacroAssembler::store_heap_oop(Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, DecoratorSet decorators) {
2611   access_store_at(T_OBJECT, IN_HEAP | decorators, obj, new_val, tmp1, tmp2, tmp3, false);
2612 }
2613 
2614 void MacroAssembler::store_heap_oop_null(Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, DecoratorSet decorators) {
2615   access_store_at(T_OBJECT, IN_HEAP, obj, new_val, tmp1, tmp2, tmp3, true);
2616 }
2617 
2618 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
2619                                     Address src, Register dst, Register tmp1, Register tmp2, Register tmp3) {
2620   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2621   decorators = AccessInternal::decorator_fixup(decorators);
2622   bool as_raw = (decorators & AS_RAW) != 0;
2623   if (as_raw) {
2624     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
2625   } else {
2626     bs->load_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
2627   }
2628 }
2629 
2630 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
2631                                      Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, bool is_null) {
2632   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2633   decorators = AccessInternal::decorator_fixup(decorators);
2634   bool as_raw = (decorators & AS_RAW) != 0;
2635   if (as_raw) {
2636     bs->BarrierSetAssembler::store_at(this, decorators, type, obj, new_val, tmp1, tmp2, tmp3, is_null);
2637   } else {
2638     bs->store_at(this, decorators, type, obj, new_val, tmp1, tmp2, tmp3, is_null);
2639   }
2640 }
2641 
2642 
2643 #ifdef AARCH64
2644 
2645 // Algorithm must match oop.inline.hpp encode_heap_oop.
2646 void MacroAssembler::encode_heap_oop(Register dst, Register src) {
2647   // This code pattern is matched in NativeIntruction::skip_encode_heap_oop.
2648   // Update it at modifications.
2649   assert (UseCompressedOops, "must be compressed");
2650   assert (Universe::heap() != NULL, "java heap should be initialized");
2651 #ifdef ASSERT
2652   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
2653 #endif
2654   verify_oop(src);
2655   if (Universe::narrow_oop_base() == NULL) {
2656     if (Universe::narrow_oop_shift() != 0) {
2657       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2658       _lsr(dst, src, Universe::narrow_oop_shift());
2659     } else if (dst != src) {
2660       mov(dst, src);
2661     }
2662   } else {
2663     tst(src, src);
2664     csel(dst, Rheap_base, src, eq);
2665     sub(dst, dst, Rheap_base);
2666     if (Universe::narrow_oop_shift() != 0) {
2667       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2668       _lsr(dst, dst, Universe::narrow_oop_shift());
2669     }
2670   }
2671 }
2672 
2673 // Same algorithm as oop.inline.hpp decode_heap_oop.
2674 void MacroAssembler::decode_heap_oop(Register dst, Register src) {
2675 #ifdef ASSERT
2676   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
2677 #endif
2678   assert(Universe::narrow_oop_shift() == 0 || LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2679   if (Universe::narrow_oop_base() != NULL) {
2680     tst(src, src);
2681     add(dst, Rheap_base, AsmOperand(src, lsl, Universe::narrow_oop_shift()));
2682     csel(dst, dst, ZR, ne);
2683   } else {
2684     _lsl(dst, src, Universe::narrow_oop_shift());
2685   }
2686   verify_oop(dst);
2687 }
2688 
2689 #ifdef COMPILER2
2690 // Algorithm must match oop.inline.hpp encode_heap_oop.
2691 // Must preserve condition codes, or C2 encodeHeapOop_not_null rule
2692 // must be changed.
2693 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
2694   assert (UseCompressedOops, "must be compressed");
2695   assert (Universe::heap() != NULL, "java heap should be initialized");
2696 #ifdef ASSERT
2697   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
2698 #endif
2699   verify_oop(src);
2700   if (Universe::narrow_oop_base() == NULL) {
2701     if (Universe::narrow_oop_shift() != 0) {
2702       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2703       _lsr(dst, src, Universe::narrow_oop_shift());
2704     } else if (dst != src) {
2705           mov(dst, src);
2706     }
2707   } else {
2708     sub(dst, src, Rheap_base);
2709     if (Universe::narrow_oop_shift() != 0) {
2710       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2711       _lsr(dst, dst, Universe::narrow_oop_shift());
2712     }
2713   }
2714 }
2715 
2716 // Same algorithm as oops.inline.hpp decode_heap_oop.
2717 // Must preserve condition codes, or C2 decodeHeapOop_not_null rule
2718 // must be changed.
2719 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
2720 #ifdef ASSERT
2721   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
2722 #endif
2723   assert(Universe::narrow_oop_shift() == 0 || LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
2724   if (Universe::narrow_oop_base() != NULL) {
2725     add(dst, Rheap_base, AsmOperand(src, lsl, Universe::narrow_oop_shift()));
2726   } else {
2727     _lsl(dst, src, Universe::narrow_oop_shift());
2728   }
2729   verify_oop(dst);
2730 }
2731 
2732 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
2733   assert(UseCompressedClassPointers, "should only be used for compressed header");
2734   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2735   int klass_index = oop_recorder()->find_index(k);
2736   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2737 
2738   // Relocation with special format (see relocInfo_arm.hpp).
2739   relocate(rspec);
2740   narrowKlass encoded_k = Klass::encode_klass(k);
2741   movz(dst, encoded_k & 0xffff, 0);
2742   movk(dst, (encoded_k >> 16) & 0xffff, 16);
2743 }
2744 
2745 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
2746   assert(UseCompressedOops, "should only be used for compressed header");
2747   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2748   int oop_index = oop_recorder()->find_index(obj);
2749   RelocationHolder rspec = oop_Relocation::spec(oop_index);
2750 
2751   relocate(rspec);
2752   movz(dst, 0xffff, 0);
2753   movk(dst, 0xffff, 16);
2754 }
2755 
2756 #endif // COMPILER2
2757 // Must preserve condition codes, or C2 encodeKlass_not_null rule
2758 // must be changed.
2759 void MacroAssembler::encode_klass_not_null(Register r) {
2760   if (Universe::narrow_klass_base() != NULL) {
2761     // Use Rheap_base as a scratch register in which to temporarily load the narrow_klass_base.
2762     assert(r != Rheap_base, "Encoding a klass in Rheap_base");
2763     mov_slow(Rheap_base, Universe::narrow_klass_base());
2764     sub(r, r, Rheap_base);
2765   }
2766   if (Universe::narrow_klass_shift() != 0) {
2767     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
2768     _lsr(r, r, Universe::narrow_klass_shift());
2769   }
2770   if (Universe::narrow_klass_base() != NULL) {
2771     reinit_heapbase();
2772   }
2773 }
2774 
2775 // Must preserve condition codes, or C2 encodeKlass_not_null rule
2776 // must be changed.
2777 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
2778   if (dst == src) {
2779     encode_klass_not_null(src);
2780     return;
2781   }
2782   if (Universe::narrow_klass_base() != NULL) {
2783     mov_slow(dst, (int64_t)Universe::narrow_klass_base());
2784     sub(dst, src, dst);
2785     if (Universe::narrow_klass_shift() != 0) {
2786       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
2787       _lsr(dst, dst, Universe::narrow_klass_shift());
2788     }
2789   } else {
2790     if (Universe::narrow_klass_shift() != 0) {
2791       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
2792       _lsr(dst, src, Universe::narrow_klass_shift());
2793     } else {
2794       mov(dst, src);
2795     }
2796   }
2797 }
2798 
2799 // Function instr_count_for_decode_klass_not_null() counts the instructions
2800 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
2801 // when (Universe::heap() != NULL).  Hence, if the instructions they
2802 // generate change, then this method needs to be updated.
2803 int MacroAssembler::instr_count_for_decode_klass_not_null() {
2804   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
2805   assert(Universe::heap() != NULL, "java heap should be initialized");
2806   if (Universe::narrow_klass_base() != NULL) {
2807     return instr_count_for_mov_slow(Universe::narrow_klass_base()) + // mov_slow
2808       1 +                                                                 // add
2809       instr_count_for_mov_slow(Universe::narrow_ptrs_base());   // reinit_heapbase() = mov_slow
2810   } else {
2811     if (Universe::narrow_klass_shift() != 0) {
2812       return 1;
2813     }
2814   }
2815   return 0;
2816 }
2817 
2818 // Must preserve condition codes, or C2 decodeKlass_not_null rule
2819 // must be changed.
2820 void MacroAssembler::decode_klass_not_null(Register r) {
2821   int off = offset();
2822   assert(UseCompressedClassPointers, "should only be used for compressed headers");
2823   assert(Universe::heap() != NULL, "java heap should be initialized");
2824   assert(r != Rheap_base, "Decoding a klass in Rheap_base");
2825   // Cannot assert, instr_count_for_decode_klass_not_null() counts instructions.
2826   // Also do not verify_oop as this is called by verify_oop.
2827   if (Universe::narrow_klass_base() != NULL) {
2828     // Use Rheap_base as a scratch register in which to temporarily load the narrow_klass_base.
2829     mov_slow(Rheap_base, Universe::narrow_klass_base());
2830     add(r, Rheap_base, AsmOperand(r, lsl, Universe::narrow_klass_shift()));
2831     reinit_heapbase();
2832   } else {
2833     if (Universe::narrow_klass_shift() != 0) {
2834       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
2835       _lsl(r, r, Universe::narrow_klass_shift());
2836     }
2837   }
2838   assert((offset() - off) == (instr_count_for_decode_klass_not_null() * InstructionSize), "need to fix instr_count_for_decode_klass_not_null");
2839 }
2840 
2841 // Must preserve condition codes, or C2 decodeKlass_not_null rule
2842 // must be changed.
2843 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
2844   if (src == dst) {
2845     decode_klass_not_null(src);
2846     return;
2847   }
2848 
2849   assert(UseCompressedClassPointers, "should only be used for compressed headers");
2850   assert(Universe::heap() != NULL, "java heap should be initialized");
2851   assert(src != Rheap_base, "Decoding a klass in Rheap_base");
2852   assert(dst != Rheap_base, "Decoding a klass into Rheap_base");
2853   // Also do not verify_oop as this is called by verify_oop.
2854   if (Universe::narrow_klass_base() != NULL) {
2855     mov_slow(dst, Universe::narrow_klass_base());
2856     add(dst, dst, AsmOperand(src, lsl, Universe::narrow_klass_shift()));
2857   } else {
2858     _lsl(dst, src, Universe::narrow_klass_shift());
2859   }
2860 }
2861 
2862 
2863 void MacroAssembler::reinit_heapbase() {
2864   if (UseCompressedOops || UseCompressedClassPointers) {
2865     if (Universe::heap() != NULL) {
2866       mov_slow(Rheap_base, Universe::narrow_ptrs_base());
2867     } else {
2868       ldr_global_ptr(Rheap_base, (address)Universe::narrow_ptrs_base_addr());
2869     }
2870   }
2871 }
2872 
2873 #ifdef ASSERT
2874 void MacroAssembler::verify_heapbase(const char* msg) {
2875   // This code pattern is matched in NativeIntruction::skip_verify_heapbase.
2876   // Update it at modifications.
2877   assert (UseCompressedOops, "should be compressed");
2878   assert (Universe::heap() != NULL, "java heap should be initialized");
2879   if (CheckCompressedOops) {
2880     Label ok;
2881     str(Rthread, Address(Rthread, in_bytes(JavaThread::in_top_frame_unsafe_section_offset())));
2882     raw_push(Rtemp, ZR);
2883     mrs(Rtemp, Assembler::SysReg_NZCV);
2884     str(Rtemp, Address(SP, 1 * wordSize));
2885     mov_slow(Rtemp, Universe::narrow_ptrs_base());
2886     cmp(Rheap_base, Rtemp);
2887     b(ok, eq);
2888     stop(msg);
2889     bind(ok);
2890     ldr(Rtemp, Address(SP, 1 * wordSize));
2891     msr(Assembler::SysReg_NZCV, Rtemp);
2892     raw_pop(Rtemp, ZR);
2893     str(ZR, Address(Rthread, in_bytes(JavaThread::in_top_frame_unsafe_section_offset())));
2894   }
2895 }
2896 #endif // ASSERT
2897 
2898 #endif // AARCH64
2899 
2900 #ifdef COMPILER2
2901 void MacroAssembler::fast_lock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2 AARCH64_ONLY_ARG(Register Rscratch3))
2902 {
2903   assert(VM_Version::supports_ldrex(), "unsupported, yet?");
2904 
2905   Register Rmark      = Rscratch2;
2906 
2907   assert(Roop != Rscratch, "");
2908   assert(Roop != Rmark, "");
2909   assert(Rbox != Rscratch, "");
2910   assert(Rbox != Rmark, "");
2911 
2912   Label fast_lock, done;
2913 
2914   if (UseBiasedLocking && !UseOptoBiasInlining) {
2915     Label failed;
2916 #ifdef AARCH64
2917     biased_locking_enter(Roop, Rmark, Rscratch, false, Rscratch3, done, failed);
2918 #else
2919     biased_locking_enter(Roop, Rmark, Rscratch, false, noreg, done, failed);
2920 #endif
2921     bind(failed);
2922   }
2923 
2924   ldr(Rmark, Address(Roop, oopDesc::mark_offset_in_bytes()));
2925   tst(Rmark, markOopDesc::unlocked_value);
2926   b(fast_lock, ne);
2927 
2928   // Check for recursive lock
2929   // See comments in InterpreterMacroAssembler::lock_object for
2930   // explanations on the fast recursive locking check.
2931 #ifdef AARCH64
2932   intptr_t mask = ((intptr_t)3) - ((intptr_t)os::vm_page_size());
2933   Assembler::LogicalImmediate imm(mask, false);
2934   mov(Rscratch, SP);
2935   sub(Rscratch, Rmark, Rscratch);
2936   ands(Rscratch, Rscratch, imm);
2937   // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8153107)
2938   str(Rscratch, Address(Rbox, BasicLock::displaced_header_offset_in_bytes()));
2939   b(done);
2940 
2941 #else
2942   // -1- test low 2 bits
2943   movs(Rscratch, AsmOperand(Rmark, lsl, 30));
2944   // -2- test (hdr - SP) if the low two bits are 0
2945   sub(Rscratch, Rmark, SP, eq);
2946   movs(Rscratch, AsmOperand(Rscratch, lsr, exact_log2(os::vm_page_size())), eq);
2947   // If still 'eq' then recursive locking OK
2948   // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8153107)
2949   str(Rscratch, Address(Rbox, BasicLock::displaced_header_offset_in_bytes()));
2950   b(done);
2951 #endif
2952 
2953   bind(fast_lock);
2954   str(Rmark, Address(Rbox, BasicLock::displaced_header_offset_in_bytes()));
2955 
2956   bool allow_fallthrough_on_failure = true;
2957   bool one_shot = true;
2958   cas_for_lock_acquire(Rmark, Rbox, Roop, Rscratch, done, allow_fallthrough_on_failure, one_shot);
2959 
2960   bind(done);
2961 
2962 }
2963 
2964 void MacroAssembler::fast_unlock(Register Roop, Register Rbox, Register Rscratch, Register Rscratch2  AARCH64_ONLY_ARG(Register Rscratch3))
2965 {
2966   assert(VM_Version::supports_ldrex(), "unsupported, yet?");
2967 
2968   Register Rmark      = Rscratch2;
2969 
2970   assert(Roop != Rscratch, "");
2971   assert(Roop != Rmark, "");
2972   assert(Rbox != Rscratch, "");
2973   assert(Rbox != Rmark, "");
2974 
2975   Label done;
2976 
2977   if (UseBiasedLocking && !UseOptoBiasInlining) {
2978     biased_locking_exit(Roop, Rscratch, done);
2979   }
2980 
2981   ldr(Rmark, Address(Rbox, BasicLock::displaced_header_offset_in_bytes()));
2982   // If hdr is NULL, we've got recursive locking and there's nothing more to do
2983   cmp(Rmark, 0);
2984   b(done, eq);
2985 
2986   // Restore the object header
2987   bool allow_fallthrough_on_failure = true;
2988   bool one_shot = true;
2989   cas_for_lock_release(Rmark, Rbox, Roop, Rscratch, done, allow_fallthrough_on_failure, one_shot);
2990 
2991   bind(done);
2992 
2993 }
2994 #endif // COMPILER2