1 /*
   2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
  26 #define CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
  27 
  28 #include "code/relocInfo.hpp"
  29 #include "code/relocInfo_ext.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Introduced AddressLiteral and its subclasses to ease portability from
  34 // x86 and avoid relocation issues
  35 class AddressLiteral {
  36   RelocationHolder _rspec;
  37   // Typically we use AddressLiterals we want to use their rval
  38   // However in some situations we want the lval (effect address) of the item.
  39   // We provide a special factory for making those lvals.
  40   bool _is_lval;
  41 
  42   address          _target;
  43 
  44  private:
  45   static relocInfo::relocType reloc_for_target(address target) {
  46     // Used for ExternalAddress or when the type is not specified
  47     // Sometimes ExternalAddress is used for values which aren't
  48     // exactly addresses, like the card table base.
  49     // external_word_type can't be used for values in the first page
  50     // so just skip the reloc in that case.
  51     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
  52   }
  53 
  54   void set_rspec(relocInfo::relocType rtype);
  55 
  56  protected:
  57   // creation
  58   AddressLiteral()
  59     : _is_lval(false),
  60       _target(NULL)
  61   {}
  62 
  63   public:
  64 
  65   AddressLiteral(address target, relocInfo::relocType rtype) {
  66     _is_lval = false;
  67     _target = target;
  68     set_rspec(rtype);
  69   }
  70 
  71   AddressLiteral(address target, RelocationHolder const& rspec)
  72     : _rspec(rspec),
  73       _is_lval(false),
  74       _target(target)
  75   {}
  76 
  77   AddressLiteral(address target) {
  78     _is_lval = false;
  79     _target = target;
  80     set_rspec(reloc_for_target(target));
  81   }
  82 
  83   AddressLiteral addr() {
  84     AddressLiteral ret = *this;
  85     ret._is_lval = true;
  86     return ret;
  87   }
  88 
  89  private:
  90 
  91   address target() { return _target; }
  92   bool is_lval() { return _is_lval; }
  93 
  94   relocInfo::relocType reloc() const { return _rspec.type(); }
  95   const RelocationHolder& rspec() const { return _rspec; }
  96 
  97   friend class Assembler;
  98   friend class MacroAssembler;
  99   friend class Address;
 100   friend class LIR_Assembler;
 101   friend class InlinedAddress;
 102 };
 103 
 104 class ExternalAddress: public AddressLiteral {
 105 
 106   public:
 107 
 108   ExternalAddress(address target) : AddressLiteral(target) {}
 109 
 110 };
 111 
 112 class InternalAddress: public AddressLiteral {
 113 
 114   public:
 115 
 116   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 117 
 118 };
 119 
 120 // Inlined constants, for use with ldr_literal / bind_literal
 121 // Note: InlinedInteger not supported (use move_slow(Register,int[,cond]))
 122 class InlinedLiteral: StackObj {
 123  public:
 124   Label label; // need to be public for direct access with &
 125   InlinedLiteral() {
 126   }
 127 };
 128 
 129 class InlinedMetadata: public InlinedLiteral {
 130  private:
 131   Metadata *_data;
 132 
 133  public:
 134   InlinedMetadata(Metadata *data): InlinedLiteral() {
 135     _data = data;
 136   }
 137   Metadata *data() { return _data; }
 138 };
 139 
 140 // Currently unused
 141 // class InlinedOop: public InlinedLiteral {
 142 //  private:
 143 //   jobject _jobject;
 144 //
 145 //  public:
 146 //   InlinedOop(jobject target): InlinedLiteral() {
 147 //     _jobject = target;
 148 //   }
 149 //   jobject jobject() { return _jobject; }
 150 // };
 151 
 152 class InlinedAddress: public InlinedLiteral {
 153  private:
 154   AddressLiteral _literal;
 155 
 156  public:
 157 
 158   InlinedAddress(jobject object): InlinedLiteral(), _literal((address)object, relocInfo::oop_type) {
 159     ShouldNotReachHere(); // use mov_oop (or implement InlinedOop)
 160   }
 161 
 162   InlinedAddress(Metadata *data): InlinedLiteral(), _literal((address)data, relocInfo::metadata_type) {
 163     ShouldNotReachHere(); // use InlinedMetadata or mov_metadata
 164   }
 165 
 166   InlinedAddress(address target, const RelocationHolder &rspec): InlinedLiteral(), _literal(target, rspec) {
 167     assert(rspec.type() != relocInfo::oop_type, "Do not use InlinedAddress for oops");
 168     assert(rspec.type() != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
 169   }
 170 
 171   InlinedAddress(address target, relocInfo::relocType rtype): InlinedLiteral(), _literal(target, rtype) {
 172     assert(rtype != relocInfo::oop_type, "Do not use InlinedAddress for oops");
 173     assert(rtype != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
 174   }
 175 
 176   // Note: default is relocInfo::none for InlinedAddress
 177   InlinedAddress(address target): InlinedLiteral(), _literal(target, relocInfo::none) {
 178   }
 179 
 180   address target() { return _literal.target(); }
 181 
 182   const RelocationHolder& rspec() const { return _literal.rspec(); }
 183 };
 184 
 185 class InlinedString: public InlinedLiteral {
 186  private:
 187   const char* _msg;
 188 
 189  public:
 190   InlinedString(const char* msg): InlinedLiteral() {
 191     _msg = msg;
 192   }
 193   const char* msg() { return _msg; }
 194 };
 195 
 196 class MacroAssembler: public Assembler {
 197 protected:
 198 
 199   // Support for VM calls
 200   //
 201 
 202   // This is the base routine called by the different versions of call_VM_leaf.
 203   void call_VM_leaf_helper(address entry_point, int number_of_arguments);
 204 
 205   // This is the base routine called by the different versions of call_VM. The interpreter
 206   // may customize this version by overriding it for its purposes (e.g., to save/restore
 207   // additional registers when doing a VM call).
 208   virtual void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);
 209 public:
 210 
 211   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 212 
 213   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 214   // The implementation is only non-empty for the InterpreterMacroAssembler,
 215   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 216   virtual void check_and_handle_popframe() {}
 217   virtual void check_and_handle_earlyret() {}
 218 
 219   // By default, we do not need relocation information for non
 220   // patchable absolute addresses. However, when needed by some
 221   // extensions, ignore_non_patchable_relocations can be modified,
 222   // returning false to preserve all relocation information.
 223   inline bool ignore_non_patchable_relocations() { return true; }
 224 
 225   // Initially added to the Assembler interface as a pure virtual:
 226   //   RegisterConstant delayed_value(..)
 227   // for:
 228   //   6812678 macro assembler needs delayed binding of a few constants (for 6655638)
 229   // this was subsequently modified to its present name and return type
 230   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
 231 
 232 #ifdef AARCH64
 233 # define NOT_IMPLEMENTED() unimplemented("NYI at " __FILE__ ":" XSTR(__LINE__))
 234 # define NOT_TESTED()      warn("Not tested at " __FILE__ ":" XSTR(__LINE__))
 235 #endif
 236 
 237   void align(int modulus);
 238 
 239   // Support for VM calls
 240   //
 241   // It is imperative that all calls into the VM are handled via the call_VM methods.
 242   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 243   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 244 
 245   void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
 246   void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
 247   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 248   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 249 
 250   // The following methods are required by templateTable.cpp,
 251   // but not used on ARM.
 252   void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 253   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 254   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 255   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 256 
 257   // Note: The super_call_VM calls are not used on ARM
 258 
 259   // Raw call, without saving/restoring registers, exception handling, etc.
 260   // Mainly used from various stubs.
 261   // Note: if 'save_R9_if_scratched' is true, call_VM may on some
 262   // platforms save values on the stack. Set it to false (and handle
 263   // R9 in the callers) if the top of the stack must not be modified
 264   // by call_VM.
 265   void call_VM(address entry_point, bool save_R9_if_scratched);
 266 
 267   void call_VM_leaf(address entry_point);
 268   void call_VM_leaf(address entry_point, Register arg_1);
 269   void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 270   void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 271   void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 272 
 273   void get_vm_result(Register oop_result, Register tmp);
 274   void get_vm_result_2(Register metadata_result, Register tmp);
 275 
 276   // Always sets/resets sp, which default to SP if (last_sp == noreg)
 277   // Optionally sets/resets fp (use noreg to avoid setting it)
 278   // Always sets/resets pc on AArch64; optionally sets/resets pc on 32-bit ARM depending on save_last_java_pc flag
 279   // Note: when saving PC, set_last_Java_frame returns PC's offset in the code section
 280   //       (for oop_maps offset computation)
 281   int set_last_Java_frame(Register last_sp, Register last_fp, bool save_last_java_pc, Register tmp);
 282   void reset_last_Java_frame(Register tmp);
 283   // status set in set_last_Java_frame for reset_last_Java_frame
 284   bool _fp_saved;
 285   bool _pc_saved;
 286 
 287 #ifdef PRODUCT
 288 #define BLOCK_COMMENT(str) /* nothing */
 289 #define STOP(error) __ stop(error)
 290 #else
 291 #define BLOCK_COMMENT(str) __ block_comment(str)
 292 #define STOP(error) __ block_comment(error); __ stop(error)
 293 #endif
 294 
 295   void lookup_virtual_method(Register recv_klass,
 296                              Register vtable_index,
 297                              Register method_result);
 298 
 299   // Test sub_klass against super_klass, with fast and slow paths.
 300 
 301   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 302   // One of the three labels can be NULL, meaning take the fall-through.
 303   // No registers are killed, except temp_regs.
 304   void check_klass_subtype_fast_path(Register sub_klass,
 305                                      Register super_klass,
 306                                      Register temp_reg,
 307                                      Register temp_reg2,
 308                                      Label* L_success,
 309                                      Label* L_failure,
 310                                      Label* L_slow_path);
 311 
 312   // The rest of the type check; must be wired to a corresponding fast path.
 313   // It does not repeat the fast path logic, so don't use it standalone.
 314   // temp_reg3 can be noreg, if no temps are available.
 315   // Updates the sub's secondary super cache as necessary.
 316   // If set_cond_codes:
 317   // - condition codes will be Z on success, NZ on failure.
 318   // - temp_reg will be 0 on success, non-0 on failure
 319   void check_klass_subtype_slow_path(Register sub_klass,
 320                                      Register super_klass,
 321                                      Register temp_reg,
 322                                      Register temp_reg2,
 323                                      Register temp_reg3, // auto assigned if noreg
 324                                      Label* L_success,
 325                                      Label* L_failure,
 326                                      bool set_cond_codes = false);
 327 
 328   // Simplified, combined version, good for typical uses.
 329   // temp_reg3 can be noreg, if no temps are available. It is used only on slow path.
 330   // Falls through on failure.
 331   void check_klass_subtype(Register sub_klass,
 332                            Register super_klass,
 333                            Register temp_reg,
 334                            Register temp_reg2,
 335                            Register temp_reg3, // auto assigned on slow path if noreg
 336                            Label& L_success);
 337 
 338   // Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.
 339   Address receiver_argument_address(Register params_base, Register params_count, Register tmp);
 340 
 341   void _verify_oop(Register reg, const char* s, const char* file, int line);
 342   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
 343 
 344   // TODO: verify method and klass metadata (compare against vptr?)
 345   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 346   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
 347 
 348 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
 349 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop ", __FILE__, __LINE__)
 350 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 351 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 352 
 353   void null_check(Register reg, Register tmp, int offset = -1);
 354   inline void null_check(Register reg) { null_check(reg, noreg, -1); } // for C1 lir_null_check
 355 
 356   // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.
 357   void eden_allocate(Register obj, Register obj_end, Register tmp1, Register tmp2,
 358                      RegisterOrConstant size_expression, Label& slow_case);
 359   void tlab_allocate(Register obj, Register obj_end, Register tmp1,
 360                      RegisterOrConstant size_expression, Label& slow_case);
 361 
 362   void zero_memory(Register start, Register end, Register tmp);
 363 
 364   void incr_allocated_bytes(RegisterOrConstant size_in_bytes, Register tmp);
 365 
 366   static bool needs_explicit_null_check(intptr_t offset);
 367 
 368   void arm_stack_overflow_check(int frame_size_in_bytes, Register tmp);
 369   void arm_stack_overflow_check(Register Rsize, Register tmp);
 370 
 371   void bang_stack_with_offset(int offset) {
 372     ShouldNotReachHere();
 373   }
 374 
 375   // Biased locking support
 376   // lock_reg and obj_reg must be loaded up with the appropriate values.
 377   // swap_reg must be supplied.
 378   // tmp_reg must be supplied.
 379   // Optional slow case is for implementations (interpreter and C1) which branch to
 380   // slow case directly. If slow_case is NULL, then leaves condition
 381   // codes set (for C2's Fast_Lock node) and jumps to done label.
 382   // Falls through for the fast locking attempt.
 383   // Returns offset of first potentially-faulting instruction for null
 384   // check info (currently consumed only by C1). If
 385   // swap_reg_contains_mark is true then returns -1 as it is assumed
 386   // the calling code has already passed any potential faults.
 387   // Notes:
 388   // - swap_reg and tmp_reg are scratched
 389   // - Rtemp was (implicitly) scratched and can now be specified as the tmp2
 390   int biased_locking_enter(Register obj_reg, Register swap_reg, Register tmp_reg,
 391                            bool swap_reg_contains_mark,
 392                            Register tmp2,
 393                            Label& done, Label& slow_case,
 394                            BiasedLockingCounters* counters = NULL);
 395   void biased_locking_exit(Register obj_reg, Register temp_reg, Label& done);
 396 
 397   // Building block for CAS cases of biased locking: makes CAS and records statistics.
 398   // Optional slow_case label is used to transfer control if CAS fails. Otherwise leaves condition codes set.
 399   void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
 400                                      Register tmp, Label& slow_case, int* counter_addr);
 401 
 402   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 403 
 404 #ifndef AARCH64
 405   void nop() {
 406     mov(R0, R0);
 407   }
 408 
 409   void push(Register rd, AsmCondition cond = al) {
 410     assert(rd != SP, "unpredictable instruction");
 411     str(rd, Address(SP, -wordSize, pre_indexed), cond);
 412   }
 413 
 414   void push(RegisterSet reg_set, AsmCondition cond = al) {
 415     assert(!reg_set.contains(SP), "unpredictable instruction");
 416     stmdb(SP, reg_set, writeback, cond);
 417   }
 418 
 419   void pop(Register rd, AsmCondition cond = al) {
 420     assert(rd != SP, "unpredictable instruction");
 421     ldr(rd, Address(SP, wordSize, post_indexed), cond);
 422   }
 423 
 424   void pop(RegisterSet reg_set, AsmCondition cond = al) {
 425     assert(!reg_set.contains(SP), "unpredictable instruction");
 426     ldmia(SP, reg_set, writeback, cond);
 427   }
 428 
 429   void fpushd(FloatRegister fd, AsmCondition cond = al) {
 430     fstmdbd(SP, FloatRegisterSet(fd), writeback, cond);
 431   }
 432 
 433   void fpushs(FloatRegister fd, AsmCondition cond = al) {
 434     fstmdbs(SP, FloatRegisterSet(fd), writeback, cond);
 435   }
 436 
 437   void fpopd(FloatRegister fd, AsmCondition cond = al) {
 438     fldmiad(SP, FloatRegisterSet(fd), writeback, cond);
 439   }
 440 
 441   void fpops(FloatRegister fd, AsmCondition cond = al) {
 442     fldmias(SP, FloatRegisterSet(fd), writeback, cond);
 443   }
 444 #endif // !AARCH64
 445 
 446   // Order access primitives
 447   enum Membar_mask_bits {
 448     StoreStore = 1 << 3,
 449     LoadStore  = 1 << 2,
 450     StoreLoad  = 1 << 1,
 451     LoadLoad   = 1 << 0
 452   };
 453 
 454 #ifdef AARCH64
 455   // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM
 456   void membar(Membar_mask_bits order_constraint, Register tmp = noreg);
 457 #else
 458   void membar(Membar_mask_bits mask,
 459               Register tmp,
 460               bool preserve_flags = true,
 461               Register load_tgt = noreg);
 462 #endif
 463 
 464   void breakpoint(AsmCondition cond = al);
 465   void stop(const char* msg);
 466   // prints msg and continues
 467   void warn(const char* msg);
 468   void unimplemented(const char* what = "");
 469   void should_not_reach_here()                   { stop("should not reach here"); }
 470   static void debug(const char* msg, const intx* registers);
 471 
 472   // Create a walkable frame to help tracking down who called this code.
 473   // Returns the frame size in words.
 474   int should_not_call_this() {
 475     raw_push(FP, LR);
 476     should_not_reach_here();
 477     flush();
 478     return 2; // frame_size_in_words (FP+LR)
 479   }
 480 
 481   int save_all_registers();
 482   void restore_all_registers();
 483   int save_caller_save_registers();
 484   void restore_caller_save_registers();
 485 
 486   void add_rc(Register dst, Register arg1, RegisterOrConstant arg2);
 487 
 488   // add_slow and mov_slow are used to manipulate offsets larger than 1024,
 489   // these functions are not expected to handle all possible constants,
 490   // only those that can really occur during compilation
 491   void add_slow(Register rd, Register rn, int c);
 492   void sub_slow(Register rd, Register rn, int c);
 493 
 494 #ifdef AARCH64
 495   static int mov_slow_helper(Register rd, intptr_t c, MacroAssembler* masm /* optional */);
 496 #endif
 497 
 498   void mov_slow(Register rd, intptr_t c NOT_AARCH64_ARG(AsmCondition cond = al));
 499   void mov_slow(Register rd, const char *string);
 500   void mov_slow(Register rd, address addr);
 501 
 502   void patchable_mov_oop(Register rd, jobject o, int oop_index) {
 503     mov_oop(rd, o, oop_index AARCH64_ONLY_ARG(true));
 504   }
 505   void mov_oop(Register rd, jobject o, int index = 0
 506                AARCH64_ONLY_ARG(bool patchable = false)
 507                NOT_AARCH64_ARG(AsmCondition cond = al));
 508 
 509 
 510   void patchable_mov_metadata(Register rd, Metadata* o, int index) {
 511     mov_metadata(rd, o, index AARCH64_ONLY_ARG(true));
 512   }
 513   void mov_metadata(Register rd, Metadata* o, int index = 0 AARCH64_ONLY_ARG(bool patchable = false));
 514 
 515   void mov_float(FloatRegister fd, jfloat c NOT_AARCH64_ARG(AsmCondition cond = al));
 516   void mov_double(FloatRegister fd, jdouble c NOT_AARCH64_ARG(AsmCondition cond = al));
 517 
 518 #ifdef AARCH64
 519   int mov_pc_to(Register rd) {
 520     Label L;
 521     adr(rd, L);
 522     bind(L);
 523     return offset();
 524   }
 525 #endif
 526 
 527   // Note: this variant of mov_address assumes the address moves with
 528   // the code. Do *not* implement it with non-relocated instructions,
 529   // unless PC-relative.
 530 #ifdef AARCH64
 531   void mov_relative_address(Register rd, address addr) {
 532     adr(rd, addr);
 533   }
 534 #else
 535   void mov_relative_address(Register rd, address addr, AsmCondition cond = al) {
 536     int offset = addr - pc() - 8;
 537     assert((offset & 3) == 0, "bad alignment");
 538     if (offset >= 0) {
 539       assert(AsmOperand::is_rotated_imm(offset), "addr too far");
 540       add(rd, PC, offset, cond);
 541     } else {
 542       assert(AsmOperand::is_rotated_imm(-offset), "addr too far");
 543       sub(rd, PC, -offset, cond);
 544     }
 545   }
 546 #endif // AARCH64
 547 
 548   // Runtime address that may vary from one execution to another. The
 549   // symbolic_reference describes what the address is, allowing
 550   // the address to be resolved in a different execution context.
 551   // Warning: do not implement as a PC relative address.
 552   void mov_address(Register rd, address addr, symbolic_Relocation::symbolic_reference t) {
 553     mov_address(rd, addr, RelocationHolder::none);
 554   }
 555 
 556   // rspec can be RelocationHolder::none (for ignored symbolic_Relocation).
 557   // In that case, the address is absolute and the generated code need
 558   // not be relocable.
 559   void mov_address(Register rd, address addr, RelocationHolder const& rspec) {
 560     assert(rspec.type() != relocInfo::runtime_call_type, "do not use mov_address for runtime calls");
 561     assert(rspec.type() != relocInfo::static_call_type, "do not use mov_address for relocable calls");
 562     if (rspec.type() == relocInfo::none) {
 563       // absolute address, relocation not needed
 564       mov_slow(rd, (intptr_t)addr);
 565       return;
 566     }
 567 #ifndef AARCH64
 568     if (VM_Version::supports_movw()) {
 569       relocate(rspec);
 570       int c = (int)addr;
 571       movw(rd, c & 0xffff);
 572       if ((unsigned int)c >> 16) {
 573         movt(rd, (unsigned int)c >> 16);
 574       }
 575       return;
 576     }
 577 #endif
 578     Label skip_literal;
 579     InlinedAddress addr_literal(addr, rspec);
 580     ldr_literal(rd, addr_literal);
 581     b(skip_literal);
 582     bind_literal(addr_literal);
 583     // AARCH64 WARNING: because of alignment padding, extra padding
 584     // may be required to get a consistent size for C2, or rules must
 585     // overestimate size see MachEpilogNode::size
 586     bind(skip_literal);
 587   }
 588 
 589   // Note: Do not define mov_address for a Label
 590   //
 591   // Load from addresses potentially within the code are now handled
 592   // InlinedLiteral subclasses (to allow more flexibility on how the
 593   // ldr_literal is performed).
 594 
 595   void ldr_literal(Register rd, InlinedAddress& L) {
 596     assert(L.rspec().type() != relocInfo::runtime_call_type, "avoid ldr_literal for calls");
 597     assert(L.rspec().type() != relocInfo::static_call_type, "avoid ldr_literal for calls");
 598     relocate(L.rspec());
 599 #ifdef AARCH64
 600     ldr(rd, target(L.label));
 601 #else
 602     ldr(rd, Address(PC, target(L.label) - pc() - 8));
 603 #endif
 604   }
 605 
 606   void ldr_literal(Register rd, InlinedString& L) {
 607     const char* msg = L.msg();
 608     if (code()->consts()->contains((address)msg)) {
 609       // string address moves with the code
 610 #ifdef AARCH64
 611       ldr(rd, (address)msg);
 612 #else
 613       ldr(rd, Address(PC, ((address)msg) - pc() - 8));
 614 #endif
 615       return;
 616     }
 617     // Warning: use external strings with care. They are not relocated
 618     // if the code moves. If needed, use code_string to move them
 619     // to the consts section.
 620 #ifdef AARCH64
 621     ldr(rd, target(L.label));
 622 #else
 623     ldr(rd, Address(PC, target(L.label) - pc() - 8));
 624 #endif
 625   }
 626 
 627   void ldr_literal(Register rd, InlinedMetadata& L) {
 628     // relocation done in the bind_literal for metadatas
 629 #ifdef AARCH64
 630     ldr(rd, target(L.label));
 631 #else
 632     ldr(rd, Address(PC, target(L.label) - pc() - 8));
 633 #endif
 634   }
 635 
 636   void bind_literal(InlinedAddress& L) {
 637     AARCH64_ONLY(align(wordSize));
 638     bind(L.label);
 639     assert(L.rspec().type() != relocInfo::metadata_type, "Must use InlinedMetadata");
 640     // We currently do not use oop 'bound' literals.
 641     // If the code evolves and the following assert is triggered,
 642     // we need to implement InlinedOop (see InlinedMetadata).
 643     assert(L.rspec().type() != relocInfo::oop_type, "Inlined oops not supported");
 644     // Note: relocation is handled by relocate calls in ldr_literal
 645     AbstractAssembler::emit_address((address)L.target());
 646   }
 647 
 648   void bind_literal(InlinedString& L) {
 649     const char* msg = L.msg();
 650     if (code()->consts()->contains((address)msg)) {
 651       // The Label should not be used; avoid binding it
 652       // to detect errors.
 653       return;
 654     }
 655     AARCH64_ONLY(align(wordSize));
 656     bind(L.label);
 657     AbstractAssembler::emit_address((address)L.msg());
 658   }
 659 
 660   void bind_literal(InlinedMetadata& L) {
 661     AARCH64_ONLY(align(wordSize));
 662     bind(L.label);
 663     relocate(metadata_Relocation::spec_for_immediate());
 664     AbstractAssembler::emit_address((address)L.data());
 665   }
 666 
 667   void resolve_oop_handle(Register result);
 668   void load_mirror(Register mirror, Register method, Register tmp);
 669 
 670   // Porting layer between 32-bit ARM and AArch64
 671 
 672 #define COMMON_INSTR_1(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg_type) \
 673   void common_mnemonic(arg_type arg) { \
 674       AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg); \
 675   }
 676 
 677 #define COMMON_INSTR_2(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg1_type, arg2_type) \
 678   void common_mnemonic(arg1_type arg1, arg2_type arg2) { \
 679       AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg1, arg2); \
 680   }
 681 
 682 #define COMMON_INSTR_3(common_mnemonic, aarch64_mnemonic, arm32_mnemonic, arg1_type, arg2_type, arg3_type) \
 683   void common_mnemonic(arg1_type arg1, arg2_type arg2, arg3_type arg3) { \
 684       AARCH64_ONLY(aarch64_mnemonic) NOT_AARCH64(arm32_mnemonic) (arg1, arg2, arg3); \
 685   }
 686 
 687   COMMON_INSTR_1(jump, br,  bx,  Register)
 688   COMMON_INSTR_1(call, blr, blx, Register)
 689 
 690   COMMON_INSTR_2(cbz_32,  cbz_w,  cbz,  Register, Label&)
 691   COMMON_INSTR_2(cbnz_32, cbnz_w, cbnz, Register, Label&)
 692 
 693   COMMON_INSTR_2(ldr_u32, ldr_w,  ldr,  Register, Address)
 694   COMMON_INSTR_2(ldr_s32, ldrsw,  ldr,  Register, Address)
 695   COMMON_INSTR_2(str_32,  str_w,  str,  Register, Address)
 696 
 697   COMMON_INSTR_2(mvn_32,  mvn_w,  mvn,  Register, Register)
 698   COMMON_INSTR_2(cmp_32,  cmp_w,  cmp,  Register, Register)
 699   COMMON_INSTR_2(neg_32,  neg_w,  neg,  Register, Register)
 700   COMMON_INSTR_2(clz_32,  clz_w,  clz,  Register, Register)
 701   COMMON_INSTR_2(rbit_32, rbit_w, rbit, Register, Register)
 702 
 703   COMMON_INSTR_2(cmp_32,  cmp_w,  cmp,  Register, int)
 704   COMMON_INSTR_2(cmn_32,  cmn_w,  cmn,  Register, int)
 705 
 706   COMMON_INSTR_3(add_32,  add_w,  add,  Register, Register, Register)
 707   COMMON_INSTR_3(sub_32,  sub_w,  sub,  Register, Register, Register)
 708   COMMON_INSTR_3(subs_32, subs_w, subs, Register, Register, Register)
 709   COMMON_INSTR_3(mul_32,  mul_w,  mul,  Register, Register, Register)
 710   COMMON_INSTR_3(and_32,  andr_w, andr, Register, Register, Register)
 711   COMMON_INSTR_3(orr_32,  orr_w,  orr,  Register, Register, Register)
 712   COMMON_INSTR_3(eor_32,  eor_w,  eor,  Register, Register, Register)
 713 
 714   COMMON_INSTR_3(add_32,  add_w,  add,  Register, Register, AsmOperand)
 715   COMMON_INSTR_3(sub_32,  sub_w,  sub,  Register, Register, AsmOperand)
 716   COMMON_INSTR_3(orr_32,  orr_w,  orr,  Register, Register, AsmOperand)
 717   COMMON_INSTR_3(eor_32,  eor_w,  eor,  Register, Register, AsmOperand)
 718   COMMON_INSTR_3(and_32,  andr_w, andr, Register, Register, AsmOperand)
 719 
 720 
 721   COMMON_INSTR_3(add_32,  add_w,  add,  Register, Register, int)
 722   COMMON_INSTR_3(adds_32, adds_w, adds, Register, Register, int)
 723   COMMON_INSTR_3(sub_32,  sub_w,  sub,  Register, Register, int)
 724   COMMON_INSTR_3(subs_32, subs_w, subs, Register, Register, int)
 725 
 726   COMMON_INSTR_2(tst_32,  tst_w,  tst,  Register, unsigned int)
 727   COMMON_INSTR_2(tst_32,  tst_w,  tst,  Register, AsmOperand)
 728 
 729   COMMON_INSTR_3(and_32,  andr_w, andr, Register, Register, uint)
 730   COMMON_INSTR_3(orr_32,  orr_w,  orr,  Register, Register, uint)
 731   COMMON_INSTR_3(eor_32,  eor_w,  eor,  Register, Register, uint)
 732 
 733   COMMON_INSTR_1(cmp_zero_float,  fcmp0_s, fcmpzs, FloatRegister)
 734   COMMON_INSTR_1(cmp_zero_double, fcmp0_d, fcmpzd, FloatRegister)
 735 
 736   COMMON_INSTR_2(ldr_float,   ldr_s,   flds,   FloatRegister, Address)
 737   COMMON_INSTR_2(str_float,   str_s,   fsts,   FloatRegister, Address)
 738   COMMON_INSTR_2(mov_float,   fmov_s,  fcpys,  FloatRegister, FloatRegister)
 739   COMMON_INSTR_2(neg_float,   fneg_s,  fnegs,  FloatRegister, FloatRegister)
 740   COMMON_INSTR_2(abs_float,   fabs_s,  fabss,  FloatRegister, FloatRegister)
 741   COMMON_INSTR_2(sqrt_float,  fsqrt_s, fsqrts, FloatRegister, FloatRegister)
 742   COMMON_INSTR_2(cmp_float,   fcmp_s,  fcmps,  FloatRegister, FloatRegister)
 743 
 744   COMMON_INSTR_3(add_float,   fadd_s,  fadds,  FloatRegister, FloatRegister, FloatRegister)
 745   COMMON_INSTR_3(sub_float,   fsub_s,  fsubs,  FloatRegister, FloatRegister, FloatRegister)
 746   COMMON_INSTR_3(mul_float,   fmul_s,  fmuls,  FloatRegister, FloatRegister, FloatRegister)
 747   COMMON_INSTR_3(div_float,   fdiv_s,  fdivs,  FloatRegister, FloatRegister, FloatRegister)
 748 
 749   COMMON_INSTR_2(ldr_double,  ldr_d,   fldd,   FloatRegister, Address)
 750   COMMON_INSTR_2(str_double,  str_d,   fstd,   FloatRegister, Address)
 751   COMMON_INSTR_2(mov_double,  fmov_d,  fcpyd,  FloatRegister, FloatRegister)
 752   COMMON_INSTR_2(neg_double,  fneg_d,  fnegd,  FloatRegister, FloatRegister)
 753   COMMON_INSTR_2(cmp_double,  fcmp_d,  fcmpd,  FloatRegister, FloatRegister)
 754   COMMON_INSTR_2(abs_double,  fabs_d,  fabsd,  FloatRegister, FloatRegister)
 755   COMMON_INSTR_2(sqrt_double, fsqrt_d, fsqrtd, FloatRegister, FloatRegister)
 756 
 757   COMMON_INSTR_3(add_double,  fadd_d,  faddd,  FloatRegister, FloatRegister, FloatRegister)
 758   COMMON_INSTR_3(sub_double,  fsub_d,  fsubd,  FloatRegister, FloatRegister, FloatRegister)
 759   COMMON_INSTR_3(mul_double,  fmul_d,  fmuld,  FloatRegister, FloatRegister, FloatRegister)
 760   COMMON_INSTR_3(div_double,  fdiv_d,  fdivd,  FloatRegister, FloatRegister, FloatRegister)
 761 
 762   COMMON_INSTR_2(convert_f2d, fcvt_ds, fcvtds, FloatRegister, FloatRegister)
 763   COMMON_INSTR_2(convert_d2f, fcvt_sd, fcvtsd, FloatRegister, FloatRegister)
 764 
 765   COMMON_INSTR_2(mov_fpr2gpr_float, fmov_ws, fmrs, Register, FloatRegister)
 766 
 767 #undef COMMON_INSTR_1
 768 #undef COMMON_INSTR_2
 769 #undef COMMON_INSTR_3
 770 
 771 
 772 #ifdef AARCH64
 773 
 774   void mov(Register dst, Register src, AsmCondition cond) {
 775     if (cond == al) {
 776       mov(dst, src);
 777     } else {
 778       csel(dst, src, dst, cond);
 779     }
 780   }
 781 
 782   // Propagate other overloaded "mov" methods from Assembler.
 783   void mov(Register dst, Register src)    { Assembler::mov(dst, src); }
 784   void mov(Register rd, int imm)          { Assembler::mov(rd, imm);  }
 785 
 786   void mov(Register dst, int imm, AsmCondition cond) {
 787     assert(imm == 0 || imm == 1, "");
 788     if (imm == 0) {
 789       mov(dst, ZR, cond);
 790     } else if (imm == 1) {
 791       csinc(dst, dst, ZR, inverse(cond));
 792     } else if (imm == -1) {
 793       csinv(dst, dst, ZR, inverse(cond));
 794     } else {
 795       fatal("illegal mov(R%d,%d,cond)", dst->encoding(), imm);
 796     }
 797   }
 798 
 799   void movs(Register dst, Register src)    { adds(dst, src, 0); }
 800 
 801 #else // AARCH64
 802 
 803   void tbz(Register rt, int bit, Label& L) {
 804     assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
 805     tst(rt, 1 << bit);
 806     b(L, eq);
 807   }
 808 
 809   void tbnz(Register rt, int bit, Label& L) {
 810     assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
 811     tst(rt, 1 << bit);
 812     b(L, ne);
 813   }
 814 
 815   void cbz(Register rt, Label& L) {
 816     cmp(rt, 0);
 817     b(L, eq);
 818   }
 819 
 820   void cbz(Register rt, address target) {
 821     cmp(rt, 0);
 822     b(target, eq);
 823   }
 824 
 825   void cbnz(Register rt, Label& L) {
 826     cmp(rt, 0);
 827     b(L, ne);
 828   }
 829 
 830   void ret(Register dst = LR) {
 831     bx(dst);
 832   }
 833 
 834 #endif // AARCH64
 835 
 836   Register zero_register(Register tmp) {
 837 #ifdef AARCH64
 838     return ZR;
 839 #else
 840     mov(tmp, 0);
 841     return tmp;
 842 #endif
 843   }
 844 
 845   void logical_shift_left(Register dst, Register src, int shift) {
 846 #ifdef AARCH64
 847     _lsl(dst, src, shift);
 848 #else
 849     mov(dst, AsmOperand(src, lsl, shift));
 850 #endif
 851   }
 852 
 853   void logical_shift_left_32(Register dst, Register src, int shift) {
 854 #ifdef AARCH64
 855     _lsl_w(dst, src, shift);
 856 #else
 857     mov(dst, AsmOperand(src, lsl, shift));
 858 #endif
 859   }
 860 
 861   void logical_shift_right(Register dst, Register src, int shift) {
 862 #ifdef AARCH64
 863     _lsr(dst, src, shift);
 864 #else
 865     mov(dst, AsmOperand(src, lsr, shift));
 866 #endif
 867   }
 868 
 869   void arith_shift_right(Register dst, Register src, int shift) {
 870 #ifdef AARCH64
 871     _asr(dst, src, shift);
 872 #else
 873     mov(dst, AsmOperand(src, asr, shift));
 874 #endif
 875   }
 876 
 877   void asr_32(Register dst, Register src, int shift) {
 878 #ifdef AARCH64
 879     _asr_w(dst, src, shift);
 880 #else
 881     mov(dst, AsmOperand(src, asr, shift));
 882 #endif
 883   }
 884 
 885   // If <cond> holds, compares r1 and r2. Otherwise, flags are set so that <cond> does not hold.
 886   void cond_cmp(Register r1, Register r2, AsmCondition cond) {
 887 #ifdef AARCH64
 888     ccmp(r1, r2, flags_for_condition(inverse(cond)), cond);
 889 #else
 890     cmp(r1, r2, cond);
 891 #endif
 892   }
 893 
 894   // If <cond> holds, compares r and imm. Otherwise, flags are set so that <cond> does not hold.
 895   void cond_cmp(Register r, int imm, AsmCondition cond) {
 896 #ifdef AARCH64
 897     ccmp(r, imm, flags_for_condition(inverse(cond)), cond);
 898 #else
 899     cmp(r, imm, cond);
 900 #endif
 901   }
 902 
 903   void align_reg(Register dst, Register src, int align) {
 904     assert (is_power_of_2(align), "should be");
 905 #ifdef AARCH64
 906     andr(dst, src, ~(uintx)(align-1));
 907 #else
 908     bic(dst, src, align-1);
 909 #endif
 910   }
 911 
 912   void prefetch_read(Address addr) {
 913 #ifdef AARCH64
 914     prfm(pldl1keep, addr);
 915 #else
 916     pld(addr);
 917 #endif
 918   }
 919 
 920   void raw_push(Register r1, Register r2) {
 921 #ifdef AARCH64
 922     stp(r1, r2, Address(SP, -2*wordSize, pre_indexed));
 923 #else
 924     assert(r1->encoding() < r2->encoding(), "should be ordered");
 925     push(RegisterSet(r1) | RegisterSet(r2));
 926 #endif
 927   }
 928 
 929   void raw_pop(Register r1, Register r2) {
 930 #ifdef AARCH64
 931     ldp(r1, r2, Address(SP, 2*wordSize, post_indexed));
 932 #else
 933     assert(r1->encoding() < r2->encoding(), "should be ordered");
 934     pop(RegisterSet(r1) | RegisterSet(r2));
 935 #endif
 936   }
 937 
 938   void raw_push(Register r1, Register r2, Register r3) {
 939 #ifdef AARCH64
 940     raw_push(r1, r2);
 941     raw_push(r3, ZR);
 942 #else
 943     assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
 944     push(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
 945 #endif
 946   }
 947 
 948   void raw_pop(Register r1, Register r2, Register r3) {
 949 #ifdef AARCH64
 950     raw_pop(r3, ZR);
 951     raw_pop(r1, r2);
 952 #else
 953     assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
 954     pop(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
 955 #endif
 956   }
 957 
 958   // Restores registers r1 and r2 previously saved by raw_push(r1, r2, ret_addr) and returns by ret_addr. Clobbers LR.
 959   void raw_pop_and_ret(Register r1, Register r2) {
 960 #ifdef AARCH64
 961     raw_pop(r1, r2, LR);
 962     ret();
 963 #else
 964     raw_pop(r1, r2, PC);
 965 #endif
 966   }
 967 
 968   void indirect_jump(Address addr, Register scratch) {
 969 #ifdef AARCH64
 970     ldr(scratch, addr);
 971     br(scratch);
 972 #else
 973     ldr(PC, addr);
 974 #endif
 975   }
 976 
 977   void indirect_jump(InlinedAddress& literal, Register scratch) {
 978 #ifdef AARCH64
 979     ldr_literal(scratch, literal);
 980     br(scratch);
 981 #else
 982     ldr_literal(PC, literal);
 983 #endif
 984   }
 985 
 986 #ifndef AARCH64
 987   void neg(Register dst, Register src) {
 988     rsb(dst, src, 0);
 989   }
 990 #endif
 991 
 992   void branch_if_negative_32(Register r, Label& L) {
 993     // Note about branch_if_negative_32() / branch_if_any_negative_32() implementation for AArch64:
 994     // tbnz is not used instead of tst & b.mi because destination may be out of tbnz range (+-32KB)
 995     // since these methods are used in LIR_Assembler::emit_arraycopy() to jump to stub entry.
 996     tst_32(r, r);
 997     b(L, mi);
 998   }
 999 
1000   void branch_if_any_negative_32(Register r1, Register r2, Register tmp, Label& L) {
1001 #ifdef AARCH64
1002     orr_32(tmp, r1, r2);
1003     tst_32(tmp, tmp);
1004 #else
1005     orrs(tmp, r1, r2);
1006 #endif
1007     b(L, mi);
1008   }
1009 
1010   void branch_if_any_negative_32(Register r1, Register r2, Register r3, Register tmp, Label& L) {
1011     orr_32(tmp, r1, r2);
1012 #ifdef AARCH64
1013     orr_32(tmp, tmp, r3);
1014     tst_32(tmp, tmp);
1015 #else
1016     orrs(tmp, tmp, r3);
1017 #endif
1018     b(L, mi);
1019   }
1020 
1021   void add_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
1022 #ifdef AARCH64
1023       add(dst, r1, r2, ex_sxtw, shift);
1024 #else
1025       add(dst, r1, AsmOperand(r2, lsl, shift));
1026 #endif
1027   }
1028 
1029   void sub_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
1030 #ifdef AARCH64
1031     sub(dst, r1, r2, ex_sxtw, shift);
1032 #else
1033     sub(dst, r1, AsmOperand(r2, lsl, shift));
1034 #endif
1035   }
1036 
1037 
1038     // klass oop manipulations if compressed
1039 
1040 #ifdef AARCH64
1041   void load_klass(Register dst_klass, Register src_oop);
1042 #else
1043   void load_klass(Register dst_klass, Register src_oop, AsmCondition cond = al);
1044 #endif // AARCH64
1045 
1046   void store_klass(Register src_klass, Register dst_oop);
1047 
1048 #ifdef AARCH64
1049   void store_klass_gap(Register dst);
1050 #endif // AARCH64
1051 
1052     // oop manipulations
1053 
1054   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
1055   void store_heap_oop(Address obj, Register new_val, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
1056   void store_heap_oop_null(Address obj, Register new_val, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
1057 
1058   void access_load_at(BasicType type, DecoratorSet decorators, Address src, Register dst, Register tmp1, Register tmp2, Register tmp3);
1059   void access_store_at(BasicType type, DecoratorSet decorators, Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, bool is_null);
1060 
1061 #ifdef AARCH64
1062   void encode_heap_oop(Register dst, Register src);
1063   void encode_heap_oop(Register r) {
1064     encode_heap_oop(r, r);
1065   }
1066   void decode_heap_oop(Register dst, Register src);
1067   void decode_heap_oop(Register r) {
1068       decode_heap_oop(r, r);
1069   }
1070 
1071 #ifdef COMPILER2
1072   void encode_heap_oop_not_null(Register dst, Register src);
1073   void decode_heap_oop_not_null(Register dst, Register src);
1074 
1075   void set_narrow_klass(Register dst, Klass* k);
1076   void set_narrow_oop(Register dst, jobject obj);
1077 #endif
1078 
1079   void encode_klass_not_null(Register r);
1080   void encode_klass_not_null(Register dst, Register src);
1081   void decode_klass_not_null(Register r);
1082   void decode_klass_not_null(Register dst, Register src);
1083 
1084   void reinit_heapbase();
1085 
1086 #ifdef ASSERT
1087   void verify_heapbase(const char* msg);
1088 #endif // ASSERT
1089 
1090   static int instr_count_for_mov_slow(intptr_t c);
1091   static int instr_count_for_mov_slow(address addr);
1092   static int instr_count_for_decode_klass_not_null();
1093 #endif // AARCH64
1094 
1095   void ldr_global_ptr(Register reg, address address_of_global);
1096   void ldr_global_s32(Register reg, address address_of_global);
1097   void ldrb_global(Register reg, address address_of_global);
1098 
1099   // address_placeholder_instruction is invalid instruction and is used
1100   // as placeholder in code for address of label
1101   enum { address_placeholder_instruction = 0xFFFFFFFF };
1102 
1103   void emit_address(Label& L) {
1104     assert(!L.is_bound(), "otherwise address will not be patched");
1105     target(L);       // creates relocation which will be patched later
1106 
1107     assert ((offset() & (wordSize-1)) == 0, "should be aligned by word size");
1108 
1109 #ifdef AARCH64
1110     emit_int32(address_placeholder_instruction);
1111     emit_int32(address_placeholder_instruction);
1112 #else
1113     AbstractAssembler::emit_address((address)address_placeholder_instruction);
1114 #endif
1115   }
1116 
1117   void b(address target, AsmCondition cond = al) {
1118     Assembler::b(target, cond);                 \
1119   }
1120   void b(Label& L, AsmCondition cond = al) {
1121     // internal jumps
1122     Assembler::b(target(L), cond);
1123   }
1124 
1125   void bl(address target NOT_AARCH64_ARG(AsmCondition cond = al)) {
1126     Assembler::bl(target NOT_AARCH64_ARG(cond));
1127   }
1128   void bl(Label& L NOT_AARCH64_ARG(AsmCondition cond = al)) {
1129     // internal calls
1130     Assembler::bl(target(L)  NOT_AARCH64_ARG(cond));
1131   }
1132 
1133 #ifndef AARCH64
1134   void adr(Register dest, Label& L, AsmCondition cond = al) {
1135     int delta = target(L) - pc() - 8;
1136     if (delta >= 0) {
1137       add(dest, PC, delta, cond);
1138     } else {
1139       sub(dest, PC, -delta, cond);
1140     }
1141   }
1142 #endif // !AARCH64
1143 
1144   // Variable-length jump and calls. We now distinguish only the
1145   // patchable case from the other cases. Patchable must be
1146   // distinguised from relocable. Relocable means the generated code
1147   // containing the jump/call may move. Patchable means that the
1148   // targeted address may be changed later.
1149 
1150   // Non patchable versions.
1151   // - used only for relocInfo::runtime_call_type and relocInfo::none
1152   // - may use relative or absolute format (do not use relocInfo::none
1153   //   if the generated code may move)
1154   // - the implementation takes into account switch to THUMB mode if the
1155   //   destination is a THUMB address
1156   // - the implementation supports far targets
1157   //
1158   // To reduce regression risk, scratch still defaults to noreg on
1159   // arm32. This results in patchable instructions. However, if
1160   // patching really matters, the call sites should be modified and
1161   // use patchable_call or patchable_jump. If patching is not required
1162   // and if a register can be cloberred, it should be explicitly
1163   // specified to allow future optimizations.
1164   void jump(address target,
1165             relocInfo::relocType rtype = relocInfo::runtime_call_type,
1166             Register scratch = AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg)
1167 #ifndef AARCH64
1168             , AsmCondition cond = al
1169 #endif
1170             );
1171 
1172   void call(address target,
1173             RelocationHolder rspec
1174             NOT_AARCH64_ARG(AsmCondition cond = al));
1175 
1176   void call(address target,
1177             relocInfo::relocType rtype = relocInfo::runtime_call_type
1178             NOT_AARCH64_ARG(AsmCondition cond = al)) {
1179     call(target, Relocation::spec_simple(rtype) NOT_AARCH64_ARG(cond));
1180   }
1181 
1182   void jump(AddressLiteral dest) {
1183     jump(dest.target(), dest.reloc());
1184   }
1185 #ifndef AARCH64
1186   void jump(address dest, relocInfo::relocType rtype, AsmCondition cond) {
1187     jump(dest, rtype, Rtemp, cond);
1188   }
1189 #endif
1190 
1191   void call(AddressLiteral dest) {
1192     call(dest.target(), dest.reloc());
1193   }
1194 
1195   // Patchable version:
1196   // - set_destination can be used to atomically change the target
1197   //
1198   // The targets for patchable_jump and patchable_call must be in the
1199   // code cache.
1200   // [ including possible extensions of the code cache, like AOT code ]
1201   //
1202   // To reduce regression risk, scratch still defaults to noreg on
1203   // arm32. If a register can be cloberred, it should be explicitly
1204   // specified to allow future optimizations.
1205   void patchable_jump(address target,
1206                       relocInfo::relocType rtype = relocInfo::runtime_call_type,
1207                       Register scratch = AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg)
1208 #ifndef AARCH64
1209                       , AsmCondition cond = al
1210 #endif
1211                       );
1212 
1213   // patchable_call may scratch Rtemp
1214   int patchable_call(address target,
1215                      RelocationHolder const& rspec,
1216                      bool c2 = false);
1217 
1218   int patchable_call(address target,
1219                      relocInfo::relocType rtype,
1220                      bool c2 = false) {
1221     return patchable_call(target, Relocation::spec_simple(rtype), c2);
1222   }
1223 
1224 #if defined(AARCH64) && defined(COMPILER2)
1225   static int call_size(address target, bool far, bool patchable);
1226 #endif
1227 
1228 #ifdef AARCH64
1229   static bool page_reachable_from_cache(address target);
1230 #endif
1231   static bool _reachable_from_cache(address target);
1232   static bool _cache_fully_reachable();
1233   bool cache_fully_reachable();
1234   bool reachable_from_cache(address target);
1235 
1236   void zero_extend(Register rd, Register rn, int bits);
1237   void sign_extend(Register rd, Register rn, int bits);
1238 
1239   inline void zap_high_non_significant_bits(Register r) {
1240 #ifdef AARCH64
1241     if(ZapHighNonSignificantBits) {
1242       movk(r, 0xBAAD, 48);
1243       movk(r, 0xF00D, 32);
1244     }
1245 #endif
1246   }
1247 
1248 #ifndef AARCH64
1249   void cmpoop(Register obj1, Register obj2);
1250 
1251   void long_move(Register rd_lo, Register rd_hi,
1252                  Register rn_lo, Register rn_hi,
1253                  AsmCondition cond = al);
1254   void long_shift(Register rd_lo, Register rd_hi,
1255                   Register rn_lo, Register rn_hi,
1256                   AsmShift shift, Register count);
1257   void long_shift(Register rd_lo, Register rd_hi,
1258                   Register rn_lo, Register rn_hi,
1259                   AsmShift shift, int count);
1260 
1261   void atomic_cas(Register tmpreg1, Register tmpreg2, Register oldval, Register newval, Register base, int offset);
1262   void atomic_cas_bool(Register oldval, Register newval, Register base, int offset, Register tmpreg);
1263   void atomic_cas64(Register temp_lo, Register temp_hi, Register temp_result, Register oldval_lo, Register oldval_hi, Register newval_lo, Register newval_hi, Register base, int offset);
1264 #endif // !AARCH64
1265 
1266   void cas_for_lock_acquire(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1267   void cas_for_lock_release(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1268 
1269 #ifndef PRODUCT
1270   // Preserves flags and all registers.
1271   // On SMP the updated value might not be visible to external observers without a sychronization barrier
1272   void cond_atomic_inc32(AsmCondition cond, int* counter_addr);
1273 #endif // !PRODUCT
1274 
1275   // unconditional non-atomic increment
1276   void inc_counter(address counter_addr, Register tmpreg1, Register tmpreg2);
1277   void inc_counter(int* counter_addr, Register tmpreg1, Register tmpreg2) {
1278     inc_counter((address) counter_addr, tmpreg1, tmpreg2);
1279   }
1280 
1281   void pd_patch_instruction(address branch, address target, const char* file, int line);
1282 
1283   // Loading and storing values by size and signed-ness;
1284   // size must not exceed wordSize (i.e. 8-byte values are not supported on 32-bit ARM);
1285   // each of these calls generates exactly one load or store instruction,
1286   // so src can be pre- or post-indexed address.
1287 #ifdef AARCH64
1288   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
1289   void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1290 #else
1291   // 32-bit ARM variants also support conditional execution
1292   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, AsmCondition cond = al);
1293   void store_sized_value(Register src, Address dst, size_t size_in_bytes, AsmCondition cond = al);
1294 #endif
1295 
1296   void lookup_interface_method(Register recv_klass,
1297                                Register intf_klass,
1298                                RegisterOrConstant itable_index,
1299                                Register method_result,
1300                                Register temp_reg1,
1301                                Register temp_reg2,
1302                                Label& L_no_such_interface);
1303 
1304   // Compare char[] arrays aligned to 4 bytes.
1305   void char_arrays_equals(Register ary1, Register ary2,
1306                           Register limit, Register result,
1307                           Register chr1, Register chr2, Label& Ldone);
1308 
1309 
1310   void floating_cmp(Register dst);
1311 
1312   // improved x86 portability (minimizing source code changes)
1313 
1314   void ldr_literal(Register rd, AddressLiteral addr) {
1315     relocate(addr.rspec());
1316 #ifdef AARCH64
1317     ldr(rd, addr.target());
1318 #else
1319     ldr(rd, Address(PC, addr.target() - pc() - 8));
1320 #endif
1321   }
1322 
1323   void lea(Register Rd, AddressLiteral addr) {
1324     // Never dereferenced, as on x86 (lval status ignored)
1325     mov_address(Rd, addr.target(), addr.rspec());
1326   }
1327 
1328   void restore_default_fp_mode();
1329 
1330 #ifdef COMPILER2
1331 #ifdef AARCH64
1332   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
1333   void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
1334   void fast_unlock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
1335 #else
1336   void fast_lock(Register obj, Register box, Register scratch, Register scratch2);
1337   void fast_unlock(Register obj, Register box, Register scratch, Register scratch2);
1338 #endif
1339 #endif
1340 
1341 #ifdef AARCH64
1342 
1343 #define F(mnemonic)                                             \
1344   void mnemonic(Register rt, address target) {                  \
1345     Assembler::mnemonic(rt, target);                            \
1346   }                                                             \
1347   void mnemonic(Register rt, Label& L) {                        \
1348     Assembler::mnemonic(rt, target(L));                         \
1349   }
1350 
1351   F(cbz_w);
1352   F(cbnz_w);
1353   F(cbz);
1354   F(cbnz);
1355 
1356 #undef F
1357 
1358 #define F(mnemonic)                                             \
1359   void mnemonic(Register rt, int bit, address target) {         \
1360     Assembler::mnemonic(rt, bit, target);                       \
1361   }                                                             \
1362   void mnemonic(Register rt, int bit, Label& L) {               \
1363     Assembler::mnemonic(rt, bit, target(L));                    \
1364   }
1365 
1366   F(tbz);
1367   F(tbnz);
1368 #undef F
1369 
1370 #endif // AARCH64
1371 
1372 };
1373 
1374 
1375 // The purpose of this class is to build several code fragments of the same size
1376 // in order to allow fast table branch.
1377 
1378 class FixedSizeCodeBlock {
1379 public:
1380   FixedSizeCodeBlock(MacroAssembler* masm, int size_in_instrs, bool enabled);
1381   ~FixedSizeCodeBlock();
1382 
1383 private:
1384   MacroAssembler* _masm;
1385   address _start;
1386   int _size_in_instrs;
1387   bool _enabled;
1388 };
1389 
1390 
1391 #endif // CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
1392