1 /*
2 * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "nativeInst_arm.hpp"
33 #include "oops/compiledICHolder.hpp"
34 #include "oops/oop.inline.hpp"
35 #include "prims/jvmtiExport.hpp"
36 #include "register_arm.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/signature.hpp"
39 #include "runtime/vframeArray.hpp"
40 #include "vmreg_arm.inline.hpp"
41 #if INCLUDE_ALL_GCS
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #endif
44
45 // Note: Rtemp usage is this file should not impact C2 and should be
46 // correct as long as it is not implicitly used in lower layers (the
47 // arm [macro]assembler) and used with care in the other C1 specific
48 // files.
49
50 // Implementation of StubAssembler
51
52 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
53 mov(R0, Rthread);
54
55 int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
56
57 call(entry);
58 if (call_offset == -1) { // PC not saved
59 call_offset = offset();
60 }
61 reset_last_Java_frame(Rtemp);
62
63 assert(frame_size() != no_frame_size, "frame must be fixed");
64 if (_stub_id != Runtime1::forward_exception_id) {
65 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
66 }
67
68 if (oop_result1->is_valid()) {
69 assert_different_registers(oop_result1, R3, Rtemp);
70 get_vm_result(oop_result1, Rtemp);
71 }
72 if (metadata_result->is_valid()) {
73 assert_different_registers(metadata_result, R3, Rtemp);
74 get_vm_result_2(metadata_result, Rtemp);
75 }
76
77 // Check for pending exception
78 // unpack_with_exception_in_tls path is taken through
79 // Runtime1::exception_handler_for_pc
80 if (_stub_id != Runtime1::forward_exception_id) {
81 assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
82 #ifdef AARCH64
83 Label skip;
84 cbz(R3, skip);
85 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
86 bind(skip);
87 #else
88 cmp(R3, 0);
89 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
90 #endif // AARCH64
91 } else {
92 #ifdef ASSERT
93 // Should not have pending exception in forward_exception stub
94 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
95 cmp(R3, 0);
96 breakpoint(ne);
97 #endif // ASSERT
98 }
99 return call_offset;
100 }
101
102
103 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
104 if (arg1 != R1) {
105 mov(R1, arg1);
106 }
107 return call_RT(oop_result1, metadata_result, entry, 1);
108 }
109
110
111 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
112 assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
113 return call_RT(oop_result1, metadata_result, entry, 2);
114 }
115
116
117 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
118 assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
119 return call_RT(oop_result1, metadata_result, entry, 3);
120 }
121
122
123 #define __ sasm->
124
125 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
126 #ifdef AARCH64
127
128 //
129 // On AArch64 registers save area has the following layout:
130 //
131 // |---------------------|
132 // | return address (LR) |
133 // | FP |
134 // |---------------------|
135 // | D31 |
136 // | ... |
137 // | D0 |
138 // |---------------------|
139 // | padding |
140 // |---------------------|
141 // | R28 |
142 // | ... |
143 // | R0 |
144 // |---------------------| <-- SP
145 //
146
147 enum RegisterLayout {
148 number_of_saved_gprs = 29,
149 number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
150
151 R0_offset = 0,
152 D0_offset = R0_offset + number_of_saved_gprs + 1,
153 FP_offset = D0_offset + number_of_saved_fprs,
154 LR_offset = FP_offset + 1,
155
156 reg_save_size = LR_offset + 1,
157
158 arg1_offset = reg_save_size * wordSize,
159 arg2_offset = (reg_save_size + 1) * wordSize
160 };
161
162 #else
163
164 enum RegisterLayout {
165 fpu_save_size = pd_nof_fpu_regs_reg_alloc,
166 #ifndef __SOFTFP__
167 D0_offset = 0,
168 #endif
169 R0_offset = fpu_save_size,
170 R1_offset,
171 R2_offset,
172 R3_offset,
173 R4_offset,
174 R5_offset,
175 R6_offset,
176 #if (FP_REG_NUM != 7)
177 R7_offset,
178 #endif
179 R8_offset,
180 R9_offset,
181 R10_offset,
182 #if (FP_REG_NUM != 11)
183 R11_offset,
184 #endif
185 R12_offset,
186 FP_offset,
187 LR_offset,
188 reg_save_size,
189 arg1_offset = reg_save_size * wordSize,
190 arg2_offset = (reg_save_size + 1) * wordSize
191 };
192
193 #endif // AARCH64
194
195 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
196 sasm->set_frame_size(reg_save_size /* in words */);
197
198 // Record saved value locations in an OopMap.
199 // Locations are offsets from sp after runtime call.
200 OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
201
202 #ifdef AARCH64
203 for (int i = 0; i < number_of_saved_gprs; i++) {
204 map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
205 }
206 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
207 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
208
209 if (save_fpu_registers) {
210 for (int i = 0; i < number_of_saved_fprs; i++) {
211 map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
212 }
213 }
214 #else
215 int j=0;
216 for (int i = R0_offset; i < R10_offset; i++) {
217 if (j == FP_REG_NUM) {
218 // skip the FP register, saved below
219 j++;
220 }
221 map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
222 j++;
223 }
224 assert(j == R10->encoding(), "must be");
225 #if (FP_REG_NUM != 11)
226 // add R11, if not saved as FP
227 map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
228 #endif
229 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
230 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
231
232 if (save_fpu_registers) {
233 for (int i = 0; i < fpu_save_size; i++) {
234 map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
235 }
236 }
237 #endif // AARCH64
238
239 return map;
240 }
241
242 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
243 __ block_comment("save_live_registers");
244 sasm->set_frame_size(reg_save_size /* in words */);
245
246 #ifdef AARCH64
247 assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
248
249 __ raw_push(FP, LR);
250
251 __ sub(SP, SP, (reg_save_size - 2) * wordSize);
252
253 for (int i = 0; i < round_down(number_of_saved_gprs, 2); i += 2) {
254 __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
255 }
256
257 if (is_odd(number_of_saved_gprs)) {
258 int i = number_of_saved_gprs - 1;
259 __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
260 }
261
262 if (save_fpu_registers) {
263 assert (is_even(number_of_saved_fprs), "adjust this code");
264 for (int i = 0; i < number_of_saved_fprs; i += 2) {
265 __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
266 }
267 }
268 #else
269 __ push(RegisterSet(FP) | RegisterSet(LR));
270 __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
271 if (save_fpu_registers) {
272 __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
273 } else {
274 __ sub(SP, SP, fpu_save_size * wordSize);
275 }
276 #endif // AARCH64
277
278 return generate_oop_map(sasm, save_fpu_registers);
279 }
280
281
282 static void restore_live_registers(StubAssembler* sasm,
283 bool restore_R0,
284 bool restore_FP_LR,
285 bool do_return,
286 bool restore_fpu_registers = HaveVFP) {
287 __ block_comment("restore_live_registers");
288
289 #ifdef AARCH64
290 if (restore_R0) {
291 __ ldr(R0, Address(SP, R0_offset * wordSize));
292 }
293
294 assert(is_odd(number_of_saved_gprs), "adjust this code");
295 for (int i = 1; i < number_of_saved_gprs; i += 2) {
296 __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
297 }
298
299 if (restore_fpu_registers) {
300 assert (is_even(number_of_saved_fprs), "adjust this code");
301 for (int i = 0; i < number_of_saved_fprs; i += 2) {
302 __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
303 }
304 }
305
306 __ add(SP, SP, (reg_save_size - 2) * wordSize);
307
308 if (restore_FP_LR) {
309 __ raw_pop(FP, LR);
310 if (do_return) {
311 __ ret();
312 }
313 } else {
314 assert (!do_return, "return without restoring FP/LR");
315 }
316 #else
317 if (restore_fpu_registers) {
318 __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
319 if (!restore_R0) {
320 __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
321 }
322 } else {
323 __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
324 }
325 __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
326 if (restore_FP_LR) {
327 __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
328 } else {
329 assert (!do_return, "return without restoring FP/LR");
330 }
331 #endif // AARCH64
332 }
333
334
335 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
336 restore_live_registers(sasm, false, true, true, restore_fpu_registers);
337 }
338
339 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
340 restore_live_registers(sasm, true, true, true, restore_fpu_registers);
341 }
342
343 #ifndef AARCH64
344 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
345 restore_live_registers(sasm, true, false, false, restore_fpu_registers);
346 }
347 #endif // !AARCH64
348
349 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
350 restore_live_registers(sasm, true, true, false, restore_fpu_registers);
351 }
352
353
354 void Runtime1::initialize_pd() {
355 }
356
357
358 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
359 OopMap* oop_map = save_live_registers(sasm);
360
361 if (has_argument) {
362 __ ldr(R1, Address(SP, arg1_offset));
363 }
364
365 int call_offset = __ call_RT(noreg, noreg, target);
366 OopMapSet* oop_maps = new OopMapSet();
367 oop_maps->add_gc_map(call_offset, oop_map);
368
369 DEBUG_ONLY(STOP("generate_exception_throw");) // Should not reach here
370 return oop_maps;
371 }
372
373
374 static void restore_sp_for_method_handle(StubAssembler* sasm) {
375 // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
376 __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
377 #ifdef AARCH64
378 Label skip;
379 __ cbz(Rtemp, skip);
380 __ mov(SP, Rmh_SP_save);
381 __ bind(skip);
382 #else
383 __ cmp(Rtemp, 0);
384 __ mov(SP, Rmh_SP_save, ne);
385 #endif // AARCH64
386 }
387
388
389 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
390 __ block_comment("generate_handle_exception");
391
392 bool save_fpu_registers = false;
393
394 // Save registers, if required.
395 OopMapSet* oop_maps = new OopMapSet();
396 OopMap* oop_map = NULL;
397
398 switch (id) {
399 case forward_exception_id: {
400 save_fpu_registers = HaveVFP;
401 oop_map = generate_oop_map(sasm);
402 __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
403 __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
404 Register zero = __ zero_register(Rtemp);
405 __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
406 break;
407 }
408 case handle_exception_id:
409 save_fpu_registers = HaveVFP;
410 // fall-through
411 case handle_exception_nofpu_id:
412 // At this point all registers MAY be live.
413 oop_map = save_live_registers(sasm, save_fpu_registers);
414 break;
415 case handle_exception_from_callee_id:
416 // At this point all registers except exception oop (R4/R19) and
417 // exception pc (R5/R20) are dead.
418 oop_map = save_live_registers(sasm); // TODO it's not required to save all registers
419 break;
420 default: ShouldNotReachHere();
421 }
422
423 __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
424 __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
425
426 __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
427
428 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
429 oop_maps->add_gc_map(call_offset, oop_map);
430
431 // Exception handler found
432 __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
433
434 // Restore the registers that were saved at the beginning, remove
435 // frame and jump to the exception handler.
436 switch (id) {
437 case forward_exception_id:
438 case handle_exception_nofpu_id:
439 case handle_exception_id:
440 restore_live_registers(sasm, save_fpu_registers);
441 // Note: the restore live registers includes the jump to LR (patched to R0)
442 break;
443 case handle_exception_from_callee_id:
444 restore_live_registers_without_return(sasm); // must not jump immediatly to handler
445 restore_sp_for_method_handle(sasm);
446 __ ret();
447 break;
448 default: ShouldNotReachHere();
449 }
450
451 DEBUG_ONLY(STOP("generate_handle_exception");) // Should not reach here
452
453 return oop_maps;
454 }
455
456
457 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
458 // FP no longer used to find the frame start
459 // on entry, remove_frame() has already been called (restoring FP and LR)
460
461 // search the exception handler address of the caller (using the return address)
462 __ mov(c_rarg0, Rthread);
463 __ mov(Rexception_pc, LR);
464 __ mov(c_rarg1, LR);
465 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
466
467 // Exception oop should be still in Rexception_obj and pc in Rexception_pc
468 // Jump to handler
469 __ verify_not_null_oop(Rexception_obj);
470
471 // JSR292 extension
472 restore_sp_for_method_handle(sasm);
473
474 __ jump(R0);
475 }
476
477
478 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
479 OopMap* oop_map = save_live_registers(sasm);
480
481 // call the runtime patching routine, returns non-zero if nmethod got deopted.
482 int call_offset = __ call_RT(noreg, noreg, target);
483 OopMapSet* oop_maps = new OopMapSet();
484 oop_maps->add_gc_map(call_offset, oop_map);
485
486 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
487 assert(deopt_blob != NULL, "deoptimization blob must have been created");
488
489 __ cmp_32(R0, 0);
490
491 #ifdef AARCH64
492 Label call_deopt;
493
494 restore_live_registers_without_return(sasm);
495 __ b(call_deopt, ne);
496 __ ret();
497
498 __ bind(call_deopt);
499 #else
500 restore_live_registers_except_FP_LR(sasm);
501 __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
502
503 // Deoptimization needed
504 // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
505 __ pop(RegisterSet(FP) | RegisterSet(LR));
506 #endif // AARCH64
507
508 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
509
510 DEBUG_ONLY(STOP("generate_patching");) // Should not reach here
511 return oop_maps;
512 }
513
514
515 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
516 const bool must_gc_arguments = true;
517 const bool dont_gc_arguments = false;
518
519 OopMapSet* oop_maps = NULL;
520 bool save_fpu_registers = HaveVFP;
521
522 switch (id) {
523 case forward_exception_id:
524 {
525 oop_maps = generate_handle_exception(id, sasm);
526 // does not return on ARM
527 }
528 break;
529
530 #if INCLUDE_ALL_GCS
531 case g1_pre_barrier_slow_id:
532 {
533 // Input:
534 // - pre_val pushed on the stack
535
536 __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
537
538 // save at least the registers that need saving if the runtime is called
539 #ifdef AARCH64
540 __ raw_push(R0, R1);
541 __ raw_push(R2, R3);
542 const int nb_saved_regs = 4;
543 #else // AARCH64
544 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
545 const int nb_saved_regs = 6;
546 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
547 __ push(saved_regs);
548 #endif // AARCH64
549
550 const Register r_pre_val_0 = R0; // must be R0, to be ready for the runtime call
551 const Register r_index_1 = R1;
552 const Register r_buffer_2 = R2;
553
554 Address queue_index(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
555 SATBMarkQueue::byte_offset_of_index()));
556 Address buffer(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
557 SATBMarkQueue::byte_offset_of_buf()));
558
559 Label done;
560 Label runtime;
561
562 __ ldr(r_index_1, queue_index);
563 __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
564 __ ldr(r_buffer_2, buffer);
565
566 __ subs(r_index_1, r_index_1, wordSize);
567 __ b(runtime, lt);
568
569 __ str(r_index_1, queue_index);
570 __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
571
572 __ bind(done);
573
574 #ifdef AARCH64
575 __ raw_pop(R2, R3);
576 __ raw_pop(R0, R1);
577 #else // AARCH64
578 __ pop(saved_regs);
579 #endif // AARCH64
580
581 __ ret();
582
583 __ bind(runtime);
584
585 save_live_registers(sasm);
586
587 assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
588 __ mov(c_rarg1, Rthread);
589 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
590
591 restore_live_registers_without_return(sasm);
592
593 __ b(done);
594 }
595 break;
596 case g1_post_barrier_slow_id:
597 {
598 // Input:
599 // - store_addr, pushed on the stack
600
601 __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
602
603 BarrierSet* bs = Universe::heap()->barrier_set();
604 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
605 Label done;
606 Label recheck;
607 Label runtime;
608
609 Address queue_index(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
610 DirtyCardQueue::byte_offset_of_index()));
611 Address buffer(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
612 DirtyCardQueue::byte_offset_of_buf()));
613
614 AddressLiteral cardtable((address)ct->byte_map_base);
615 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
616
617 // save at least the registers that need saving if the runtime is called
618 #ifdef AARCH64
619 __ raw_push(R0, R1);
620 __ raw_push(R2, R3);
621 const int nb_saved_regs = 4;
622 #else // AARCH64
623 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
624 const int nb_saved_regs = 6;
625 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
626 __ push(saved_regs);
627 #endif // AARCH64
628
629 const Register r_card_addr_0 = R0; // must be R0 for the slow case
630 const Register r_obj_0 = R0;
631 const Register r_card_base_1 = R1;
632 const Register r_tmp2 = R2;
633 const Register r_index_2 = R2;
634 const Register r_buffer_3 = R3;
635 const Register tmp1 = Rtemp;
636
637 __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
638 // Note: there is a comment in x86 code about not using
639 // ExternalAddress / lea, due to relocation not working
640 // properly for that address. Should be OK for arm, where we
641 // explicitly specify that 'cartable' has a relocInfo::none
642 // type.
643 __ lea(r_card_base_1, cardtable);
644 __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTableModRefBS::card_shift));
645
646 // first quick check without barrier
647 __ ldrb(r_tmp2, Address(r_card_addr_0));
648
649 __ cmp(r_tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
650 __ b(recheck, ne);
651
652 __ bind(done);
653
654 #ifdef AARCH64
655 __ raw_pop(R2, R3);
656 __ raw_pop(R0, R1);
657 #else // AARCH64
658 __ pop(saved_regs);
659 #endif // AARCH64
660
661 __ ret();
662
663 __ bind(recheck);
664
665 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
666
667 // reload card state after the barrier that ensures the stored oop was visible
668 __ ldrb(r_tmp2, Address(r_card_addr_0));
669
670 assert(CardTableModRefBS::dirty_card_val() == 0, "adjust this code");
671 __ cbz(r_tmp2, done);
672
673 // storing region crossing non-NULL, card is clean.
674 // dirty card and log.
675
676 assert(0 == (int)CardTableModRefBS::dirty_card_val(), "adjust this code");
677 if (((intptr_t)ct->byte_map_base & 0xff) == 0) {
678 // Card table is aligned so the lowest byte of the table address base is zero.
679 __ strb(r_card_base_1, Address(r_card_addr_0));
680 } else {
681 __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
682 }
683
684 __ ldr(r_index_2, queue_index);
685 __ ldr(r_buffer_3, buffer);
686
687 __ subs(r_index_2, r_index_2, wordSize);
688 __ b(runtime, lt); // go to runtime if now negative
689
690 __ str(r_index_2, queue_index);
691
692 __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
693
694 __ b(done);
695
696 __ bind(runtime);
697
698 save_live_registers(sasm);
699
700 assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
701 __ mov(c_rarg1, Rthread);
702 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
703
704 restore_live_registers_without_return(sasm);
705
706 __ b(done);
707 }
708 break;
709 #endif // INCLUDE_ALL_GCS
710 case new_instance_id:
711 case fast_new_instance_id:
712 case fast_new_instance_init_check_id:
713 {
714 const Register result = R0;
715 const Register klass = R1;
716
717 if (UseTLAB && FastTLABRefill && id != new_instance_id) {
718 // We come here when TLAB allocation failed.
719 // In this case we either refill TLAB or allocate directly from eden.
720 Label retry_tlab, try_eden, slow_case, slow_case_no_pop;
721
722 // Make sure the class is fully initialized
723 if (id == fast_new_instance_init_check_id) {
724 __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
725 __ cmp(result, InstanceKlass::fully_initialized);
726 __ b(slow_case_no_pop, ne);
727 }
728
729 // Free some temporary registers
730 const Register obj_size = R4;
731 const Register tmp1 = R5;
732 const Register tmp2 = LR;
733 const Register obj_end = Rtemp;
734
735 __ raw_push(R4, R5, LR);
736
737 __ tlab_refill(result, obj_size, tmp1, tmp2, obj_end, try_eden, slow_case);
738
739 __ bind(retry_tlab);
740 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
741 __ tlab_allocate(result, obj_end, tmp1, obj_size, slow_case); // initializes result and obj_end
742 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
743 instanceOopDesc::header_size() * HeapWordSize, -1,
744 /* is_tlab_allocated */ true);
745 __ raw_pop_and_ret(R4, R5);
746
747 __ bind(try_eden);
748 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
749 __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case); // initializes result and obj_end
750 __ incr_allocated_bytes(obj_size, tmp2);
751 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
752 instanceOopDesc::header_size() * HeapWordSize, -1,
753 /* is_tlab_allocated */ false);
754 __ raw_pop_and_ret(R4, R5);
755
756 __ bind(slow_case);
757 __ raw_pop(R4, R5, LR);
758
759 __ bind(slow_case_no_pop);
760 }
761
762 OopMap* map = save_live_registers(sasm);
763 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
764 oop_maps = new OopMapSet();
765 oop_maps->add_gc_map(call_offset, map);
766
767 // MacroAssembler::StoreStore useless (included in the runtime exit path)
768
769 restore_live_registers_except_R0(sasm);
770 }
771 break;
772
773 case counter_overflow_id:
774 {
775 OopMap* oop_map = save_live_registers(sasm);
776 __ ldr(R1, Address(SP, arg1_offset));
777 __ ldr(R2, Address(SP, arg2_offset));
778 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
779 oop_maps = new OopMapSet();
780 oop_maps->add_gc_map(call_offset, oop_map);
781 restore_live_registers(sasm);
782 }
783 break;
784
785 case new_type_array_id:
786 case new_object_array_id:
787 {
788 if (id == new_type_array_id) {
789 __ set_info("new_type_array", dont_gc_arguments);
790 } else {
791 __ set_info("new_object_array", dont_gc_arguments);
792 }
793
794 const Register result = R0;
795 const Register klass = R1;
796 const Register length = R2;
797
798 if (UseTLAB && FastTLABRefill) {
799 // We come here when TLAB allocation failed.
800 // In this case we either refill TLAB or allocate directly from eden.
801 Label retry_tlab, try_eden, slow_case, slow_case_no_pop;
802
803 #ifdef AARCH64
804 __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
805 __ cmp_32(length, Rtemp);
806 #else
807 __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
808 #endif // AARCH64
809 __ b(slow_case_no_pop, hs);
810
811 // Free some temporary registers
812 const Register arr_size = R4;
813 const Register tmp1 = R5;
814 const Register tmp2 = LR;
815 const Register tmp3 = Rtemp;
816 const Register obj_end = tmp3;
817
818 __ raw_push(R4, R5, LR);
819
820 __ tlab_refill(result, arr_size, tmp1, tmp2, tmp3, try_eden, slow_case);
821
822 __ bind(retry_tlab);
823 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
824 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
825 __ mov(arr_size, MinObjAlignmentInBytesMask);
826 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
827
828 #ifdef AARCH64
829 __ lslv_w(tmp3, length, tmp1);
830 __ add(arr_size, arr_size, tmp3);
831 #else
832 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
833 #endif // AARCH64
834
835 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
836 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
837
838 // tlab_allocate initializes result and obj_end, and preserves tmp2 which contains header_size
839 __ tlab_allocate(result, obj_end, tmp1, arr_size, slow_case);
840
841 assert_different_registers(result, obj_end, klass, length, tmp1, tmp2);
842 __ initialize_header(result, klass, length, tmp1);
843
844 __ add(tmp2, result, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
845 if (!ZeroTLAB) {
846 __ initialize_body(tmp2, obj_end, tmp1);
847 }
848
849 __ membar(MacroAssembler::StoreStore, tmp1);
850
851 __ raw_pop_and_ret(R4, R5);
852
853 __ bind(try_eden);
854 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
855 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
856 __ mov(arr_size, MinObjAlignmentInBytesMask);
857 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
858
859 #ifdef AARCH64
860 __ lslv_w(tmp3, length, tmp1);
861 __ add(arr_size, arr_size, tmp3);
862 #else
863 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
864 #endif // AARCH64
865
866 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
867 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
868
869 // eden_allocate destroys tmp2, so reload header_size after allocation
870 // eden_allocate initializes result and obj_end
871 __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
872 __ incr_allocated_bytes(arr_size, tmp2);
873 __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
874 Klass::_lh_header_size_shift / BitsPerByte));
875 __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
876 __ raw_pop_and_ret(R4, R5);
877
878 __ bind(slow_case);
879 __ raw_pop(R4, R5, LR);
880 __ bind(slow_case_no_pop);
881 }
882
883 OopMap* map = save_live_registers(sasm);
884 int call_offset;
885 if (id == new_type_array_id) {
886 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
887 } else {
888 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
889 }
890 oop_maps = new OopMapSet();
891 oop_maps->add_gc_map(call_offset, map);
892
893 // MacroAssembler::StoreStore useless (included in the runtime exit path)
894
895 restore_live_registers_except_R0(sasm);
896 }
897 break;
898
899 case new_multi_array_id:
900 {
901 __ set_info("new_multi_array", dont_gc_arguments);
902
903 // R0: klass
904 // R2: rank
905 // SP: address of 1st dimension
906 const Register result = R0;
907 OopMap* map = save_live_registers(sasm);
908
909 __ mov(R1, R0);
910 __ add(R3, SP, arg1_offset);
911 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
912
913 oop_maps = new OopMapSet();
914 oop_maps->add_gc_map(call_offset, map);
915
916 // MacroAssembler::StoreStore useless (included in the runtime exit path)
917
918 restore_live_registers_except_R0(sasm);
919 }
920 break;
921
922 case register_finalizer_id:
923 {
924 __ set_info("register_finalizer", dont_gc_arguments);
925
926 // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
927 __ load_klass(Rtemp, R0);
928 __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
929
930 #ifdef AARCH64
931 Label L;
932 __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
933 __ ret();
934 __ bind(L);
935 #else
936 __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
937 __ bx(LR, eq);
938 #endif // AARCH64
939
940 // Call VM
941 OopMap* map = save_live_registers(sasm);
942 oop_maps = new OopMapSet();
943 int call_offset = __ call_RT(noreg, noreg,
944 CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
945 oop_maps->add_gc_map(call_offset, map);
946 restore_live_registers(sasm);
947 }
948 break;
949
950 case throw_range_check_failed_id:
951 {
952 __ set_info("range_check_failed", dont_gc_arguments);
953 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
954 }
955 break;
956
957 case throw_index_exception_id:
958 {
959 __ set_info("index_range_check_failed", dont_gc_arguments);
960 #ifdef AARCH64
961 __ NOT_TESTED();
962 #endif
963 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
964 }
965 break;
966
967 case throw_div0_exception_id:
968 {
969 __ set_info("throw_div0_exception", dont_gc_arguments);
970 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
971 }
972 break;
973
974 case throw_null_pointer_exception_id:
975 {
976 __ set_info("throw_null_pointer_exception", dont_gc_arguments);
977 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
978 }
979 break;
980
981 case handle_exception_nofpu_id:
982 case handle_exception_id:
983 {
984 __ set_info("handle_exception", dont_gc_arguments);
985 oop_maps = generate_handle_exception(id, sasm);
986 }
987 break;
988
989 case handle_exception_from_callee_id:
990 {
991 __ set_info("handle_exception_from_callee", dont_gc_arguments);
992 oop_maps = generate_handle_exception(id, sasm);
993 }
994 break;
995
996 case unwind_exception_id:
997 {
998 __ set_info("unwind_exception", dont_gc_arguments);
999 generate_unwind_exception(sasm);
1000 }
1001 break;
1002
1003 case throw_array_store_exception_id:
1004 {
1005 __ set_info("throw_array_store_exception", dont_gc_arguments);
1006 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1007 }
1008 break;
1009
1010 case throw_class_cast_exception_id:
1011 {
1012 __ set_info("throw_class_cast_exception", dont_gc_arguments);
1013 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1014 }
1015 break;
1016
1017 case throw_incompatible_class_change_error_id:
1018 {
1019 __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
1020 #ifdef AARCH64
1021 __ NOT_TESTED();
1022 #endif
1023 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1024 }
1025 break;
1026
1027 case slow_subtype_check_id:
1028 {
1029 // (in) R0 - sub, destroyed,
1030 // (in) R1 - super, not changed
1031 // (out) R0 - result: 1 if check passed, 0 otherwise
1032 __ raw_push(R2, R3, LR);
1033
1034 // Load an array of secondary_supers
1035 __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
1036 // Length goes to R3
1037 __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
1038 __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
1039
1040 Label loop, miss;
1041 __ bind(loop);
1042 __ cbz(R3, miss);
1043 __ ldr(LR, Address(R2, wordSize, post_indexed));
1044 __ sub(R3, R3, 1);
1045 __ cmp(LR, R1);
1046 __ b(loop, ne);
1047
1048 // We get here if an equal cache entry is found
1049 __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
1050 __ mov(R0, 1);
1051 __ raw_pop_and_ret(R2, R3);
1052
1053 // A cache entry not found - return false
1054 __ bind(miss);
1055 __ mov(R0, 0);
1056 __ raw_pop_and_ret(R2, R3);
1057 }
1058 break;
1059
1060 case monitorenter_nofpu_id:
1061 save_fpu_registers = false;
1062 // fall through
1063 case monitorenter_id:
1064 {
1065 __ set_info("monitorenter", dont_gc_arguments);
1066 const Register obj = R1;
1067 const Register lock = R2;
1068 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1069 __ ldr(obj, Address(SP, arg1_offset));
1070 __ ldr(lock, Address(SP, arg2_offset));
1071 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
1072 oop_maps = new OopMapSet();
1073 oop_maps->add_gc_map(call_offset, map);
1074 restore_live_registers(sasm, save_fpu_registers);
1075 }
1076 break;
1077
1078 case monitorexit_nofpu_id:
1079 save_fpu_registers = false;
1080 // fall through
1081 case monitorexit_id:
1082 {
1083 __ set_info("monitorexit", dont_gc_arguments);
1084 const Register lock = R1;
1085 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1086 __ ldr(lock, Address(SP, arg1_offset));
1087 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
1088 oop_maps = new OopMapSet();
1089 oop_maps->add_gc_map(call_offset, map);
1090 restore_live_registers(sasm, save_fpu_registers);
1091 }
1092 break;
1093
1094 case deoptimize_id:
1095 {
1096 __ set_info("deoptimize", dont_gc_arguments);
1097 OopMap* oop_map = save_live_registers(sasm);
1098 const Register trap_request = R1;
1099 __ ldr(trap_request, Address(SP, arg1_offset));
1100 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
1101 oop_maps = new OopMapSet();
1102 oop_maps->add_gc_map(call_offset, oop_map);
1103 restore_live_registers_without_return(sasm);
1104 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1105 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1106 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
1107 }
1108 break;
1109
1110 case access_field_patching_id:
1111 {
1112 __ set_info("access_field_patching", dont_gc_arguments);
1113 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1114 }
1115 break;
1116
1117 case load_klass_patching_id:
1118 {
1119 __ set_info("load_klass_patching", dont_gc_arguments);
1120 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1121 }
1122 break;
1123
1124 case load_appendix_patching_id:
1125 {
1126 __ set_info("load_appendix_patching", dont_gc_arguments);
1127 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1128 }
1129 break;
1130
1131 case load_mirror_patching_id:
1132 {
1133 __ set_info("load_mirror_patching", dont_gc_arguments);
1134 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1135 }
1136 break;
1137
1138 case predicate_failed_trap_id:
1139 {
1140 __ set_info("predicate_failed_trap", dont_gc_arguments);
1141
1142 OopMap* oop_map = save_live_registers(sasm);
1143 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1144
1145 oop_maps = new OopMapSet();
1146 oop_maps->add_gc_map(call_offset, oop_map);
1147
1148 restore_live_registers_without_return(sasm);
1149
1150 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1151 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1152 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
1153 }
1154 break;
1155
1156 default:
1157 {
1158 __ set_info("unimplemented entry", dont_gc_arguments);
1159 STOP("unimplemented entry");
1160 }
1161 break;
1162 }
1163 return oop_maps;
1164 }
1165
1166 #undef __
1167
1168 #ifdef __SOFTFP__
1169 const char *Runtime1::pd_name_for_address(address entry) {
1170
1171 #define FUNCTION_CASE(a, f) \
1172 if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f)) return #f
1173
1174 FUNCTION_CASE(entry, __aeabi_fadd_glibc);
1175 FUNCTION_CASE(entry, __aeabi_fmul);
1176 FUNCTION_CASE(entry, __aeabi_fsub_glibc);
1177 FUNCTION_CASE(entry, __aeabi_fdiv);
1178
1179 // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
1180 FUNCTION_CASE(entry, __aeabi_dadd_glibc);
1181 FUNCTION_CASE(entry, __aeabi_dmul);
1182 FUNCTION_CASE(entry, __aeabi_dsub_glibc);
1183 FUNCTION_CASE(entry, __aeabi_ddiv);
1184
1185 FUNCTION_CASE(entry, __aeabi_f2d);
1186 FUNCTION_CASE(entry, __aeabi_d2f);
1187 FUNCTION_CASE(entry, __aeabi_i2f);
1188 FUNCTION_CASE(entry, __aeabi_i2d);
1189 FUNCTION_CASE(entry, __aeabi_f2iz);
1190
1191 FUNCTION_CASE(entry, SharedRuntime::fcmpl);
1192 FUNCTION_CASE(entry, SharedRuntime::fcmpg);
1193 FUNCTION_CASE(entry, SharedRuntime::dcmpl);
1194 FUNCTION_CASE(entry, SharedRuntime::dcmpg);
1195
1196 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
1197 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
1198 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
1199 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
1200 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
1201 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
1202 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
1203 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
1204
1205 FUNCTION_CASE(entry, SharedRuntime::fneg);
1206 FUNCTION_CASE(entry, SharedRuntime::dneg);
1207
1208 FUNCTION_CASE(entry, __aeabi_fcmpeq);
1209 FUNCTION_CASE(entry, __aeabi_fcmplt);
1210 FUNCTION_CASE(entry, __aeabi_fcmple);
1211 FUNCTION_CASE(entry, __aeabi_fcmpge);
1212 FUNCTION_CASE(entry, __aeabi_fcmpgt);
1213
1214 FUNCTION_CASE(entry, __aeabi_dcmpeq);
1215 FUNCTION_CASE(entry, __aeabi_dcmplt);
1216 FUNCTION_CASE(entry, __aeabi_dcmple);
1217 FUNCTION_CASE(entry, __aeabi_dcmpge);
1218 FUNCTION_CASE(entry, __aeabi_dcmpgt);
1219 #undef FUNCTION_CASE
1220 return "";
1221 }
1222 #else // __SOFTFP__
1223 const char *Runtime1::pd_name_for_address(address entry) {
1224 return "<unknown function>";
1225 }
1226 #endif // __SOFTFP__