1 /* 2 * Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP 26 #define CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP 27 28 #include "asm/assembler.inline.hpp" 29 #include "asm/codeBuffer.hpp" 30 #include "code/codeCache.hpp" 31 #include "runtime/handles.inline.hpp" 32 33 inline void MacroAssembler::pd_patch_instruction(address branch, address target) { 34 int instr = *(int*)branch; 35 int new_offset = (int)(target - branch NOT_AARCH64(- 8)); 36 assert((new_offset & 3) == 0, "bad alignment"); 37 38 #ifdef AARCH64 39 if ((instr & (0x1f << 26)) == (0b00101 << 26)) { 40 // Unconditional B or BL 41 assert (is_offset_in_range(new_offset, 26), "offset is too large"); 42 *(int*)branch = (instr & ~right_n_bits(26)) | encode_offset(new_offset, 26, 0); 43 } else if ((instr & (0xff << 24)) == (0b01010100 << 24) && (instr & (1 << 4)) == 0) { 44 // Conditional B 45 assert (is_offset_in_range(new_offset, 19), "offset is too large"); 46 *(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); 47 } else if ((instr & (0b111111 << 25)) == (0b011010 << 25)) { 48 // Compare & branch CBZ/CBNZ 49 assert (is_offset_in_range(new_offset, 19), "offset is too large"); 50 *(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); 51 } else if ((instr & (0b111111 << 25)) == (0b011011 << 25)) { 52 // Test & branch TBZ/TBNZ 53 assert (is_offset_in_range(new_offset, 14), "offset is too large"); 54 *(int*)branch = (instr & ~(right_n_bits(14) << 5)) | encode_offset(new_offset, 14, 5); 55 } else if ((instr & (0b111011 << 24)) == (0b011000 << 24)) { 56 // LDR (literal) 57 unsigned opc = ((unsigned)instr >> 30); 58 assert (opc != 0b01 || ((uintx)target & 7) == 0, "ldr target should be aligned"); 59 assert (is_offset_in_range(new_offset, 19), "offset is too large"); 60 *(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_offset(new_offset, 19, 5); 61 } else if (((instr & (1 << 31)) == 0) && ((instr & (0b11111 << 24)) == (0b10000 << 24))) { 62 // ADR 63 assert (is_imm_in_range(new_offset, 21, 0), "offset is too large"); 64 instr = (instr & ~(right_n_bits(2) << 29)) | (new_offset & 3) << 29; 65 *(int*)branch = (instr & ~(right_n_bits(19) << 5)) | encode_imm(new_offset >> 2, 19, 0, 5); 66 } else if((unsigned int)instr == address_placeholder_instruction) { 67 // address 68 assert (*(unsigned int *)(branch + InstructionSize) == address_placeholder_instruction, "address placeholder occupies two instructions"); 69 *(intx*)branch = (intx)target; 70 } else { 71 ::tty->print_cr("=============== instruction: 0x%x ================\n", instr); 72 Unimplemented(); // TODO-AARCH64 73 } 74 #else 75 if ((instr & 0x0e000000) == 0x0a000000) { 76 // B or BL instruction 77 assert(new_offset < 0x2000000 && new_offset > -0x2000000, "encoding constraint"); 78 *(int*)branch = (instr & 0xff000000) | ((unsigned int)new_offset << 6 >> 8); 79 } else if((unsigned int)instr == address_placeholder_instruction) { 80 // address 81 *(int*)branch = (int)target; 82 } else if ((instr & 0x0fff0000) == 0x028f0000 || ((instr & 0x0fff0000) == 0x024f0000)) { 83 // ADR 84 int encoding = 0x8 << 20; // ADD 85 if (new_offset < 0) { 86 encoding = 0x4 << 20; // SUB 87 new_offset = -new_offset; 88 } 89 AsmOperand o(new_offset); 90 *(int*)branch = (instr & 0xff0ff000) | encoding | o.encoding(); 91 } else { 92 // LDR Rd, [PC, offset] instruction 93 assert((instr & 0x0f7f0000) == 0x051f0000, "Must be ldr_literal"); 94 assert(new_offset < 4096 && new_offset > -4096, "encoding constraint"); 95 if (new_offset >= 0) { 96 *(int*)branch = (instr & 0xff0ff000) | 9 << 20 | new_offset; 97 } else { 98 *(int*)branch = (instr & 0xff0ff000) | 1 << 20 | -new_offset; 99 } 100 } 101 #endif // AARCH64 102 } 103 104 #endif // CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP