*** old/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp	Mon Sep 17 10:29:35 2018
--- new/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp	Mon Sep 17 10:29:35 2018

*** 47,59 ****
--- 47,56 ----
  LIR_Opr FrameMap::R2_metadata_opr;
  LIR_Opr FrameMap::R3_metadata_opr;
  LIR_Opr FrameMap::R4_metadata_opr;
  LIR_Opr FrameMap::R5_metadata_opr;
  
  #ifdef AARCH64
  LIR_Opr FrameMap::ZR_opr;
  #endif // AARCH64
  
  LIR_Opr FrameMap::LR_opr;
  LIR_Opr FrameMap::LR_oop_opr;
  LIR_Opr FrameMap::LR_ptr_opr;
  LIR_Opr FrameMap::FP_opr;

*** 80,95 ****
--- 77,87 ----
      int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
      opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off, type));
    } else if (r_1->is_Register()) {
      Register reg = r_1->as_Register();
      if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
  #ifdef AARCH64
        assert(r_1->next() == r_2, "should be the same");
        opr = as_long_opr(reg);
  #else
        opr = as_long_opr(reg, r_2->as_Register());
  #endif
      } else if (type == T_OBJECT || type == T_ARRAY) {
        opr = as_oop_opr(reg);
      } else if (type == T_METADATA) {
        opr = as_metadata_opr(reg);
      } else {

*** 113,151 ****
--- 105,129 ----
  
    int i;
    int rnum = 0;
  
    // Registers used for allocation
  #ifdef AARCH64
    assert(Rthread == R28 && Rheap_base == R27 && Rtemp == R16, "change the code here");
    for (i = 0; i < 16; i++) {
      map_register(rnum++, as_Register(i));
    }
    for (i = 17; i < 28; i++) {
      map_register(rnum++, as_Register(i));
    }
  #else
    assert(Rthread == R10 && Rtemp == R12, "change the code here");
    for (i = 0; i < 10; i++) {
      map_register(rnum++, as_Register(i));
    }
  #endif // AARCH64
    assert(rnum == pd_nof_cpu_regs_reg_alloc, "should be");
  
    // Registers not used for allocation
    map_register(rnum++, LR); // LR register should be listed first, see c1_LinearScan_arm.hpp::is_processed_reg_num.
    assert(rnum == pd_nof_cpu_regs_processed_in_linearscan, "should be");
  
    map_register(rnum++, Rtemp);
    map_register(rnum++, Rthread);
    map_register(rnum++, FP); // ARM32: R7 or R11
    map_register(rnum++, SP);
  #ifdef AARCH64
    map_register(rnum++, ZR);
  #else
    map_register(rnum++, PC);
  #endif
    assert(rnum == pd_nof_cpu_regs_frame_map, "should be");
  
    _init_done = true;
  
    R0_opr  = as_opr(R0);   R0_oop_opr = as_oop_opr(R0);    R0_metadata_opr = as_metadata_opr(R0);

*** 153,165 ****
--- 131,140 ----
    R2_opr  = as_opr(R2);   R2_oop_opr = as_oop_opr(R2);    R2_metadata_opr = as_metadata_opr(R2);
    R3_opr  = as_opr(R3);   R3_oop_opr = as_oop_opr(R3);    R3_metadata_opr = as_metadata_opr(R3);
    R4_opr  = as_opr(R4);   R4_oop_opr = as_oop_opr(R4);    R4_metadata_opr = as_metadata_opr(R4);
    R5_opr  = as_opr(R5);   R5_oop_opr = as_oop_opr(R5);    R5_metadata_opr = as_metadata_opr(R5);
  
  #ifdef AARCH64
    ZR_opr = as_opr(ZR);
  #endif // AARCH64
  
    LR_opr      = as_opr(LR);
    LR_oop_opr  = as_oop_opr(LR);
    LR_ptr_opr  = as_pointer_opr(LR);
    FP_opr      = as_pointer_opr(FP);

*** 167,190 ****
--- 142,159 ----
    Rthread_opr = as_pointer_opr(Rthread);
  
    // LIR operands for result
    Int_result_opr = R0_opr;
    Object_result_opr = R0_oop_opr;
  #ifdef AARCH64
    Long_result_opr = as_long_opr(R0);
    Float_result_opr = as_float_opr(S0);
    Double_result_opr = as_double_opr(D0);
  #else
    Long_result_opr = as_long_opr(R0, R1);
  #ifdef __ABI_HARD__
    Float_result_opr = as_float_opr(S0);
    Double_result_opr = as_double_opr(D0);
  #else
    Float_result_opr = LIR_OprFact::single_softfp(0);
    Double_result_opr = LIR_OprFact::double_softfp(0, 1);
  #endif // __ABI_HARD__
  #endif // AARCH64
  
    Exception_oop_opr = as_oop_opr(Rexception_obj);
    Exception_pc_opr = as_opr(Rexception_pc);
  
    for (i = 0; i < nof_caller_save_cpu_regs(); i++) {

*** 220,230 ****
--- 189,199 ----
          max_offset = arg_offset;
        }
      }
      java_index += type2size[opr->type()];
    }
!   return max_offset < AARCH64_ONLY(16384) NOT_AARCH64(4096); // TODO-AARCH64 check that LIRAssembler does not generate load/store of byte and half-word with SP as address base
!   return max_offset < 4096;
  }
  
  VMReg FrameMap::fpu_regname(int n) {
    return as_FloatRegister(n)->as_VMReg();
  }