1 /*
   2  * Copyright (c) 2010, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_LIR.hpp"
  27 
  28 FloatRegister LIR_OprDesc::as_float_reg() const {
  29   return as_FloatRegister(fpu_regnr());
  30 }
  31 
  32 FloatRegister LIR_OprDesc::as_double_reg() const {
  33   return as_FloatRegister(fpu_regnrLo());
  34 }
  35 
  36 #ifdef AARCH64
  37 // Reg2 unused.
  38 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
  39   assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
  40   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
  41                              (reg1 << LIR_OprDesc::reg2_shift) |
  42                              LIR_OprDesc::double_type          |
  43                              LIR_OprDesc::fpu_register         |
  44                              LIR_OprDesc::double_size);
  45 }
  46 #else
  47 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
  48   assert(as_FloatRegister(reg2) != fnoreg, "Arm32 holds double in two regs.");
  49   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
  50                              (reg2 << LIR_OprDesc::reg2_shift) |
  51                              LIR_OprDesc::double_type          |
  52                              LIR_OprDesc::fpu_register         |
  53                              LIR_OprDesc::double_size);
  54 }
  55 #endif
  56 
  57 #ifndef PRODUCT
  58 void LIR_Address::verify() const {
  59 #ifdef _LP64
  60   assert(base()->is_cpu_register(), "wrong base operand");
  61 #endif
  62 #ifdef AARCH64
  63   if (base()->type() == T_INT) {
  64     assert(index()->is_single_cpu() && (index()->type() == T_INT), "wrong index operand");
  65   } else {
  66     assert(index()->is_illegal() || index()->is_double_cpu() ||
  67            (index()->is_single_cpu() && (index()->is_oop_register() || index()->type() == T_INT)), "wrong index operand");
  68     assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, "wrong type for addresses");
  69   }
  70 #else
  71   assert(disp() == 0 || index()->is_illegal(), "can't have both");
  72   // Note: offsets higher than 4096 must not be rejected here. They can
  73   // be handled by the back-end or will be rejected if not.
  74 #ifdef _LP64
  75   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
  76   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
  77          "wrong type for addresses");
  78 #else
  79   assert(base()->is_single_cpu(), "wrong base operand");
  80   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
  81   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
  82          "wrong type for addresses");
  83 #endif
  84 #endif // AARCH64
  85 }
  86 #endif // PRODUCT