src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp
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open Cdiff src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp
src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp
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*** 33,48 ****
bool in_native = (decorators & IN_NATIVE) != 0;
switch (type) {
case T_OBJECT:
case T_ARRAY: {
if (in_heap) {
- #ifdef AARCH64
- if (UseCompressedOops) {
- __ ldr_w(dst, src);
- __ decode_heap_oop(dst);
- } else
- #endif // AARCH64
{
__ ldr(dst, src);
}
} else {
assert(in_native, "why else?");
--- 33,42 ----
*** 55,71 ****
case T_CHAR: __ ldrh (dst, src); break;
case T_SHORT: __ ldrsh (dst, src); break;
case T_INT: __ ldr_s32 (dst, src); break;
case T_ADDRESS: __ ldr (dst, src); break;
case T_LONG:
- #ifdef AARCH64
- __ ldr (dst, src); break;
- #else
assert(dst == noreg, "only to ltos");
__ add (src.index(), src.index(), src.base());
__ ldmia (src.index(), RegisterSet(R0_tos_lo) | RegisterSet(R1_tos_hi));
- #endif // AARCH64
break;
#ifdef __SOFTFP__
case T_FLOAT:
assert(dst == noreg, "only to ftos");
__ ldr (R0_tos, src);
--- 49,61 ----
*** 98,116 ****
bool in_native = (decorators & IN_NATIVE) != 0;
switch (type) {
case T_OBJECT:
case T_ARRAY: {
if (in_heap) {
- #ifdef AARCH64
- if (UseCompressedOops) {
- assert(!dst.uses(src), "not enough registers");
- if (!is_null) {
- __ encode_heap_oop(src);
- }
- __ str_w(val, obj);
- } else
- #endif // AARCH64
{
__ str(val, obj);
}
} else {
assert(in_native, "why else?");
--- 88,97 ----
*** 126,142 ****
case T_CHAR: __ strh (val, obj); break;
case T_SHORT: __ strh (val, obj); break;
case T_INT: __ str (val, obj); break;
case T_ADDRESS: __ str (val, obj); break;
case T_LONG:
- #ifdef AARCH64
- __ str (val, obj); break;
- #else // AARCH64
assert(val == noreg, "only tos");
__ add (obj.index(), obj.index(), obj.base());
__ stmia (obj.index(), RegisterSet(R0_tos_lo) | RegisterSet(R1_tos_hi));
- #endif // AARCH64
break;
#ifdef __SOFTFP__
case T_FLOAT:
assert(val == noreg, "only tos");
__ str (R0_tos, obj);
--- 107,119 ----
src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp
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