1 /*
   2  * Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP
  26 #define CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP
  27 
  28 #include "asm/assembler.inline.hpp"
  29 #include "asm/codeBuffer.hpp"
  30 #include "code/codeCache.hpp"
  31 #include "runtime/handles.inline.hpp"
  32 
  33 inline void MacroAssembler::pd_patch_instruction(address branch, address target, const char* file, int line) {
  34   int instr = *(int*)branch;
  35   int new_offset = (int)(target - branch - 8);
  36   assert((new_offset & 3) == 0, "bad alignment");
  37 
  38   if ((instr & 0x0e000000) == 0x0a000000) {
  39     // B or BL instruction
  40     assert(new_offset < 0x2000000 && new_offset > -0x2000000, "encoding constraint");
  41     *(int*)branch = (instr & 0xff000000) | ((unsigned int)new_offset << 6 >> 8);
  42   } else if((unsigned int)instr == address_placeholder_instruction) {
  43     // address
  44     *(int*)branch = (int)target;
  45   } else if ((instr & 0x0fff0000) == 0x028f0000 || ((instr & 0x0fff0000) == 0x024f0000)) {
  46     // ADR
  47     int encoding = 0x8 << 20; // ADD
  48     if (new_offset < 0) {
  49       encoding = 0x4 << 20; // SUB
  50       new_offset = -new_offset;
  51     }
  52     AsmOperand o(new_offset);
  53     *(int*)branch = (instr & 0xff0ff000) | encoding | o.encoding();
  54   } else {
  55     // LDR Rd, [PC, offset] instruction
  56     assert((instr & 0x0f7f0000) == 0x051f0000, "Must be ldr_literal");
  57     assert(new_offset < 4096 && new_offset > -4096, "encoding constraint");
  58     if (new_offset >= 0) {
  59       *(int*)branch = (instr & 0xff0ff000) | 9 << 20 | new_offset;
  60     } else {
  61       *(int*)branch = (instr & 0xff0ff000) | 1 << 20 | -new_offset;
  62     }
  63   }
  64 }
  65 
  66 #endif // CPU_ARM_VM_MACROASSEMBLER_ARM_INLINE_HPP