1 /*
   2  * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  23  */
  24 
  25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
  26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
  27 
  28 #include "runtime/orderAccess.hpp"
  29 #include "runtime/os.hpp"
  30 #include "vm_version_arm.hpp"
  31 
  32 // Implementation of class OrderAccess.
  33 // - we define the high level barriers below and use the general
  34 //   implementation in orderAccess.inline.hpp, with customizations
  35 //   on AARCH64 via the specialized_* template functions
  36 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1
  37 
  38 // Memory Ordering on ARM is weak.
  39 //
  40 // Implement all 4 memory ordering barriers by DMB, since it is a
  41 // lighter version of DSB.
  42 // dmb_sy implies full system shareability domain. RD/WR access type.
  43 // dmb_st implies full system shareability domain. WR only access type.
  44 //
  45 // NOP on < ARMv6 (MP not supported)
  46 //
  47 // Non mcr instructions can be used if we build for armv7 or higher arch
  48 //    __asm__ __volatile__ ("dmb" : : : "memory");
  49 //    __asm__ __volatile__ ("dsb" : : : "memory");
  50 //
  51 // inline void _OrderAccess_dsb() {
  52 //    volatile intptr_t dummy = 0;
  53 //    if (os::is_MP()) {
  54 //      __asm__ volatile (
  55 //        "mcr p15, 0, %0, c7, c10, 4"
  56 //        : : "r" (dummy) : "memory");
  57 //   }
  58 // }
  59 
  60 inline static void dmb_sy() {
  61    if (!os::is_MP()) {
  62      return;
  63    }
  64 #ifdef AARCH64
  65    __asm__ __volatile__ ("dmb sy" : : : "memory");
  66 #else
  67    if (VM_Version::arm_arch() >= 7) {
  68 #ifdef __thumb__
  69      __asm__ volatile (
  70      "dmb sy": : : "memory");
  71 #else
  72      __asm__ volatile (
  73      ".word 0xF57FF050 | 0xf" : : : "memory");
  74 #endif
  75    } else {
  76      intptr_t zero = 0;
  77      __asm__ volatile (
  78        "mcr p15, 0, %0, c7, c10, 5"
  79        : : "r" (zero) : "memory");
  80    }
  81 #endif
  82 }
  83 
  84 inline static void dmb_st() {
  85    if (!os::is_MP()) {
  86      return;
  87    }
  88 #ifdef AARCH64
  89    __asm__ __volatile__ ("dmb st" : : : "memory");
  90 #else
  91    if (VM_Version::arm_arch() >= 7) {
  92 #ifdef __thumb__
  93      __asm__ volatile (
  94      "dmb st": : : "memory");
  95 #else
  96      __asm__ volatile (
  97      ".word 0xF57FF050 | 0xe" : : : "memory");
  98 #endif
  99    } else {
 100      intptr_t zero = 0;
 101      __asm__ volatile (
 102        "mcr p15, 0, %0, c7, c10, 5"
 103        : : "r" (zero) : "memory");
 104    }
 105 #endif
 106 }
 107 
 108 // Load-Load/Store barrier
 109 inline static void dmb_ld() {
 110 #ifdef AARCH64
 111    if (!os::is_MP()) {
 112      return;
 113    }
 114    __asm__ __volatile__ ("dmb ld" : : : "memory");
 115 #else
 116    dmb_sy();
 117 #endif
 118 }
 119 
 120 
 121 inline void OrderAccess::loadload()   { dmb_ld(); }
 122 inline void OrderAccess::loadstore()  { dmb_ld(); }
 123 inline void OrderAccess::acquire()    { dmb_ld(); }
 124 inline void OrderAccess::storestore() { dmb_st(); }
 125 inline void OrderAccess::storeload()  { dmb_sy(); }
 126 inline void OrderAccess::release()    { dmb_sy(); }
 127 inline void OrderAccess::fence()      { dmb_sy(); }
 128 
 129 // specializations for Aarch64
 130 // TODO-AARCH64: evaluate effectiveness of ldar*/stlr* implementations compared to 32-bit ARM approach
 131 
 132 #ifdef AARCH64
 133 
 134 template<> inline jbyte    OrderAccess::specialized_load_acquire<jbyte>(volatile jbyte*   p) {
 135   volatile jbyte result;
 136   __asm__ volatile(
 137     "ldarb %w[res], [%[ptr]]"
 138     : [res] "=&r" (result)
 139     : [ptr] "r" (p)
 140     : "memory");
 141   return result;
 142 }
 143 
 144 template<> inline jshort   OrderAccess::specialized_load_acquire<jshort>(volatile jshort*  p) {
 145   volatile jshort result;
 146   __asm__ volatile(
 147     "ldarh %w[res], [%[ptr]]"
 148     : [res] "=&r" (result)
 149     : [ptr] "r" (p)
 150     : "memory");
 151   return result;
 152 }
 153 
 154 template<> inline jint     OrderAccess::specialized_load_acquire<jint>(volatile jint*    p) {
 155   volatile jint result;
 156   __asm__ volatile(
 157     "ldar %w[res], [%[ptr]]"
 158     : [res] "=&r" (result)
 159     : [ptr] "r" (p)
 160     : "memory");
 161   return result;
 162 }
 163 
 164 template<> inline jfloat   OrderAccess::specialized_load_acquire<jfloat>(volatile jfloat*  p) {
 165   return jfloat_cast(specialized_load_acquire((volatile jint*)p));
 166 }
 167 
 168 // This is implicit as jlong and intptr_t are both "long int"
 169 //template<> inline jlong    OrderAccess::specialized_load_acquire(volatile jlong*   p) {
 170 //  return (volatile jlong)specialized_load_acquire((volatile intptr_t*)p);
 171 //}
 172 
 173 template<> inline intptr_t OrderAccess::specialized_load_acquire<intptr_t>(volatile intptr_t*   p) {
 174   volatile intptr_t result;
 175   __asm__ volatile(
 176     "ldar %[res], [%[ptr]]"
 177     : [res] "=&r" (result)
 178     : [ptr] "r" (p)
 179     : "memory");
 180   return result;
 181 }
 182 
 183 template<> inline jdouble  OrderAccess::specialized_load_acquire<jdouble>(volatile jdouble* p) {
 184   return jdouble_cast(specialized_load_acquire((volatile intptr_t*)p));
 185 }
 186 
 187 
 188 template<> inline void     OrderAccess::specialized_release_store<jbyte>(volatile jbyte*   p, jbyte   v) {
 189   __asm__ volatile(
 190     "stlrb %w[val], [%[ptr]]"
 191     :
 192     : [ptr] "r" (p), [val] "r" (v)
 193     : "memory");
 194 }
 195 
 196 template<> inline void     OrderAccess::specialized_release_store<jshort>(volatile jshort*  p, jshort  v) {
 197   __asm__ volatile(
 198     "stlrh %w[val], [%[ptr]]"
 199     :
 200     : [ptr] "r" (p), [val] "r" (v)
 201     : "memory");
 202 }
 203 
 204 template<> inline void     OrderAccess::specialized_release_store<jint>(volatile jint*    p, jint    v) {
 205   __asm__ volatile(
 206     "stlr %w[val], [%[ptr]]"
 207     :
 208     : [ptr] "r" (p), [val] "r" (v)
 209     : "memory");
 210 }
 211 
 212 template<> inline void     OrderAccess::specialized_release_store<jlong>(volatile jlong*   p, jlong   v) {
 213   __asm__ volatile(
 214     "stlr %[val], [%[ptr]]"
 215     :
 216     : [ptr] "r" (p), [val] "r" (v)
 217     : "memory");
 218 }
 219 #endif // AARCH64
 220 
 221 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP