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src/hotspot/cpu/x86/x86_64.ad
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*** 3656,3665 ****
--- 3656,3674 ----
format %{ %}
interface(REG_INTER);
%}
// Float register operands
+ operand legRegF() %{
+ constraint(ALLOC_IN_RC(float_reg_legacy));
+ match(RegF);
+
+ format %{ %}
+ interface(REG_INTER);
+ %}
+
+ // Float register operands
operand vlRegF() %{
constraint(ALLOC_IN_RC(float_reg_vl));
match(RegF);
format %{ %}
*** 3674,3683 ****
--- 3683,3701 ----
format %{ %}
interface(REG_INTER);
%}
// Double register operands
+ operand legRegD() %{
+ constraint(ALLOC_IN_RC(double_reg_legacy));
+ match(RegD);
+
+ format %{ %}
+ interface(REG_INTER);
+ %}
+
+ // Double register operands
operand vlRegD() %{
constraint(ALLOC_IN_RC(double_reg_vl));
match(RegD);
format %{ %}
*** 5412,5430 ****
--- 5430,5472 ----
%}
ins_pipe( fpu_reg_reg );
%}
// Load Float
+ instruct MoveF2LEG(legRegF dst, regF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
+ // Load Float
instruct MoveVL2F(regF dst, vlRegF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
ins_encode %{
__ movflt($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe( fpu_reg_reg );
%}
+ // Load Float
+ instruct MoveLEG2F(regF dst, legRegF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
// Load Double
instruct loadD_partial(regD dst, memory mem)
%{
predicate(!UseXmmLoadAndClearUpper);
match(Set dst (LoadD mem));
*** 5459,5477 ****
--- 5501,5644 ----
%}
ins_pipe( fpu_reg_reg );
%}
// Load Double
+ instruct MoveD2LEG(legRegD dst, regD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
+ // Load Double
instruct MoveVL2D(regD dst, vlRegD src) %{
match(Set dst src);
format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
ins_encode %{
__ movdbl($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe( fpu_reg_reg );
%}
+ // Load Double
+ instruct MoveLEG2D(regD dst, legRegD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
+ // Following pseudo code describes the algorithm for max[FD]:
+ // Min algorithm is on similar lines
+ // btmp = (b < +0.0) ? a : b
+ // atmp = (b < +0.0) ? b : a
+ // Tmp = Max_Float(atmp , btmp)
+ // Res = (atmp == NaN) ? atmp : Tmp
+
+ // max = java.lang.Math.max(float a, float b)
+ instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
+ predicate(UseAVX > 0);
+ match(Set dst (MaxF a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvps $btmp,$b,$a,$b \n\t"
+ "blendvps $atmp,$a,$b,$b \n\t"
+ "vmaxss $tmp,$atmp,$btmp \n\t"
+ "cmpps.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvps $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+ %}
+
+
+ // max = java.lang.Math.max(double a, double b)
+ instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
+ predicate(UseAVX > 0);
+ match(Set dst (MaxD a b));
+ effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
+ format %{
+ "blendvpd $btmp,$b,$a,$b \n\t"
+ "blendvpd $atmp,$a,$b,$b \n\t"
+ "vmaxsd $tmp,$atmp,$btmp \n\t"
+ "cmppd.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
+ __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+ %}
+
+
+ // min = java.lang.Math.min(float a, float b)
+ instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
+ predicate(UseAVX > 0);
+ match(Set dst (MinF a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvps $atmp,$a,$b,$a \n\t"
+ "blendvps $btmp,$b,$a,$a \n\t"
+ "vminss $tmp,$atmp,$btmp \n\t"
+ "cmpps.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvps $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+ %}
+
+ // min = java.lang.Math.min(double a, double b)
+ instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
+ predicate(UseAVX > 0);
+ match(Set dst (MinD a b));
+ effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
+ format %{
+ "blendvpd $atmp,$a,$b,$a \n\t"
+ "blendvpd $btmp,$b,$a,$a \n\t"
+ "vminsd $tmp,$atmp,$btmp \n\t"
+ "cmppd.unordered $btmp,$atmp,$atmp \n\t"
+ "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
+ %}
+ ins_encode %{
+ int vector_len = Assembler::AVX_128bit;
+ __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
+ __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
+ __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
+ __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
+ %}
+ ins_pipe( pipe_slow );
+ %}
+
// Load Effective Address
instruct leaP8(rRegP dst, indOffset8 mem)
%{
match(Set dst mem);
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