1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer/long registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all int registers
191 reg_class all_int_reg(RAX
192 RDX,
193 RBP,
194 RDI,
195 RSI,
196 RCX,
197 RBX,
198 R8,
199 R9,
200 R10,
201 R11,
202 R12,
203 R13,
204 R14);
205
206 // Class for all pointer registers
207 reg_class any_reg %{
208 return _ANY_REG_mask;
209 %}
210
211 // Class for all pointer registers (excluding RSP)
212 reg_class ptr_reg %{
213 return _PTR_REG_mask;
214 %}
215
216 // Class for all pointer registers (excluding RSP and RBP)
217 reg_class ptr_reg_no_rbp %{
218 return _PTR_REG_NO_RBP_mask;
219 %}
220
221 // Class for all pointer registers (excluding RAX and RSP)
222 reg_class ptr_no_rax_reg %{
223 return _PTR_NO_RAX_REG_mask;
224 %}
225
226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
227 reg_class ptr_no_rax_rbx_reg %{
228 return _PTR_NO_RAX_RBX_REG_mask;
229 %}
230
231 // Class for all long registers (excluding RSP)
232 reg_class long_reg %{
233 return _LONG_REG_mask;
234 %}
235
236 // Class for all long registers (excluding RAX, RDX and RSP)
237 reg_class long_no_rax_rdx_reg %{
238 return _LONG_NO_RAX_RDX_REG_mask;
239 %}
240
241 // Class for all long registers (excluding RCX and RSP)
242 reg_class long_no_rcx_reg %{
243 return _LONG_NO_RCX_REG_mask;
244 %}
245
246 // Class for all int registers (excluding RSP)
247 reg_class int_reg %{
248 return _INT_REG_mask;
249 %}
250
251 // Class for all int registers (excluding RAX, RDX, and RSP)
252 reg_class int_no_rax_rdx_reg %{
253 return _INT_NO_RAX_RDX_REG_mask;
254 %}
255
256 // Class for all int registers (excluding RCX and RSP)
257 reg_class int_no_rcx_reg %{
258 return _INT_NO_RCX_REG_mask;
259 %}
260
261 // Singleton class for RAX pointer register
262 reg_class ptr_rax_reg(RAX, RAX_H);
263
264 // Singleton class for RBX pointer register
265 reg_class ptr_rbx_reg(RBX, RBX_H);
266
267 // Singleton class for RSI pointer register
268 reg_class ptr_rsi_reg(RSI, RSI_H);
269
270 // Singleton class for RDI pointer register
271 reg_class ptr_rdi_reg(RDI, RDI_H);
272
273 // Singleton class for stack pointer
274 reg_class ptr_rsp_reg(RSP, RSP_H);
275
276 // Singleton class for TLS pointer
277 reg_class ptr_r15_reg(R15, R15_H);
278
279 // Singleton class for RAX long register
280 reg_class long_rax_reg(RAX, RAX_H);
281
282 // Singleton class for RCX long register
283 reg_class long_rcx_reg(RCX, RCX_H);
284
285 // Singleton class for RDX long register
286 reg_class long_rdx_reg(RDX, RDX_H);
287
288 // Singleton class for RAX int register
289 reg_class int_rax_reg(RAX);
290
291 // Singleton class for RBX int register
292 reg_class int_rbx_reg(RBX);
293
294 // Singleton class for RCX int register
295 reg_class int_rcx_reg(RCX);
296
297 // Singleton class for RCX int register
298 reg_class int_rdx_reg(RDX);
299
300 // Singleton class for RCX int register
301 reg_class int_rdi_reg(RDI);
302
303 // Singleton class for instruction pointer
304 // reg_class ip_reg(RIP);
305
306 %}
307
308 //----------SOURCE BLOCK-------------------------------------------------------
309 // This is a block of C++ code which provides values, functions, and
310 // definitions necessary in the rest of the architecture description
311 source_hpp %{
312
313 extern RegMask _ANY_REG_mask;
314 extern RegMask _PTR_REG_mask;
315 extern RegMask _PTR_REG_NO_RBP_mask;
316 extern RegMask _PTR_NO_RAX_REG_mask;
317 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
318 extern RegMask _LONG_REG_mask;
319 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
320 extern RegMask _LONG_NO_RCX_REG_mask;
321 extern RegMask _INT_REG_mask;
322 extern RegMask _INT_NO_RAX_RDX_REG_mask;
323 extern RegMask _INT_NO_RCX_REG_mask;
324
325 extern RegMask _STACK_OR_PTR_REG_mask;
326 extern RegMask _STACK_OR_LONG_REG_mask;
327 extern RegMask _STACK_OR_INT_REG_mask;
328
329 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
330 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
331 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
332
333 %}
334
335 source %{
336 #define RELOC_IMM64 Assembler::imm_operand
337 #define RELOC_DISP32 Assembler::disp32_operand
338
339 #define __ _masm.
340
341 RegMask _ANY_REG_mask;
342 RegMask _PTR_REG_mask;
343 RegMask _PTR_REG_NO_RBP_mask;
344 RegMask _PTR_NO_RAX_REG_mask;
345 RegMask _PTR_NO_RAX_RBX_REG_mask;
346 RegMask _LONG_REG_mask;
347 RegMask _LONG_NO_RAX_RDX_REG_mask;
348 RegMask _LONG_NO_RCX_REG_mask;
349 RegMask _INT_REG_mask;
350 RegMask _INT_NO_RAX_RDX_REG_mask;
351 RegMask _INT_NO_RCX_REG_mask;
352 RegMask _STACK_OR_PTR_REG_mask;
353 RegMask _STACK_OR_LONG_REG_mask;
354 RegMask _STACK_OR_INT_REG_mask;
355
356 static bool need_r12_heapbase() {
357 return UseCompressedOops || UseCompressedClassPointers;
358 }
359
360 void reg_mask_init() {
361 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
362 // We derive a number of subsets from it.
363 _ANY_REG_mask = _ALL_REG_mask;
364
365 if (PreserveFramePointer) {
366 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
367 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
368 }
369 if (need_r12_heapbase()) {
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
371 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
372 }
373
374 _PTR_REG_mask = _ANY_REG_mask;
375 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
376 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
377 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
379
380 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
381 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
382
383 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
384 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
385 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
386
387 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
388 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
389 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
390
391 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
392 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
393 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
394
395 _LONG_REG_mask = _PTR_REG_mask;
396 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
397 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
398
399 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
400 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
401 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
402 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
404
405 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
406 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
407 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
408
409 _INT_REG_mask = _ALL_INT_REG_mask;
410 if (PreserveFramePointer) {
411 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
412 }
413 if (need_r12_heapbase()) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
415 }
416
417 _STACK_OR_INT_REG_mask = _INT_REG_mask;
418 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
419
420 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
421 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
422 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
423
424 _INT_NO_RCX_REG_mask = _INT_REG_mask;
425 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
426 }
427
428 static bool generate_vzeroupper(Compile* C) {
429 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
430 }
431
432 static int clear_avx_size() {
433 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
434 }
435
436 // !!!!! Special hack to get all types of calls to specify the byte offset
437 // from the start of the call to the point where the return address
438 // will point.
439 int MachCallStaticJavaNode::ret_addr_offset()
440 {
441 int offset = 5; // 5 bytes from start of call to where return address points
442 offset += clear_avx_size();
443 return offset;
444 }
445
446 int MachCallDynamicJavaNode::ret_addr_offset()
447 {
448 int offset = 15; // 15 bytes from start of call to where return address points
449 offset += clear_avx_size();
450 return offset;
451 }
452
453 int MachCallRuntimeNode::ret_addr_offset() {
454 int offset = 13; // movq r10,#addr; callq (r10)
455 offset += clear_avx_size();
456 return offset;
457 }
458
459 // Indicate if the safepoint node needs the polling page as an input,
460 // it does if the polling page is more than disp32 away.
461 bool SafePointNode::needs_polling_address_input()
462 {
463 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
464 }
465
466 //
467 // Compute padding required for nodes which need alignment
468 //
469
470 // The address of the call instruction needs to be 4-byte aligned to
471 // ensure that it does not span a cache line so that it can be patched.
472 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
473 {
474 current_offset += clear_avx_size(); // skip vzeroupper
475 current_offset += 1; // skip call opcode byte
476 return align_up(current_offset, alignment_required()) - current_offset;
477 }
478
479 // The address of the call instruction needs to be 4-byte aligned to
480 // ensure that it does not span a cache line so that it can be patched.
481 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
482 {
483 current_offset += clear_avx_size(); // skip vzeroupper
484 current_offset += 11; // skip movq instruction + call opcode byte
485 return align_up(current_offset, alignment_required()) - current_offset;
486 }
487
488 // EMIT_RM()
489 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
490 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
491 cbuf.insts()->emit_int8(c);
492 }
493
494 // EMIT_CC()
495 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
496 unsigned char c = (unsigned char) (f1 | f2);
497 cbuf.insts()->emit_int8(c);
498 }
499
500 // EMIT_OPCODE()
501 void emit_opcode(CodeBuffer &cbuf, int code) {
502 cbuf.insts()->emit_int8((unsigned char) code);
503 }
504
505 // EMIT_OPCODE() w/ relocation information
506 void emit_opcode(CodeBuffer &cbuf,
507 int code, relocInfo::relocType reloc, int offset, int format)
508 {
509 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
510 emit_opcode(cbuf, code);
511 }
512
513 // EMIT_D8()
514 void emit_d8(CodeBuffer &cbuf, int d8) {
515 cbuf.insts()->emit_int8((unsigned char) d8);
516 }
517
518 // EMIT_D16()
519 void emit_d16(CodeBuffer &cbuf, int d16) {
520 cbuf.insts()->emit_int16(d16);
521 }
522
523 // EMIT_D32()
524 void emit_d32(CodeBuffer &cbuf, int d32) {
525 cbuf.insts()->emit_int32(d32);
526 }
527
528 // EMIT_D64()
529 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
530 cbuf.insts()->emit_int64(d64);
531 }
532
533 // emit 32 bit value and construct relocation entry from relocInfo::relocType
534 void emit_d32_reloc(CodeBuffer& cbuf,
535 int d32,
536 relocInfo::relocType reloc,
537 int format)
538 {
539 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
540 cbuf.relocate(cbuf.insts_mark(), reloc, format);
541 cbuf.insts()->emit_int32(d32);
542 }
543
544 // emit 32 bit value and construct relocation entry from RelocationHolder
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
546 #ifdef ASSERT
547 if (rspec.reloc()->type() == relocInfo::oop_type &&
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
549 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
551 }
552 #endif
553 cbuf.relocate(cbuf.insts_mark(), rspec, format);
554 cbuf.insts()->emit_int32(d32);
555 }
556
557 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
558 address next_ip = cbuf.insts_end() + 4;
559 emit_d32_reloc(cbuf, (int) (addr - next_ip),
560 external_word_Relocation::spec(addr),
561 RELOC_DISP32);
562 }
563
564
565 // emit 64 bit value and construct relocation entry from relocInfo::relocType
566 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
567 cbuf.relocate(cbuf.insts_mark(), reloc, format);
568 cbuf.insts()->emit_int64(d64);
569 }
570
571 // emit 64 bit value and construct relocation entry from RelocationHolder
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
573 #ifdef ASSERT
574 if (rspec.reloc()->type() == relocInfo::oop_type &&
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
576 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
577 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
578 "cannot embed scavengable oops in code");
579 }
580 #endif
581 cbuf.relocate(cbuf.insts_mark(), rspec, format);
582 cbuf.insts()->emit_int64(d64);
583 }
584
585 // Access stack slot for load or store
586 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
587 {
588 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
589 if (-0x80 <= disp && disp < 0x80) {
590 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
591 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
592 emit_d8(cbuf, disp); // Displacement // R/M byte
593 } else {
594 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
595 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
596 emit_d32(cbuf, disp); // Displacement // R/M byte
597 }
598 }
599
600 // rRegI ereg, memory mem) %{ // emit_reg_mem
601 void encode_RegMem(CodeBuffer &cbuf,
602 int reg,
603 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
604 {
605 assert(disp_reloc == relocInfo::none, "cannot have disp");
606 int regenc = reg & 7;
607 int baseenc = base & 7;
608 int indexenc = index & 7;
609
610 // There is no index & no scale, use form without SIB byte
611 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
612 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
613 if (disp == 0 && base != RBP_enc && base != R13_enc) {
614 emit_rm(cbuf, 0x0, regenc, baseenc); // *
615 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
616 // If 8-bit displacement, mode 0x1
617 emit_rm(cbuf, 0x1, regenc, baseenc); // *
618 emit_d8(cbuf, disp);
619 } else {
620 // If 32-bit displacement
621 if (base == -1) { // Special flag for absolute address
622 emit_rm(cbuf, 0x0, regenc, 0x5); // *
623 if (disp_reloc != relocInfo::none) {
624 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
625 } else {
626 emit_d32(cbuf, disp);
627 }
628 } else {
629 // Normal base + offset
630 emit_rm(cbuf, 0x2, regenc, baseenc); // *
631 if (disp_reloc != relocInfo::none) {
632 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
633 } else {
634 emit_d32(cbuf, disp);
635 }
636 }
637 }
638 } else {
639 // Else, encode with the SIB byte
640 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
641 if (disp == 0 && base != RBP_enc && base != R13_enc) {
642 // If no displacement
643 emit_rm(cbuf, 0x0, regenc, 0x4); // *
644 emit_rm(cbuf, scale, indexenc, baseenc);
645 } else {
646 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
647 // If 8-bit displacement, mode 0x1
648 emit_rm(cbuf, 0x1, regenc, 0x4); // *
649 emit_rm(cbuf, scale, indexenc, baseenc);
650 emit_d8(cbuf, disp);
651 } else {
652 // If 32-bit displacement
653 if (base == 0x04 ) {
654 emit_rm(cbuf, 0x2, regenc, 0x4);
655 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
656 } else {
657 emit_rm(cbuf, 0x2, regenc, 0x4);
658 emit_rm(cbuf, scale, indexenc, baseenc); // *
659 }
660 if (disp_reloc != relocInfo::none) {
661 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
662 } else {
663 emit_d32(cbuf, disp);
664 }
665 }
666 }
667 }
668 }
669
670 // This could be in MacroAssembler but it's fairly C2 specific
671 void emit_cmpfp_fixup(MacroAssembler& _masm) {
672 Label exit;
673 __ jccb(Assembler::noParity, exit);
674 __ pushf();
675 //
676 // comiss/ucomiss instructions set ZF,PF,CF flags and
677 // zero OF,AF,SF for NaN values.
678 // Fixup flags by zeroing ZF,PF so that compare of NaN
679 // values returns 'less than' result (CF is set).
680 // Leave the rest of flags unchanged.
681 //
682 // 7 6 5 4 3 2 1 0
683 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
684 // 0 0 1 0 1 0 1 1 (0x2B)
685 //
686 __ andq(Address(rsp, 0), 0xffffff2b);
687 __ popf();
688 __ bind(exit);
689 }
690
691 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
692 Label done;
693 __ movl(dst, -1);
694 __ jcc(Assembler::parity, done);
695 __ jcc(Assembler::below, done);
696 __ setb(Assembler::notEqual, dst);
697 __ movzbl(dst, dst);
698 __ bind(done);
699 }
700
701 // Math.min() # Math.max()
702 // --------------------------
703 // ucomis[s/d] #
704 // ja -> b # a
705 // jp -> NaN # NaN
706 // jb -> a # b
707 // je #
708 // |-jz -> a | b # a & b
709 // | -> a #
710 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
711 XMMRegister a, XMMRegister b,
712 XMMRegister xmmt, Register rt,
713 bool min, bool single) {
714
715 Label nan, zero, below, above, done;
716
717 if (single)
718 __ ucomiss(a, b);
719 else
720 __ ucomisd(a, b);
721
722 if (dst->encoding() != (min ? b : a)->encoding())
723 __ jccb(Assembler::above, above); // CF=0 & ZF=0
724 else
725 __ jccb(Assembler::above, done);
726
727 __ jccb(Assembler::parity, nan); // PF=1
728 __ jccb(Assembler::below, below); // CF=1
729
730 // equal
731 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
732 if (single) {
733 __ ucomiss(a, xmmt);
734 __ jccb(Assembler::equal, zero);
735
736 __ movflt(dst, a);
737 __ jmp(done);
738 }
739 else {
740 __ ucomisd(a, xmmt);
741 __ jccb(Assembler::equal, zero);
742
743 __ movdbl(dst, a);
744 __ jmp(done);
745 }
746
747 __ bind(zero);
748 if (min)
749 __ vpor(dst, a, b, Assembler::AVX_128bit);
750 else
751 __ vpand(dst, a, b, Assembler::AVX_128bit);
752
753 __ jmp(done);
754
755 __ bind(above);
756 if (single)
757 __ movflt(dst, min ? b : a);
758 else
759 __ movdbl(dst, min ? b : a);
760
761 __ jmp(done);
762
763 __ bind(nan);
764 if (single) {
765 __ movl(rt, 0x7fc00000); // Float.NaN
766 __ movdl(dst, rt);
767 }
768 else {
769 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
770 __ movdq(dst, rt);
771 }
772 __ jmp(done);
773
774 __ bind(below);
775 if (single)
776 __ movflt(dst, min ? a : b);
777 else
778 __ movdbl(dst, min ? a : b);
779
780 __ bind(done);
781 }
782
783 //=============================================================================
784 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
785
786 int Compile::ConstantTable::calculate_table_base_offset() const {
787 return 0; // absolute addressing, no offset
788 }
789
790 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
791 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
792 ShouldNotReachHere();
793 }
794
795 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
796 // Empty encoding
797 }
798
799 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
800 return 0;
801 }
802
803 #ifndef PRODUCT
804 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
805 st->print("# MachConstantBaseNode (empty encoding)");
806 }
807 #endif
808
809
810 //=============================================================================
811 #ifndef PRODUCT
812 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
813 Compile* C = ra_->C;
814
815 int framesize = C->frame_size_in_bytes();
816 int bangsize = C->bang_size_in_bytes();
817 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
818 // Remove wordSize for return addr which is already pushed.
819 framesize -= wordSize;
820
821 if (C->need_stack_bang(bangsize)) {
822 framesize -= wordSize;
823 st->print("# stack bang (%d bytes)", bangsize);
824 st->print("\n\t");
825 st->print("pushq rbp\t# Save rbp");
826 if (PreserveFramePointer) {
827 st->print("\n\t");
828 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
829 }
830 if (framesize) {
831 st->print("\n\t");
832 st->print("subq rsp, #%d\t# Create frame",framesize);
833 }
834 } else {
835 st->print("subq rsp, #%d\t# Create frame",framesize);
836 st->print("\n\t");
837 framesize -= wordSize;
838 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
839 if (PreserveFramePointer) {
840 st->print("\n\t");
841 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
842 if (framesize > 0) {
843 st->print("\n\t");
844 st->print("addq rbp, #%d", framesize);
845 }
846 }
847 }
848
849 if (VerifyStackAtCalls) {
850 st->print("\n\t");
851 framesize -= wordSize;
852 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
853 #ifdef ASSERT
854 st->print("\n\t");
855 st->print("# stack alignment check");
856 #endif
857 }
858 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
859 st->print("\n\t");
860 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
861 st->print("\n\t");
862 st->print("je fast_entry\t");
863 st->print("\n\t");
864 st->print("call #nmethod_entry_barrier_stub\t");
865 st->print("\n\tfast_entry:");
866 }
867 st->cr();
868 }
869 #endif
870
871 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
872 Compile* C = ra_->C;
873 MacroAssembler _masm(&cbuf);
874
875 int framesize = C->frame_size_in_bytes();
876 int bangsize = C->bang_size_in_bytes();
877
878 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
879
880 C->set_frame_complete(cbuf.insts_size());
881
882 if (C->has_mach_constant_base_node()) {
883 // NOTE: We set the table base offset here because users might be
884 // emitted before MachConstantBaseNode.
885 Compile::ConstantTable& constant_table = C->constant_table();
886 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
887 }
888 }
889
890 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
891 {
892 return MachNode::size(ra_); // too many variables; just compute it
893 // the hard way
894 }
895
896 int MachPrologNode::reloc() const
897 {
898 return 0; // a large enough number
899 }
900
901 //=============================================================================
902 #ifndef PRODUCT
903 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
904 {
905 Compile* C = ra_->C;
906 if (generate_vzeroupper(C)) {
907 st->print("vzeroupper");
908 st->cr(); st->print("\t");
909 }
910
911 int framesize = C->frame_size_in_bytes();
912 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
913 // Remove word for return adr already pushed
914 // and RBP
915 framesize -= 2*wordSize;
916
917 if (framesize) {
918 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
919 st->print("\t");
920 }
921
922 st->print_cr("popq rbp");
923 if (do_polling() && C->is_method_compilation()) {
924 st->print("\t");
925 if (SafepointMechanism::uses_thread_local_poll()) {
926 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
927 "testl rax, [rscratch1]\t"
928 "# Safepoint: poll for GC");
929 } else if (Assembler::is_polling_page_far()) {
930 st->print_cr("movq rscratch1, #polling_page_address\n\t"
931 "testl rax, [rscratch1]\t"
932 "# Safepoint: poll for GC");
933 } else {
934 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
935 "# Safepoint: poll for GC");
936 }
937 }
938 }
939 #endif
940
941 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
942 {
943 Compile* C = ra_->C;
944 MacroAssembler _masm(&cbuf);
945
946 if (generate_vzeroupper(C)) {
947 // Clear upper bits of YMM registers when current compiled code uses
948 // wide vectors to avoid AVX <-> SSE transition penalty during call.
949 __ vzeroupper();
950 }
951
952 int framesize = C->frame_size_in_bytes();
953 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
954 // Remove word for return adr already pushed
955 // and RBP
956 framesize -= 2*wordSize;
957
958 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
959
960 if (framesize) {
961 emit_opcode(cbuf, Assembler::REX_W);
962 if (framesize < 0x80) {
963 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
964 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
965 emit_d8(cbuf, framesize);
966 } else {
967 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
968 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
969 emit_d32(cbuf, framesize);
970 }
971 }
972
973 // popq rbp
974 emit_opcode(cbuf, 0x58 | RBP_enc);
975
976 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
977 __ reserved_stack_check();
978 }
979
980 if (do_polling() && C->is_method_compilation()) {
981 MacroAssembler _masm(&cbuf);
982 if (SafepointMechanism::uses_thread_local_poll()) {
983 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
984 __ relocate(relocInfo::poll_return_type);
985 __ testl(rax, Address(rscratch1, 0));
986 } else {
987 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
988 if (Assembler::is_polling_page_far()) {
989 __ lea(rscratch1, polling_page);
990 __ relocate(relocInfo::poll_return_type);
991 __ testl(rax, Address(rscratch1, 0));
992 } else {
993 __ testl(rax, polling_page);
994 }
995 }
996 }
997 }
998
999 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1000 {
1001 return MachNode::size(ra_); // too many variables; just compute it
1002 // the hard way
1003 }
1004
1005 int MachEpilogNode::reloc() const
1006 {
1007 return 2; // a large enough number
1008 }
1009
1010 const Pipeline* MachEpilogNode::pipeline() const
1011 {
1012 return MachNode::pipeline_class();
1013 }
1014
1015 int MachEpilogNode::safepoint_offset() const
1016 {
1017 return 0;
1018 }
1019
1020 //=============================================================================
1021
1022 enum RC {
1023 rc_bad,
1024 rc_int,
1025 rc_float,
1026 rc_stack
1027 };
1028
1029 static enum RC rc_class(OptoReg::Name reg)
1030 {
1031 if( !OptoReg::is_valid(reg) ) return rc_bad;
1032
1033 if (OptoReg::is_stack(reg)) return rc_stack;
1034
1035 VMReg r = OptoReg::as_VMReg(reg);
1036
1037 if (r->is_Register()) return rc_int;
1038
1039 assert(r->is_XMMRegister(), "must be");
1040 return rc_float;
1041 }
1042
1043 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1044 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1045 int src_hi, int dst_hi, uint ireg, outputStream* st);
1046
1047 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1048 int stack_offset, int reg, uint ireg, outputStream* st);
1049
1050 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1051 int dst_offset, uint ireg, outputStream* st) {
1052 if (cbuf) {
1053 MacroAssembler _masm(cbuf);
1054 switch (ireg) {
1055 case Op_VecS:
1056 __ movq(Address(rsp, -8), rax);
1057 __ movl(rax, Address(rsp, src_offset));
1058 __ movl(Address(rsp, dst_offset), rax);
1059 __ movq(rax, Address(rsp, -8));
1060 break;
1061 case Op_VecD:
1062 __ pushq(Address(rsp, src_offset));
1063 __ popq (Address(rsp, dst_offset));
1064 break;
1065 case Op_VecX:
1066 __ pushq(Address(rsp, src_offset));
1067 __ popq (Address(rsp, dst_offset));
1068 __ pushq(Address(rsp, src_offset+8));
1069 __ popq (Address(rsp, dst_offset+8));
1070 break;
1071 case Op_VecY:
1072 __ vmovdqu(Address(rsp, -32), xmm0);
1073 __ vmovdqu(xmm0, Address(rsp, src_offset));
1074 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1075 __ vmovdqu(xmm0, Address(rsp, -32));
1076 break;
1077 case Op_VecZ:
1078 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1079 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1080 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1081 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1082 break;
1083 default:
1084 ShouldNotReachHere();
1085 }
1086 #ifndef PRODUCT
1087 } else {
1088 switch (ireg) {
1089 case Op_VecS:
1090 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1091 "movl rax, [rsp + #%d]\n\t"
1092 "movl [rsp + #%d], rax\n\t"
1093 "movq rax, [rsp - #8]",
1094 src_offset, dst_offset);
1095 break;
1096 case Op_VecD:
1097 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1098 "popq [rsp + #%d]",
1099 src_offset, dst_offset);
1100 break;
1101 case Op_VecX:
1102 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1103 "popq [rsp + #%d]\n\t"
1104 "pushq [rsp + #%d]\n\t"
1105 "popq [rsp + #%d]",
1106 src_offset, dst_offset, src_offset+8, dst_offset+8);
1107 break;
1108 case Op_VecY:
1109 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1110 "vmovdqu xmm0, [rsp + #%d]\n\t"
1111 "vmovdqu [rsp + #%d], xmm0\n\t"
1112 "vmovdqu xmm0, [rsp - #32]",
1113 src_offset, dst_offset);
1114 break;
1115 case Op_VecZ:
1116 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1117 "vmovdqu xmm0, [rsp + #%d]\n\t"
1118 "vmovdqu [rsp + #%d], xmm0\n\t"
1119 "vmovdqu xmm0, [rsp - #64]",
1120 src_offset, dst_offset);
1121 break;
1122 default:
1123 ShouldNotReachHere();
1124 }
1125 #endif
1126 }
1127 }
1128
1129 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1130 PhaseRegAlloc* ra_,
1131 bool do_size,
1132 outputStream* st) const {
1133 assert(cbuf != NULL || st != NULL, "sanity");
1134 // Get registers to move
1135 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1136 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1137 OptoReg::Name dst_second = ra_->get_reg_second(this);
1138 OptoReg::Name dst_first = ra_->get_reg_first(this);
1139
1140 enum RC src_second_rc = rc_class(src_second);
1141 enum RC src_first_rc = rc_class(src_first);
1142 enum RC dst_second_rc = rc_class(dst_second);
1143 enum RC dst_first_rc = rc_class(dst_first);
1144
1145 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1146 "must move at least 1 register" );
1147
1148 if (src_first == dst_first && src_second == dst_second) {
1149 // Self copy, no move
1150 return 0;
1151 }
1152 if (bottom_type()->isa_vect() != NULL) {
1153 uint ireg = ideal_reg();
1154 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1155 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1156 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1157 // mem -> mem
1158 int src_offset = ra_->reg2offset(src_first);
1159 int dst_offset = ra_->reg2offset(dst_first);
1160 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1161 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1162 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1163 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1164 int stack_offset = ra_->reg2offset(dst_first);
1165 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1166 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1167 int stack_offset = ra_->reg2offset(src_first);
1168 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1169 } else {
1170 ShouldNotReachHere();
1171 }
1172 return 0;
1173 }
1174 if (src_first_rc == rc_stack) {
1175 // mem ->
1176 if (dst_first_rc == rc_stack) {
1177 // mem -> mem
1178 assert(src_second != dst_first, "overlap");
1179 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1180 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1181 // 64-bit
1182 int src_offset = ra_->reg2offset(src_first);
1183 int dst_offset = ra_->reg2offset(dst_first);
1184 if (cbuf) {
1185 MacroAssembler _masm(cbuf);
1186 __ pushq(Address(rsp, src_offset));
1187 __ popq (Address(rsp, dst_offset));
1188 #ifndef PRODUCT
1189 } else {
1190 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1191 "popq [rsp + #%d]",
1192 src_offset, dst_offset);
1193 #endif
1194 }
1195 } else {
1196 // 32-bit
1197 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1198 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1199 // No pushl/popl, so:
1200 int src_offset = ra_->reg2offset(src_first);
1201 int dst_offset = ra_->reg2offset(dst_first);
1202 if (cbuf) {
1203 MacroAssembler _masm(cbuf);
1204 __ movq(Address(rsp, -8), rax);
1205 __ movl(rax, Address(rsp, src_offset));
1206 __ movl(Address(rsp, dst_offset), rax);
1207 __ movq(rax, Address(rsp, -8));
1208 #ifndef PRODUCT
1209 } else {
1210 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1211 "movl rax, [rsp + #%d]\n\t"
1212 "movl [rsp + #%d], rax\n\t"
1213 "movq rax, [rsp - #8]",
1214 src_offset, dst_offset);
1215 #endif
1216 }
1217 }
1218 return 0;
1219 } else if (dst_first_rc == rc_int) {
1220 // mem -> gpr
1221 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1223 // 64-bit
1224 int offset = ra_->reg2offset(src_first);
1225 if (cbuf) {
1226 MacroAssembler _masm(cbuf);
1227 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1228 #ifndef PRODUCT
1229 } else {
1230 st->print("movq %s, [rsp + #%d]\t# spill",
1231 Matcher::regName[dst_first],
1232 offset);
1233 #endif
1234 }
1235 } else {
1236 // 32-bit
1237 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1238 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1239 int offset = ra_->reg2offset(src_first);
1240 if (cbuf) {
1241 MacroAssembler _masm(cbuf);
1242 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1243 #ifndef PRODUCT
1244 } else {
1245 st->print("movl %s, [rsp + #%d]\t# spill",
1246 Matcher::regName[dst_first],
1247 offset);
1248 #endif
1249 }
1250 }
1251 return 0;
1252 } else if (dst_first_rc == rc_float) {
1253 // mem-> xmm
1254 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1255 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1256 // 64-bit
1257 int offset = ra_->reg2offset(src_first);
1258 if (cbuf) {
1259 MacroAssembler _masm(cbuf);
1260 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1261 #ifndef PRODUCT
1262 } else {
1263 st->print("%s %s, [rsp + #%d]\t# spill",
1264 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1265 Matcher::regName[dst_first],
1266 offset);
1267 #endif
1268 }
1269 } else {
1270 // 32-bit
1271 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1272 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1273 int offset = ra_->reg2offset(src_first);
1274 if (cbuf) {
1275 MacroAssembler _masm(cbuf);
1276 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1277 #ifndef PRODUCT
1278 } else {
1279 st->print("movss %s, [rsp + #%d]\t# spill",
1280 Matcher::regName[dst_first],
1281 offset);
1282 #endif
1283 }
1284 }
1285 return 0;
1286 }
1287 } else if (src_first_rc == rc_int) {
1288 // gpr ->
1289 if (dst_first_rc == rc_stack) {
1290 // gpr -> mem
1291 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1292 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1293 // 64-bit
1294 int offset = ra_->reg2offset(dst_first);
1295 if (cbuf) {
1296 MacroAssembler _masm(cbuf);
1297 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1298 #ifndef PRODUCT
1299 } else {
1300 st->print("movq [rsp + #%d], %s\t# spill",
1301 offset,
1302 Matcher::regName[src_first]);
1303 #endif
1304 }
1305 } else {
1306 // 32-bit
1307 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1308 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1309 int offset = ra_->reg2offset(dst_first);
1310 if (cbuf) {
1311 MacroAssembler _masm(cbuf);
1312 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1313 #ifndef PRODUCT
1314 } else {
1315 st->print("movl [rsp + #%d], %s\t# spill",
1316 offset,
1317 Matcher::regName[src_first]);
1318 #endif
1319 }
1320 }
1321 return 0;
1322 } else if (dst_first_rc == rc_int) {
1323 // gpr -> gpr
1324 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1325 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1326 // 64-bit
1327 if (cbuf) {
1328 MacroAssembler _masm(cbuf);
1329 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1330 as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movq %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 return 0;
1339 } else {
1340 // 32-bit
1341 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1342 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1343 if (cbuf) {
1344 MacroAssembler _masm(cbuf);
1345 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1346 as_Register(Matcher::_regEncode[src_first]));
1347 #ifndef PRODUCT
1348 } else {
1349 st->print("movl %s, %s\t# spill",
1350 Matcher::regName[dst_first],
1351 Matcher::regName[src_first]);
1352 #endif
1353 }
1354 return 0;
1355 }
1356 } else if (dst_first_rc == rc_float) {
1357 // gpr -> xmm
1358 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1359 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1360 // 64-bit
1361 if (cbuf) {
1362 MacroAssembler _masm(cbuf);
1363 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1364 #ifndef PRODUCT
1365 } else {
1366 st->print("movdq %s, %s\t# spill",
1367 Matcher::regName[dst_first],
1368 Matcher::regName[src_first]);
1369 #endif
1370 }
1371 } else {
1372 // 32-bit
1373 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1374 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1375 if (cbuf) {
1376 MacroAssembler _masm(cbuf);
1377 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1378 #ifndef PRODUCT
1379 } else {
1380 st->print("movdl %s, %s\t# spill",
1381 Matcher::regName[dst_first],
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 }
1386 return 0;
1387 }
1388 } else if (src_first_rc == rc_float) {
1389 // xmm ->
1390 if (dst_first_rc == rc_stack) {
1391 // xmm -> mem
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 int offset = ra_->reg2offset(dst_first);
1396 if (cbuf) {
1397 MacroAssembler _masm(cbuf);
1398 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1399 #ifndef PRODUCT
1400 } else {
1401 st->print("movsd [rsp + #%d], %s\t# spill",
1402 offset,
1403 Matcher::regName[src_first]);
1404 #endif
1405 }
1406 } else {
1407 // 32-bit
1408 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1409 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1410 int offset = ra_->reg2offset(dst_first);
1411 if (cbuf) {
1412 MacroAssembler _masm(cbuf);
1413 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1414 #ifndef PRODUCT
1415 } else {
1416 st->print("movss [rsp + #%d], %s\t# spill",
1417 offset,
1418 Matcher::regName[src_first]);
1419 #endif
1420 }
1421 }
1422 return 0;
1423 } else if (dst_first_rc == rc_int) {
1424 // xmm -> gpr
1425 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1426 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1427 // 64-bit
1428 if (cbuf) {
1429 MacroAssembler _masm(cbuf);
1430 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1431 #ifndef PRODUCT
1432 } else {
1433 st->print("movdq %s, %s\t# spill",
1434 Matcher::regName[dst_first],
1435 Matcher::regName[src_first]);
1436 #endif
1437 }
1438 } else {
1439 // 32-bit
1440 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1441 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1442 if (cbuf) {
1443 MacroAssembler _masm(cbuf);
1444 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1445 #ifndef PRODUCT
1446 } else {
1447 st->print("movdl %s, %s\t# spill",
1448 Matcher::regName[dst_first],
1449 Matcher::regName[src_first]);
1450 #endif
1451 }
1452 }
1453 return 0;
1454 } else if (dst_first_rc == rc_float) {
1455 // xmm -> xmm
1456 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1457 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1458 // 64-bit
1459 if (cbuf) {
1460 MacroAssembler _masm(cbuf);
1461 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1462 #ifndef PRODUCT
1463 } else {
1464 st->print("%s %s, %s\t# spill",
1465 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1466 Matcher::regName[dst_first],
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 } else {
1471 // 32-bit
1472 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1473 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1474 if (cbuf) {
1475 MacroAssembler _masm(cbuf);
1476 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1477 #ifndef PRODUCT
1478 } else {
1479 st->print("%s %s, %s\t# spill",
1480 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 }
1486 return 0;
1487 }
1488 }
1489
1490 assert(0," foo ");
1491 Unimplemented();
1492 return 0;
1493 }
1494
1495 #ifndef PRODUCT
1496 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1497 implementation(NULL, ra_, false, st);
1498 }
1499 #endif
1500
1501 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1502 implementation(&cbuf, ra_, false, NULL);
1503 }
1504
1505 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1506 return MachNode::size(ra_);
1507 }
1508
1509 //=============================================================================
1510 #ifndef PRODUCT
1511 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1512 {
1513 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1514 int reg = ra_->get_reg_first(this);
1515 st->print("leaq %s, [rsp + #%d]\t# box lock",
1516 Matcher::regName[reg], offset);
1517 }
1518 #endif
1519
1520 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1521 {
1522 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1523 int reg = ra_->get_encode(this);
1524 if (offset >= 0x80) {
1525 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1526 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1527 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1528 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1529 emit_d32(cbuf, offset);
1530 } else {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d8(cbuf, offset);
1536 }
1537 }
1538
1539 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1540 {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 return (offset < 0x80) ? 5 : 8; // REX
1543 }
1544
1545 //=============================================================================
1546 #ifndef PRODUCT
1547 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1548 {
1549 if (UseCompressedClassPointers) {
1550 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1551 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1552 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1553 } else {
1554 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1555 "# Inline cache check");
1556 }
1557 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1558 st->print_cr("\tnop\t# nops to align entry point");
1559 }
1560 #endif
1561
1562 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1563 {
1564 MacroAssembler masm(&cbuf);
1565 uint insts_size = cbuf.insts_size();
1566 if (UseCompressedClassPointers) {
1567 masm.load_klass(rscratch1, j_rarg0);
1568 masm.cmpptr(rax, rscratch1);
1569 } else {
1570 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1571 }
1572
1573 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1574
1575 /* WARNING these NOPs are critical so that verified entry point is properly
1576 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1577 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1578 if (OptoBreakpoint) {
1579 // Leave space for int3
1580 nops_cnt -= 1;
1581 }
1582 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1583 if (nops_cnt > 0)
1584 masm.nop(nops_cnt);
1585 }
1586
1587 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1588 {
1589 return MachNode::size(ra_); // too many variables; just compute it
1590 // the hard way
1591 }
1592
1593
1594 //=============================================================================
1595
1596 int Matcher::regnum_to_fpu_offset(int regnum)
1597 {
1598 return regnum - 32; // The FP registers are in the second chunk
1599 }
1600
1601 // This is UltraSparc specific, true just means we have fast l2f conversion
1602 const bool Matcher::convL2FSupported(void) {
1603 return true;
1604 }
1605
1606 // Is this branch offset short enough that a short branch can be used?
1607 //
1608 // NOTE: If the platform does not provide any short branch variants, then
1609 // this method should return false for offset 0.
1610 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1611 // The passed offset is relative to address of the branch.
1612 // On 86 a branch displacement is calculated relative to address
1613 // of a next instruction.
1614 offset -= br_size;
1615
1616 // the short version of jmpConUCF2 contains multiple branches,
1617 // making the reach slightly less
1618 if (rule == jmpConUCF2_rule)
1619 return (-126 <= offset && offset <= 125);
1620 return (-128 <= offset && offset <= 127);
1621 }
1622
1623 const bool Matcher::isSimpleConstant64(jlong value) {
1624 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1625 //return value == (int) value; // Cf. storeImmL and immL32.
1626
1627 // Probably always true, even if a temp register is required.
1628 return true;
1629 }
1630
1631 // The ecx parameter to rep stosq for the ClearArray node is in words.
1632 const bool Matcher::init_array_count_is_in_bytes = false;
1633
1634 // No additional cost for CMOVL.
1635 const int Matcher::long_cmove_cost() { return 0; }
1636
1637 // No CMOVF/CMOVD with SSE2
1638 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1639
1640 // Does the CPU require late expand (see block.cpp for description of late expand)?
1641 const bool Matcher::require_postalloc_expand = false;
1642
1643 // Do we need to mask the count passed to shift instructions or does
1644 // the cpu only look at the lower 5/6 bits anyway?
1645 const bool Matcher::need_masked_shift_count = false;
1646
1647 bool Matcher::narrow_oop_use_complex_address() {
1648 assert(UseCompressedOops, "only for compressed oops code");
1649 return (LogMinObjAlignmentInBytes <= 3);
1650 }
1651
1652 bool Matcher::narrow_klass_use_complex_address() {
1653 assert(UseCompressedClassPointers, "only for compressed klass code");
1654 return (LogKlassAlignmentInBytes <= 3);
1655 }
1656
1657 bool Matcher::const_oop_prefer_decode() {
1658 // Prefer ConN+DecodeN over ConP.
1659 return true;
1660 }
1661
1662 bool Matcher::const_klass_prefer_decode() {
1663 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1664 // or condisider the following:
1665 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1666 //return Universe::narrow_klass_base() == NULL;
1667 return true;
1668 }
1669
1670 // Is it better to copy float constants, or load them directly from
1671 // memory? Intel can load a float constant from a direct address,
1672 // requiring no extra registers. Most RISCs will have to materialize
1673 // an address into a register first, so they would do better to copy
1674 // the constant from stack.
1675 const bool Matcher::rematerialize_float_constants = true; // XXX
1676
1677 // If CPU can load and store mis-aligned doubles directly then no
1678 // fixup is needed. Else we split the double into 2 integer pieces
1679 // and move it piece-by-piece. Only happens when passing doubles into
1680 // C code as the Java calling convention forces doubles to be aligned.
1681 const bool Matcher::misaligned_doubles_ok = true;
1682
1683 // No-op on amd64
1684 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1685
1686 // Advertise here if the CPU requires explicit rounding operations to
1687 // implement the UseStrictFP mode.
1688 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1689
1690 // Are floats conerted to double when stored to stack during deoptimization?
1691 // On x64 it is stored without convertion so we can use normal access.
1692 bool Matcher::float_in_double() { return false; }
1693
1694 // Do ints take an entire long register or just half?
1695 const bool Matcher::int_in_long = true;
1696
1697 // Return whether or not this register is ever used as an argument.
1698 // This function is used on startup to build the trampoline stubs in
1699 // generateOptoStub. Registers not mentioned will be killed by the VM
1700 // call in the trampoline, and arguments in those registers not be
1701 // available to the callee.
1702 bool Matcher::can_be_java_arg(int reg)
1703 {
1704 return
1705 reg == RDI_num || reg == RDI_H_num ||
1706 reg == RSI_num || reg == RSI_H_num ||
1707 reg == RDX_num || reg == RDX_H_num ||
1708 reg == RCX_num || reg == RCX_H_num ||
1709 reg == R8_num || reg == R8_H_num ||
1710 reg == R9_num || reg == R9_H_num ||
1711 reg == R12_num || reg == R12_H_num ||
1712 reg == XMM0_num || reg == XMM0b_num ||
1713 reg == XMM1_num || reg == XMM1b_num ||
1714 reg == XMM2_num || reg == XMM2b_num ||
1715 reg == XMM3_num || reg == XMM3b_num ||
1716 reg == XMM4_num || reg == XMM4b_num ||
1717 reg == XMM5_num || reg == XMM5b_num ||
1718 reg == XMM6_num || reg == XMM6b_num ||
1719 reg == XMM7_num || reg == XMM7b_num;
1720 }
1721
1722 bool Matcher::is_spillable_arg(int reg)
1723 {
1724 return can_be_java_arg(reg);
1725 }
1726
1727 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1728 // In 64 bit mode a code which use multiply when
1729 // devisor is constant is faster than hardware
1730 // DIV instruction (it uses MulHiL).
1731 return false;
1732 }
1733
1734 // Register for DIVI projection of divmodI
1735 RegMask Matcher::divI_proj_mask() {
1736 return INT_RAX_REG_mask();
1737 }
1738
1739 // Register for MODI projection of divmodI
1740 RegMask Matcher::modI_proj_mask() {
1741 return INT_RDX_REG_mask();
1742 }
1743
1744 // Register for DIVL projection of divmodL
1745 RegMask Matcher::divL_proj_mask() {
1746 return LONG_RAX_REG_mask();
1747 }
1748
1749 // Register for MODL projection of divmodL
1750 RegMask Matcher::modL_proj_mask() {
1751 return LONG_RDX_REG_mask();
1752 }
1753
1754 // Register for saving SP into on method handle invokes. Not used on x86_64.
1755 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1756 return NO_REG_mask();
1757 }
1758
1759 %}
1760
1761 //----------ENCODING BLOCK-----------------------------------------------------
1762 // This block specifies the encoding classes used by the compiler to
1763 // output byte streams. Encoding classes are parameterized macros
1764 // used by Machine Instruction Nodes in order to generate the bit
1765 // encoding of the instruction. Operands specify their base encoding
1766 // interface with the interface keyword. There are currently
1767 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1768 // COND_INTER. REG_INTER causes an operand to generate a function
1769 // which returns its register number when queried. CONST_INTER causes
1770 // an operand to generate a function which returns the value of the
1771 // constant when queried. MEMORY_INTER causes an operand to generate
1772 // four functions which return the Base Register, the Index Register,
1773 // the Scale Value, and the Offset Value of the operand when queried.
1774 // COND_INTER causes an operand to generate six functions which return
1775 // the encoding code (ie - encoding bits for the instruction)
1776 // associated with each basic boolean condition for a conditional
1777 // instruction.
1778 //
1779 // Instructions specify two basic values for encoding. Again, a
1780 // function is available to check if the constant displacement is an
1781 // oop. They use the ins_encode keyword to specify their encoding
1782 // classes (which must be a sequence of enc_class names, and their
1783 // parameters, specified in the encoding block), and they use the
1784 // opcode keyword to specify, in order, their primary, secondary, and
1785 // tertiary opcode. Only the opcode sections which a particular
1786 // instruction needs for encoding need to be specified.
1787 encode %{
1788 // Build emit functions for each basic byte or larger field in the
1789 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1790 // from C++ code in the enc_class source block. Emit functions will
1791 // live in the main source block for now. In future, we can
1792 // generalize this by adding a syntax that specifies the sizes of
1793 // fields in an order, so that the adlc can build the emit functions
1794 // automagically
1795
1796 // Emit primary opcode
1797 enc_class OpcP
1798 %{
1799 emit_opcode(cbuf, $primary);
1800 %}
1801
1802 // Emit secondary opcode
1803 enc_class OpcS
1804 %{
1805 emit_opcode(cbuf, $secondary);
1806 %}
1807
1808 // Emit tertiary opcode
1809 enc_class OpcT
1810 %{
1811 emit_opcode(cbuf, $tertiary);
1812 %}
1813
1814 // Emit opcode directly
1815 enc_class Opcode(immI d8)
1816 %{
1817 emit_opcode(cbuf, $d8$$constant);
1818 %}
1819
1820 // Emit size prefix
1821 enc_class SizePrefix
1822 %{
1823 emit_opcode(cbuf, 0x66);
1824 %}
1825
1826 enc_class reg(rRegI reg)
1827 %{
1828 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1829 %}
1830
1831 enc_class reg_reg(rRegI dst, rRegI src)
1832 %{
1833 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1834 %}
1835
1836 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1837 %{
1838 emit_opcode(cbuf, $opcode$$constant);
1839 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1840 %}
1841
1842 enc_class cdql_enc(no_rax_rdx_RegI div)
1843 %{
1844 // Full implementation of Java idiv and irem; checks for
1845 // special case as described in JVM spec., p.243 & p.271.
1846 //
1847 // normal case special case
1848 //
1849 // input : rax: dividend min_int
1850 // reg: divisor -1
1851 //
1852 // output: rax: quotient (= rax idiv reg) min_int
1853 // rdx: remainder (= rax irem reg) 0
1854 //
1855 // Code sequnce:
1856 //
1857 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1858 // 5: 75 07/08 jne e <normal>
1859 // 7: 33 d2 xor %edx,%edx
1860 // [div >= 8 -> offset + 1]
1861 // [REX_B]
1862 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1863 // c: 74 03/04 je 11 <done>
1864 // 000000000000000e <normal>:
1865 // e: 99 cltd
1866 // [div >= 8 -> offset + 1]
1867 // [REX_B]
1868 // f: f7 f9 idiv $div
1869 // 0000000000000011 <done>:
1870
1871 // cmp $0x80000000,%eax
1872 emit_opcode(cbuf, 0x3d);
1873 emit_d8(cbuf, 0x00);
1874 emit_d8(cbuf, 0x00);
1875 emit_d8(cbuf, 0x00);
1876 emit_d8(cbuf, 0x80);
1877
1878 // jne e <normal>
1879 emit_opcode(cbuf, 0x75);
1880 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1881
1882 // xor %edx,%edx
1883 emit_opcode(cbuf, 0x33);
1884 emit_d8(cbuf, 0xD2);
1885
1886 // cmp $0xffffffffffffffff,%ecx
1887 if ($div$$reg >= 8) {
1888 emit_opcode(cbuf, Assembler::REX_B);
1889 }
1890 emit_opcode(cbuf, 0x83);
1891 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1892 emit_d8(cbuf, 0xFF);
1893
1894 // je 11 <done>
1895 emit_opcode(cbuf, 0x74);
1896 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1897
1898 // <normal>
1899 // cltd
1900 emit_opcode(cbuf, 0x99);
1901
1902 // idivl (note: must be emitted by the user of this rule)
1903 // <done>
1904 %}
1905
1906 enc_class cdqq_enc(no_rax_rdx_RegL div)
1907 %{
1908 // Full implementation of Java ldiv and lrem; checks for
1909 // special case as described in JVM spec., p.243 & p.271.
1910 //
1911 // normal case special case
1912 //
1913 // input : rax: dividend min_long
1914 // reg: divisor -1
1915 //
1916 // output: rax: quotient (= rax idiv reg) min_long
1917 // rdx: remainder (= rax irem reg) 0
1918 //
1919 // Code sequnce:
1920 //
1921 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1922 // 7: 00 00 80
1923 // a: 48 39 d0 cmp %rdx,%rax
1924 // d: 75 08 jne 17 <normal>
1925 // f: 33 d2 xor %edx,%edx
1926 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1927 // 15: 74 05 je 1c <done>
1928 // 0000000000000017 <normal>:
1929 // 17: 48 99 cqto
1930 // 19: 48 f7 f9 idiv $div
1931 // 000000000000001c <done>:
1932
1933 // mov $0x8000000000000000,%rdx
1934 emit_opcode(cbuf, Assembler::REX_W);
1935 emit_opcode(cbuf, 0xBA);
1936 emit_d8(cbuf, 0x00);
1937 emit_d8(cbuf, 0x00);
1938 emit_d8(cbuf, 0x00);
1939 emit_d8(cbuf, 0x00);
1940 emit_d8(cbuf, 0x00);
1941 emit_d8(cbuf, 0x00);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x80);
1944
1945 // cmp %rdx,%rax
1946 emit_opcode(cbuf, Assembler::REX_W);
1947 emit_opcode(cbuf, 0x39);
1948 emit_d8(cbuf, 0xD0);
1949
1950 // jne 17 <normal>
1951 emit_opcode(cbuf, 0x75);
1952 emit_d8(cbuf, 0x08);
1953
1954 // xor %edx,%edx
1955 emit_opcode(cbuf, 0x33);
1956 emit_d8(cbuf, 0xD2);
1957
1958 // cmp $0xffffffffffffffff,$div
1959 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1960 emit_opcode(cbuf, 0x83);
1961 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1962 emit_d8(cbuf, 0xFF);
1963
1964 // je 1e <done>
1965 emit_opcode(cbuf, 0x74);
1966 emit_d8(cbuf, 0x05);
1967
1968 // <normal>
1969 // cqto
1970 emit_opcode(cbuf, Assembler::REX_W);
1971 emit_opcode(cbuf, 0x99);
1972
1973 // idivq (note: must be emitted by the user of this rule)
1974 // <done>
1975 %}
1976
1977 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1978 enc_class OpcSE(immI imm)
1979 %{
1980 // Emit primary opcode and set sign-extend bit
1981 // Check for 8-bit immediate, and set sign extend bit in opcode
1982 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1983 emit_opcode(cbuf, $primary | 0x02);
1984 } else {
1985 // 32-bit immediate
1986 emit_opcode(cbuf, $primary);
1987 }
1988 %}
1989
1990 enc_class OpcSErm(rRegI dst, immI imm)
1991 %{
1992 // OpcSEr/m
1993 int dstenc = $dst$$reg;
1994 if (dstenc >= 8) {
1995 emit_opcode(cbuf, Assembler::REX_B);
1996 dstenc -= 8;
1997 }
1998 // Emit primary opcode and set sign-extend bit
1999 // Check for 8-bit immediate, and set sign extend bit in opcode
2000 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2001 emit_opcode(cbuf, $primary | 0x02);
2002 } else {
2003 // 32-bit immediate
2004 emit_opcode(cbuf, $primary);
2005 }
2006 // Emit r/m byte with secondary opcode, after primary opcode.
2007 emit_rm(cbuf, 0x3, $secondary, dstenc);
2008 %}
2009
2010 enc_class OpcSErm_wide(rRegL dst, immI imm)
2011 %{
2012 // OpcSEr/m
2013 int dstenc = $dst$$reg;
2014 if (dstenc < 8) {
2015 emit_opcode(cbuf, Assembler::REX_W);
2016 } else {
2017 emit_opcode(cbuf, Assembler::REX_WB);
2018 dstenc -= 8;
2019 }
2020 // Emit primary opcode and set sign-extend bit
2021 // Check for 8-bit immediate, and set sign extend bit in opcode
2022 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2023 emit_opcode(cbuf, $primary | 0x02);
2024 } else {
2025 // 32-bit immediate
2026 emit_opcode(cbuf, $primary);
2027 }
2028 // Emit r/m byte with secondary opcode, after primary opcode.
2029 emit_rm(cbuf, 0x3, $secondary, dstenc);
2030 %}
2031
2032 enc_class Con8or32(immI imm)
2033 %{
2034 // Check for 8-bit immediate, and set sign extend bit in opcode
2035 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2036 $$$emit8$imm$$constant;
2037 } else {
2038 // 32-bit immediate
2039 $$$emit32$imm$$constant;
2040 }
2041 %}
2042
2043 enc_class opc2_reg(rRegI dst)
2044 %{
2045 // BSWAP
2046 emit_cc(cbuf, $secondary, $dst$$reg);
2047 %}
2048
2049 enc_class opc3_reg(rRegI dst)
2050 %{
2051 // BSWAP
2052 emit_cc(cbuf, $tertiary, $dst$$reg);
2053 %}
2054
2055 enc_class reg_opc(rRegI div)
2056 %{
2057 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2058 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2059 %}
2060
2061 enc_class enc_cmov(cmpOp cop)
2062 %{
2063 // CMOV
2064 $$$emit8$primary;
2065 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2066 %}
2067
2068 enc_class enc_PartialSubtypeCheck()
2069 %{
2070 Register Rrdi = as_Register(RDI_enc); // result register
2071 Register Rrax = as_Register(RAX_enc); // super class
2072 Register Rrcx = as_Register(RCX_enc); // killed
2073 Register Rrsi = as_Register(RSI_enc); // sub class
2074 Label miss;
2075 const bool set_cond_codes = true;
2076
2077 MacroAssembler _masm(&cbuf);
2078 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2079 NULL, &miss,
2080 /*set_cond_codes:*/ true);
2081 if ($primary) {
2082 __ xorptr(Rrdi, Rrdi);
2083 }
2084 __ bind(miss);
2085 %}
2086
2087 enc_class clear_avx %{
2088 debug_only(int off0 = cbuf.insts_size());
2089 if (generate_vzeroupper(Compile::current())) {
2090 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2091 // Clear upper bits of YMM registers when current compiled code uses
2092 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2093 MacroAssembler _masm(&cbuf);
2094 __ vzeroupper();
2095 }
2096 debug_only(int off1 = cbuf.insts_size());
2097 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2098 %}
2099
2100 enc_class Java_To_Runtime(method meth) %{
2101 // No relocation needed
2102 MacroAssembler _masm(&cbuf);
2103 __ mov64(r10, (int64_t) $meth$$method);
2104 __ call(r10);
2105 %}
2106
2107 enc_class Java_To_Interpreter(method meth)
2108 %{
2109 // CALL Java_To_Interpreter
2110 // This is the instruction starting address for relocation info.
2111 cbuf.set_insts_mark();
2112 $$$emit8$primary;
2113 // CALL directly to the runtime
2114 emit_d32_reloc(cbuf,
2115 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2116 runtime_call_Relocation::spec(),
2117 RELOC_DISP32);
2118 %}
2119
2120 enc_class Java_Static_Call(method meth)
2121 %{
2122 // JAVA STATIC CALL
2123 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2124 // determine who we intended to call.
2125 cbuf.set_insts_mark();
2126 $$$emit8$primary;
2127
2128 if (!_method) {
2129 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2130 runtime_call_Relocation::spec(),
2131 RELOC_DISP32);
2132 } else {
2133 int method_index = resolved_method_index(cbuf);
2134 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2135 : static_call_Relocation::spec(method_index);
2136 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2137 rspec, RELOC_DISP32);
2138 // Emit stubs for static call.
2139 address mark = cbuf.insts_mark();
2140 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2141 if (stub == NULL) {
2142 ciEnv::current()->record_failure("CodeCache is full");
2143 return;
2144 }
2145 #if INCLUDE_AOT
2146 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2147 #endif
2148 }
2149 %}
2150
2151 enc_class Java_Dynamic_Call(method meth) %{
2152 MacroAssembler _masm(&cbuf);
2153 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2154 %}
2155
2156 enc_class Java_Compiled_Call(method meth)
2157 %{
2158 // JAVA COMPILED CALL
2159 int disp = in_bytes(Method:: from_compiled_offset());
2160
2161 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2162 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2163
2164 // callq *disp(%rax)
2165 cbuf.set_insts_mark();
2166 $$$emit8$primary;
2167 if (disp < 0x80) {
2168 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2169 emit_d8(cbuf, disp); // Displacement
2170 } else {
2171 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2172 emit_d32(cbuf, disp); // Displacement
2173 }
2174 %}
2175
2176 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2177 %{
2178 // SAL, SAR, SHR
2179 int dstenc = $dst$$reg;
2180 if (dstenc >= 8) {
2181 emit_opcode(cbuf, Assembler::REX_B);
2182 dstenc -= 8;
2183 }
2184 $$$emit8$primary;
2185 emit_rm(cbuf, 0x3, $secondary, dstenc);
2186 $$$emit8$shift$$constant;
2187 %}
2188
2189 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2190 %{
2191 // SAL, SAR, SHR
2192 int dstenc = $dst$$reg;
2193 if (dstenc < 8) {
2194 emit_opcode(cbuf, Assembler::REX_W);
2195 } else {
2196 emit_opcode(cbuf, Assembler::REX_WB);
2197 dstenc -= 8;
2198 }
2199 $$$emit8$primary;
2200 emit_rm(cbuf, 0x3, $secondary, dstenc);
2201 $$$emit8$shift$$constant;
2202 %}
2203
2204 enc_class load_immI(rRegI dst, immI src)
2205 %{
2206 int dstenc = $dst$$reg;
2207 if (dstenc >= 8) {
2208 emit_opcode(cbuf, Assembler::REX_B);
2209 dstenc -= 8;
2210 }
2211 emit_opcode(cbuf, 0xB8 | dstenc);
2212 $$$emit32$src$$constant;
2213 %}
2214
2215 enc_class load_immL(rRegL dst, immL src)
2216 %{
2217 int dstenc = $dst$$reg;
2218 if (dstenc < 8) {
2219 emit_opcode(cbuf, Assembler::REX_W);
2220 } else {
2221 emit_opcode(cbuf, Assembler::REX_WB);
2222 dstenc -= 8;
2223 }
2224 emit_opcode(cbuf, 0xB8 | dstenc);
2225 emit_d64(cbuf, $src$$constant);
2226 %}
2227
2228 enc_class load_immUL32(rRegL dst, immUL32 src)
2229 %{
2230 // same as load_immI, but this time we care about zeroes in the high word
2231 int dstenc = $dst$$reg;
2232 if (dstenc >= 8) {
2233 emit_opcode(cbuf, Assembler::REX_B);
2234 dstenc -= 8;
2235 }
2236 emit_opcode(cbuf, 0xB8 | dstenc);
2237 $$$emit32$src$$constant;
2238 %}
2239
2240 enc_class load_immL32(rRegL dst, immL32 src)
2241 %{
2242 int dstenc = $dst$$reg;
2243 if (dstenc < 8) {
2244 emit_opcode(cbuf, Assembler::REX_W);
2245 } else {
2246 emit_opcode(cbuf, Assembler::REX_WB);
2247 dstenc -= 8;
2248 }
2249 emit_opcode(cbuf, 0xC7);
2250 emit_rm(cbuf, 0x03, 0x00, dstenc);
2251 $$$emit32$src$$constant;
2252 %}
2253
2254 enc_class load_immP31(rRegP dst, immP32 src)
2255 %{
2256 // same as load_immI, but this time we care about zeroes in the high word
2257 int dstenc = $dst$$reg;
2258 if (dstenc >= 8) {
2259 emit_opcode(cbuf, Assembler::REX_B);
2260 dstenc -= 8;
2261 }
2262 emit_opcode(cbuf, 0xB8 | dstenc);
2263 $$$emit32$src$$constant;
2264 %}
2265
2266 enc_class load_immP(rRegP dst, immP src)
2267 %{
2268 int dstenc = $dst$$reg;
2269 if (dstenc < 8) {
2270 emit_opcode(cbuf, Assembler::REX_W);
2271 } else {
2272 emit_opcode(cbuf, Assembler::REX_WB);
2273 dstenc -= 8;
2274 }
2275 emit_opcode(cbuf, 0xB8 | dstenc);
2276 // This next line should be generated from ADLC
2277 if ($src->constant_reloc() != relocInfo::none) {
2278 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2279 } else {
2280 emit_d64(cbuf, $src$$constant);
2281 }
2282 %}
2283
2284 enc_class Con32(immI src)
2285 %{
2286 // Output immediate
2287 $$$emit32$src$$constant;
2288 %}
2289
2290 enc_class Con32F_as_bits(immF src)
2291 %{
2292 // Output Float immediate bits
2293 jfloat jf = $src$$constant;
2294 jint jf_as_bits = jint_cast(jf);
2295 emit_d32(cbuf, jf_as_bits);
2296 %}
2297
2298 enc_class Con16(immI src)
2299 %{
2300 // Output immediate
2301 $$$emit16$src$$constant;
2302 %}
2303
2304 // How is this different from Con32??? XXX
2305 enc_class Con_d32(immI src)
2306 %{
2307 emit_d32(cbuf,$src$$constant);
2308 %}
2309
2310 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2311 // Output immediate memory reference
2312 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2313 emit_d32(cbuf, 0x00);
2314 %}
2315
2316 enc_class lock_prefix()
2317 %{
2318 emit_opcode(cbuf, 0xF0); // lock
2319 %}
2320
2321 enc_class REX_mem(memory mem)
2322 %{
2323 if ($mem$$base >= 8) {
2324 if ($mem$$index < 8) {
2325 emit_opcode(cbuf, Assembler::REX_B);
2326 } else {
2327 emit_opcode(cbuf, Assembler::REX_XB);
2328 }
2329 } else {
2330 if ($mem$$index >= 8) {
2331 emit_opcode(cbuf, Assembler::REX_X);
2332 }
2333 }
2334 %}
2335
2336 enc_class REX_mem_wide(memory mem)
2337 %{
2338 if ($mem$$base >= 8) {
2339 if ($mem$$index < 8) {
2340 emit_opcode(cbuf, Assembler::REX_WB);
2341 } else {
2342 emit_opcode(cbuf, Assembler::REX_WXB);
2343 }
2344 } else {
2345 if ($mem$$index < 8) {
2346 emit_opcode(cbuf, Assembler::REX_W);
2347 } else {
2348 emit_opcode(cbuf, Assembler::REX_WX);
2349 }
2350 }
2351 %}
2352
2353 // for byte regs
2354 enc_class REX_breg(rRegI reg)
2355 %{
2356 if ($reg$$reg >= 4) {
2357 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2358 }
2359 %}
2360
2361 // for byte regs
2362 enc_class REX_reg_breg(rRegI dst, rRegI src)
2363 %{
2364 if ($dst$$reg < 8) {
2365 if ($src$$reg >= 4) {
2366 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2367 }
2368 } else {
2369 if ($src$$reg < 8) {
2370 emit_opcode(cbuf, Assembler::REX_R);
2371 } else {
2372 emit_opcode(cbuf, Assembler::REX_RB);
2373 }
2374 }
2375 %}
2376
2377 // for byte regs
2378 enc_class REX_breg_mem(rRegI reg, memory mem)
2379 %{
2380 if ($reg$$reg < 8) {
2381 if ($mem$$base < 8) {
2382 if ($mem$$index >= 8) {
2383 emit_opcode(cbuf, Assembler::REX_X);
2384 } else if ($reg$$reg >= 4) {
2385 emit_opcode(cbuf, Assembler::REX);
2386 }
2387 } else {
2388 if ($mem$$index < 8) {
2389 emit_opcode(cbuf, Assembler::REX_B);
2390 } else {
2391 emit_opcode(cbuf, Assembler::REX_XB);
2392 }
2393 }
2394 } else {
2395 if ($mem$$base < 8) {
2396 if ($mem$$index < 8) {
2397 emit_opcode(cbuf, Assembler::REX_R);
2398 } else {
2399 emit_opcode(cbuf, Assembler::REX_RX);
2400 }
2401 } else {
2402 if ($mem$$index < 8) {
2403 emit_opcode(cbuf, Assembler::REX_RB);
2404 } else {
2405 emit_opcode(cbuf, Assembler::REX_RXB);
2406 }
2407 }
2408 }
2409 %}
2410
2411 enc_class REX_reg(rRegI reg)
2412 %{
2413 if ($reg$$reg >= 8) {
2414 emit_opcode(cbuf, Assembler::REX_B);
2415 }
2416 %}
2417
2418 enc_class REX_reg_wide(rRegI reg)
2419 %{
2420 if ($reg$$reg < 8) {
2421 emit_opcode(cbuf, Assembler::REX_W);
2422 } else {
2423 emit_opcode(cbuf, Assembler::REX_WB);
2424 }
2425 %}
2426
2427 enc_class REX_reg_reg(rRegI dst, rRegI src)
2428 %{
2429 if ($dst$$reg < 8) {
2430 if ($src$$reg >= 8) {
2431 emit_opcode(cbuf, Assembler::REX_B);
2432 }
2433 } else {
2434 if ($src$$reg < 8) {
2435 emit_opcode(cbuf, Assembler::REX_R);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_RB);
2438 }
2439 }
2440 %}
2441
2442 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2443 %{
2444 if ($dst$$reg < 8) {
2445 if ($src$$reg < 8) {
2446 emit_opcode(cbuf, Assembler::REX_W);
2447 } else {
2448 emit_opcode(cbuf, Assembler::REX_WB);
2449 }
2450 } else {
2451 if ($src$$reg < 8) {
2452 emit_opcode(cbuf, Assembler::REX_WR);
2453 } else {
2454 emit_opcode(cbuf, Assembler::REX_WRB);
2455 }
2456 }
2457 %}
2458
2459 enc_class REX_reg_mem(rRegI reg, memory mem)
2460 %{
2461 if ($reg$$reg < 8) {
2462 if ($mem$$base < 8) {
2463 if ($mem$$index >= 8) {
2464 emit_opcode(cbuf, Assembler::REX_X);
2465 }
2466 } else {
2467 if ($mem$$index < 8) {
2468 emit_opcode(cbuf, Assembler::REX_B);
2469 } else {
2470 emit_opcode(cbuf, Assembler::REX_XB);
2471 }
2472 }
2473 } else {
2474 if ($mem$$base < 8) {
2475 if ($mem$$index < 8) {
2476 emit_opcode(cbuf, Assembler::REX_R);
2477 } else {
2478 emit_opcode(cbuf, Assembler::REX_RX);
2479 }
2480 } else {
2481 if ($mem$$index < 8) {
2482 emit_opcode(cbuf, Assembler::REX_RB);
2483 } else {
2484 emit_opcode(cbuf, Assembler::REX_RXB);
2485 }
2486 }
2487 }
2488 %}
2489
2490 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2491 %{
2492 if ($reg$$reg < 8) {
2493 if ($mem$$base < 8) {
2494 if ($mem$$index < 8) {
2495 emit_opcode(cbuf, Assembler::REX_W);
2496 } else {
2497 emit_opcode(cbuf, Assembler::REX_WX);
2498 }
2499 } else {
2500 if ($mem$$index < 8) {
2501 emit_opcode(cbuf, Assembler::REX_WB);
2502 } else {
2503 emit_opcode(cbuf, Assembler::REX_WXB);
2504 }
2505 }
2506 } else {
2507 if ($mem$$base < 8) {
2508 if ($mem$$index < 8) {
2509 emit_opcode(cbuf, Assembler::REX_WR);
2510 } else {
2511 emit_opcode(cbuf, Assembler::REX_WRX);
2512 }
2513 } else {
2514 if ($mem$$index < 8) {
2515 emit_opcode(cbuf, Assembler::REX_WRB);
2516 } else {
2517 emit_opcode(cbuf, Assembler::REX_WRXB);
2518 }
2519 }
2520 }
2521 %}
2522
2523 enc_class reg_mem(rRegI ereg, memory mem)
2524 %{
2525 // High registers handle in encode_RegMem
2526 int reg = $ereg$$reg;
2527 int base = $mem$$base;
2528 int index = $mem$$index;
2529 int scale = $mem$$scale;
2530 int disp = $mem$$disp;
2531 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2532
2533 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2534 %}
2535
2536 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2537 %{
2538 int rm_byte_opcode = $rm_opcode$$constant;
2539
2540 // High registers handle in encode_RegMem
2541 int base = $mem$$base;
2542 int index = $mem$$index;
2543 int scale = $mem$$scale;
2544 int displace = $mem$$disp;
2545
2546 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2547 // working with static
2548 // globals
2549 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2550 disp_reloc);
2551 %}
2552
2553 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2554 %{
2555 int reg_encoding = $dst$$reg;
2556 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2557 int index = 0x04; // 0x04 indicates no index
2558 int scale = 0x00; // 0x00 indicates no scale
2559 int displace = $src1$$constant; // 0x00 indicates no displacement
2560 relocInfo::relocType disp_reloc = relocInfo::none;
2561 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2562 disp_reloc);
2563 %}
2564
2565 enc_class neg_reg(rRegI dst)
2566 %{
2567 int dstenc = $dst$$reg;
2568 if (dstenc >= 8) {
2569 emit_opcode(cbuf, Assembler::REX_B);
2570 dstenc -= 8;
2571 }
2572 // NEG $dst
2573 emit_opcode(cbuf, 0xF7);
2574 emit_rm(cbuf, 0x3, 0x03, dstenc);
2575 %}
2576
2577 enc_class neg_reg_wide(rRegI dst)
2578 %{
2579 int dstenc = $dst$$reg;
2580 if (dstenc < 8) {
2581 emit_opcode(cbuf, Assembler::REX_W);
2582 } else {
2583 emit_opcode(cbuf, Assembler::REX_WB);
2584 dstenc -= 8;
2585 }
2586 // NEG $dst
2587 emit_opcode(cbuf, 0xF7);
2588 emit_rm(cbuf, 0x3, 0x03, dstenc);
2589 %}
2590
2591 enc_class setLT_reg(rRegI dst)
2592 %{
2593 int dstenc = $dst$$reg;
2594 if (dstenc >= 8) {
2595 emit_opcode(cbuf, Assembler::REX_B);
2596 dstenc -= 8;
2597 } else if (dstenc >= 4) {
2598 emit_opcode(cbuf, Assembler::REX);
2599 }
2600 // SETLT $dst
2601 emit_opcode(cbuf, 0x0F);
2602 emit_opcode(cbuf, 0x9C);
2603 emit_rm(cbuf, 0x3, 0x0, dstenc);
2604 %}
2605
2606 enc_class setNZ_reg(rRegI dst)
2607 %{
2608 int dstenc = $dst$$reg;
2609 if (dstenc >= 8) {
2610 emit_opcode(cbuf, Assembler::REX_B);
2611 dstenc -= 8;
2612 } else if (dstenc >= 4) {
2613 emit_opcode(cbuf, Assembler::REX);
2614 }
2615 // SETNZ $dst
2616 emit_opcode(cbuf, 0x0F);
2617 emit_opcode(cbuf, 0x95);
2618 emit_rm(cbuf, 0x3, 0x0, dstenc);
2619 %}
2620
2621
2622 // Compare the lonogs and set -1, 0, or 1 into dst
2623 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2624 %{
2625 int src1enc = $src1$$reg;
2626 int src2enc = $src2$$reg;
2627 int dstenc = $dst$$reg;
2628
2629 // cmpq $src1, $src2
2630 if (src1enc < 8) {
2631 if (src2enc < 8) {
2632 emit_opcode(cbuf, Assembler::REX_W);
2633 } else {
2634 emit_opcode(cbuf, Assembler::REX_WB);
2635 }
2636 } else {
2637 if (src2enc < 8) {
2638 emit_opcode(cbuf, Assembler::REX_WR);
2639 } else {
2640 emit_opcode(cbuf, Assembler::REX_WRB);
2641 }
2642 }
2643 emit_opcode(cbuf, 0x3B);
2644 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2645
2646 // movl $dst, -1
2647 if (dstenc >= 8) {
2648 emit_opcode(cbuf, Assembler::REX_B);
2649 }
2650 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2651 emit_d32(cbuf, -1);
2652
2653 // jl,s done
2654 emit_opcode(cbuf, 0x7C);
2655 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2656
2657 // setne $dst
2658 if (dstenc >= 4) {
2659 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2660 }
2661 emit_opcode(cbuf, 0x0F);
2662 emit_opcode(cbuf, 0x95);
2663 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2664
2665 // movzbl $dst, $dst
2666 if (dstenc >= 4) {
2667 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2668 }
2669 emit_opcode(cbuf, 0x0F);
2670 emit_opcode(cbuf, 0xB6);
2671 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2672 %}
2673
2674 enc_class Push_ResultXD(regD dst) %{
2675 MacroAssembler _masm(&cbuf);
2676 __ fstp_d(Address(rsp, 0));
2677 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2678 __ addptr(rsp, 8);
2679 %}
2680
2681 enc_class Push_SrcXD(regD src) %{
2682 MacroAssembler _masm(&cbuf);
2683 __ subptr(rsp, 8);
2684 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2685 __ fld_d(Address(rsp, 0));
2686 %}
2687
2688
2689 enc_class enc_rethrow()
2690 %{
2691 cbuf.set_insts_mark();
2692 emit_opcode(cbuf, 0xE9); // jmp entry
2693 emit_d32_reloc(cbuf,
2694 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2695 runtime_call_Relocation::spec(),
2696 RELOC_DISP32);
2697 %}
2698
2699 %}
2700
2701
2702
2703 //----------FRAME--------------------------------------------------------------
2704 // Definition of frame structure and management information.
2705 //
2706 // S T A C K L A Y O U T Allocators stack-slot number
2707 // | (to get allocators register number
2708 // G Owned by | | v add OptoReg::stack0())
2709 // r CALLER | |
2710 // o | +--------+ pad to even-align allocators stack-slot
2711 // w V | pad0 | numbers; owned by CALLER
2712 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2713 // h ^ | in | 5
2714 // | | args | 4 Holes in incoming args owned by SELF
2715 // | | | | 3
2716 // | | +--------+
2717 // V | | old out| Empty on Intel, window on Sparc
2718 // | old |preserve| Must be even aligned.
2719 // | SP-+--------+----> Matcher::_old_SP, even aligned
2720 // | | in | 3 area for Intel ret address
2721 // Owned by |preserve| Empty on Sparc.
2722 // SELF +--------+
2723 // | | pad2 | 2 pad to align old SP
2724 // | +--------+ 1
2725 // | | locks | 0
2726 // | +--------+----> OptoReg::stack0(), even aligned
2727 // | | pad1 | 11 pad to align new SP
2728 // | +--------+
2729 // | | | 10
2730 // | | spills | 9 spills
2731 // V | | 8 (pad0 slot for callee)
2732 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2733 // ^ | out | 7
2734 // | | args | 6 Holes in outgoing args owned by CALLEE
2735 // Owned by +--------+
2736 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2737 // | new |preserve| Must be even-aligned.
2738 // | SP-+--------+----> Matcher::_new_SP, even aligned
2739 // | | |
2740 //
2741 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2742 // known from SELF's arguments and the Java calling convention.
2743 // Region 6-7 is determined per call site.
2744 // Note 2: If the calling convention leaves holes in the incoming argument
2745 // area, those holes are owned by SELF. Holes in the outgoing area
2746 // are owned by the CALLEE. Holes should not be nessecary in the
2747 // incoming area, as the Java calling convention is completely under
2748 // the control of the AD file. Doubles can be sorted and packed to
2749 // avoid holes. Holes in the outgoing arguments may be nessecary for
2750 // varargs C calling conventions.
2751 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2752 // even aligned with pad0 as needed.
2753 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2754 // region 6-11 is even aligned; it may be padded out more so that
2755 // the region from SP to FP meets the minimum stack alignment.
2756 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2757 // alignment. Region 11, pad1, may be dynamically extended so that
2758 // SP meets the minimum alignment.
2759
2760 frame
2761 %{
2762 // What direction does stack grow in (assumed to be same for C & Java)
2763 stack_direction(TOWARDS_LOW);
2764
2765 // These three registers define part of the calling convention
2766 // between compiled code and the interpreter.
2767 inline_cache_reg(RAX); // Inline Cache Register
2768 interpreter_method_oop_reg(RBX); // Method Oop Register when
2769 // calling interpreter
2770
2771 // Optional: name the operand used by cisc-spilling to access
2772 // [stack_pointer + offset]
2773 cisc_spilling_operand_name(indOffset32);
2774
2775 // Number of stack slots consumed by locking an object
2776 sync_stack_slots(2);
2777
2778 // Compiled code's Frame Pointer
2779 frame_pointer(RSP);
2780
2781 // Interpreter stores its frame pointer in a register which is
2782 // stored to the stack by I2CAdaptors.
2783 // I2CAdaptors convert from interpreted java to compiled java.
2784 interpreter_frame_pointer(RBP);
2785
2786 // Stack alignment requirement
2787 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2788
2789 // Number of stack slots between incoming argument block and the start of
2790 // a new frame. The PROLOG must add this many slots to the stack. The
2791 // EPILOG must remove this many slots. amd64 needs two slots for
2792 // return address.
2793 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2794
2795 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2796 // for calls to C. Supports the var-args backing area for register parms.
2797 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2798
2799 // The after-PROLOG location of the return address. Location of
2800 // return address specifies a type (REG or STACK) and a number
2801 // representing the register number (i.e. - use a register name) or
2802 // stack slot.
2803 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2804 // Otherwise, it is above the locks and verification slot and alignment word
2805 return_addr(STACK - 2 +
2806 align_up((Compile::current()->in_preserve_stack_slots() +
2807 Compile::current()->fixed_slots()),
2808 stack_alignment_in_slots()));
2809
2810 // Body of function which returns an integer array locating
2811 // arguments either in registers or in stack slots. Passed an array
2812 // of ideal registers called "sig" and a "length" count. Stack-slot
2813 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2814 // arguments for a CALLEE. Incoming stack arguments are
2815 // automatically biased by the preserve_stack_slots field above.
2816
2817 calling_convention
2818 %{
2819 // No difference between ingoing/outgoing just pass false
2820 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2821 %}
2822
2823 c_calling_convention
2824 %{
2825 // This is obviously always outgoing
2826 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2827 %}
2828
2829 // Location of compiled Java return values. Same as C for now.
2830 return_value
2831 %{
2832 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2833 "only return normal values");
2834
2835 static const int lo[Op_RegL + 1] = {
2836 0,
2837 0,
2838 RAX_num, // Op_RegN
2839 RAX_num, // Op_RegI
2840 RAX_num, // Op_RegP
2841 XMM0_num, // Op_RegF
2842 XMM0_num, // Op_RegD
2843 RAX_num // Op_RegL
2844 };
2845 static const int hi[Op_RegL + 1] = {
2846 0,
2847 0,
2848 OptoReg::Bad, // Op_RegN
2849 OptoReg::Bad, // Op_RegI
2850 RAX_H_num, // Op_RegP
2851 OptoReg::Bad, // Op_RegF
2852 XMM0b_num, // Op_RegD
2853 RAX_H_num // Op_RegL
2854 };
2855 // Excluded flags and vector registers.
2856 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2857 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2858 %}
2859 %}
2860
2861 //----------ATTRIBUTES---------------------------------------------------------
2862 //----------Operand Attributes-------------------------------------------------
2863 op_attrib op_cost(0); // Required cost attribute
2864
2865 //----------Instruction Attributes---------------------------------------------
2866 ins_attrib ins_cost(100); // Required cost attribute
2867 ins_attrib ins_size(8); // Required size attribute (in bits)
2868 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2869 // a non-matching short branch variant
2870 // of some long branch?
2871 ins_attrib ins_alignment(1); // Required alignment attribute (must
2872 // be a power of 2) specifies the
2873 // alignment that some part of the
2874 // instruction (not necessarily the
2875 // start) requires. If > 1, a
2876 // compute_padding() function must be
2877 // provided for the instruction
2878
2879 //----------OPERANDS-----------------------------------------------------------
2880 // Operand definitions must precede instruction definitions for correct parsing
2881 // in the ADLC because operands constitute user defined types which are used in
2882 // instruction definitions.
2883
2884 //----------Simple Operands----------------------------------------------------
2885 // Immediate Operands
2886 // Integer Immediate
2887 operand immI()
2888 %{
2889 match(ConI);
2890
2891 op_cost(10);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // Constant for test vs zero
2897 operand immI0()
2898 %{
2899 predicate(n->get_int() == 0);
2900 match(ConI);
2901
2902 op_cost(0);
2903 format %{ %}
2904 interface(CONST_INTER);
2905 %}
2906
2907 // Constant for increment
2908 operand immI1()
2909 %{
2910 predicate(n->get_int() == 1);
2911 match(ConI);
2912
2913 op_cost(0);
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 // Constant for decrement
2919 operand immI_M1()
2920 %{
2921 predicate(n->get_int() == -1);
2922 match(ConI);
2923
2924 op_cost(0);
2925 format %{ %}
2926 interface(CONST_INTER);
2927 %}
2928
2929 // Valid scale values for addressing modes
2930 operand immI2()
2931 %{
2932 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2933 match(ConI);
2934
2935 format %{ %}
2936 interface(CONST_INTER);
2937 %}
2938
2939 operand immI8()
2940 %{
2941 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2942 match(ConI);
2943
2944 op_cost(5);
2945 format %{ %}
2946 interface(CONST_INTER);
2947 %}
2948
2949 operand immU8()
2950 %{
2951 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2952 match(ConI);
2953
2954 op_cost(5);
2955 format %{ %}
2956 interface(CONST_INTER);
2957 %}
2958
2959 operand immI16()
2960 %{
2961 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2962 match(ConI);
2963
2964 op_cost(10);
2965 format %{ %}
2966 interface(CONST_INTER);
2967 %}
2968
2969 // Int Immediate non-negative
2970 operand immU31()
2971 %{
2972 predicate(n->get_int() >= 0);
2973 match(ConI);
2974
2975 op_cost(0);
2976 format %{ %}
2977 interface(CONST_INTER);
2978 %}
2979
2980 // Constant for long shifts
2981 operand immI_32()
2982 %{
2983 predicate( n->get_int() == 32 );
2984 match(ConI);
2985
2986 op_cost(0);
2987 format %{ %}
2988 interface(CONST_INTER);
2989 %}
2990
2991 // Constant for long shifts
2992 operand immI_64()
2993 %{
2994 predicate( n->get_int() == 64 );
2995 match(ConI);
2996
2997 op_cost(0);
2998 format %{ %}
2999 interface(CONST_INTER);
3000 %}
3001
3002 // Pointer Immediate
3003 operand immP()
3004 %{
3005 match(ConP);
3006
3007 op_cost(10);
3008 format %{ %}
3009 interface(CONST_INTER);
3010 %}
3011
3012 // NULL Pointer Immediate
3013 operand immP0()
3014 %{
3015 predicate(n->get_ptr() == 0);
3016 match(ConP);
3017
3018 op_cost(5);
3019 format %{ %}
3020 interface(CONST_INTER);
3021 %}
3022
3023 // Pointer Immediate
3024 operand immN() %{
3025 match(ConN);
3026
3027 op_cost(10);
3028 format %{ %}
3029 interface(CONST_INTER);
3030 %}
3031
3032 operand immNKlass() %{
3033 match(ConNKlass);
3034
3035 op_cost(10);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 // NULL Pointer Immediate
3041 operand immN0() %{
3042 predicate(n->get_narrowcon() == 0);
3043 match(ConN);
3044
3045 op_cost(5);
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050 operand immP31()
3051 %{
3052 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3053 && (n->get_ptr() >> 31) == 0);
3054 match(ConP);
3055
3056 op_cost(5);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061
3062 // Long Immediate
3063 operand immL()
3064 %{
3065 match(ConL);
3066
3067 op_cost(20);
3068 format %{ %}
3069 interface(CONST_INTER);
3070 %}
3071
3072 // Long Immediate 8-bit
3073 operand immL8()
3074 %{
3075 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3076 match(ConL);
3077
3078 op_cost(5);
3079 format %{ %}
3080 interface(CONST_INTER);
3081 %}
3082
3083 // Long Immediate 32-bit unsigned
3084 operand immUL32()
3085 %{
3086 predicate(n->get_long() == (unsigned int) (n->get_long()));
3087 match(ConL);
3088
3089 op_cost(10);
3090 format %{ %}
3091 interface(CONST_INTER);
3092 %}
3093
3094 // Long Immediate 32-bit signed
3095 operand immL32()
3096 %{
3097 predicate(n->get_long() == (int) (n->get_long()));
3098 match(ConL);
3099
3100 op_cost(15);
3101 format %{ %}
3102 interface(CONST_INTER);
3103 %}
3104
3105 // Long Immediate zero
3106 operand immL0()
3107 %{
3108 predicate(n->get_long() == 0L);
3109 match(ConL);
3110
3111 op_cost(10);
3112 format %{ %}
3113 interface(CONST_INTER);
3114 %}
3115
3116 // Constant for increment
3117 operand immL1()
3118 %{
3119 predicate(n->get_long() == 1);
3120 match(ConL);
3121
3122 format %{ %}
3123 interface(CONST_INTER);
3124 %}
3125
3126 // Constant for decrement
3127 operand immL_M1()
3128 %{
3129 predicate(n->get_long() == -1);
3130 match(ConL);
3131
3132 format %{ %}
3133 interface(CONST_INTER);
3134 %}
3135
3136 // Long Immediate: the value 10
3137 operand immL10()
3138 %{
3139 predicate(n->get_long() == 10);
3140 match(ConL);
3141
3142 format %{ %}
3143 interface(CONST_INTER);
3144 %}
3145
3146 // Long immediate from 0 to 127.
3147 // Used for a shorter form of long mul by 10.
3148 operand immL_127()
3149 %{
3150 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3151 match(ConL);
3152
3153 op_cost(10);
3154 format %{ %}
3155 interface(CONST_INTER);
3156 %}
3157
3158 // Long Immediate: low 32-bit mask
3159 operand immL_32bits()
3160 %{
3161 predicate(n->get_long() == 0xFFFFFFFFL);
3162 match(ConL);
3163 op_cost(20);
3164
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3168
3169 // Float Immediate zero
3170 operand immF0()
3171 %{
3172 predicate(jint_cast(n->getf()) == 0);
3173 match(ConF);
3174
3175 op_cost(5);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Float Immediate
3181 operand immF()
3182 %{
3183 match(ConF);
3184
3185 op_cost(15);
3186 format %{ %}
3187 interface(CONST_INTER);
3188 %}
3189
3190 // Double Immediate zero
3191 operand immD0()
3192 %{
3193 predicate(jlong_cast(n->getd()) == 0);
3194 match(ConD);
3195
3196 op_cost(5);
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Double Immediate
3202 operand immD()
3203 %{
3204 match(ConD);
3205
3206 op_cost(15);
3207 format %{ %}
3208 interface(CONST_INTER);
3209 %}
3210
3211 // Immediates for special shifts (sign extend)
3212
3213 // Constants for increment
3214 operand immI_16()
3215 %{
3216 predicate(n->get_int() == 16);
3217 match(ConI);
3218
3219 format %{ %}
3220 interface(CONST_INTER);
3221 %}
3222
3223 operand immI_24()
3224 %{
3225 predicate(n->get_int() == 24);
3226 match(ConI);
3227
3228 format %{ %}
3229 interface(CONST_INTER);
3230 %}
3231
3232 // Constant for byte-wide masking
3233 operand immI_255()
3234 %{
3235 predicate(n->get_int() == 255);
3236 match(ConI);
3237
3238 format %{ %}
3239 interface(CONST_INTER);
3240 %}
3241
3242 // Constant for short-wide masking
3243 operand immI_65535()
3244 %{
3245 predicate(n->get_int() == 65535);
3246 match(ConI);
3247
3248 format %{ %}
3249 interface(CONST_INTER);
3250 %}
3251
3252 // Constant for byte-wide masking
3253 operand immL_255()
3254 %{
3255 predicate(n->get_long() == 255);
3256 match(ConL);
3257
3258 format %{ %}
3259 interface(CONST_INTER);
3260 %}
3261
3262 // Constant for short-wide masking
3263 operand immL_65535()
3264 %{
3265 predicate(n->get_long() == 65535);
3266 match(ConL);
3267
3268 format %{ %}
3269 interface(CONST_INTER);
3270 %}
3271
3272 // Register Operands
3273 // Integer Register
3274 operand rRegI()
3275 %{
3276 constraint(ALLOC_IN_RC(int_reg));
3277 match(RegI);
3278
3279 match(rax_RegI);
3280 match(rbx_RegI);
3281 match(rcx_RegI);
3282 match(rdx_RegI);
3283 match(rdi_RegI);
3284
3285 format %{ %}
3286 interface(REG_INTER);
3287 %}
3288
3289 // Special Registers
3290 operand rax_RegI()
3291 %{
3292 constraint(ALLOC_IN_RC(int_rax_reg));
3293 match(RegI);
3294 match(rRegI);
3295
3296 format %{ "RAX" %}
3297 interface(REG_INTER);
3298 %}
3299
3300 // Special Registers
3301 operand rbx_RegI()
3302 %{
3303 constraint(ALLOC_IN_RC(int_rbx_reg));
3304 match(RegI);
3305 match(rRegI);
3306
3307 format %{ "RBX" %}
3308 interface(REG_INTER);
3309 %}
3310
3311 operand rcx_RegI()
3312 %{
3313 constraint(ALLOC_IN_RC(int_rcx_reg));
3314 match(RegI);
3315 match(rRegI);
3316
3317 format %{ "RCX" %}
3318 interface(REG_INTER);
3319 %}
3320
3321 operand rdx_RegI()
3322 %{
3323 constraint(ALLOC_IN_RC(int_rdx_reg));
3324 match(RegI);
3325 match(rRegI);
3326
3327 format %{ "RDX" %}
3328 interface(REG_INTER);
3329 %}
3330
3331 operand rdi_RegI()
3332 %{
3333 constraint(ALLOC_IN_RC(int_rdi_reg));
3334 match(RegI);
3335 match(rRegI);
3336
3337 format %{ "RDI" %}
3338 interface(REG_INTER);
3339 %}
3340
3341 operand no_rcx_RegI()
3342 %{
3343 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3344 match(RegI);
3345 match(rax_RegI);
3346 match(rbx_RegI);
3347 match(rdx_RegI);
3348 match(rdi_RegI);
3349
3350 format %{ %}
3351 interface(REG_INTER);
3352 %}
3353
3354 operand no_rax_rdx_RegI()
3355 %{
3356 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3357 match(RegI);
3358 match(rbx_RegI);
3359 match(rcx_RegI);
3360 match(rdi_RegI);
3361
3362 format %{ %}
3363 interface(REG_INTER);
3364 %}
3365
3366 // Pointer Register
3367 operand any_RegP()
3368 %{
3369 constraint(ALLOC_IN_RC(any_reg));
3370 match(RegP);
3371 match(rax_RegP);
3372 match(rbx_RegP);
3373 match(rdi_RegP);
3374 match(rsi_RegP);
3375 match(rbp_RegP);
3376 match(r15_RegP);
3377 match(rRegP);
3378
3379 format %{ %}
3380 interface(REG_INTER);
3381 %}
3382
3383 operand rRegP()
3384 %{
3385 constraint(ALLOC_IN_RC(ptr_reg));
3386 match(RegP);
3387 match(rax_RegP);
3388 match(rbx_RegP);
3389 match(rdi_RegP);
3390 match(rsi_RegP);
3391 match(rbp_RegP); // See Q&A below about
3392 match(r15_RegP); // r15_RegP and rbp_RegP.
3393
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 operand rRegN() %{
3399 constraint(ALLOC_IN_RC(int_reg));
3400 match(RegN);
3401
3402 format %{ %}
3403 interface(REG_INTER);
3404 %}
3405
3406 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3407 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3408 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3409 // The output of an instruction is controlled by the allocator, which respects
3410 // register class masks, not match rules. Unless an instruction mentions
3411 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3412 // by the allocator as an input.
3413 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3414 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3415 // result, RBP is not included in the output of the instruction either.
3416
3417 operand no_rax_RegP()
3418 %{
3419 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3420 match(RegP);
3421 match(rbx_RegP);
3422 match(rsi_RegP);
3423 match(rdi_RegP);
3424
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 // This operand is not allowed to use RBP even if
3430 // RBP is not used to hold the frame pointer.
3431 operand no_rbp_RegP()
3432 %{
3433 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3434 match(RegP);
3435 match(rbx_RegP);
3436 match(rsi_RegP);
3437 match(rdi_RegP);
3438
3439 format %{ %}
3440 interface(REG_INTER);
3441 %}
3442
3443 operand no_rax_rbx_RegP()
3444 %{
3445 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3446 match(RegP);
3447 match(rsi_RegP);
3448 match(rdi_RegP);
3449
3450 format %{ %}
3451 interface(REG_INTER);
3452 %}
3453
3454 // Special Registers
3455 // Return a pointer value
3456 operand rax_RegP()
3457 %{
3458 constraint(ALLOC_IN_RC(ptr_rax_reg));
3459 match(RegP);
3460 match(rRegP);
3461
3462 format %{ %}
3463 interface(REG_INTER);
3464 %}
3465
3466 // Special Registers
3467 // Return a compressed pointer value
3468 operand rax_RegN()
3469 %{
3470 constraint(ALLOC_IN_RC(int_rax_reg));
3471 match(RegN);
3472 match(rRegN);
3473
3474 format %{ %}
3475 interface(REG_INTER);
3476 %}
3477
3478 // Used in AtomicAdd
3479 operand rbx_RegP()
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3482 match(RegP);
3483 match(rRegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand rsi_RegP()
3490 %{
3491 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3492 match(RegP);
3493 match(rRegP);
3494
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 // Used in rep stosq
3500 operand rdi_RegP()
3501 %{
3502 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3503 match(RegP);
3504 match(rRegP);
3505
3506 format %{ %}
3507 interface(REG_INTER);
3508 %}
3509
3510 operand r15_RegP()
3511 %{
3512 constraint(ALLOC_IN_RC(ptr_r15_reg));
3513 match(RegP);
3514 match(rRegP);
3515
3516 format %{ %}
3517 interface(REG_INTER);
3518 %}
3519
3520 operand rRegL()
3521 %{
3522 constraint(ALLOC_IN_RC(long_reg));
3523 match(RegL);
3524 match(rax_RegL);
3525 match(rdx_RegL);
3526
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 // Special Registers
3532 operand no_rax_rdx_RegL()
3533 %{
3534 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3535 match(RegL);
3536 match(rRegL);
3537
3538 format %{ %}
3539 interface(REG_INTER);
3540 %}
3541
3542 operand no_rax_RegL()
3543 %{
3544 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3545 match(RegL);
3546 match(rRegL);
3547 match(rdx_RegL);
3548
3549 format %{ %}
3550 interface(REG_INTER);
3551 %}
3552
3553 operand no_rcx_RegL()
3554 %{
3555 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3556 match(RegL);
3557 match(rRegL);
3558
3559 format %{ %}
3560 interface(REG_INTER);
3561 %}
3562
3563 operand rax_RegL()
3564 %{
3565 constraint(ALLOC_IN_RC(long_rax_reg));
3566 match(RegL);
3567 match(rRegL);
3568
3569 format %{ "RAX" %}
3570 interface(REG_INTER);
3571 %}
3572
3573 operand rcx_RegL()
3574 %{
3575 constraint(ALLOC_IN_RC(long_rcx_reg));
3576 match(RegL);
3577 match(rRegL);
3578
3579 format %{ %}
3580 interface(REG_INTER);
3581 %}
3582
3583 operand rdx_RegL()
3584 %{
3585 constraint(ALLOC_IN_RC(long_rdx_reg));
3586 match(RegL);
3587 match(rRegL);
3588
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3592
3593 // Flags register, used as output of compare instructions
3594 operand rFlagsReg()
3595 %{
3596 constraint(ALLOC_IN_RC(int_flags));
3597 match(RegFlags);
3598
3599 format %{ "RFLAGS" %}
3600 interface(REG_INTER);
3601 %}
3602
3603 // Flags register, used as output of FLOATING POINT compare instructions
3604 operand rFlagsRegU()
3605 %{
3606 constraint(ALLOC_IN_RC(int_flags));
3607 match(RegFlags);
3608
3609 format %{ "RFLAGS_U" %}
3610 interface(REG_INTER);
3611 %}
3612
3613 operand rFlagsRegUCF() %{
3614 constraint(ALLOC_IN_RC(int_flags));
3615 match(RegFlags);
3616 predicate(false);
3617
3618 format %{ "RFLAGS_U_CF" %}
3619 interface(REG_INTER);
3620 %}
3621
3622 // Float register operands
3623 operand regF() %{
3624 constraint(ALLOC_IN_RC(float_reg));
3625 match(RegF);
3626
3627 format %{ %}
3628 interface(REG_INTER);
3629 %}
3630
3631 // Float register operands
3632 operand legRegF() %{
3633 constraint(ALLOC_IN_RC(float_reg_legacy));
3634 match(RegF);
3635
3636 format %{ %}
3637 interface(REG_INTER);
3638 %}
3639
3640 // Float register operands
3641 operand vlRegF() %{
3642 constraint(ALLOC_IN_RC(float_reg_vl));
3643 match(RegF);
3644
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 // Double register operands
3650 operand regD() %{
3651 constraint(ALLOC_IN_RC(double_reg));
3652 match(RegD);
3653
3654 format %{ %}
3655 interface(REG_INTER);
3656 %}
3657
3658 // Double register operands
3659 operand legRegD() %{
3660 constraint(ALLOC_IN_RC(double_reg_legacy));
3661 match(RegD);
3662
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3666
3667 // Double register operands
3668 operand vlRegD() %{
3669 constraint(ALLOC_IN_RC(double_reg_vl));
3670 match(RegD);
3671
3672 format %{ %}
3673 interface(REG_INTER);
3674 %}
3675
3676 // Vectors
3677 operand vecS() %{
3678 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3679 match(VecS);
3680
3681 format %{ %}
3682 interface(REG_INTER);
3683 %}
3684
3685 // Vectors
3686 operand legVecS() %{
3687 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3688 match(VecS);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 operand vecD() %{
3695 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3696 match(VecD);
3697
3698 format %{ %}
3699 interface(REG_INTER);
3700 %}
3701
3702 operand legVecD() %{
3703 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3704 match(VecD);
3705
3706 format %{ %}
3707 interface(REG_INTER);
3708 %}
3709
3710 operand vecX() %{
3711 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3712 match(VecX);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 operand legVecX() %{
3719 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3720 match(VecX);
3721
3722 format %{ %}
3723 interface(REG_INTER);
3724 %}
3725
3726 operand vecY() %{
3727 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3728 match(VecY);
3729
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3733
3734 operand legVecY() %{
3735 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3736 match(VecY);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 //----------Memory Operands----------------------------------------------------
3743 // Direct Memory Operand
3744 // operand direct(immP addr)
3745 // %{
3746 // match(addr);
3747
3748 // format %{ "[$addr]" %}
3749 // interface(MEMORY_INTER) %{
3750 // base(0xFFFFFFFF);
3751 // index(0x4);
3752 // scale(0x0);
3753 // disp($addr);
3754 // %}
3755 // %}
3756
3757 // Indirect Memory Operand
3758 operand indirect(any_RegP reg)
3759 %{
3760 constraint(ALLOC_IN_RC(ptr_reg));
3761 match(reg);
3762
3763 format %{ "[$reg]" %}
3764 interface(MEMORY_INTER) %{
3765 base($reg);
3766 index(0x4);
3767 scale(0x0);
3768 disp(0x0);
3769 %}
3770 %}
3771
3772 // Indirect Memory Plus Short Offset Operand
3773 operand indOffset8(any_RegP reg, immL8 off)
3774 %{
3775 constraint(ALLOC_IN_RC(ptr_reg));
3776 match(AddP reg off);
3777
3778 format %{ "[$reg + $off (8-bit)]" %}
3779 interface(MEMORY_INTER) %{
3780 base($reg);
3781 index(0x4);
3782 scale(0x0);
3783 disp($off);
3784 %}
3785 %}
3786
3787 // Indirect Memory Plus Long Offset Operand
3788 operand indOffset32(any_RegP reg, immL32 off)
3789 %{
3790 constraint(ALLOC_IN_RC(ptr_reg));
3791 match(AddP reg off);
3792
3793 format %{ "[$reg + $off (32-bit)]" %}
3794 interface(MEMORY_INTER) %{
3795 base($reg);
3796 index(0x4);
3797 scale(0x0);
3798 disp($off);
3799 %}
3800 %}
3801
3802 // Indirect Memory Plus Index Register Plus Offset Operand
3803 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3804 %{
3805 constraint(ALLOC_IN_RC(ptr_reg));
3806 match(AddP (AddP reg lreg) off);
3807
3808 op_cost(10);
3809 format %{"[$reg + $off + $lreg]" %}
3810 interface(MEMORY_INTER) %{
3811 base($reg);
3812 index($lreg);
3813 scale(0x0);
3814 disp($off);
3815 %}
3816 %}
3817
3818 // Indirect Memory Plus Index Register Plus Offset Operand
3819 operand indIndex(any_RegP reg, rRegL lreg)
3820 %{
3821 constraint(ALLOC_IN_RC(ptr_reg));
3822 match(AddP reg lreg);
3823
3824 op_cost(10);
3825 format %{"[$reg + $lreg]" %}
3826 interface(MEMORY_INTER) %{
3827 base($reg);
3828 index($lreg);
3829 scale(0x0);
3830 disp(0x0);
3831 %}
3832 %}
3833
3834 // Indirect Memory Times Scale Plus Index Register
3835 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3836 %{
3837 constraint(ALLOC_IN_RC(ptr_reg));
3838 match(AddP reg (LShiftL lreg scale));
3839
3840 op_cost(10);
3841 format %{"[$reg + $lreg << $scale]" %}
3842 interface(MEMORY_INTER) %{
3843 base($reg);
3844 index($lreg);
3845 scale($scale);
3846 disp(0x0);
3847 %}
3848 %}
3849
3850 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3851 %{
3852 constraint(ALLOC_IN_RC(ptr_reg));
3853 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3854 match(AddP reg (LShiftL (ConvI2L idx) scale));
3855
3856 op_cost(10);
3857 format %{"[$reg + pos $idx << $scale]" %}
3858 interface(MEMORY_INTER) %{
3859 base($reg);
3860 index($idx);
3861 scale($scale);
3862 disp(0x0);
3863 %}
3864 %}
3865
3866 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3867 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3868 %{
3869 constraint(ALLOC_IN_RC(ptr_reg));
3870 match(AddP (AddP reg (LShiftL lreg scale)) off);
3871
3872 op_cost(10);
3873 format %{"[$reg + $off + $lreg << $scale]" %}
3874 interface(MEMORY_INTER) %{
3875 base($reg);
3876 index($lreg);
3877 scale($scale);
3878 disp($off);
3879 %}
3880 %}
3881
3882 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3883 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3884 %{
3885 constraint(ALLOC_IN_RC(ptr_reg));
3886 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3887 match(AddP (AddP reg (ConvI2L idx)) off);
3888
3889 op_cost(10);
3890 format %{"[$reg + $off + $idx]" %}
3891 interface(MEMORY_INTER) %{
3892 base($reg);
3893 index($idx);
3894 scale(0x0);
3895 disp($off);
3896 %}
3897 %}
3898
3899 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3900 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3901 %{
3902 constraint(ALLOC_IN_RC(ptr_reg));
3903 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3904 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3905
3906 op_cost(10);
3907 format %{"[$reg + $off + $idx << $scale]" %}
3908 interface(MEMORY_INTER) %{
3909 base($reg);
3910 index($idx);
3911 scale($scale);
3912 disp($off);
3913 %}
3914 %}
3915
3916 // Indirect Narrow Oop Plus Offset Operand
3917 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3918 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3919 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3920 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3921 constraint(ALLOC_IN_RC(ptr_reg));
3922 match(AddP (DecodeN reg) off);
3923
3924 op_cost(10);
3925 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3926 interface(MEMORY_INTER) %{
3927 base(0xc); // R12
3928 index($reg);
3929 scale(0x3);
3930 disp($off);
3931 %}
3932 %}
3933
3934 // Indirect Memory Operand
3935 operand indirectNarrow(rRegN reg)
3936 %{
3937 predicate(Universe::narrow_oop_shift() == 0);
3938 constraint(ALLOC_IN_RC(ptr_reg));
3939 match(DecodeN reg);
3940
3941 format %{ "[$reg]" %}
3942 interface(MEMORY_INTER) %{
3943 base($reg);
3944 index(0x4);
3945 scale(0x0);
3946 disp(0x0);
3947 %}
3948 %}
3949
3950 // Indirect Memory Plus Short Offset Operand
3951 operand indOffset8Narrow(rRegN reg, immL8 off)
3952 %{
3953 predicate(Universe::narrow_oop_shift() == 0);
3954 constraint(ALLOC_IN_RC(ptr_reg));
3955 match(AddP (DecodeN reg) off);
3956
3957 format %{ "[$reg + $off (8-bit)]" %}
3958 interface(MEMORY_INTER) %{
3959 base($reg);
3960 index(0x4);
3961 scale(0x0);
3962 disp($off);
3963 %}
3964 %}
3965
3966 // Indirect Memory Plus Long Offset Operand
3967 operand indOffset32Narrow(rRegN reg, immL32 off)
3968 %{
3969 predicate(Universe::narrow_oop_shift() == 0);
3970 constraint(ALLOC_IN_RC(ptr_reg));
3971 match(AddP (DecodeN reg) off);
3972
3973 format %{ "[$reg + $off (32-bit)]" %}
3974 interface(MEMORY_INTER) %{
3975 base($reg);
3976 index(0x4);
3977 scale(0x0);
3978 disp($off);
3979 %}
3980 %}
3981
3982 // Indirect Memory Plus Index Register Plus Offset Operand
3983 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3984 %{
3985 predicate(Universe::narrow_oop_shift() == 0);
3986 constraint(ALLOC_IN_RC(ptr_reg));
3987 match(AddP (AddP (DecodeN reg) lreg) off);
3988
3989 op_cost(10);
3990 format %{"[$reg + $off + $lreg]" %}
3991 interface(MEMORY_INTER) %{
3992 base($reg);
3993 index($lreg);
3994 scale(0x0);
3995 disp($off);
3996 %}
3997 %}
3998
3999 // Indirect Memory Plus Index Register Plus Offset Operand
4000 operand indIndexNarrow(rRegN reg, rRegL lreg)
4001 %{
4002 predicate(Universe::narrow_oop_shift() == 0);
4003 constraint(ALLOC_IN_RC(ptr_reg));
4004 match(AddP (DecodeN reg) lreg);
4005
4006 op_cost(10);
4007 format %{"[$reg + $lreg]" %}
4008 interface(MEMORY_INTER) %{
4009 base($reg);
4010 index($lreg);
4011 scale(0x0);
4012 disp(0x0);
4013 %}
4014 %}
4015
4016 // Indirect Memory Times Scale Plus Index Register
4017 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4018 %{
4019 predicate(Universe::narrow_oop_shift() == 0);
4020 constraint(ALLOC_IN_RC(ptr_reg));
4021 match(AddP (DecodeN reg) (LShiftL lreg scale));
4022
4023 op_cost(10);
4024 format %{"[$reg + $lreg << $scale]" %}
4025 interface(MEMORY_INTER) %{
4026 base($reg);
4027 index($lreg);
4028 scale($scale);
4029 disp(0x0);
4030 %}
4031 %}
4032
4033 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4034 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4035 %{
4036 predicate(Universe::narrow_oop_shift() == 0);
4037 constraint(ALLOC_IN_RC(ptr_reg));
4038 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4039
4040 op_cost(10);
4041 format %{"[$reg + $off + $lreg << $scale]" %}
4042 interface(MEMORY_INTER) %{
4043 base($reg);
4044 index($lreg);
4045 scale($scale);
4046 disp($off);
4047 %}
4048 %}
4049
4050 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4051 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4052 %{
4053 constraint(ALLOC_IN_RC(ptr_reg));
4054 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4055 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4056
4057 op_cost(10);
4058 format %{"[$reg + $off + $idx]" %}
4059 interface(MEMORY_INTER) %{
4060 base($reg);
4061 index($idx);
4062 scale(0x0);
4063 disp($off);
4064 %}
4065 %}
4066
4067 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4068 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4069 %{
4070 constraint(ALLOC_IN_RC(ptr_reg));
4071 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4072 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4073
4074 op_cost(10);
4075 format %{"[$reg + $off + $idx << $scale]" %}
4076 interface(MEMORY_INTER) %{
4077 base($reg);
4078 index($idx);
4079 scale($scale);
4080 disp($off);
4081 %}
4082 %}
4083
4084 //----------Special Memory Operands--------------------------------------------
4085 // Stack Slot Operand - This operand is used for loading and storing temporary
4086 // values on the stack where a match requires a value to
4087 // flow through memory.
4088 operand stackSlotP(sRegP reg)
4089 %{
4090 constraint(ALLOC_IN_RC(stack_slots));
4091 // No match rule because this operand is only generated in matching
4092
4093 format %{ "[$reg]" %}
4094 interface(MEMORY_INTER) %{
4095 base(0x4); // RSP
4096 index(0x4); // No Index
4097 scale(0x0); // No Scale
4098 disp($reg); // Stack Offset
4099 %}
4100 %}
4101
4102 operand stackSlotI(sRegI reg)
4103 %{
4104 constraint(ALLOC_IN_RC(stack_slots));
4105 // No match rule because this operand is only generated in matching
4106
4107 format %{ "[$reg]" %}
4108 interface(MEMORY_INTER) %{
4109 base(0x4); // RSP
4110 index(0x4); // No Index
4111 scale(0x0); // No Scale
4112 disp($reg); // Stack Offset
4113 %}
4114 %}
4115
4116 operand stackSlotF(sRegF reg)
4117 %{
4118 constraint(ALLOC_IN_RC(stack_slots));
4119 // No match rule because this operand is only generated in matching
4120
4121 format %{ "[$reg]" %}
4122 interface(MEMORY_INTER) %{
4123 base(0x4); // RSP
4124 index(0x4); // No Index
4125 scale(0x0); // No Scale
4126 disp($reg); // Stack Offset
4127 %}
4128 %}
4129
4130 operand stackSlotD(sRegD reg)
4131 %{
4132 constraint(ALLOC_IN_RC(stack_slots));
4133 // No match rule because this operand is only generated in matching
4134
4135 format %{ "[$reg]" %}
4136 interface(MEMORY_INTER) %{
4137 base(0x4); // RSP
4138 index(0x4); // No Index
4139 scale(0x0); // No Scale
4140 disp($reg); // Stack Offset
4141 %}
4142 %}
4143 operand stackSlotL(sRegL reg)
4144 %{
4145 constraint(ALLOC_IN_RC(stack_slots));
4146 // No match rule because this operand is only generated in matching
4147
4148 format %{ "[$reg]" %}
4149 interface(MEMORY_INTER) %{
4150 base(0x4); // RSP
4151 index(0x4); // No Index
4152 scale(0x0); // No Scale
4153 disp($reg); // Stack Offset
4154 %}
4155 %}
4156
4157 //----------Conditional Branch Operands----------------------------------------
4158 // Comparison Op - This is the operation of the comparison, and is limited to
4159 // the following set of codes:
4160 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4161 //
4162 // Other attributes of the comparison, such as unsignedness, are specified
4163 // by the comparison instruction that sets a condition code flags register.
4164 // That result is represented by a flags operand whose subtype is appropriate
4165 // to the unsignedness (etc.) of the comparison.
4166 //
4167 // Later, the instruction which matches both the Comparison Op (a Bool) and
4168 // the flags (produced by the Cmp) specifies the coding of the comparison op
4169 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4170
4171 // Comparision Code
4172 operand cmpOp()
4173 %{
4174 match(Bool);
4175
4176 format %{ "" %}
4177 interface(COND_INTER) %{
4178 equal(0x4, "e");
4179 not_equal(0x5, "ne");
4180 less(0xC, "l");
4181 greater_equal(0xD, "ge");
4182 less_equal(0xE, "le");
4183 greater(0xF, "g");
4184 overflow(0x0, "o");
4185 no_overflow(0x1, "no");
4186 %}
4187 %}
4188
4189 // Comparison Code, unsigned compare. Used by FP also, with
4190 // C2 (unordered) turned into GT or LT already. The other bits
4191 // C0 and C3 are turned into Carry & Zero flags.
4192 operand cmpOpU()
4193 %{
4194 match(Bool);
4195
4196 format %{ "" %}
4197 interface(COND_INTER) %{
4198 equal(0x4, "e");
4199 not_equal(0x5, "ne");
4200 less(0x2, "b");
4201 greater_equal(0x3, "nb");
4202 less_equal(0x6, "be");
4203 greater(0x7, "nbe");
4204 overflow(0x0, "o");
4205 no_overflow(0x1, "no");
4206 %}
4207 %}
4208
4209
4210 // Floating comparisons that don't require any fixup for the unordered case
4211 operand cmpOpUCF() %{
4212 match(Bool);
4213 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4214 n->as_Bool()->_test._test == BoolTest::ge ||
4215 n->as_Bool()->_test._test == BoolTest::le ||
4216 n->as_Bool()->_test._test == BoolTest::gt);
4217 format %{ "" %}
4218 interface(COND_INTER) %{
4219 equal(0x4, "e");
4220 not_equal(0x5, "ne");
4221 less(0x2, "b");
4222 greater_equal(0x3, "nb");
4223 less_equal(0x6, "be");
4224 greater(0x7, "nbe");
4225 overflow(0x0, "o");
4226 no_overflow(0x1, "no");
4227 %}
4228 %}
4229
4230
4231 // Floating comparisons that can be fixed up with extra conditional jumps
4232 operand cmpOpUCF2() %{
4233 match(Bool);
4234 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4235 n->as_Bool()->_test._test == BoolTest::eq);
4236 format %{ "" %}
4237 interface(COND_INTER) %{
4238 equal(0x4, "e");
4239 not_equal(0x5, "ne");
4240 less(0x2, "b");
4241 greater_equal(0x3, "nb");
4242 less_equal(0x6, "be");
4243 greater(0x7, "nbe");
4244 overflow(0x0, "o");
4245 no_overflow(0x1, "no");
4246 %}
4247 %}
4248
4249 // Operands for bound floating pointer register arguments
4250 operand rxmm0() %{
4251 constraint(ALLOC_IN_RC(xmm0_reg));
4252 match(VecX);
4253 format%{%}
4254 interface(REG_INTER);
4255 %}
4256 operand rxmm1() %{
4257 constraint(ALLOC_IN_RC(xmm1_reg));
4258 match(VecX);
4259 format%{%}
4260 interface(REG_INTER);
4261 %}
4262 operand rxmm2() %{
4263 constraint(ALLOC_IN_RC(xmm2_reg));
4264 match(VecX);
4265 format%{%}
4266 interface(REG_INTER);
4267 %}
4268 operand rxmm3() %{
4269 constraint(ALLOC_IN_RC(xmm3_reg));
4270 match(VecX);
4271 format%{%}
4272 interface(REG_INTER);
4273 %}
4274 operand rxmm4() %{
4275 constraint(ALLOC_IN_RC(xmm4_reg));
4276 match(VecX);
4277 format%{%}
4278 interface(REG_INTER);
4279 %}
4280 operand rxmm5() %{
4281 constraint(ALLOC_IN_RC(xmm5_reg));
4282 match(VecX);
4283 format%{%}
4284 interface(REG_INTER);
4285 %}
4286 operand rxmm6() %{
4287 constraint(ALLOC_IN_RC(xmm6_reg));
4288 match(VecX);
4289 format%{%}
4290 interface(REG_INTER);
4291 %}
4292 operand rxmm7() %{
4293 constraint(ALLOC_IN_RC(xmm7_reg));
4294 match(VecX);
4295 format%{%}
4296 interface(REG_INTER);
4297 %}
4298 operand rxmm8() %{
4299 constraint(ALLOC_IN_RC(xmm8_reg));
4300 match(VecX);
4301 format%{%}
4302 interface(REG_INTER);
4303 %}
4304 operand rxmm9() %{
4305 constraint(ALLOC_IN_RC(xmm9_reg));
4306 match(VecX);
4307 format%{%}
4308 interface(REG_INTER);
4309 %}
4310 operand rxmm10() %{
4311 constraint(ALLOC_IN_RC(xmm10_reg));
4312 match(VecX);
4313 format%{%}
4314 interface(REG_INTER);
4315 %}
4316 operand rxmm11() %{
4317 constraint(ALLOC_IN_RC(xmm11_reg));
4318 match(VecX);
4319 format%{%}
4320 interface(REG_INTER);
4321 %}
4322 operand rxmm12() %{
4323 constraint(ALLOC_IN_RC(xmm12_reg));
4324 match(VecX);
4325 format%{%}
4326 interface(REG_INTER);
4327 %}
4328 operand rxmm13() %{
4329 constraint(ALLOC_IN_RC(xmm13_reg));
4330 match(VecX);
4331 format%{%}
4332 interface(REG_INTER);
4333 %}
4334 operand rxmm14() %{
4335 constraint(ALLOC_IN_RC(xmm14_reg));
4336 match(VecX);
4337 format%{%}
4338 interface(REG_INTER);
4339 %}
4340 operand rxmm15() %{
4341 constraint(ALLOC_IN_RC(xmm15_reg));
4342 match(VecX);
4343 format%{%}
4344 interface(REG_INTER);
4345 %}
4346 operand rxmm16() %{
4347 constraint(ALLOC_IN_RC(xmm16_reg));
4348 match(VecX);
4349 format%{%}
4350 interface(REG_INTER);
4351 %}
4352 operand rxmm17() %{
4353 constraint(ALLOC_IN_RC(xmm17_reg));
4354 match(VecX);
4355 format%{%}
4356 interface(REG_INTER);
4357 %}
4358 operand rxmm18() %{
4359 constraint(ALLOC_IN_RC(xmm18_reg));
4360 match(VecX);
4361 format%{%}
4362 interface(REG_INTER);
4363 %}
4364 operand rxmm19() %{
4365 constraint(ALLOC_IN_RC(xmm19_reg));
4366 match(VecX);
4367 format%{%}
4368 interface(REG_INTER);
4369 %}
4370 operand rxmm20() %{
4371 constraint(ALLOC_IN_RC(xmm20_reg));
4372 match(VecX);
4373 format%{%}
4374 interface(REG_INTER);
4375 %}
4376 operand rxmm21() %{
4377 constraint(ALLOC_IN_RC(xmm21_reg));
4378 match(VecX);
4379 format%{%}
4380 interface(REG_INTER);
4381 %}
4382 operand rxmm22() %{
4383 constraint(ALLOC_IN_RC(xmm22_reg));
4384 match(VecX);
4385 format%{%}
4386 interface(REG_INTER);
4387 %}
4388 operand rxmm23() %{
4389 constraint(ALLOC_IN_RC(xmm23_reg));
4390 match(VecX);
4391 format%{%}
4392 interface(REG_INTER);
4393 %}
4394 operand rxmm24() %{
4395 constraint(ALLOC_IN_RC(xmm24_reg));
4396 match(VecX);
4397 format%{%}
4398 interface(REG_INTER);
4399 %}
4400 operand rxmm25() %{
4401 constraint(ALLOC_IN_RC(xmm25_reg));
4402 match(VecX);
4403 format%{%}
4404 interface(REG_INTER);
4405 %}
4406 operand rxmm26() %{
4407 constraint(ALLOC_IN_RC(xmm26_reg));
4408 match(VecX);
4409 format%{%}
4410 interface(REG_INTER);
4411 %}
4412 operand rxmm27() %{
4413 constraint(ALLOC_IN_RC(xmm27_reg));
4414 match(VecX);
4415 format%{%}
4416 interface(REG_INTER);
4417 %}
4418 operand rxmm28() %{
4419 constraint(ALLOC_IN_RC(xmm28_reg));
4420 match(VecX);
4421 format%{%}
4422 interface(REG_INTER);
4423 %}
4424 operand rxmm29() %{
4425 constraint(ALLOC_IN_RC(xmm29_reg));
4426 match(VecX);
4427 format%{%}
4428 interface(REG_INTER);
4429 %}
4430 operand rxmm30() %{
4431 constraint(ALLOC_IN_RC(xmm30_reg));
4432 match(VecX);
4433 format%{%}
4434 interface(REG_INTER);
4435 %}
4436 operand rxmm31() %{
4437 constraint(ALLOC_IN_RC(xmm31_reg));
4438 match(VecX);
4439 format%{%}
4440 interface(REG_INTER);
4441 %}
4442
4443 //----------OPERAND CLASSES----------------------------------------------------
4444 // Operand Classes are groups of operands that are used as to simplify
4445 // instruction definitions by not requiring the AD writer to specify separate
4446 // instructions for every form of operand when the instruction accepts
4447 // multiple operand types with the same basic encoding and format. The classic
4448 // case of this is memory operands.
4449
4450 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4451 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4452 indCompressedOopOffset,
4453 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4454 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4455 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4456
4457 //----------PIPELINE-----------------------------------------------------------
4458 // Rules which define the behavior of the target architectures pipeline.
4459 pipeline %{
4460
4461 //----------ATTRIBUTES---------------------------------------------------------
4462 attributes %{
4463 variable_size_instructions; // Fixed size instructions
4464 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4465 instruction_unit_size = 1; // An instruction is 1 bytes long
4466 instruction_fetch_unit_size = 16; // The processor fetches one line
4467 instruction_fetch_units = 1; // of 16 bytes
4468
4469 // List of nop instructions
4470 nops( MachNop );
4471 %}
4472
4473 //----------RESOURCES----------------------------------------------------------
4474 // Resources are the functional units available to the machine
4475
4476 // Generic P2/P3 pipeline
4477 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4478 // 3 instructions decoded per cycle.
4479 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4480 // 3 ALU op, only ALU0 handles mul instructions.
4481 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4482 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4483 BR, FPU,
4484 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4485
4486 //----------PIPELINE DESCRIPTION-----------------------------------------------
4487 // Pipeline Description specifies the stages in the machine's pipeline
4488
4489 // Generic P2/P3 pipeline
4490 pipe_desc(S0, S1, S2, S3, S4, S5);
4491
4492 //----------PIPELINE CLASSES---------------------------------------------------
4493 // Pipeline Classes describe the stages in which input and output are
4494 // referenced by the hardware pipeline.
4495
4496 // Naming convention: ialu or fpu
4497 // Then: _reg
4498 // Then: _reg if there is a 2nd register
4499 // Then: _long if it's a pair of instructions implementing a long
4500 // Then: _fat if it requires the big decoder
4501 // Or: _mem if it requires the big decoder and a memory unit.
4502
4503 // Integer ALU reg operation
4504 pipe_class ialu_reg(rRegI dst)
4505 %{
4506 single_instruction;
4507 dst : S4(write);
4508 dst : S3(read);
4509 DECODE : S0; // any decoder
4510 ALU : S3; // any alu
4511 %}
4512
4513 // Long ALU reg operation
4514 pipe_class ialu_reg_long(rRegL dst)
4515 %{
4516 instruction_count(2);
4517 dst : S4(write);
4518 dst : S3(read);
4519 DECODE : S0(2); // any 2 decoders
4520 ALU : S3(2); // both alus
4521 %}
4522
4523 // Integer ALU reg operation using big decoder
4524 pipe_class ialu_reg_fat(rRegI dst)
4525 %{
4526 single_instruction;
4527 dst : S4(write);
4528 dst : S3(read);
4529 D0 : S0; // big decoder only
4530 ALU : S3; // any alu
4531 %}
4532
4533 // Long ALU reg operation using big decoder
4534 pipe_class ialu_reg_long_fat(rRegL dst)
4535 %{
4536 instruction_count(2);
4537 dst : S4(write);
4538 dst : S3(read);
4539 D0 : S0(2); // big decoder only; twice
4540 ALU : S3(2); // any 2 alus
4541 %}
4542
4543 // Integer ALU reg-reg operation
4544 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4545 %{
4546 single_instruction;
4547 dst : S4(write);
4548 src : S3(read);
4549 DECODE : S0; // any decoder
4550 ALU : S3; // any alu
4551 %}
4552
4553 // Long ALU reg-reg operation
4554 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4555 %{
4556 instruction_count(2);
4557 dst : S4(write);
4558 src : S3(read);
4559 DECODE : S0(2); // any 2 decoders
4560 ALU : S3(2); // both alus
4561 %}
4562
4563 // Integer ALU reg-reg operation
4564 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4565 %{
4566 single_instruction;
4567 dst : S4(write);
4568 src : S3(read);
4569 D0 : S0; // big decoder only
4570 ALU : S3; // any alu
4571 %}
4572
4573 // Long ALU reg-reg operation
4574 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4575 %{
4576 instruction_count(2);
4577 dst : S4(write);
4578 src : S3(read);
4579 D0 : S0(2); // big decoder only; twice
4580 ALU : S3(2); // both alus
4581 %}
4582
4583 // Integer ALU reg-mem operation
4584 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4585 %{
4586 single_instruction;
4587 dst : S5(write);
4588 mem : S3(read);
4589 D0 : S0; // big decoder only
4590 ALU : S4; // any alu
4591 MEM : S3; // any mem
4592 %}
4593
4594 // Integer mem operation (prefetch)
4595 pipe_class ialu_mem(memory mem)
4596 %{
4597 single_instruction;
4598 mem : S3(read);
4599 D0 : S0; // big decoder only
4600 MEM : S3; // any mem
4601 %}
4602
4603 // Integer Store to Memory
4604 pipe_class ialu_mem_reg(memory mem, rRegI src)
4605 %{
4606 single_instruction;
4607 mem : S3(read);
4608 src : S5(read);
4609 D0 : S0; // big decoder only
4610 ALU : S4; // any alu
4611 MEM : S3;
4612 %}
4613
4614 // // Long Store to Memory
4615 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4616 // %{
4617 // instruction_count(2);
4618 // mem : S3(read);
4619 // src : S5(read);
4620 // D0 : S0(2); // big decoder only; twice
4621 // ALU : S4(2); // any 2 alus
4622 // MEM : S3(2); // Both mems
4623 // %}
4624
4625 // Integer Store to Memory
4626 pipe_class ialu_mem_imm(memory mem)
4627 %{
4628 single_instruction;
4629 mem : S3(read);
4630 D0 : S0; // big decoder only
4631 ALU : S4; // any alu
4632 MEM : S3;
4633 %}
4634
4635 // Integer ALU0 reg-reg operation
4636 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4637 %{
4638 single_instruction;
4639 dst : S4(write);
4640 src : S3(read);
4641 D0 : S0; // Big decoder only
4642 ALU0 : S3; // only alu0
4643 %}
4644
4645 // Integer ALU0 reg-mem operation
4646 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4647 %{
4648 single_instruction;
4649 dst : S5(write);
4650 mem : S3(read);
4651 D0 : S0; // big decoder only
4652 ALU0 : S4; // ALU0 only
4653 MEM : S3; // any mem
4654 %}
4655
4656 // Integer ALU reg-reg operation
4657 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4658 %{
4659 single_instruction;
4660 cr : S4(write);
4661 src1 : S3(read);
4662 src2 : S3(read);
4663 DECODE : S0; // any decoder
4664 ALU : S3; // any alu
4665 %}
4666
4667 // Integer ALU reg-imm operation
4668 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4669 %{
4670 single_instruction;
4671 cr : S4(write);
4672 src1 : S3(read);
4673 DECODE : S0; // any decoder
4674 ALU : S3; // any alu
4675 %}
4676
4677 // Integer ALU reg-mem operation
4678 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4679 %{
4680 single_instruction;
4681 cr : S4(write);
4682 src1 : S3(read);
4683 src2 : S3(read);
4684 D0 : S0; // big decoder only
4685 ALU : S4; // any alu
4686 MEM : S3;
4687 %}
4688
4689 // Conditional move reg-reg
4690 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4691 %{
4692 instruction_count(4);
4693 y : S4(read);
4694 q : S3(read);
4695 p : S3(read);
4696 DECODE : S0(4); // any decoder
4697 %}
4698
4699 // Conditional move reg-reg
4700 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4701 %{
4702 single_instruction;
4703 dst : S4(write);
4704 src : S3(read);
4705 cr : S3(read);
4706 DECODE : S0; // any decoder
4707 %}
4708
4709 // Conditional move reg-mem
4710 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4711 %{
4712 single_instruction;
4713 dst : S4(write);
4714 src : S3(read);
4715 cr : S3(read);
4716 DECODE : S0; // any decoder
4717 MEM : S3;
4718 %}
4719
4720 // Conditional move reg-reg long
4721 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4722 %{
4723 single_instruction;
4724 dst : S4(write);
4725 src : S3(read);
4726 cr : S3(read);
4727 DECODE : S0(2); // any 2 decoders
4728 %}
4729
4730 // XXX
4731 // // Conditional move double reg-reg
4732 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4733 // %{
4734 // single_instruction;
4735 // dst : S4(write);
4736 // src : S3(read);
4737 // cr : S3(read);
4738 // DECODE : S0; // any decoder
4739 // %}
4740
4741 // Float reg-reg operation
4742 pipe_class fpu_reg(regD dst)
4743 %{
4744 instruction_count(2);
4745 dst : S3(read);
4746 DECODE : S0(2); // any 2 decoders
4747 FPU : S3;
4748 %}
4749
4750 // Float reg-reg operation
4751 pipe_class fpu_reg_reg(regD dst, regD src)
4752 %{
4753 instruction_count(2);
4754 dst : S4(write);
4755 src : S3(read);
4756 DECODE : S0(2); // any 2 decoders
4757 FPU : S3;
4758 %}
4759
4760 // Float reg-reg operation
4761 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4762 %{
4763 instruction_count(3);
4764 dst : S4(write);
4765 src1 : S3(read);
4766 src2 : S3(read);
4767 DECODE : S0(3); // any 3 decoders
4768 FPU : S3(2);
4769 %}
4770
4771 // Float reg-reg operation
4772 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4773 %{
4774 instruction_count(4);
4775 dst : S4(write);
4776 src1 : S3(read);
4777 src2 : S3(read);
4778 src3 : S3(read);
4779 DECODE : S0(4); // any 3 decoders
4780 FPU : S3(2);
4781 %}
4782
4783 // Float reg-reg operation
4784 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4785 %{
4786 instruction_count(4);
4787 dst : S4(write);
4788 src1 : S3(read);
4789 src2 : S3(read);
4790 src3 : S3(read);
4791 DECODE : S1(3); // any 3 decoders
4792 D0 : S0; // Big decoder only
4793 FPU : S3(2);
4794 MEM : S3;
4795 %}
4796
4797 // Float reg-mem operation
4798 pipe_class fpu_reg_mem(regD dst, memory mem)
4799 %{
4800 instruction_count(2);
4801 dst : S5(write);
4802 mem : S3(read);
4803 D0 : S0; // big decoder only
4804 DECODE : S1; // any decoder for FPU POP
4805 FPU : S4;
4806 MEM : S3; // any mem
4807 %}
4808
4809 // Float reg-mem operation
4810 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4811 %{
4812 instruction_count(3);
4813 dst : S5(write);
4814 src1 : S3(read);
4815 mem : S3(read);
4816 D0 : S0; // big decoder only
4817 DECODE : S1(2); // any decoder for FPU POP
4818 FPU : S4;
4819 MEM : S3; // any mem
4820 %}
4821
4822 // Float mem-reg operation
4823 pipe_class fpu_mem_reg(memory mem, regD src)
4824 %{
4825 instruction_count(2);
4826 src : S5(read);
4827 mem : S3(read);
4828 DECODE : S0; // any decoder for FPU PUSH
4829 D0 : S1; // big decoder only
4830 FPU : S4;
4831 MEM : S3; // any mem
4832 %}
4833
4834 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4835 %{
4836 instruction_count(3);
4837 src1 : S3(read);
4838 src2 : S3(read);
4839 mem : S3(read);
4840 DECODE : S0(2); // any decoder for FPU PUSH
4841 D0 : S1; // big decoder only
4842 FPU : S4;
4843 MEM : S3; // any mem
4844 %}
4845
4846 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4847 %{
4848 instruction_count(3);
4849 src1 : S3(read);
4850 src2 : S3(read);
4851 mem : S4(read);
4852 DECODE : S0; // any decoder for FPU PUSH
4853 D0 : S0(2); // big decoder only
4854 FPU : S4;
4855 MEM : S3(2); // any mem
4856 %}
4857
4858 pipe_class fpu_mem_mem(memory dst, memory src1)
4859 %{
4860 instruction_count(2);
4861 src1 : S3(read);
4862 dst : S4(read);
4863 D0 : S0(2); // big decoder only
4864 MEM : S3(2); // any mem
4865 %}
4866
4867 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4868 %{
4869 instruction_count(3);
4870 src1 : S3(read);
4871 src2 : S3(read);
4872 dst : S4(read);
4873 D0 : S0(3); // big decoder only
4874 FPU : S4;
4875 MEM : S3(3); // any mem
4876 %}
4877
4878 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4879 %{
4880 instruction_count(3);
4881 src1 : S4(read);
4882 mem : S4(read);
4883 DECODE : S0; // any decoder for FPU PUSH
4884 D0 : S0(2); // big decoder only
4885 FPU : S4;
4886 MEM : S3(2); // any mem
4887 %}
4888
4889 // Float load constant
4890 pipe_class fpu_reg_con(regD dst)
4891 %{
4892 instruction_count(2);
4893 dst : S5(write);
4894 D0 : S0; // big decoder only for the load
4895 DECODE : S1; // any decoder for FPU POP
4896 FPU : S4;
4897 MEM : S3; // any mem
4898 %}
4899
4900 // Float load constant
4901 pipe_class fpu_reg_reg_con(regD dst, regD src)
4902 %{
4903 instruction_count(3);
4904 dst : S5(write);
4905 src : S3(read);
4906 D0 : S0; // big decoder only for the load
4907 DECODE : S1(2); // any decoder for FPU POP
4908 FPU : S4;
4909 MEM : S3; // any mem
4910 %}
4911
4912 // UnConditional branch
4913 pipe_class pipe_jmp(label labl)
4914 %{
4915 single_instruction;
4916 BR : S3;
4917 %}
4918
4919 // Conditional branch
4920 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4921 %{
4922 single_instruction;
4923 cr : S1(read);
4924 BR : S3;
4925 %}
4926
4927 // Allocation idiom
4928 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4929 %{
4930 instruction_count(1); force_serialization;
4931 fixed_latency(6);
4932 heap_ptr : S3(read);
4933 DECODE : S0(3);
4934 D0 : S2;
4935 MEM : S3;
4936 ALU : S3(2);
4937 dst : S5(write);
4938 BR : S5;
4939 %}
4940
4941 // Generic big/slow expanded idiom
4942 pipe_class pipe_slow()
4943 %{
4944 instruction_count(10); multiple_bundles; force_serialization;
4945 fixed_latency(100);
4946 D0 : S0(2);
4947 MEM : S3(2);
4948 %}
4949
4950 // The real do-nothing guy
4951 pipe_class empty()
4952 %{
4953 instruction_count(0);
4954 %}
4955
4956 // Define the class for the Nop node
4957 define
4958 %{
4959 MachNop = empty;
4960 %}
4961
4962 %}
4963
4964 //----------INSTRUCTIONS-------------------------------------------------------
4965 //
4966 // match -- States which machine-independent subtree may be replaced
4967 // by this instruction.
4968 // ins_cost -- The estimated cost of this instruction is used by instruction
4969 // selection to identify a minimum cost tree of machine
4970 // instructions that matches a tree of machine-independent
4971 // instructions.
4972 // format -- A string providing the disassembly for this instruction.
4973 // The value of an instruction's operand may be inserted
4974 // by referring to it with a '$' prefix.
4975 // opcode -- Three instruction opcodes may be provided. These are referred
4976 // to within an encode class as $primary, $secondary, and $tertiary
4977 // rrspectively. The primary opcode is commonly used to
4978 // indicate the type of machine instruction, while secondary
4979 // and tertiary are often used for prefix options or addressing
4980 // modes.
4981 // ins_encode -- A list of encode classes with parameters. The encode class
4982 // name must have been defined in an 'enc_class' specification
4983 // in the encode section of the architecture description.
4984
4985
4986 //----------Load/Store/Move Instructions---------------------------------------
4987 //----------Load Instructions--------------------------------------------------
4988
4989 // Load Byte (8 bit signed)
4990 instruct loadB(rRegI dst, memory mem)
4991 %{
4992 match(Set dst (LoadB mem));
4993
4994 ins_cost(125);
4995 format %{ "movsbl $dst, $mem\t# byte" %}
4996
4997 ins_encode %{
4998 __ movsbl($dst$$Register, $mem$$Address);
4999 %}
5000
5001 ins_pipe(ialu_reg_mem);
5002 %}
5003
5004 // Load Byte (8 bit signed) into Long Register
5005 instruct loadB2L(rRegL dst, memory mem)
5006 %{
5007 match(Set dst (ConvI2L (LoadB mem)));
5008
5009 ins_cost(125);
5010 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5011
5012 ins_encode %{
5013 __ movsbq($dst$$Register, $mem$$Address);
5014 %}
5015
5016 ins_pipe(ialu_reg_mem);
5017 %}
5018
5019 // Load Unsigned Byte (8 bit UNsigned)
5020 instruct loadUB(rRegI dst, memory mem)
5021 %{
5022 match(Set dst (LoadUB mem));
5023
5024 ins_cost(125);
5025 format %{ "movzbl $dst, $mem\t# ubyte" %}
5026
5027 ins_encode %{
5028 __ movzbl($dst$$Register, $mem$$Address);
5029 %}
5030
5031 ins_pipe(ialu_reg_mem);
5032 %}
5033
5034 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5035 instruct loadUB2L(rRegL dst, memory mem)
5036 %{
5037 match(Set dst (ConvI2L (LoadUB mem)));
5038
5039 ins_cost(125);
5040 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5041
5042 ins_encode %{
5043 __ movzbq($dst$$Register, $mem$$Address);
5044 %}
5045
5046 ins_pipe(ialu_reg_mem);
5047 %}
5048
5049 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5050 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5051 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5052 effect(KILL cr);
5053
5054 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5055 "andl $dst, right_n_bits($mask, 8)" %}
5056 ins_encode %{
5057 Register Rdst = $dst$$Register;
5058 __ movzbq(Rdst, $mem$$Address);
5059 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5060 %}
5061 ins_pipe(ialu_reg_mem);
5062 %}
5063
5064 // Load Short (16 bit signed)
5065 instruct loadS(rRegI dst, memory mem)
5066 %{
5067 match(Set dst (LoadS mem));
5068
5069 ins_cost(125);
5070 format %{ "movswl $dst, $mem\t# short" %}
5071
5072 ins_encode %{
5073 __ movswl($dst$$Register, $mem$$Address);
5074 %}
5075
5076 ins_pipe(ialu_reg_mem);
5077 %}
5078
5079 // Load Short (16 bit signed) to Byte (8 bit signed)
5080 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5081 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5082
5083 ins_cost(125);
5084 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5085 ins_encode %{
5086 __ movsbl($dst$$Register, $mem$$Address);
5087 %}
5088 ins_pipe(ialu_reg_mem);
5089 %}
5090
5091 // Load Short (16 bit signed) into Long Register
5092 instruct loadS2L(rRegL dst, memory mem)
5093 %{
5094 match(Set dst (ConvI2L (LoadS mem)));
5095
5096 ins_cost(125);
5097 format %{ "movswq $dst, $mem\t# short -> long" %}
5098
5099 ins_encode %{
5100 __ movswq($dst$$Register, $mem$$Address);
5101 %}
5102
5103 ins_pipe(ialu_reg_mem);
5104 %}
5105
5106 // Load Unsigned Short/Char (16 bit UNsigned)
5107 instruct loadUS(rRegI dst, memory mem)
5108 %{
5109 match(Set dst (LoadUS mem));
5110
5111 ins_cost(125);
5112 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5113
5114 ins_encode %{
5115 __ movzwl($dst$$Register, $mem$$Address);
5116 %}
5117
5118 ins_pipe(ialu_reg_mem);
5119 %}
5120
5121 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5122 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5123 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5124
5125 ins_cost(125);
5126 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5127 ins_encode %{
5128 __ movsbl($dst$$Register, $mem$$Address);
5129 %}
5130 ins_pipe(ialu_reg_mem);
5131 %}
5132
5133 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5134 instruct loadUS2L(rRegL dst, memory mem)
5135 %{
5136 match(Set dst (ConvI2L (LoadUS mem)));
5137
5138 ins_cost(125);
5139 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5140
5141 ins_encode %{
5142 __ movzwq($dst$$Register, $mem$$Address);
5143 %}
5144
5145 ins_pipe(ialu_reg_mem);
5146 %}
5147
5148 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5149 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5150 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5151
5152 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5153 ins_encode %{
5154 __ movzbq($dst$$Register, $mem$$Address);
5155 %}
5156 ins_pipe(ialu_reg_mem);
5157 %}
5158
5159 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5160 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5161 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5162 effect(KILL cr);
5163
5164 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5165 "andl $dst, right_n_bits($mask, 16)" %}
5166 ins_encode %{
5167 Register Rdst = $dst$$Register;
5168 __ movzwq(Rdst, $mem$$Address);
5169 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5170 %}
5171 ins_pipe(ialu_reg_mem);
5172 %}
5173
5174 // Load Integer
5175 instruct loadI(rRegI dst, memory mem)
5176 %{
5177 match(Set dst (LoadI mem));
5178
5179 ins_cost(125);
5180 format %{ "movl $dst, $mem\t# int" %}
5181
5182 ins_encode %{
5183 __ movl($dst$$Register, $mem$$Address);
5184 %}
5185
5186 ins_pipe(ialu_reg_mem);
5187 %}
5188
5189 // Load Integer (32 bit signed) to Byte (8 bit signed)
5190 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5191 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5192
5193 ins_cost(125);
5194 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5195 ins_encode %{
5196 __ movsbl($dst$$Register, $mem$$Address);
5197 %}
5198 ins_pipe(ialu_reg_mem);
5199 %}
5200
5201 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5202 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5203 match(Set dst (AndI (LoadI mem) mask));
5204
5205 ins_cost(125);
5206 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5207 ins_encode %{
5208 __ movzbl($dst$$Register, $mem$$Address);
5209 %}
5210 ins_pipe(ialu_reg_mem);
5211 %}
5212
5213 // Load Integer (32 bit signed) to Short (16 bit signed)
5214 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5215 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5216
5217 ins_cost(125);
5218 format %{ "movswl $dst, $mem\t# int -> short" %}
5219 ins_encode %{
5220 __ movswl($dst$$Register, $mem$$Address);
5221 %}
5222 ins_pipe(ialu_reg_mem);
5223 %}
5224
5225 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5226 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5227 match(Set dst (AndI (LoadI mem) mask));
5228
5229 ins_cost(125);
5230 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5231 ins_encode %{
5232 __ movzwl($dst$$Register, $mem$$Address);
5233 %}
5234 ins_pipe(ialu_reg_mem);
5235 %}
5236
5237 // Load Integer into Long Register
5238 instruct loadI2L(rRegL dst, memory mem)
5239 %{
5240 match(Set dst (ConvI2L (LoadI mem)));
5241
5242 ins_cost(125);
5243 format %{ "movslq $dst, $mem\t# int -> long" %}
5244
5245 ins_encode %{
5246 __ movslq($dst$$Register, $mem$$Address);
5247 %}
5248
5249 ins_pipe(ialu_reg_mem);
5250 %}
5251
5252 // Load Integer with mask 0xFF into Long Register
5253 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5254 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5255
5256 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5257 ins_encode %{
5258 __ movzbq($dst$$Register, $mem$$Address);
5259 %}
5260 ins_pipe(ialu_reg_mem);
5261 %}
5262
5263 // Load Integer with mask 0xFFFF into Long Register
5264 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5265 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5266
5267 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5268 ins_encode %{
5269 __ movzwq($dst$$Register, $mem$$Address);
5270 %}
5271 ins_pipe(ialu_reg_mem);
5272 %}
5273
5274 // Load Integer with a 31-bit mask into Long Register
5275 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5276 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5277 effect(KILL cr);
5278
5279 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5280 "andl $dst, $mask" %}
5281 ins_encode %{
5282 Register Rdst = $dst$$Register;
5283 __ movl(Rdst, $mem$$Address);
5284 __ andl(Rdst, $mask$$constant);
5285 %}
5286 ins_pipe(ialu_reg_mem);
5287 %}
5288
5289 // Load Unsigned Integer into Long Register
5290 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5291 %{
5292 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5293
5294 ins_cost(125);
5295 format %{ "movl $dst, $mem\t# uint -> long" %}
5296
5297 ins_encode %{
5298 __ movl($dst$$Register, $mem$$Address);
5299 %}
5300
5301 ins_pipe(ialu_reg_mem);
5302 %}
5303
5304 // Load Long
5305 instruct loadL(rRegL dst, memory mem)
5306 %{
5307 match(Set dst (LoadL mem));
5308
5309 ins_cost(125);
5310 format %{ "movq $dst, $mem\t# long" %}
5311
5312 ins_encode %{
5313 __ movq($dst$$Register, $mem$$Address);
5314 %}
5315
5316 ins_pipe(ialu_reg_mem); // XXX
5317 %}
5318
5319 // Load Range
5320 instruct loadRange(rRegI dst, memory mem)
5321 %{
5322 match(Set dst (LoadRange mem));
5323
5324 ins_cost(125); // XXX
5325 format %{ "movl $dst, $mem\t# range" %}
5326 opcode(0x8B);
5327 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5328 ins_pipe(ialu_reg_mem);
5329 %}
5330
5331 // Load Pointer
5332 instruct loadP(rRegP dst, memory mem)
5333 %{
5334 match(Set dst (LoadP mem));
5335
5336 ins_cost(125); // XXX
5337 format %{ "movq $dst, $mem\t# ptr" %}
5338 opcode(0x8B);
5339 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5340 ins_pipe(ialu_reg_mem); // XXX
5341 %}
5342
5343 // Load Compressed Pointer
5344 instruct loadN(rRegN dst, memory mem)
5345 %{
5346 match(Set dst (LoadN mem));
5347
5348 ins_cost(125); // XXX
5349 format %{ "movl $dst, $mem\t# compressed ptr" %}
5350 ins_encode %{
5351 __ movl($dst$$Register, $mem$$Address);
5352 %}
5353 ins_pipe(ialu_reg_mem); // XXX
5354 %}
5355
5356
5357 // Load Klass Pointer
5358 instruct loadKlass(rRegP dst, memory mem)
5359 %{
5360 match(Set dst (LoadKlass mem));
5361
5362 ins_cost(125); // XXX
5363 format %{ "movq $dst, $mem\t# class" %}
5364 opcode(0x8B);
5365 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5366 ins_pipe(ialu_reg_mem); // XXX
5367 %}
5368
5369 // Load narrow Klass Pointer
5370 instruct loadNKlass(rRegN dst, memory mem)
5371 %{
5372 match(Set dst (LoadNKlass mem));
5373
5374 ins_cost(125); // XXX
5375 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5376 ins_encode %{
5377 __ movl($dst$$Register, $mem$$Address);
5378 %}
5379 ins_pipe(ialu_reg_mem); // XXX
5380 %}
5381
5382 // Load Float
5383 instruct loadF(regF dst, memory mem)
5384 %{
5385 match(Set dst (LoadF mem));
5386
5387 ins_cost(145); // XXX
5388 format %{ "movss $dst, $mem\t# float" %}
5389 ins_encode %{
5390 __ movflt($dst$$XMMRegister, $mem$$Address);
5391 %}
5392 ins_pipe(pipe_slow); // XXX
5393 %}
5394
5395 // Load Float
5396 instruct MoveF2VL(vlRegF dst, regF src) %{
5397 match(Set dst src);
5398 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5399 ins_encode %{
5400 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5401 %}
5402 ins_pipe( fpu_reg_reg );
5403 %}
5404
5405 // Load Float
5406 instruct MoveF2LEG(legRegF dst, regF src) %{
5407 match(Set dst src);
5408 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5409 ins_encode %{
5410 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5411 %}
5412 ins_pipe( fpu_reg_reg );
5413 %}
5414
5415 // Load Float
5416 instruct MoveVL2F(regF dst, vlRegF src) %{
5417 match(Set dst src);
5418 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5419 ins_encode %{
5420 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5421 %}
5422 ins_pipe( fpu_reg_reg );
5423 %}
5424
5425 // Load Float
5426 instruct MoveLEG2F(regF dst, legRegF src) %{
5427 match(Set dst src);
5428 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5429 ins_encode %{
5430 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5431 %}
5432 ins_pipe( fpu_reg_reg );
5433 %}
5434
5435 // Load Double
5436 instruct loadD_partial(regD dst, memory mem)
5437 %{
5438 predicate(!UseXmmLoadAndClearUpper);
5439 match(Set dst (LoadD mem));
5440
5441 ins_cost(145); // XXX
5442 format %{ "movlpd $dst, $mem\t# double" %}
5443 ins_encode %{
5444 __ movdbl($dst$$XMMRegister, $mem$$Address);
5445 %}
5446 ins_pipe(pipe_slow); // XXX
5447 %}
5448
5449 instruct loadD(regD dst, memory mem)
5450 %{
5451 predicate(UseXmmLoadAndClearUpper);
5452 match(Set dst (LoadD mem));
5453
5454 ins_cost(145); // XXX
5455 format %{ "movsd $dst, $mem\t# double" %}
5456 ins_encode %{
5457 __ movdbl($dst$$XMMRegister, $mem$$Address);
5458 %}
5459 ins_pipe(pipe_slow); // XXX
5460 %}
5461
5462 // Load Double
5463 instruct MoveD2VL(vlRegD dst, regD src) %{
5464 match(Set dst src);
5465 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5466 ins_encode %{
5467 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5468 %}
5469 ins_pipe( fpu_reg_reg );
5470 %}
5471
5472 // Load Double
5473 instruct MoveD2LEG(legRegD dst, regD src) %{
5474 match(Set dst src);
5475 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5476 ins_encode %{
5477 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5478 %}
5479 ins_pipe( fpu_reg_reg );
5480 %}
5481
5482 // Load Double
5483 instruct MoveVL2D(regD dst, vlRegD src) %{
5484 match(Set dst src);
5485 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5486 ins_encode %{
5487 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5488 %}
5489 ins_pipe( fpu_reg_reg );
5490 %}
5491
5492 // Load Double
5493 instruct MoveLEG2D(regD dst, legRegD src) %{
5494 match(Set dst src);
5495 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5496 ins_encode %{
5497 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5498 %}
5499 ins_pipe( fpu_reg_reg );
5500 %}
5501
5502 // Following pseudo code describes the algorithm for max[FD]:
5503 // Min algorithm is on similar lines
5504 // btmp = (b < +0.0) ? a : b
5505 // atmp = (b < +0.0) ? b : a
5506 // Tmp = Max_Float(atmp , btmp)
5507 // Res = (atmp == NaN) ? atmp : Tmp
5508
5509 // max = java.lang.Math.max(float a, float b)
5510 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5511 predicate(UseAVX > 0 && !n->is_reduction());
5512 match(Set dst (MaxF a b));
5513 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5514 format %{
5515 "blendvps $btmp,$b,$a,$b \n\t"
5516 "blendvps $atmp,$a,$b,$b \n\t"
5517 "vmaxss $tmp,$atmp,$btmp \n\t"
5518 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5519 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5520 %}
5521 ins_encode %{
5522 int vector_len = Assembler::AVX_128bit;
5523 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5524 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5525 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5526 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5527 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5528 %}
5529 ins_pipe( pipe_slow );
5530 %}
5531
5532 instruct maxF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5533 predicate(UseAVX > 0 && n->is_reduction());
5534 match(Set dst (MaxF a b));
5535 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5536
5537 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5538 ins_encode %{
5539 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5540 false /*min*/, true /*single*/);
5541 %}
5542 ins_pipe( pipe_slow );
5543 %}
5544
5545 // max = java.lang.Math.max(double a, double b)
5546 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5547 predicate(UseAVX > 0 && !n->is_reduction());
5548 match(Set dst (MaxD a b));
5549 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5550 format %{
5551 "blendvpd $btmp,$b,$a,$b \n\t"
5552 "blendvpd $atmp,$a,$b,$b \n\t"
5553 "vmaxsd $tmp,$atmp,$btmp \n\t"
5554 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5555 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5556 %}
5557 ins_encode %{
5558 int vector_len = Assembler::AVX_128bit;
5559 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5560 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5561 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5562 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5563 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5564 %}
5565 ins_pipe( pipe_slow );
5566 %}
5567
5568 instruct maxD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5569 predicate(UseAVX > 0 && n->is_reduction());
5570 match(Set dst (MaxD a b));
5571 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5572
5573 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5574 ins_encode %{
5575 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5576 false /*min*/, false /*single*/);
5577 %}
5578 ins_pipe( pipe_slow );
5579 %}
5580
5581 // min = java.lang.Math.min(float a, float b)
5582 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5583 predicate(UseAVX > 0 && !n->is_reduction());
5584 match(Set dst (MinF a b));
5585 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5586 format %{
5587 "blendvps $atmp,$a,$b,$a \n\t"
5588 "blendvps $btmp,$b,$a,$a \n\t"
5589 "vminss $tmp,$atmp,$btmp \n\t"
5590 "cmpps.unordered $btmp,$atmp,$atmp \n\t"
5591 "blendvps $dst,$tmp,$atmp,$btmp \n\t"
5592 %}
5593 ins_encode %{
5594 int vector_len = Assembler::AVX_128bit;
5595 __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5596 __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5597 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5598 __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5599 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5600 %}
5601 ins_pipe( pipe_slow );
5602 %}
5603
5604 instruct minF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
5605 predicate(UseAVX > 0 && n->is_reduction());
5606 match(Set dst (MinF a b));
5607 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5608
5609 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5610 ins_encode %{
5611 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5612 true /*min*/, true /*single*/);
5613 %}
5614 ins_pipe( pipe_slow );
5615 %}
5616
5617 // min = java.lang.Math.min(double a, double b)
5618 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5619 predicate(UseAVX > 0 && !n->is_reduction());
5620 match(Set dst (MinD a b));
5621 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5622 format %{
5623 "blendvpd $atmp,$a,$b,$a \n\t"
5624 "blendvpd $btmp,$b,$a,$a \n\t"
5625 "vminsd $tmp,$atmp,$btmp \n\t"
5626 "cmppd.unordered $btmp,$atmp,$atmp \n\t"
5627 "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
5628 %}
5629 ins_encode %{
5630 int vector_len = Assembler::AVX_128bit;
5631 __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5632 __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5633 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5634 __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5635 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5636 %}
5637 ins_pipe( pipe_slow );
5638 %}
5639
5640 instruct minD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
5641 predicate(UseAVX > 0 && n->is_reduction());
5642 match(Set dst (MinD a b));
5643 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5644
5645 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5646 ins_encode %{
5647 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5648 true /*min*/, false /*single*/);
5649 %}
5650 ins_pipe( pipe_slow );
5651 %}
5652
5653 // Load Effective Address
5654 instruct leaP8(rRegP dst, indOffset8 mem)
5655 %{
5656 match(Set dst mem);
5657
5658 ins_cost(110); // XXX
5659 format %{ "leaq $dst, $mem\t# ptr 8" %}
5660 opcode(0x8D);
5661 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5662 ins_pipe(ialu_reg_reg_fat);
5663 %}
5664
5665 instruct leaP32(rRegP dst, indOffset32 mem)
5666 %{
5667 match(Set dst mem);
5668
5669 ins_cost(110);
5670 format %{ "leaq $dst, $mem\t# ptr 32" %}
5671 opcode(0x8D);
5672 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5673 ins_pipe(ialu_reg_reg_fat);
5674 %}
5675
5676 // instruct leaPIdx(rRegP dst, indIndex mem)
5677 // %{
5678 // match(Set dst mem);
5679
5680 // ins_cost(110);
5681 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5682 // opcode(0x8D);
5683 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5684 // ins_pipe(ialu_reg_reg_fat);
5685 // %}
5686
5687 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5688 %{
5689 match(Set dst mem);
5690
5691 ins_cost(110);
5692 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5693 opcode(0x8D);
5694 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5695 ins_pipe(ialu_reg_reg_fat);
5696 %}
5697
5698 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5699 %{
5700 match(Set dst mem);
5701
5702 ins_cost(110);
5703 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5704 opcode(0x8D);
5705 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5706 ins_pipe(ialu_reg_reg_fat);
5707 %}
5708
5709 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5710 %{
5711 match(Set dst mem);
5712
5713 ins_cost(110);
5714 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5715 opcode(0x8D);
5716 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5717 ins_pipe(ialu_reg_reg_fat);
5718 %}
5719
5720 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5721 %{
5722 match(Set dst mem);
5723
5724 ins_cost(110);
5725 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5726 opcode(0x8D);
5727 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5728 ins_pipe(ialu_reg_reg_fat);
5729 %}
5730
5731 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5732 %{
5733 match(Set dst mem);
5734
5735 ins_cost(110);
5736 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5737 opcode(0x8D);
5738 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5739 ins_pipe(ialu_reg_reg_fat);
5740 %}
5741
5742 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5743 %{
5744 match(Set dst mem);
5745
5746 ins_cost(110);
5747 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5748 opcode(0x8D);
5749 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5750 ins_pipe(ialu_reg_reg_fat);
5751 %}
5752
5753 // Load Effective Address which uses Narrow (32-bits) oop
5754 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5755 %{
5756 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5757 match(Set dst mem);
5758
5759 ins_cost(110);
5760 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5761 opcode(0x8D);
5762 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5763 ins_pipe(ialu_reg_reg_fat);
5764 %}
5765
5766 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5767 %{
5768 predicate(Universe::narrow_oop_shift() == 0);
5769 match(Set dst mem);
5770
5771 ins_cost(110); // XXX
5772 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5773 opcode(0x8D);
5774 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5775 ins_pipe(ialu_reg_reg_fat);
5776 %}
5777
5778 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5779 %{
5780 predicate(Universe::narrow_oop_shift() == 0);
5781 match(Set dst mem);
5782
5783 ins_cost(110);
5784 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5785 opcode(0x8D);
5786 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5787 ins_pipe(ialu_reg_reg_fat);
5788 %}
5789
5790 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5791 %{
5792 predicate(Universe::narrow_oop_shift() == 0);
5793 match(Set dst mem);
5794
5795 ins_cost(110);
5796 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5797 opcode(0x8D);
5798 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5799 ins_pipe(ialu_reg_reg_fat);
5800 %}
5801
5802 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5803 %{
5804 predicate(Universe::narrow_oop_shift() == 0);
5805 match(Set dst mem);
5806
5807 ins_cost(110);
5808 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5809 opcode(0x8D);
5810 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5811 ins_pipe(ialu_reg_reg_fat);
5812 %}
5813
5814 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5815 %{
5816 predicate(Universe::narrow_oop_shift() == 0);
5817 match(Set dst mem);
5818
5819 ins_cost(110);
5820 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5821 opcode(0x8D);
5822 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5823 ins_pipe(ialu_reg_reg_fat);
5824 %}
5825
5826 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5827 %{
5828 predicate(Universe::narrow_oop_shift() == 0);
5829 match(Set dst mem);
5830
5831 ins_cost(110);
5832 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5833 opcode(0x8D);
5834 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5835 ins_pipe(ialu_reg_reg_fat);
5836 %}
5837
5838 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5839 %{
5840 predicate(Universe::narrow_oop_shift() == 0);
5841 match(Set dst mem);
5842
5843 ins_cost(110);
5844 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5845 opcode(0x8D);
5846 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5847 ins_pipe(ialu_reg_reg_fat);
5848 %}
5849
5850 instruct loadConI(rRegI dst, immI src)
5851 %{
5852 match(Set dst src);
5853
5854 format %{ "movl $dst, $src\t# int" %}
5855 ins_encode(load_immI(dst, src));
5856 ins_pipe(ialu_reg_fat); // XXX
5857 %}
5858
5859 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5860 %{
5861 match(Set dst src);
5862 effect(KILL cr);
5863
5864 ins_cost(50);
5865 format %{ "xorl $dst, $dst\t# int" %}
5866 opcode(0x33); /* + rd */
5867 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5868 ins_pipe(ialu_reg);
5869 %}
5870
5871 instruct loadConL(rRegL dst, immL src)
5872 %{
5873 match(Set dst src);
5874
5875 ins_cost(150);
5876 format %{ "movq $dst, $src\t# long" %}
5877 ins_encode(load_immL(dst, src));
5878 ins_pipe(ialu_reg);
5879 %}
5880
5881 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5882 %{
5883 match(Set dst src);
5884 effect(KILL cr);
5885
5886 ins_cost(50);
5887 format %{ "xorl $dst, $dst\t# long" %}
5888 opcode(0x33); /* + rd */
5889 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5890 ins_pipe(ialu_reg); // XXX
5891 %}
5892
5893 instruct loadConUL32(rRegL dst, immUL32 src)
5894 %{
5895 match(Set dst src);
5896
5897 ins_cost(60);
5898 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5899 ins_encode(load_immUL32(dst, src));
5900 ins_pipe(ialu_reg);
5901 %}
5902
5903 instruct loadConL32(rRegL dst, immL32 src)
5904 %{
5905 match(Set dst src);
5906
5907 ins_cost(70);
5908 format %{ "movq $dst, $src\t# long (32-bit)" %}
5909 ins_encode(load_immL32(dst, src));
5910 ins_pipe(ialu_reg);
5911 %}
5912
5913 instruct loadConP(rRegP dst, immP con) %{
5914 match(Set dst con);
5915
5916 format %{ "movq $dst, $con\t# ptr" %}
5917 ins_encode(load_immP(dst, con));
5918 ins_pipe(ialu_reg_fat); // XXX
5919 %}
5920
5921 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5922 %{
5923 match(Set dst src);
5924 effect(KILL cr);
5925
5926 ins_cost(50);
5927 format %{ "xorl $dst, $dst\t# ptr" %}
5928 opcode(0x33); /* + rd */
5929 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5930 ins_pipe(ialu_reg);
5931 %}
5932
5933 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5934 %{
5935 match(Set dst src);
5936 effect(KILL cr);
5937
5938 ins_cost(60);
5939 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5940 ins_encode(load_immP31(dst, src));
5941 ins_pipe(ialu_reg);
5942 %}
5943
5944 instruct loadConF(regF dst, immF con) %{
5945 match(Set dst con);
5946 ins_cost(125);
5947 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5948 ins_encode %{
5949 __ movflt($dst$$XMMRegister, $constantaddress($con));
5950 %}
5951 ins_pipe(pipe_slow);
5952 %}
5953
5954 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5955 match(Set dst src);
5956 effect(KILL cr);
5957 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5958 ins_encode %{
5959 __ xorq($dst$$Register, $dst$$Register);
5960 %}
5961 ins_pipe(ialu_reg);
5962 %}
5963
5964 instruct loadConN(rRegN dst, immN src) %{
5965 match(Set dst src);
5966
5967 ins_cost(125);
5968 format %{ "movl $dst, $src\t# compressed ptr" %}
5969 ins_encode %{
5970 address con = (address)$src$$constant;
5971 if (con == NULL) {
5972 ShouldNotReachHere();
5973 } else {
5974 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5975 }
5976 %}
5977 ins_pipe(ialu_reg_fat); // XXX
5978 %}
5979
5980 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5981 match(Set dst src);
5982
5983 ins_cost(125);
5984 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5985 ins_encode %{
5986 address con = (address)$src$$constant;
5987 if (con == NULL) {
5988 ShouldNotReachHere();
5989 } else {
5990 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5991 }
5992 %}
5993 ins_pipe(ialu_reg_fat); // XXX
5994 %}
5995
5996 instruct loadConF0(regF dst, immF0 src)
5997 %{
5998 match(Set dst src);
5999 ins_cost(100);
6000
6001 format %{ "xorps $dst, $dst\t# float 0.0" %}
6002 ins_encode %{
6003 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6004 %}
6005 ins_pipe(pipe_slow);
6006 %}
6007
6008 // Use the same format since predicate() can not be used here.
6009 instruct loadConD(regD dst, immD con) %{
6010 match(Set dst con);
6011 ins_cost(125);
6012 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
6013 ins_encode %{
6014 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6015 %}
6016 ins_pipe(pipe_slow);
6017 %}
6018
6019 instruct loadConD0(regD dst, immD0 src)
6020 %{
6021 match(Set dst src);
6022 ins_cost(100);
6023
6024 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6025 ins_encode %{
6026 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6027 %}
6028 ins_pipe(pipe_slow);
6029 %}
6030
6031 instruct loadSSI(rRegI dst, stackSlotI src)
6032 %{
6033 match(Set dst src);
6034
6035 ins_cost(125);
6036 format %{ "movl $dst, $src\t# int stk" %}
6037 opcode(0x8B);
6038 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6039 ins_pipe(ialu_reg_mem);
6040 %}
6041
6042 instruct loadSSL(rRegL dst, stackSlotL src)
6043 %{
6044 match(Set dst src);
6045
6046 ins_cost(125);
6047 format %{ "movq $dst, $src\t# long stk" %}
6048 opcode(0x8B);
6049 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6050 ins_pipe(ialu_reg_mem);
6051 %}
6052
6053 instruct loadSSP(rRegP dst, stackSlotP src)
6054 %{
6055 match(Set dst src);
6056
6057 ins_cost(125);
6058 format %{ "movq $dst, $src\t# ptr stk" %}
6059 opcode(0x8B);
6060 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6061 ins_pipe(ialu_reg_mem);
6062 %}
6063
6064 instruct loadSSF(regF dst, stackSlotF src)
6065 %{
6066 match(Set dst src);
6067
6068 ins_cost(125);
6069 format %{ "movss $dst, $src\t# float stk" %}
6070 ins_encode %{
6071 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
6072 %}
6073 ins_pipe(pipe_slow); // XXX
6074 %}
6075
6076 // Use the same format since predicate() can not be used here.
6077 instruct loadSSD(regD dst, stackSlotD src)
6078 %{
6079 match(Set dst src);
6080
6081 ins_cost(125);
6082 format %{ "movsd $dst, $src\t# double stk" %}
6083 ins_encode %{
6084 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6085 %}
6086 ins_pipe(pipe_slow); // XXX
6087 %}
6088
6089 // Prefetch instructions for allocation.
6090 // Must be safe to execute with invalid address (cannot fault).
6091
6092 instruct prefetchAlloc( memory mem ) %{
6093 predicate(AllocatePrefetchInstr==3);
6094 match(PrefetchAllocation mem);
6095 ins_cost(125);
6096
6097 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6098 ins_encode %{
6099 __ prefetchw($mem$$Address);
6100 %}
6101 ins_pipe(ialu_mem);
6102 %}
6103
6104 instruct prefetchAllocNTA( memory mem ) %{
6105 predicate(AllocatePrefetchInstr==0);
6106 match(PrefetchAllocation mem);
6107 ins_cost(125);
6108
6109 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6110 ins_encode %{
6111 __ prefetchnta($mem$$Address);
6112 %}
6113 ins_pipe(ialu_mem);
6114 %}
6115
6116 instruct prefetchAllocT0( memory mem ) %{
6117 predicate(AllocatePrefetchInstr==1);
6118 match(PrefetchAllocation mem);
6119 ins_cost(125);
6120
6121 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6122 ins_encode %{
6123 __ prefetcht0($mem$$Address);
6124 %}
6125 ins_pipe(ialu_mem);
6126 %}
6127
6128 instruct prefetchAllocT2( memory mem ) %{
6129 predicate(AllocatePrefetchInstr==2);
6130 match(PrefetchAllocation mem);
6131 ins_cost(125);
6132
6133 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6134 ins_encode %{
6135 __ prefetcht2($mem$$Address);
6136 %}
6137 ins_pipe(ialu_mem);
6138 %}
6139
6140 //----------Store Instructions-------------------------------------------------
6141
6142 // Store Byte
6143 instruct storeB(memory mem, rRegI src)
6144 %{
6145 match(Set mem (StoreB mem src));
6146
6147 ins_cost(125); // XXX
6148 format %{ "movb $mem, $src\t# byte" %}
6149 opcode(0x88);
6150 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6151 ins_pipe(ialu_mem_reg);
6152 %}
6153
6154 // Store Char/Short
6155 instruct storeC(memory mem, rRegI src)
6156 %{
6157 match(Set mem (StoreC mem src));
6158
6159 ins_cost(125); // XXX
6160 format %{ "movw $mem, $src\t# char/short" %}
6161 opcode(0x89);
6162 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6163 ins_pipe(ialu_mem_reg);
6164 %}
6165
6166 // Store Integer
6167 instruct storeI(memory mem, rRegI src)
6168 %{
6169 match(Set mem (StoreI mem src));
6170
6171 ins_cost(125); // XXX
6172 format %{ "movl $mem, $src\t# int" %}
6173 opcode(0x89);
6174 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6175 ins_pipe(ialu_mem_reg);
6176 %}
6177
6178 // Store Long
6179 instruct storeL(memory mem, rRegL src)
6180 %{
6181 match(Set mem (StoreL mem src));
6182
6183 ins_cost(125); // XXX
6184 format %{ "movq $mem, $src\t# long" %}
6185 opcode(0x89);
6186 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6187 ins_pipe(ialu_mem_reg); // XXX
6188 %}
6189
6190 // Store Pointer
6191 instruct storeP(memory mem, any_RegP src)
6192 %{
6193 match(Set mem (StoreP mem src));
6194
6195 ins_cost(125); // XXX
6196 format %{ "movq $mem, $src\t# ptr" %}
6197 opcode(0x89);
6198 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6199 ins_pipe(ialu_mem_reg);
6200 %}
6201
6202 instruct storeImmP0(memory mem, immP0 zero)
6203 %{
6204 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6205 match(Set mem (StoreP mem zero));
6206
6207 ins_cost(125); // XXX
6208 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6209 ins_encode %{
6210 __ movq($mem$$Address, r12);
6211 %}
6212 ins_pipe(ialu_mem_reg);
6213 %}
6214
6215 // Store NULL Pointer, mark word, or other simple pointer constant.
6216 instruct storeImmP(memory mem, immP31 src)
6217 %{
6218 match(Set mem (StoreP mem src));
6219
6220 ins_cost(150); // XXX
6221 format %{ "movq $mem, $src\t# ptr" %}
6222 opcode(0xC7); /* C7 /0 */
6223 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6224 ins_pipe(ialu_mem_imm);
6225 %}
6226
6227 // Store Compressed Pointer
6228 instruct storeN(memory mem, rRegN src)
6229 %{
6230 match(Set mem (StoreN mem src));
6231
6232 ins_cost(125); // XXX
6233 format %{ "movl $mem, $src\t# compressed ptr" %}
6234 ins_encode %{
6235 __ movl($mem$$Address, $src$$Register);
6236 %}
6237 ins_pipe(ialu_mem_reg);
6238 %}
6239
6240 instruct storeNKlass(memory mem, rRegN src)
6241 %{
6242 match(Set mem (StoreNKlass mem src));
6243
6244 ins_cost(125); // XXX
6245 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6246 ins_encode %{
6247 __ movl($mem$$Address, $src$$Register);
6248 %}
6249 ins_pipe(ialu_mem_reg);
6250 %}
6251
6252 instruct storeImmN0(memory mem, immN0 zero)
6253 %{
6254 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6255 match(Set mem (StoreN mem zero));
6256
6257 ins_cost(125); // XXX
6258 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6259 ins_encode %{
6260 __ movl($mem$$Address, r12);
6261 %}
6262 ins_pipe(ialu_mem_reg);
6263 %}
6264
6265 instruct storeImmN(memory mem, immN src)
6266 %{
6267 match(Set mem (StoreN mem src));
6268
6269 ins_cost(150); // XXX
6270 format %{ "movl $mem, $src\t# compressed ptr" %}
6271 ins_encode %{
6272 address con = (address)$src$$constant;
6273 if (con == NULL) {
6274 __ movl($mem$$Address, (int32_t)0);
6275 } else {
6276 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6277 }
6278 %}
6279 ins_pipe(ialu_mem_imm);
6280 %}
6281
6282 instruct storeImmNKlass(memory mem, immNKlass src)
6283 %{
6284 match(Set mem (StoreNKlass mem src));
6285
6286 ins_cost(150); // XXX
6287 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6288 ins_encode %{
6289 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6290 %}
6291 ins_pipe(ialu_mem_imm);
6292 %}
6293
6294 // Store Integer Immediate
6295 instruct storeImmI0(memory mem, immI0 zero)
6296 %{
6297 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6298 match(Set mem (StoreI mem zero));
6299
6300 ins_cost(125); // XXX
6301 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6302 ins_encode %{
6303 __ movl($mem$$Address, r12);
6304 %}
6305 ins_pipe(ialu_mem_reg);
6306 %}
6307
6308 instruct storeImmI(memory mem, immI src)
6309 %{
6310 match(Set mem (StoreI mem src));
6311
6312 ins_cost(150);
6313 format %{ "movl $mem, $src\t# int" %}
6314 opcode(0xC7); /* C7 /0 */
6315 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6316 ins_pipe(ialu_mem_imm);
6317 %}
6318
6319 // Store Long Immediate
6320 instruct storeImmL0(memory mem, immL0 zero)
6321 %{
6322 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6323 match(Set mem (StoreL mem zero));
6324
6325 ins_cost(125); // XXX
6326 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6327 ins_encode %{
6328 __ movq($mem$$Address, r12);
6329 %}
6330 ins_pipe(ialu_mem_reg);
6331 %}
6332
6333 instruct storeImmL(memory mem, immL32 src)
6334 %{
6335 match(Set mem (StoreL mem src));
6336
6337 ins_cost(150);
6338 format %{ "movq $mem, $src\t# long" %}
6339 opcode(0xC7); /* C7 /0 */
6340 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6341 ins_pipe(ialu_mem_imm);
6342 %}
6343
6344 // Store Short/Char Immediate
6345 instruct storeImmC0(memory mem, immI0 zero)
6346 %{
6347 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6348 match(Set mem (StoreC mem zero));
6349
6350 ins_cost(125); // XXX
6351 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6352 ins_encode %{
6353 __ movw($mem$$Address, r12);
6354 %}
6355 ins_pipe(ialu_mem_reg);
6356 %}
6357
6358 instruct storeImmI16(memory mem, immI16 src)
6359 %{
6360 predicate(UseStoreImmI16);
6361 match(Set mem (StoreC mem src));
6362
6363 ins_cost(150);
6364 format %{ "movw $mem, $src\t# short/char" %}
6365 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6366 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6367 ins_pipe(ialu_mem_imm);
6368 %}
6369
6370 // Store Byte Immediate
6371 instruct storeImmB0(memory mem, immI0 zero)
6372 %{
6373 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6374 match(Set mem (StoreB mem zero));
6375
6376 ins_cost(125); // XXX
6377 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6378 ins_encode %{
6379 __ movb($mem$$Address, r12);
6380 %}
6381 ins_pipe(ialu_mem_reg);
6382 %}
6383
6384 instruct storeImmB(memory mem, immI8 src)
6385 %{
6386 match(Set mem (StoreB mem src));
6387
6388 ins_cost(150); // XXX
6389 format %{ "movb $mem, $src\t# byte" %}
6390 opcode(0xC6); /* C6 /0 */
6391 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6392 ins_pipe(ialu_mem_imm);
6393 %}
6394
6395 // Store CMS card-mark Immediate
6396 instruct storeImmCM0_reg(memory mem, immI0 zero)
6397 %{
6398 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6399 match(Set mem (StoreCM mem zero));
6400
6401 ins_cost(125); // XXX
6402 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6403 ins_encode %{
6404 __ movb($mem$$Address, r12);
6405 %}
6406 ins_pipe(ialu_mem_reg);
6407 %}
6408
6409 instruct storeImmCM0(memory mem, immI0 src)
6410 %{
6411 match(Set mem (StoreCM mem src));
6412
6413 ins_cost(150); // XXX
6414 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6415 opcode(0xC6); /* C6 /0 */
6416 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6417 ins_pipe(ialu_mem_imm);
6418 %}
6419
6420 // Store Float
6421 instruct storeF(memory mem, regF src)
6422 %{
6423 match(Set mem (StoreF mem src));
6424
6425 ins_cost(95); // XXX
6426 format %{ "movss $mem, $src\t# float" %}
6427 ins_encode %{
6428 __ movflt($mem$$Address, $src$$XMMRegister);
6429 %}
6430 ins_pipe(pipe_slow); // XXX
6431 %}
6432
6433 // Store immediate Float value (it is faster than store from XMM register)
6434 instruct storeF0(memory mem, immF0 zero)
6435 %{
6436 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6437 match(Set mem (StoreF mem zero));
6438
6439 ins_cost(25); // XXX
6440 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6441 ins_encode %{
6442 __ movl($mem$$Address, r12);
6443 %}
6444 ins_pipe(ialu_mem_reg);
6445 %}
6446
6447 instruct storeF_imm(memory mem, immF src)
6448 %{
6449 match(Set mem (StoreF mem src));
6450
6451 ins_cost(50);
6452 format %{ "movl $mem, $src\t# float" %}
6453 opcode(0xC7); /* C7 /0 */
6454 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6455 ins_pipe(ialu_mem_imm);
6456 %}
6457
6458 // Store Double
6459 instruct storeD(memory mem, regD src)
6460 %{
6461 match(Set mem (StoreD mem src));
6462
6463 ins_cost(95); // XXX
6464 format %{ "movsd $mem, $src\t# double" %}
6465 ins_encode %{
6466 __ movdbl($mem$$Address, $src$$XMMRegister);
6467 %}
6468 ins_pipe(pipe_slow); // XXX
6469 %}
6470
6471 // Store immediate double 0.0 (it is faster than store from XMM register)
6472 instruct storeD0_imm(memory mem, immD0 src)
6473 %{
6474 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6475 match(Set mem (StoreD mem src));
6476
6477 ins_cost(50);
6478 format %{ "movq $mem, $src\t# double 0." %}
6479 opcode(0xC7); /* C7 /0 */
6480 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6481 ins_pipe(ialu_mem_imm);
6482 %}
6483
6484 instruct storeD0(memory mem, immD0 zero)
6485 %{
6486 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6487 match(Set mem (StoreD mem zero));
6488
6489 ins_cost(25); // XXX
6490 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6491 ins_encode %{
6492 __ movq($mem$$Address, r12);
6493 %}
6494 ins_pipe(ialu_mem_reg);
6495 %}
6496
6497 instruct storeSSI(stackSlotI dst, rRegI src)
6498 %{
6499 match(Set dst src);
6500
6501 ins_cost(100);
6502 format %{ "movl $dst, $src\t# int stk" %}
6503 opcode(0x89);
6504 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6505 ins_pipe( ialu_mem_reg );
6506 %}
6507
6508 instruct storeSSL(stackSlotL dst, rRegL src)
6509 %{
6510 match(Set dst src);
6511
6512 ins_cost(100);
6513 format %{ "movq $dst, $src\t# long stk" %}
6514 opcode(0x89);
6515 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6516 ins_pipe(ialu_mem_reg);
6517 %}
6518
6519 instruct storeSSP(stackSlotP dst, rRegP src)
6520 %{
6521 match(Set dst src);
6522
6523 ins_cost(100);
6524 format %{ "movq $dst, $src\t# ptr stk" %}
6525 opcode(0x89);
6526 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6527 ins_pipe(ialu_mem_reg);
6528 %}
6529
6530 instruct storeSSF(stackSlotF dst, regF src)
6531 %{
6532 match(Set dst src);
6533
6534 ins_cost(95); // XXX
6535 format %{ "movss $dst, $src\t# float stk" %}
6536 ins_encode %{
6537 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6538 %}
6539 ins_pipe(pipe_slow); // XXX
6540 %}
6541
6542 instruct storeSSD(stackSlotD dst, regD src)
6543 %{
6544 match(Set dst src);
6545
6546 ins_cost(95); // XXX
6547 format %{ "movsd $dst, $src\t# double stk" %}
6548 ins_encode %{
6549 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6550 %}
6551 ins_pipe(pipe_slow); // XXX
6552 %}
6553
6554 //----------BSWAP Instructions-------------------------------------------------
6555 instruct bytes_reverse_int(rRegI dst) %{
6556 match(Set dst (ReverseBytesI dst));
6557
6558 format %{ "bswapl $dst" %}
6559 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6560 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6561 ins_pipe( ialu_reg );
6562 %}
6563
6564 instruct bytes_reverse_long(rRegL dst) %{
6565 match(Set dst (ReverseBytesL dst));
6566
6567 format %{ "bswapq $dst" %}
6568 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6569 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6570 ins_pipe( ialu_reg);
6571 %}
6572
6573 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6574 match(Set dst (ReverseBytesUS dst));
6575 effect(KILL cr);
6576
6577 format %{ "bswapl $dst\n\t"
6578 "shrl $dst,16\n\t" %}
6579 ins_encode %{
6580 __ bswapl($dst$$Register);
6581 __ shrl($dst$$Register, 16);
6582 %}
6583 ins_pipe( ialu_reg );
6584 %}
6585
6586 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6587 match(Set dst (ReverseBytesS dst));
6588 effect(KILL cr);
6589
6590 format %{ "bswapl $dst\n\t"
6591 "sar $dst,16\n\t" %}
6592 ins_encode %{
6593 __ bswapl($dst$$Register);
6594 __ sarl($dst$$Register, 16);
6595 %}
6596 ins_pipe( ialu_reg );
6597 %}
6598
6599 //---------- Zeros Count Instructions ------------------------------------------
6600
6601 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6602 predicate(UseCountLeadingZerosInstruction);
6603 match(Set dst (CountLeadingZerosI src));
6604 effect(KILL cr);
6605
6606 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6607 ins_encode %{
6608 __ lzcntl($dst$$Register, $src$$Register);
6609 %}
6610 ins_pipe(ialu_reg);
6611 %}
6612
6613 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6614 predicate(!UseCountLeadingZerosInstruction);
6615 match(Set dst (CountLeadingZerosI src));
6616 effect(KILL cr);
6617
6618 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6619 "jnz skip\n\t"
6620 "movl $dst, -1\n"
6621 "skip:\n\t"
6622 "negl $dst\n\t"
6623 "addl $dst, 31" %}
6624 ins_encode %{
6625 Register Rdst = $dst$$Register;
6626 Register Rsrc = $src$$Register;
6627 Label skip;
6628 __ bsrl(Rdst, Rsrc);
6629 __ jccb(Assembler::notZero, skip);
6630 __ movl(Rdst, -1);
6631 __ bind(skip);
6632 __ negl(Rdst);
6633 __ addl(Rdst, BitsPerInt - 1);
6634 %}
6635 ins_pipe(ialu_reg);
6636 %}
6637
6638 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6639 predicate(UseCountLeadingZerosInstruction);
6640 match(Set dst (CountLeadingZerosL src));
6641 effect(KILL cr);
6642
6643 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6644 ins_encode %{
6645 __ lzcntq($dst$$Register, $src$$Register);
6646 %}
6647 ins_pipe(ialu_reg);
6648 %}
6649
6650 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6651 predicate(!UseCountLeadingZerosInstruction);
6652 match(Set dst (CountLeadingZerosL src));
6653 effect(KILL cr);
6654
6655 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6656 "jnz skip\n\t"
6657 "movl $dst, -1\n"
6658 "skip:\n\t"
6659 "negl $dst\n\t"
6660 "addl $dst, 63" %}
6661 ins_encode %{
6662 Register Rdst = $dst$$Register;
6663 Register Rsrc = $src$$Register;
6664 Label skip;
6665 __ bsrq(Rdst, Rsrc);
6666 __ jccb(Assembler::notZero, skip);
6667 __ movl(Rdst, -1);
6668 __ bind(skip);
6669 __ negl(Rdst);
6670 __ addl(Rdst, BitsPerLong - 1);
6671 %}
6672 ins_pipe(ialu_reg);
6673 %}
6674
6675 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6676 predicate(UseCountTrailingZerosInstruction);
6677 match(Set dst (CountTrailingZerosI src));
6678 effect(KILL cr);
6679
6680 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6681 ins_encode %{
6682 __ tzcntl($dst$$Register, $src$$Register);
6683 %}
6684 ins_pipe(ialu_reg);
6685 %}
6686
6687 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6688 predicate(!UseCountTrailingZerosInstruction);
6689 match(Set dst (CountTrailingZerosI src));
6690 effect(KILL cr);
6691
6692 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6693 "jnz done\n\t"
6694 "movl $dst, 32\n"
6695 "done:" %}
6696 ins_encode %{
6697 Register Rdst = $dst$$Register;
6698 Label done;
6699 __ bsfl(Rdst, $src$$Register);
6700 __ jccb(Assembler::notZero, done);
6701 __ movl(Rdst, BitsPerInt);
6702 __ bind(done);
6703 %}
6704 ins_pipe(ialu_reg);
6705 %}
6706
6707 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6708 predicate(UseCountTrailingZerosInstruction);
6709 match(Set dst (CountTrailingZerosL src));
6710 effect(KILL cr);
6711
6712 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6713 ins_encode %{
6714 __ tzcntq($dst$$Register, $src$$Register);
6715 %}
6716 ins_pipe(ialu_reg);
6717 %}
6718
6719 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6720 predicate(!UseCountTrailingZerosInstruction);
6721 match(Set dst (CountTrailingZerosL src));
6722 effect(KILL cr);
6723
6724 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6725 "jnz done\n\t"
6726 "movl $dst, 64\n"
6727 "done:" %}
6728 ins_encode %{
6729 Register Rdst = $dst$$Register;
6730 Label done;
6731 __ bsfq(Rdst, $src$$Register);
6732 __ jccb(Assembler::notZero, done);
6733 __ movl(Rdst, BitsPerLong);
6734 __ bind(done);
6735 %}
6736 ins_pipe(ialu_reg);
6737 %}
6738
6739
6740 //---------- Population Count Instructions -------------------------------------
6741
6742 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6743 predicate(UsePopCountInstruction);
6744 match(Set dst (PopCountI src));
6745 effect(KILL cr);
6746
6747 format %{ "popcnt $dst, $src" %}
6748 ins_encode %{
6749 __ popcntl($dst$$Register, $src$$Register);
6750 %}
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6755 predicate(UsePopCountInstruction);
6756 match(Set dst (PopCountI (LoadI mem)));
6757 effect(KILL cr);
6758
6759 format %{ "popcnt $dst, $mem" %}
6760 ins_encode %{
6761 __ popcntl($dst$$Register, $mem$$Address);
6762 %}
6763 ins_pipe(ialu_reg);
6764 %}
6765
6766 // Note: Long.bitCount(long) returns an int.
6767 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6768 predicate(UsePopCountInstruction);
6769 match(Set dst (PopCountL src));
6770 effect(KILL cr);
6771
6772 format %{ "popcnt $dst, $src" %}
6773 ins_encode %{
6774 __ popcntq($dst$$Register, $src$$Register);
6775 %}
6776 ins_pipe(ialu_reg);
6777 %}
6778
6779 // Note: Long.bitCount(long) returns an int.
6780 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6781 predicate(UsePopCountInstruction);
6782 match(Set dst (PopCountL (LoadL mem)));
6783 effect(KILL cr);
6784
6785 format %{ "popcnt $dst, $mem" %}
6786 ins_encode %{
6787 __ popcntq($dst$$Register, $mem$$Address);
6788 %}
6789 ins_pipe(ialu_reg);
6790 %}
6791
6792
6793 //----------MemBar Instructions-----------------------------------------------
6794 // Memory barrier flavors
6795
6796 instruct membar_acquire()
6797 %{
6798 match(MemBarAcquire);
6799 match(LoadFence);
6800 ins_cost(0);
6801
6802 size(0);
6803 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6804 ins_encode();
6805 ins_pipe(empty);
6806 %}
6807
6808 instruct membar_acquire_lock()
6809 %{
6810 match(MemBarAcquireLock);
6811 ins_cost(0);
6812
6813 size(0);
6814 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6815 ins_encode();
6816 ins_pipe(empty);
6817 %}
6818
6819 instruct membar_release()
6820 %{
6821 match(MemBarRelease);
6822 match(StoreFence);
6823 ins_cost(0);
6824
6825 size(0);
6826 format %{ "MEMBAR-release ! (empty encoding)" %}
6827 ins_encode();
6828 ins_pipe(empty);
6829 %}
6830
6831 instruct membar_release_lock()
6832 %{
6833 match(MemBarReleaseLock);
6834 ins_cost(0);
6835
6836 size(0);
6837 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6838 ins_encode();
6839 ins_pipe(empty);
6840 %}
6841
6842 instruct membar_volatile(rFlagsReg cr) %{
6843 match(MemBarVolatile);
6844 effect(KILL cr);
6845 ins_cost(400);
6846
6847 format %{
6848 $$template
6849 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6850 %}
6851 ins_encode %{
6852 __ membar(Assembler::StoreLoad);
6853 %}
6854 ins_pipe(pipe_slow);
6855 %}
6856
6857 instruct unnecessary_membar_volatile()
6858 %{
6859 match(MemBarVolatile);
6860 predicate(Matcher::post_store_load_barrier(n));
6861 ins_cost(0);
6862
6863 size(0);
6864 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6865 ins_encode();
6866 ins_pipe(empty);
6867 %}
6868
6869 instruct membar_storestore() %{
6870 match(MemBarStoreStore);
6871 ins_cost(0);
6872
6873 size(0);
6874 format %{ "MEMBAR-storestore (empty encoding)" %}
6875 ins_encode( );
6876 ins_pipe(empty);
6877 %}
6878
6879 //----------Move Instructions--------------------------------------------------
6880
6881 instruct castX2P(rRegP dst, rRegL src)
6882 %{
6883 match(Set dst (CastX2P src));
6884
6885 format %{ "movq $dst, $src\t# long->ptr" %}
6886 ins_encode %{
6887 if ($dst$$reg != $src$$reg) {
6888 __ movptr($dst$$Register, $src$$Register);
6889 }
6890 %}
6891 ins_pipe(ialu_reg_reg); // XXX
6892 %}
6893
6894 instruct castP2X(rRegL dst, rRegP src)
6895 %{
6896 match(Set dst (CastP2X src));
6897
6898 format %{ "movq $dst, $src\t# ptr -> long" %}
6899 ins_encode %{
6900 if ($dst$$reg != $src$$reg) {
6901 __ movptr($dst$$Register, $src$$Register);
6902 }
6903 %}
6904 ins_pipe(ialu_reg_reg); // XXX
6905 %}
6906
6907 // Convert oop into int for vectors alignment masking
6908 instruct convP2I(rRegI dst, rRegP src)
6909 %{
6910 match(Set dst (ConvL2I (CastP2X src)));
6911
6912 format %{ "movl $dst, $src\t# ptr -> int" %}
6913 ins_encode %{
6914 __ movl($dst$$Register, $src$$Register);
6915 %}
6916 ins_pipe(ialu_reg_reg); // XXX
6917 %}
6918
6919 // Convert compressed oop into int for vectors alignment masking
6920 // in case of 32bit oops (heap < 4Gb).
6921 instruct convN2I(rRegI dst, rRegN src)
6922 %{
6923 predicate(Universe::narrow_oop_shift() == 0);
6924 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6925
6926 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6927 ins_encode %{
6928 __ movl($dst$$Register, $src$$Register);
6929 %}
6930 ins_pipe(ialu_reg_reg); // XXX
6931 %}
6932
6933 // Convert oop pointer into compressed form
6934 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6935 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6936 match(Set dst (EncodeP src));
6937 effect(KILL cr);
6938 format %{ "encode_heap_oop $dst,$src" %}
6939 ins_encode %{
6940 Register s = $src$$Register;
6941 Register d = $dst$$Register;
6942 if (s != d) {
6943 __ movq(d, s);
6944 }
6945 __ encode_heap_oop(d);
6946 %}
6947 ins_pipe(ialu_reg_long);
6948 %}
6949
6950 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6951 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6952 match(Set dst (EncodeP src));
6953 effect(KILL cr);
6954 format %{ "encode_heap_oop_not_null $dst,$src" %}
6955 ins_encode %{
6956 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6957 %}
6958 ins_pipe(ialu_reg_long);
6959 %}
6960
6961 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6962 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6963 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6964 match(Set dst (DecodeN src));
6965 effect(KILL cr);
6966 format %{ "decode_heap_oop $dst,$src" %}
6967 ins_encode %{
6968 Register s = $src$$Register;
6969 Register d = $dst$$Register;
6970 if (s != d) {
6971 __ movq(d, s);
6972 }
6973 __ decode_heap_oop(d);
6974 %}
6975 ins_pipe(ialu_reg_long);
6976 %}
6977
6978 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6979 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6980 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6981 match(Set dst (DecodeN src));
6982 effect(KILL cr);
6983 format %{ "decode_heap_oop_not_null $dst,$src" %}
6984 ins_encode %{
6985 Register s = $src$$Register;
6986 Register d = $dst$$Register;
6987 if (s != d) {
6988 __ decode_heap_oop_not_null(d, s);
6989 } else {
6990 __ decode_heap_oop_not_null(d);
6991 }
6992 %}
6993 ins_pipe(ialu_reg_long);
6994 %}
6995
6996 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6997 match(Set dst (EncodePKlass src));
6998 effect(KILL cr);
6999 format %{ "encode_klass_not_null $dst,$src" %}
7000 ins_encode %{
7001 __ encode_klass_not_null($dst$$Register, $src$$Register);
7002 %}
7003 ins_pipe(ialu_reg_long);
7004 %}
7005
7006 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
7007 match(Set dst (DecodeNKlass src));
7008 effect(KILL cr);
7009 format %{ "decode_klass_not_null $dst,$src" %}
7010 ins_encode %{
7011 Register s = $src$$Register;
7012 Register d = $dst$$Register;
7013 if (s != d) {
7014 __ decode_klass_not_null(d, s);
7015 } else {
7016 __ decode_klass_not_null(d);
7017 }
7018 %}
7019 ins_pipe(ialu_reg_long);
7020 %}
7021
7022
7023 //----------Conditional Move---------------------------------------------------
7024 // Jump
7025 // dummy instruction for generating temp registers
7026 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7027 match(Jump (LShiftL switch_val shift));
7028 ins_cost(350);
7029 predicate(false);
7030 effect(TEMP dest);
7031
7032 format %{ "leaq $dest, [$constantaddress]\n\t"
7033 "jmp [$dest + $switch_val << $shift]\n\t" %}
7034 ins_encode %{
7035 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7036 // to do that and the compiler is using that register as one it can allocate.
7037 // So we build it all by hand.
7038 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
7039 // ArrayAddress dispatch(table, index);
7040 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
7041 __ lea($dest$$Register, $constantaddress);
7042 __ jmp(dispatch);
7043 %}
7044 ins_pipe(pipe_jmp);
7045 %}
7046
7047 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7048 match(Jump (AddL (LShiftL switch_val shift) offset));
7049 ins_cost(350);
7050 effect(TEMP dest);
7051
7052 format %{ "leaq $dest, [$constantaddress]\n\t"
7053 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7054 ins_encode %{
7055 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7056 // to do that and the compiler is using that register as one it can allocate.
7057 // So we build it all by hand.
7058 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7059 // ArrayAddress dispatch(table, index);
7060 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7061 __ lea($dest$$Register, $constantaddress);
7062 __ jmp(dispatch);
7063 %}
7064 ins_pipe(pipe_jmp);
7065 %}
7066
7067 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7068 match(Jump switch_val);
7069 ins_cost(350);
7070 effect(TEMP dest);
7071
7072 format %{ "leaq $dest, [$constantaddress]\n\t"
7073 "jmp [$dest + $switch_val]\n\t" %}
7074 ins_encode %{
7075 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7076 // to do that and the compiler is using that register as one it can allocate.
7077 // So we build it all by hand.
7078 // Address index(noreg, switch_reg, Address::times_1);
7079 // ArrayAddress dispatch(table, index);
7080 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
7081 __ lea($dest$$Register, $constantaddress);
7082 __ jmp(dispatch);
7083 %}
7084 ins_pipe(pipe_jmp);
7085 %}
7086
7087 // Conditional move
7088 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7089 %{
7090 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7091
7092 ins_cost(200); // XXX
7093 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7094 opcode(0x0F, 0x40);
7095 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7096 ins_pipe(pipe_cmov_reg);
7097 %}
7098
7099 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7100 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7101
7102 ins_cost(200); // XXX
7103 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7104 opcode(0x0F, 0x40);
7105 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7106 ins_pipe(pipe_cmov_reg);
7107 %}
7108
7109 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7110 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7111 ins_cost(200);
7112 expand %{
7113 cmovI_regU(cop, cr, dst, src);
7114 %}
7115 %}
7116
7117 // Conditional move
7118 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7119 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7120
7121 ins_cost(250); // XXX
7122 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7123 opcode(0x0F, 0x40);
7124 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7125 ins_pipe(pipe_cmov_mem);
7126 %}
7127
7128 // Conditional move
7129 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7130 %{
7131 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7132
7133 ins_cost(250); // XXX
7134 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7135 opcode(0x0F, 0x40);
7136 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7137 ins_pipe(pipe_cmov_mem);
7138 %}
7139
7140 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7141 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7142 ins_cost(250);
7143 expand %{
7144 cmovI_memU(cop, cr, dst, src);
7145 %}
7146 %}
7147
7148 // Conditional move
7149 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7150 %{
7151 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7152
7153 ins_cost(200); // XXX
7154 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7155 opcode(0x0F, 0x40);
7156 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7157 ins_pipe(pipe_cmov_reg);
7158 %}
7159
7160 // Conditional move
7161 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7162 %{
7163 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7164
7165 ins_cost(200); // XXX
7166 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7167 opcode(0x0F, 0x40);
7168 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7169 ins_pipe(pipe_cmov_reg);
7170 %}
7171
7172 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7173 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7174 ins_cost(200);
7175 expand %{
7176 cmovN_regU(cop, cr, dst, src);
7177 %}
7178 %}
7179
7180 // Conditional move
7181 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7182 %{
7183 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7184
7185 ins_cost(200); // XXX
7186 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7187 opcode(0x0F, 0x40);
7188 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7189 ins_pipe(pipe_cmov_reg); // XXX
7190 %}
7191
7192 // Conditional move
7193 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7194 %{
7195 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7196
7197 ins_cost(200); // XXX
7198 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7199 opcode(0x0F, 0x40);
7200 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7201 ins_pipe(pipe_cmov_reg); // XXX
7202 %}
7203
7204 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7205 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7206 ins_cost(200);
7207 expand %{
7208 cmovP_regU(cop, cr, dst, src);
7209 %}
7210 %}
7211
7212 // DISABLED: Requires the ADLC to emit a bottom_type call that
7213 // correctly meets the two pointer arguments; one is an incoming
7214 // register but the other is a memory operand. ALSO appears to
7215 // be buggy with implicit null checks.
7216 //
7217 //// Conditional move
7218 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7219 //%{
7220 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7221 // ins_cost(250);
7222 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7223 // opcode(0x0F,0x40);
7224 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7225 // ins_pipe( pipe_cmov_mem );
7226 //%}
7227 //
7228 //// Conditional move
7229 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7230 //%{
7231 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7232 // ins_cost(250);
7233 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7234 // opcode(0x0F,0x40);
7235 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7236 // ins_pipe( pipe_cmov_mem );
7237 //%}
7238
7239 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7240 %{
7241 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7242
7243 ins_cost(200); // XXX
7244 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7245 opcode(0x0F, 0x40);
7246 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7247 ins_pipe(pipe_cmov_reg); // XXX
7248 %}
7249
7250 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7251 %{
7252 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7253
7254 ins_cost(200); // XXX
7255 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7256 opcode(0x0F, 0x40);
7257 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7258 ins_pipe(pipe_cmov_mem); // XXX
7259 %}
7260
7261 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7262 %{
7263 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7264
7265 ins_cost(200); // XXX
7266 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7267 opcode(0x0F, 0x40);
7268 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7269 ins_pipe(pipe_cmov_reg); // XXX
7270 %}
7271
7272 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7273 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7274 ins_cost(200);
7275 expand %{
7276 cmovL_regU(cop, cr, dst, src);
7277 %}
7278 %}
7279
7280 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7281 %{
7282 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7283
7284 ins_cost(200); // XXX
7285 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7286 opcode(0x0F, 0x40);
7287 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7288 ins_pipe(pipe_cmov_mem); // XXX
7289 %}
7290
7291 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7292 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7293 ins_cost(200);
7294 expand %{
7295 cmovL_memU(cop, cr, dst, src);
7296 %}
7297 %}
7298
7299 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7300 %{
7301 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7302
7303 ins_cost(200); // XXX
7304 format %{ "jn$cop skip\t# signed cmove float\n\t"
7305 "movss $dst, $src\n"
7306 "skip:" %}
7307 ins_encode %{
7308 Label Lskip;
7309 // Invert sense of branch from sense of CMOV
7310 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7311 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7312 __ bind(Lskip);
7313 %}
7314 ins_pipe(pipe_slow);
7315 %}
7316
7317 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7318 // %{
7319 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7320
7321 // ins_cost(200); // XXX
7322 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7323 // "movss $dst, $src\n"
7324 // "skip:" %}
7325 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7326 // ins_pipe(pipe_slow);
7327 // %}
7328
7329 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7330 %{
7331 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7332
7333 ins_cost(200); // XXX
7334 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7335 "movss $dst, $src\n"
7336 "skip:" %}
7337 ins_encode %{
7338 Label Lskip;
7339 // Invert sense of branch from sense of CMOV
7340 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7341 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7342 __ bind(Lskip);
7343 %}
7344 ins_pipe(pipe_slow);
7345 %}
7346
7347 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7348 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7349 ins_cost(200);
7350 expand %{
7351 cmovF_regU(cop, cr, dst, src);
7352 %}
7353 %}
7354
7355 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7356 %{
7357 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7358
7359 ins_cost(200); // XXX
7360 format %{ "jn$cop skip\t# signed cmove double\n\t"
7361 "movsd $dst, $src\n"
7362 "skip:" %}
7363 ins_encode %{
7364 Label Lskip;
7365 // Invert sense of branch from sense of CMOV
7366 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7367 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7368 __ bind(Lskip);
7369 %}
7370 ins_pipe(pipe_slow);
7371 %}
7372
7373 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7374 %{
7375 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7376
7377 ins_cost(200); // XXX
7378 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7379 "movsd $dst, $src\n"
7380 "skip:" %}
7381 ins_encode %{
7382 Label Lskip;
7383 // Invert sense of branch from sense of CMOV
7384 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7385 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7386 __ bind(Lskip);
7387 %}
7388 ins_pipe(pipe_slow);
7389 %}
7390
7391 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7392 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7393 ins_cost(200);
7394 expand %{
7395 cmovD_regU(cop, cr, dst, src);
7396 %}
7397 %}
7398
7399 //----------Arithmetic Instructions--------------------------------------------
7400 //----------Addition Instructions----------------------------------------------
7401
7402 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7403 %{
7404 match(Set dst (AddI dst src));
7405 effect(KILL cr);
7406
7407 format %{ "addl $dst, $src\t# int" %}
7408 opcode(0x03);
7409 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7410 ins_pipe(ialu_reg_reg);
7411 %}
7412
7413 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7414 %{
7415 match(Set dst (AddI dst src));
7416 effect(KILL cr);
7417
7418 format %{ "addl $dst, $src\t# int" %}
7419 opcode(0x81, 0x00); /* /0 id */
7420 ins_encode(OpcSErm(dst, src), Con8or32(src));
7421 ins_pipe( ialu_reg );
7422 %}
7423
7424 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7425 %{
7426 match(Set dst (AddI dst (LoadI src)));
7427 effect(KILL cr);
7428
7429 ins_cost(125); // XXX
7430 format %{ "addl $dst, $src\t# int" %}
7431 opcode(0x03);
7432 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7433 ins_pipe(ialu_reg_mem);
7434 %}
7435
7436 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7437 %{
7438 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7439 effect(KILL cr);
7440
7441 ins_cost(150); // XXX
7442 format %{ "addl $dst, $src\t# int" %}
7443 opcode(0x01); /* Opcode 01 /r */
7444 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7445 ins_pipe(ialu_mem_reg);
7446 %}
7447
7448 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7449 %{
7450 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7451 effect(KILL cr);
7452
7453 ins_cost(125); // XXX
7454 format %{ "addl $dst, $src\t# int" %}
7455 opcode(0x81); /* Opcode 81 /0 id */
7456 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7457 ins_pipe(ialu_mem_imm);
7458 %}
7459
7460 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7461 %{
7462 predicate(UseIncDec);
7463 match(Set dst (AddI dst src));
7464 effect(KILL cr);
7465
7466 format %{ "incl $dst\t# int" %}
7467 opcode(0xFF, 0x00); // FF /0
7468 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7469 ins_pipe(ialu_reg);
7470 %}
7471
7472 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7473 %{
7474 predicate(UseIncDec);
7475 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7476 effect(KILL cr);
7477
7478 ins_cost(125); // XXX
7479 format %{ "incl $dst\t# int" %}
7480 opcode(0xFF); /* Opcode FF /0 */
7481 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7482 ins_pipe(ialu_mem_imm);
7483 %}
7484
7485 // XXX why does that use AddI
7486 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7487 %{
7488 predicate(UseIncDec);
7489 match(Set dst (AddI dst src));
7490 effect(KILL cr);
7491
7492 format %{ "decl $dst\t# int" %}
7493 opcode(0xFF, 0x01); // FF /1
7494 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7495 ins_pipe(ialu_reg);
7496 %}
7497
7498 // XXX why does that use AddI
7499 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7500 %{
7501 predicate(UseIncDec);
7502 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7503 effect(KILL cr);
7504
7505 ins_cost(125); // XXX
7506 format %{ "decl $dst\t# int" %}
7507 opcode(0xFF); /* Opcode FF /1 */
7508 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7509 ins_pipe(ialu_mem_imm);
7510 %}
7511
7512 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7513 %{
7514 match(Set dst (AddI src0 src1));
7515
7516 ins_cost(110);
7517 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7518 opcode(0x8D); /* 0x8D /r */
7519 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7520 ins_pipe(ialu_reg_reg);
7521 %}
7522
7523 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7524 %{
7525 match(Set dst (AddL dst src));
7526 effect(KILL cr);
7527
7528 format %{ "addq $dst, $src\t# long" %}
7529 opcode(0x03);
7530 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7535 %{
7536 match(Set dst (AddL dst src));
7537 effect(KILL cr);
7538
7539 format %{ "addq $dst, $src\t# long" %}
7540 opcode(0x81, 0x00); /* /0 id */
7541 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7542 ins_pipe( ialu_reg );
7543 %}
7544
7545 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7546 %{
7547 match(Set dst (AddL dst (LoadL src)));
7548 effect(KILL cr);
7549
7550 ins_cost(125); // XXX
7551 format %{ "addq $dst, $src\t# long" %}
7552 opcode(0x03);
7553 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7554 ins_pipe(ialu_reg_mem);
7555 %}
7556
7557 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7558 %{
7559 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7560 effect(KILL cr);
7561
7562 ins_cost(150); // XXX
7563 format %{ "addq $dst, $src\t# long" %}
7564 opcode(0x01); /* Opcode 01 /r */
7565 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7566 ins_pipe(ialu_mem_reg);
7567 %}
7568
7569 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7570 %{
7571 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7572 effect(KILL cr);
7573
7574 ins_cost(125); // XXX
7575 format %{ "addq $dst, $src\t# long" %}
7576 opcode(0x81); /* Opcode 81 /0 id */
7577 ins_encode(REX_mem_wide(dst),
7578 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7579 ins_pipe(ialu_mem_imm);
7580 %}
7581
7582 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7583 %{
7584 predicate(UseIncDec);
7585 match(Set dst (AddL dst src));
7586 effect(KILL cr);
7587
7588 format %{ "incq $dst\t# long" %}
7589 opcode(0xFF, 0x00); // FF /0
7590 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7591 ins_pipe(ialu_reg);
7592 %}
7593
7594 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7595 %{
7596 predicate(UseIncDec);
7597 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7598 effect(KILL cr);
7599
7600 ins_cost(125); // XXX
7601 format %{ "incq $dst\t# long" %}
7602 opcode(0xFF); /* Opcode FF /0 */
7603 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7604 ins_pipe(ialu_mem_imm);
7605 %}
7606
7607 // XXX why does that use AddL
7608 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7609 %{
7610 predicate(UseIncDec);
7611 match(Set dst (AddL dst src));
7612 effect(KILL cr);
7613
7614 format %{ "decq $dst\t# long" %}
7615 opcode(0xFF, 0x01); // FF /1
7616 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7617 ins_pipe(ialu_reg);
7618 %}
7619
7620 // XXX why does that use AddL
7621 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7622 %{
7623 predicate(UseIncDec);
7624 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7625 effect(KILL cr);
7626
7627 ins_cost(125); // XXX
7628 format %{ "decq $dst\t# long" %}
7629 opcode(0xFF); /* Opcode FF /1 */
7630 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7631 ins_pipe(ialu_mem_imm);
7632 %}
7633
7634 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7635 %{
7636 match(Set dst (AddL src0 src1));
7637
7638 ins_cost(110);
7639 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7640 opcode(0x8D); /* 0x8D /r */
7641 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7642 ins_pipe(ialu_reg_reg);
7643 %}
7644
7645 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7646 %{
7647 match(Set dst (AddP dst src));
7648 effect(KILL cr);
7649
7650 format %{ "addq $dst, $src\t# ptr" %}
7651 opcode(0x03);
7652 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7653 ins_pipe(ialu_reg_reg);
7654 %}
7655
7656 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7657 %{
7658 match(Set dst (AddP dst src));
7659 effect(KILL cr);
7660
7661 format %{ "addq $dst, $src\t# ptr" %}
7662 opcode(0x81, 0x00); /* /0 id */
7663 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7664 ins_pipe( ialu_reg );
7665 %}
7666
7667 // XXX addP mem ops ????
7668
7669 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7670 %{
7671 match(Set dst (AddP src0 src1));
7672
7673 ins_cost(110);
7674 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7675 opcode(0x8D); /* 0x8D /r */
7676 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7677 ins_pipe(ialu_reg_reg);
7678 %}
7679
7680 instruct checkCastPP(rRegP dst)
7681 %{
7682 match(Set dst (CheckCastPP dst));
7683
7684 size(0);
7685 format %{ "# checkcastPP of $dst" %}
7686 ins_encode(/* empty encoding */);
7687 ins_pipe(empty);
7688 %}
7689
7690 instruct castPP(rRegP dst)
7691 %{
7692 match(Set dst (CastPP dst));
7693
7694 size(0);
7695 format %{ "# castPP of $dst" %}
7696 ins_encode(/* empty encoding */);
7697 ins_pipe(empty);
7698 %}
7699
7700 instruct castII(rRegI dst)
7701 %{
7702 match(Set dst (CastII dst));
7703
7704 size(0);
7705 format %{ "# castII of $dst" %}
7706 ins_encode(/* empty encoding */);
7707 ins_cost(0);
7708 ins_pipe(empty);
7709 %}
7710
7711 // LoadP-locked same as a regular LoadP when used with compare-swap
7712 instruct loadPLocked(rRegP dst, memory mem)
7713 %{
7714 match(Set dst (LoadPLocked mem));
7715
7716 ins_cost(125); // XXX
7717 format %{ "movq $dst, $mem\t# ptr locked" %}
7718 opcode(0x8B);
7719 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7720 ins_pipe(ialu_reg_mem); // XXX
7721 %}
7722
7723 // Conditional-store of the updated heap-top.
7724 // Used during allocation of the shared heap.
7725 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7726
7727 instruct storePConditional(memory heap_top_ptr,
7728 rax_RegP oldval, rRegP newval,
7729 rFlagsReg cr)
7730 %{
7731 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7732
7733 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7734 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7735 opcode(0x0F, 0xB1);
7736 ins_encode(lock_prefix,
7737 REX_reg_mem_wide(newval, heap_top_ptr),
7738 OpcP, OpcS,
7739 reg_mem(newval, heap_top_ptr));
7740 ins_pipe(pipe_cmpxchg);
7741 %}
7742
7743 // Conditional-store of an int value.
7744 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7745 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7746 %{
7747 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7748 effect(KILL oldval);
7749
7750 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7751 opcode(0x0F, 0xB1);
7752 ins_encode(lock_prefix,
7753 REX_reg_mem(newval, mem),
7754 OpcP, OpcS,
7755 reg_mem(newval, mem));
7756 ins_pipe(pipe_cmpxchg);
7757 %}
7758
7759 // Conditional-store of a long value.
7760 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7761 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7762 %{
7763 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7764 effect(KILL oldval);
7765
7766 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7767 opcode(0x0F, 0xB1);
7768 ins_encode(lock_prefix,
7769 REX_reg_mem_wide(newval, mem),
7770 OpcP, OpcS,
7771 reg_mem(newval, mem));
7772 ins_pipe(pipe_cmpxchg);
7773 %}
7774
7775
7776 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7777 instruct compareAndSwapP(rRegI res,
7778 memory mem_ptr,
7779 rax_RegP oldval, rRegP newval,
7780 rFlagsReg cr)
7781 %{
7782 predicate(VM_Version::supports_cx8());
7783 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7784 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7785 effect(KILL cr, KILL oldval);
7786
7787 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7788 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7789 "sete $res\n\t"
7790 "movzbl $res, $res" %}
7791 opcode(0x0F, 0xB1);
7792 ins_encode(lock_prefix,
7793 REX_reg_mem_wide(newval, mem_ptr),
7794 OpcP, OpcS,
7795 reg_mem(newval, mem_ptr),
7796 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7797 REX_reg_breg(res, res), // movzbl
7798 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7799 ins_pipe( pipe_cmpxchg );
7800 %}
7801
7802 instruct compareAndSwapL(rRegI res,
7803 memory mem_ptr,
7804 rax_RegL oldval, rRegL newval,
7805 rFlagsReg cr)
7806 %{
7807 predicate(VM_Version::supports_cx8());
7808 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7809 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7810 effect(KILL cr, KILL oldval);
7811
7812 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7813 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7814 "sete $res\n\t"
7815 "movzbl $res, $res" %}
7816 opcode(0x0F, 0xB1);
7817 ins_encode(lock_prefix,
7818 REX_reg_mem_wide(newval, mem_ptr),
7819 OpcP, OpcS,
7820 reg_mem(newval, mem_ptr),
7821 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7822 REX_reg_breg(res, res), // movzbl
7823 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7824 ins_pipe( pipe_cmpxchg );
7825 %}
7826
7827 instruct compareAndSwapI(rRegI res,
7828 memory mem_ptr,
7829 rax_RegI oldval, rRegI newval,
7830 rFlagsReg cr)
7831 %{
7832 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7833 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7834 effect(KILL cr, KILL oldval);
7835
7836 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7837 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7838 "sete $res\n\t"
7839 "movzbl $res, $res" %}
7840 opcode(0x0F, 0xB1);
7841 ins_encode(lock_prefix,
7842 REX_reg_mem(newval, mem_ptr),
7843 OpcP, OpcS,
7844 reg_mem(newval, mem_ptr),
7845 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7846 REX_reg_breg(res, res), // movzbl
7847 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7848 ins_pipe( pipe_cmpxchg );
7849 %}
7850
7851 instruct compareAndSwapB(rRegI res,
7852 memory mem_ptr,
7853 rax_RegI oldval, rRegI newval,
7854 rFlagsReg cr)
7855 %{
7856 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7857 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7858 effect(KILL cr, KILL oldval);
7859
7860 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7861 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7862 "sete $res\n\t"
7863 "movzbl $res, $res" %}
7864 opcode(0x0F, 0xB0);
7865 ins_encode(lock_prefix,
7866 REX_breg_mem(newval, mem_ptr),
7867 OpcP, OpcS,
7868 reg_mem(newval, mem_ptr),
7869 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7870 REX_reg_breg(res, res), // movzbl
7871 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7872 ins_pipe( pipe_cmpxchg );
7873 %}
7874
7875 instruct compareAndSwapS(rRegI res,
7876 memory mem_ptr,
7877 rax_RegI oldval, rRegI newval,
7878 rFlagsReg cr)
7879 %{
7880 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7881 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7882 effect(KILL cr, KILL oldval);
7883
7884 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7885 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7886 "sete $res\n\t"
7887 "movzbl $res, $res" %}
7888 opcode(0x0F, 0xB1);
7889 ins_encode(lock_prefix,
7890 SizePrefix,
7891 REX_reg_mem(newval, mem_ptr),
7892 OpcP, OpcS,
7893 reg_mem(newval, mem_ptr),
7894 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7895 REX_reg_breg(res, res), // movzbl
7896 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7897 ins_pipe( pipe_cmpxchg );
7898 %}
7899
7900 instruct compareAndSwapN(rRegI res,
7901 memory mem_ptr,
7902 rax_RegN oldval, rRegN newval,
7903 rFlagsReg cr) %{
7904 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7905 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7906 effect(KILL cr, KILL oldval);
7907
7908 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7909 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7910 "sete $res\n\t"
7911 "movzbl $res, $res" %}
7912 opcode(0x0F, 0xB1);
7913 ins_encode(lock_prefix,
7914 REX_reg_mem(newval, mem_ptr),
7915 OpcP, OpcS,
7916 reg_mem(newval, mem_ptr),
7917 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7918 REX_reg_breg(res, res), // movzbl
7919 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7920 ins_pipe( pipe_cmpxchg );
7921 %}
7922
7923 instruct compareAndExchangeB(
7924 memory mem_ptr,
7925 rax_RegI oldval, rRegI newval,
7926 rFlagsReg cr)
7927 %{
7928 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7929 effect(KILL cr);
7930
7931 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7932 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7933 opcode(0x0F, 0xB0);
7934 ins_encode(lock_prefix,
7935 REX_breg_mem(newval, mem_ptr),
7936 OpcP, OpcS,
7937 reg_mem(newval, mem_ptr) // lock cmpxchg
7938 );
7939 ins_pipe( pipe_cmpxchg );
7940 %}
7941
7942 instruct compareAndExchangeS(
7943 memory mem_ptr,
7944 rax_RegI oldval, rRegI newval,
7945 rFlagsReg cr)
7946 %{
7947 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7948 effect(KILL cr);
7949
7950 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7951 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7952 opcode(0x0F, 0xB1);
7953 ins_encode(lock_prefix,
7954 SizePrefix,
7955 REX_reg_mem(newval, mem_ptr),
7956 OpcP, OpcS,
7957 reg_mem(newval, mem_ptr) // lock cmpxchg
7958 );
7959 ins_pipe( pipe_cmpxchg );
7960 %}
7961
7962 instruct compareAndExchangeI(
7963 memory mem_ptr,
7964 rax_RegI oldval, rRegI newval,
7965 rFlagsReg cr)
7966 %{
7967 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7968 effect(KILL cr);
7969
7970 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7971 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7972 opcode(0x0F, 0xB1);
7973 ins_encode(lock_prefix,
7974 REX_reg_mem(newval, mem_ptr),
7975 OpcP, OpcS,
7976 reg_mem(newval, mem_ptr) // lock cmpxchg
7977 );
7978 ins_pipe( pipe_cmpxchg );
7979 %}
7980
7981 instruct compareAndExchangeL(
7982 memory mem_ptr,
7983 rax_RegL oldval, rRegL newval,
7984 rFlagsReg cr)
7985 %{
7986 predicate(VM_Version::supports_cx8());
7987 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7988 effect(KILL cr);
7989
7990 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7991 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7992 opcode(0x0F, 0xB1);
7993 ins_encode(lock_prefix,
7994 REX_reg_mem_wide(newval, mem_ptr),
7995 OpcP, OpcS,
7996 reg_mem(newval, mem_ptr) // lock cmpxchg
7997 );
7998 ins_pipe( pipe_cmpxchg );
7999 %}
8000
8001 instruct compareAndExchangeN(
8002 memory mem_ptr,
8003 rax_RegN oldval, rRegN newval,
8004 rFlagsReg cr) %{
8005 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
8006 effect(KILL cr);
8007
8008 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8009 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8010 opcode(0x0F, 0xB1);
8011 ins_encode(lock_prefix,
8012 REX_reg_mem(newval, mem_ptr),
8013 OpcP, OpcS,
8014 reg_mem(newval, mem_ptr) // lock cmpxchg
8015 );
8016 ins_pipe( pipe_cmpxchg );
8017 %}
8018
8019 instruct compareAndExchangeP(
8020 memory mem_ptr,
8021 rax_RegP oldval, rRegP newval,
8022 rFlagsReg cr)
8023 %{
8024 predicate(VM_Version::supports_cx8());
8025 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
8026 effect(KILL cr);
8027
8028 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8029 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8030 opcode(0x0F, 0xB1);
8031 ins_encode(lock_prefix,
8032 REX_reg_mem_wide(newval, mem_ptr),
8033 OpcP, OpcS,
8034 reg_mem(newval, mem_ptr) // lock cmpxchg
8035 );
8036 ins_pipe( pipe_cmpxchg );
8037 %}
8038
8039 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8040 predicate(n->as_LoadStore()->result_not_used());
8041 match(Set dummy (GetAndAddB mem add));
8042 effect(KILL cr);
8043 format %{ "ADDB [$mem],$add" %}
8044 ins_encode %{
8045 __ lock();
8046 __ addb($mem$$Address, $add$$constant);
8047 %}
8048 ins_pipe( pipe_cmpxchg );
8049 %}
8050
8051 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
8052 match(Set newval (GetAndAddB mem newval));
8053 effect(KILL cr);
8054 format %{ "XADDB [$mem],$newval" %}
8055 ins_encode %{
8056 __ lock();
8057 __ xaddb($mem$$Address, $newval$$Register);
8058 %}
8059 ins_pipe( pipe_cmpxchg );
8060 %}
8061
8062 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8063 predicate(n->as_LoadStore()->result_not_used());
8064 match(Set dummy (GetAndAddS mem add));
8065 effect(KILL cr);
8066 format %{ "ADDW [$mem],$add" %}
8067 ins_encode %{
8068 __ lock();
8069 __ addw($mem$$Address, $add$$constant);
8070 %}
8071 ins_pipe( pipe_cmpxchg );
8072 %}
8073
8074 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8075 match(Set newval (GetAndAddS mem newval));
8076 effect(KILL cr);
8077 format %{ "XADDW [$mem],$newval" %}
8078 ins_encode %{
8079 __ lock();
8080 __ xaddw($mem$$Address, $newval$$Register);
8081 %}
8082 ins_pipe( pipe_cmpxchg );
8083 %}
8084
8085 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8086 predicate(n->as_LoadStore()->result_not_used());
8087 match(Set dummy (GetAndAddI mem add));
8088 effect(KILL cr);
8089 format %{ "ADDL [$mem],$add" %}
8090 ins_encode %{
8091 __ lock();
8092 __ addl($mem$$Address, $add$$constant);
8093 %}
8094 ins_pipe( pipe_cmpxchg );
8095 %}
8096
8097 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8098 match(Set newval (GetAndAddI mem newval));
8099 effect(KILL cr);
8100 format %{ "XADDL [$mem],$newval" %}
8101 ins_encode %{
8102 __ lock();
8103 __ xaddl($mem$$Address, $newval$$Register);
8104 %}
8105 ins_pipe( pipe_cmpxchg );
8106 %}
8107
8108 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8109 predicate(n->as_LoadStore()->result_not_used());
8110 match(Set dummy (GetAndAddL mem add));
8111 effect(KILL cr);
8112 format %{ "ADDQ [$mem],$add" %}
8113 ins_encode %{
8114 __ lock();
8115 __ addq($mem$$Address, $add$$constant);
8116 %}
8117 ins_pipe( pipe_cmpxchg );
8118 %}
8119
8120 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8121 match(Set newval (GetAndAddL mem newval));
8122 effect(KILL cr);
8123 format %{ "XADDQ [$mem],$newval" %}
8124 ins_encode %{
8125 __ lock();
8126 __ xaddq($mem$$Address, $newval$$Register);
8127 %}
8128 ins_pipe( pipe_cmpxchg );
8129 %}
8130
8131 instruct xchgB( memory mem, rRegI newval) %{
8132 match(Set newval (GetAndSetB mem newval));
8133 format %{ "XCHGB $newval,[$mem]" %}
8134 ins_encode %{
8135 __ xchgb($newval$$Register, $mem$$Address);
8136 %}
8137 ins_pipe( pipe_cmpxchg );
8138 %}
8139
8140 instruct xchgS( memory mem, rRegI newval) %{
8141 match(Set newval (GetAndSetS mem newval));
8142 format %{ "XCHGW $newval,[$mem]" %}
8143 ins_encode %{
8144 __ xchgw($newval$$Register, $mem$$Address);
8145 %}
8146 ins_pipe( pipe_cmpxchg );
8147 %}
8148
8149 instruct xchgI( memory mem, rRegI newval) %{
8150 match(Set newval (GetAndSetI mem newval));
8151 format %{ "XCHGL $newval,[$mem]" %}
8152 ins_encode %{
8153 __ xchgl($newval$$Register, $mem$$Address);
8154 %}
8155 ins_pipe( pipe_cmpxchg );
8156 %}
8157
8158 instruct xchgL( memory mem, rRegL newval) %{
8159 match(Set newval (GetAndSetL mem newval));
8160 format %{ "XCHGL $newval,[$mem]" %}
8161 ins_encode %{
8162 __ xchgq($newval$$Register, $mem$$Address);
8163 %}
8164 ins_pipe( pipe_cmpxchg );
8165 %}
8166
8167 instruct xchgP( memory mem, rRegP newval) %{
8168 match(Set newval (GetAndSetP mem newval));
8169 format %{ "XCHGQ $newval,[$mem]" %}
8170 ins_encode %{
8171 __ xchgq($newval$$Register, $mem$$Address);
8172 %}
8173 ins_pipe( pipe_cmpxchg );
8174 %}
8175
8176 instruct xchgN( memory mem, rRegN newval) %{
8177 match(Set newval (GetAndSetN mem newval));
8178 format %{ "XCHGL $newval,$mem]" %}
8179 ins_encode %{
8180 __ xchgl($newval$$Register, $mem$$Address);
8181 %}
8182 ins_pipe( pipe_cmpxchg );
8183 %}
8184
8185 //----------Subtraction Instructions-------------------------------------------
8186
8187 // Integer Subtraction Instructions
8188 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8189 %{
8190 match(Set dst (SubI dst src));
8191 effect(KILL cr);
8192
8193 format %{ "subl $dst, $src\t# int" %}
8194 opcode(0x2B);
8195 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8196 ins_pipe(ialu_reg_reg);
8197 %}
8198
8199 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8200 %{
8201 match(Set dst (SubI dst src));
8202 effect(KILL cr);
8203
8204 format %{ "subl $dst, $src\t# int" %}
8205 opcode(0x81, 0x05); /* Opcode 81 /5 */
8206 ins_encode(OpcSErm(dst, src), Con8or32(src));
8207 ins_pipe(ialu_reg);
8208 %}
8209
8210 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8211 %{
8212 match(Set dst (SubI dst (LoadI src)));
8213 effect(KILL cr);
8214
8215 ins_cost(125);
8216 format %{ "subl $dst, $src\t# int" %}
8217 opcode(0x2B);
8218 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8219 ins_pipe(ialu_reg_mem);
8220 %}
8221
8222 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8223 %{
8224 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8225 effect(KILL cr);
8226
8227 ins_cost(150);
8228 format %{ "subl $dst, $src\t# int" %}
8229 opcode(0x29); /* Opcode 29 /r */
8230 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8231 ins_pipe(ialu_mem_reg);
8232 %}
8233
8234 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8235 %{
8236 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8237 effect(KILL cr);
8238
8239 ins_cost(125); // XXX
8240 format %{ "subl $dst, $src\t# int" %}
8241 opcode(0x81); /* Opcode 81 /5 id */
8242 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8243 ins_pipe(ialu_mem_imm);
8244 %}
8245
8246 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8247 %{
8248 match(Set dst (SubL dst src));
8249 effect(KILL cr);
8250
8251 format %{ "subq $dst, $src\t# long" %}
8252 opcode(0x2B);
8253 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8254 ins_pipe(ialu_reg_reg);
8255 %}
8256
8257 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8258 %{
8259 match(Set dst (SubL dst src));
8260 effect(KILL cr);
8261
8262 format %{ "subq $dst, $src\t# long" %}
8263 opcode(0x81, 0x05); /* Opcode 81 /5 */
8264 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8265 ins_pipe(ialu_reg);
8266 %}
8267
8268 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8269 %{
8270 match(Set dst (SubL dst (LoadL src)));
8271 effect(KILL cr);
8272
8273 ins_cost(125);
8274 format %{ "subq $dst, $src\t# long" %}
8275 opcode(0x2B);
8276 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8277 ins_pipe(ialu_reg_mem);
8278 %}
8279
8280 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8281 %{
8282 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8283 effect(KILL cr);
8284
8285 ins_cost(150);
8286 format %{ "subq $dst, $src\t# long" %}
8287 opcode(0x29); /* Opcode 29 /r */
8288 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8289 ins_pipe(ialu_mem_reg);
8290 %}
8291
8292 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8293 %{
8294 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8295 effect(KILL cr);
8296
8297 ins_cost(125); // XXX
8298 format %{ "subq $dst, $src\t# long" %}
8299 opcode(0x81); /* Opcode 81 /5 id */
8300 ins_encode(REX_mem_wide(dst),
8301 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8302 ins_pipe(ialu_mem_imm);
8303 %}
8304
8305 // Subtract from a pointer
8306 // XXX hmpf???
8307 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8308 %{
8309 match(Set dst (AddP dst (SubI zero src)));
8310 effect(KILL cr);
8311
8312 format %{ "subq $dst, $src\t# ptr - int" %}
8313 opcode(0x2B);
8314 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8315 ins_pipe(ialu_reg_reg);
8316 %}
8317
8318 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8319 %{
8320 match(Set dst (SubI zero dst));
8321 effect(KILL cr);
8322
8323 format %{ "negl $dst\t# int" %}
8324 opcode(0xF7, 0x03); // Opcode F7 /3
8325 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8326 ins_pipe(ialu_reg);
8327 %}
8328
8329 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8330 %{
8331 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8332 effect(KILL cr);
8333
8334 format %{ "negl $dst\t# int" %}
8335 opcode(0xF7, 0x03); // Opcode F7 /3
8336 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8337 ins_pipe(ialu_reg);
8338 %}
8339
8340 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8341 %{
8342 match(Set dst (SubL zero dst));
8343 effect(KILL cr);
8344
8345 format %{ "negq $dst\t# long" %}
8346 opcode(0xF7, 0x03); // Opcode F7 /3
8347 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8348 ins_pipe(ialu_reg);
8349 %}
8350
8351 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8352 %{
8353 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8354 effect(KILL cr);
8355
8356 format %{ "negq $dst\t# long" %}
8357 opcode(0xF7, 0x03); // Opcode F7 /3
8358 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8359 ins_pipe(ialu_reg);
8360 %}
8361
8362 //----------Multiplication/Division Instructions-------------------------------
8363 // Integer Multiplication Instructions
8364 // Multiply Register
8365
8366 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8367 %{
8368 match(Set dst (MulI dst src));
8369 effect(KILL cr);
8370
8371 ins_cost(300);
8372 format %{ "imull $dst, $src\t# int" %}
8373 opcode(0x0F, 0xAF);
8374 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8375 ins_pipe(ialu_reg_reg_alu0);
8376 %}
8377
8378 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8379 %{
8380 match(Set dst (MulI src imm));
8381 effect(KILL cr);
8382
8383 ins_cost(300);
8384 format %{ "imull $dst, $src, $imm\t# int" %}
8385 opcode(0x69); /* 69 /r id */
8386 ins_encode(REX_reg_reg(dst, src),
8387 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8388 ins_pipe(ialu_reg_reg_alu0);
8389 %}
8390
8391 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8392 %{
8393 match(Set dst (MulI dst (LoadI src)));
8394 effect(KILL cr);
8395
8396 ins_cost(350);
8397 format %{ "imull $dst, $src\t# int" %}
8398 opcode(0x0F, 0xAF);
8399 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8400 ins_pipe(ialu_reg_mem_alu0);
8401 %}
8402
8403 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8404 %{
8405 match(Set dst (MulI (LoadI src) imm));
8406 effect(KILL cr);
8407
8408 ins_cost(300);
8409 format %{ "imull $dst, $src, $imm\t# int" %}
8410 opcode(0x69); /* 69 /r id */
8411 ins_encode(REX_reg_mem(dst, src),
8412 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8413 ins_pipe(ialu_reg_mem_alu0);
8414 %}
8415
8416 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8417 %{
8418 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8419 effect(KILL cr, KILL src2);
8420
8421 expand %{ mulI_rReg(dst, src1, cr);
8422 mulI_rReg(src2, src3, cr);
8423 addI_rReg(dst, src2, cr); %}
8424 %}
8425
8426 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8427 %{
8428 match(Set dst (MulL dst src));
8429 effect(KILL cr);
8430
8431 ins_cost(300);
8432 format %{ "imulq $dst, $src\t# long" %}
8433 opcode(0x0F, 0xAF);
8434 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8435 ins_pipe(ialu_reg_reg_alu0);
8436 %}
8437
8438 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8439 %{
8440 match(Set dst (MulL src imm));
8441 effect(KILL cr);
8442
8443 ins_cost(300);
8444 format %{ "imulq $dst, $src, $imm\t# long" %}
8445 opcode(0x69); /* 69 /r id */
8446 ins_encode(REX_reg_reg_wide(dst, src),
8447 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8448 ins_pipe(ialu_reg_reg_alu0);
8449 %}
8450
8451 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8452 %{
8453 match(Set dst (MulL dst (LoadL src)));
8454 effect(KILL cr);
8455
8456 ins_cost(350);
8457 format %{ "imulq $dst, $src\t# long" %}
8458 opcode(0x0F, 0xAF);
8459 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8460 ins_pipe(ialu_reg_mem_alu0);
8461 %}
8462
8463 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8464 %{
8465 match(Set dst (MulL (LoadL src) imm));
8466 effect(KILL cr);
8467
8468 ins_cost(300);
8469 format %{ "imulq $dst, $src, $imm\t# long" %}
8470 opcode(0x69); /* 69 /r id */
8471 ins_encode(REX_reg_mem_wide(dst, src),
8472 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8473 ins_pipe(ialu_reg_mem_alu0);
8474 %}
8475
8476 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8477 %{
8478 match(Set dst (MulHiL src rax));
8479 effect(USE_KILL rax, KILL cr);
8480
8481 ins_cost(300);
8482 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8483 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8484 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8485 ins_pipe(ialu_reg_reg_alu0);
8486 %}
8487
8488 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8489 rFlagsReg cr)
8490 %{
8491 match(Set rax (DivI rax div));
8492 effect(KILL rdx, KILL cr);
8493
8494 ins_cost(30*100+10*100); // XXX
8495 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8496 "jne,s normal\n\t"
8497 "xorl rdx, rdx\n\t"
8498 "cmpl $div, -1\n\t"
8499 "je,s done\n"
8500 "normal: cdql\n\t"
8501 "idivl $div\n"
8502 "done:" %}
8503 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8504 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8505 ins_pipe(ialu_reg_reg_alu0);
8506 %}
8507
8508 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8509 rFlagsReg cr)
8510 %{
8511 match(Set rax (DivL rax div));
8512 effect(KILL rdx, KILL cr);
8513
8514 ins_cost(30*100+10*100); // XXX
8515 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8516 "cmpq rax, rdx\n\t"
8517 "jne,s normal\n\t"
8518 "xorl rdx, rdx\n\t"
8519 "cmpq $div, -1\n\t"
8520 "je,s done\n"
8521 "normal: cdqq\n\t"
8522 "idivq $div\n"
8523 "done:" %}
8524 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8525 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8526 ins_pipe(ialu_reg_reg_alu0);
8527 %}
8528
8529 // Integer DIVMOD with Register, both quotient and mod results
8530 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8531 rFlagsReg cr)
8532 %{
8533 match(DivModI rax div);
8534 effect(KILL cr);
8535
8536 ins_cost(30*100+10*100); // XXX
8537 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8538 "jne,s normal\n\t"
8539 "xorl rdx, rdx\n\t"
8540 "cmpl $div, -1\n\t"
8541 "je,s done\n"
8542 "normal: cdql\n\t"
8543 "idivl $div\n"
8544 "done:" %}
8545 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8546 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8547 ins_pipe(pipe_slow);
8548 %}
8549
8550 // Long DIVMOD with Register, both quotient and mod results
8551 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8552 rFlagsReg cr)
8553 %{
8554 match(DivModL rax div);
8555 effect(KILL cr);
8556
8557 ins_cost(30*100+10*100); // XXX
8558 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8559 "cmpq rax, rdx\n\t"
8560 "jne,s normal\n\t"
8561 "xorl rdx, rdx\n\t"
8562 "cmpq $div, -1\n\t"
8563 "je,s done\n"
8564 "normal: cdqq\n\t"
8565 "idivq $div\n"
8566 "done:" %}
8567 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8568 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8569 ins_pipe(pipe_slow);
8570 %}
8571
8572 //----------- DivL-By-Constant-Expansions--------------------------------------
8573 // DivI cases are handled by the compiler
8574
8575 // Magic constant, reciprocal of 10
8576 instruct loadConL_0x6666666666666667(rRegL dst)
8577 %{
8578 effect(DEF dst);
8579
8580 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8581 ins_encode(load_immL(dst, 0x6666666666666667));
8582 ins_pipe(ialu_reg);
8583 %}
8584
8585 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8586 %{
8587 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8588
8589 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8590 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8591 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8592 ins_pipe(ialu_reg_reg_alu0);
8593 %}
8594
8595 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8596 %{
8597 effect(USE_DEF dst, KILL cr);
8598
8599 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8600 opcode(0xC1, 0x7); /* C1 /7 ib */
8601 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8602 ins_pipe(ialu_reg);
8603 %}
8604
8605 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8606 %{
8607 effect(USE_DEF dst, KILL cr);
8608
8609 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8610 opcode(0xC1, 0x7); /* C1 /7 ib */
8611 ins_encode(reg_opc_imm_wide(dst, 0x2));
8612 ins_pipe(ialu_reg);
8613 %}
8614
8615 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8616 %{
8617 match(Set dst (DivL src div));
8618
8619 ins_cost((5+8)*100);
8620 expand %{
8621 rax_RegL rax; // Killed temp
8622 rFlagsReg cr; // Killed
8623 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8624 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8625 sarL_rReg_63(src, cr); // sarq src, 63
8626 sarL_rReg_2(dst, cr); // sarq rdx, 2
8627 subL_rReg(dst, src, cr); // subl rdx, src
8628 %}
8629 %}
8630
8631 //-----------------------------------------------------------------------------
8632
8633 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8634 rFlagsReg cr)
8635 %{
8636 match(Set rdx (ModI rax div));
8637 effect(KILL rax, KILL cr);
8638
8639 ins_cost(300); // XXX
8640 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8641 "jne,s normal\n\t"
8642 "xorl rdx, rdx\n\t"
8643 "cmpl $div, -1\n\t"
8644 "je,s done\n"
8645 "normal: cdql\n\t"
8646 "idivl $div\n"
8647 "done:" %}
8648 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8649 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8650 ins_pipe(ialu_reg_reg_alu0);
8651 %}
8652
8653 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8654 rFlagsReg cr)
8655 %{
8656 match(Set rdx (ModL rax div));
8657 effect(KILL rax, KILL cr);
8658
8659 ins_cost(300); // XXX
8660 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8661 "cmpq rax, rdx\n\t"
8662 "jne,s normal\n\t"
8663 "xorl rdx, rdx\n\t"
8664 "cmpq $div, -1\n\t"
8665 "je,s done\n"
8666 "normal: cdqq\n\t"
8667 "idivq $div\n"
8668 "done:" %}
8669 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8670 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8671 ins_pipe(ialu_reg_reg_alu0);
8672 %}
8673
8674 // Integer Shift Instructions
8675 // Shift Left by one
8676 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8677 %{
8678 match(Set dst (LShiftI dst shift));
8679 effect(KILL cr);
8680
8681 format %{ "sall $dst, $shift" %}
8682 opcode(0xD1, 0x4); /* D1 /4 */
8683 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8684 ins_pipe(ialu_reg);
8685 %}
8686
8687 // Shift Left by one
8688 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8689 %{
8690 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8691 effect(KILL cr);
8692
8693 format %{ "sall $dst, $shift\t" %}
8694 opcode(0xD1, 0x4); /* D1 /4 */
8695 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8696 ins_pipe(ialu_mem_imm);
8697 %}
8698
8699 // Shift Left by 8-bit immediate
8700 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8701 %{
8702 match(Set dst (LShiftI dst shift));
8703 effect(KILL cr);
8704
8705 format %{ "sall $dst, $shift" %}
8706 opcode(0xC1, 0x4); /* C1 /4 ib */
8707 ins_encode(reg_opc_imm(dst, shift));
8708 ins_pipe(ialu_reg);
8709 %}
8710
8711 // Shift Left by 8-bit immediate
8712 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8713 %{
8714 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8715 effect(KILL cr);
8716
8717 format %{ "sall $dst, $shift" %}
8718 opcode(0xC1, 0x4); /* C1 /4 ib */
8719 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8720 ins_pipe(ialu_mem_imm);
8721 %}
8722
8723 // Shift Left by variable
8724 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8725 %{
8726 match(Set dst (LShiftI dst shift));
8727 effect(KILL cr);
8728
8729 format %{ "sall $dst, $shift" %}
8730 opcode(0xD3, 0x4); /* D3 /4 */
8731 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8732 ins_pipe(ialu_reg_reg);
8733 %}
8734
8735 // Shift Left by variable
8736 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8737 %{
8738 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8739 effect(KILL cr);
8740
8741 format %{ "sall $dst, $shift" %}
8742 opcode(0xD3, 0x4); /* D3 /4 */
8743 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8744 ins_pipe(ialu_mem_reg);
8745 %}
8746
8747 // Arithmetic shift right by one
8748 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8749 %{
8750 match(Set dst (RShiftI dst shift));
8751 effect(KILL cr);
8752
8753 format %{ "sarl $dst, $shift" %}
8754 opcode(0xD1, 0x7); /* D1 /7 */
8755 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8756 ins_pipe(ialu_reg);
8757 %}
8758
8759 // Arithmetic shift right by one
8760 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8761 %{
8762 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8763 effect(KILL cr);
8764
8765 format %{ "sarl $dst, $shift" %}
8766 opcode(0xD1, 0x7); /* D1 /7 */
8767 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8768 ins_pipe(ialu_mem_imm);
8769 %}
8770
8771 // Arithmetic Shift Right by 8-bit immediate
8772 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8773 %{
8774 match(Set dst (RShiftI dst shift));
8775 effect(KILL cr);
8776
8777 format %{ "sarl $dst, $shift" %}
8778 opcode(0xC1, 0x7); /* C1 /7 ib */
8779 ins_encode(reg_opc_imm(dst, shift));
8780 ins_pipe(ialu_mem_imm);
8781 %}
8782
8783 // Arithmetic Shift Right by 8-bit immediate
8784 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8785 %{
8786 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8787 effect(KILL cr);
8788
8789 format %{ "sarl $dst, $shift" %}
8790 opcode(0xC1, 0x7); /* C1 /7 ib */
8791 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8792 ins_pipe(ialu_mem_imm);
8793 %}
8794
8795 // Arithmetic Shift Right by variable
8796 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8797 %{
8798 match(Set dst (RShiftI dst shift));
8799 effect(KILL cr);
8800
8801 format %{ "sarl $dst, $shift" %}
8802 opcode(0xD3, 0x7); /* D3 /7 */
8803 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8804 ins_pipe(ialu_reg_reg);
8805 %}
8806
8807 // Arithmetic Shift Right by variable
8808 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8809 %{
8810 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8811 effect(KILL cr);
8812
8813 format %{ "sarl $dst, $shift" %}
8814 opcode(0xD3, 0x7); /* D3 /7 */
8815 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8816 ins_pipe(ialu_mem_reg);
8817 %}
8818
8819 // Logical shift right by one
8820 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8821 %{
8822 match(Set dst (URShiftI dst shift));
8823 effect(KILL cr);
8824
8825 format %{ "shrl $dst, $shift" %}
8826 opcode(0xD1, 0x5); /* D1 /5 */
8827 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8828 ins_pipe(ialu_reg);
8829 %}
8830
8831 // Logical shift right by one
8832 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8833 %{
8834 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8835 effect(KILL cr);
8836
8837 format %{ "shrl $dst, $shift" %}
8838 opcode(0xD1, 0x5); /* D1 /5 */
8839 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8840 ins_pipe(ialu_mem_imm);
8841 %}
8842
8843 // Logical Shift Right by 8-bit immediate
8844 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8845 %{
8846 match(Set dst (URShiftI dst shift));
8847 effect(KILL cr);
8848
8849 format %{ "shrl $dst, $shift" %}
8850 opcode(0xC1, 0x5); /* C1 /5 ib */
8851 ins_encode(reg_opc_imm(dst, shift));
8852 ins_pipe(ialu_reg);
8853 %}
8854
8855 // Logical Shift Right by 8-bit immediate
8856 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8857 %{
8858 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8859 effect(KILL cr);
8860
8861 format %{ "shrl $dst, $shift" %}
8862 opcode(0xC1, 0x5); /* C1 /5 ib */
8863 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8864 ins_pipe(ialu_mem_imm);
8865 %}
8866
8867 // Logical Shift Right by variable
8868 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8869 %{
8870 match(Set dst (URShiftI dst shift));
8871 effect(KILL cr);
8872
8873 format %{ "shrl $dst, $shift" %}
8874 opcode(0xD3, 0x5); /* D3 /5 */
8875 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8876 ins_pipe(ialu_reg_reg);
8877 %}
8878
8879 // Logical Shift Right by variable
8880 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8881 %{
8882 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8883 effect(KILL cr);
8884
8885 format %{ "shrl $dst, $shift" %}
8886 opcode(0xD3, 0x5); /* D3 /5 */
8887 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8888 ins_pipe(ialu_mem_reg);
8889 %}
8890
8891 // Long Shift Instructions
8892 // Shift Left by one
8893 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8894 %{
8895 match(Set dst (LShiftL dst shift));
8896 effect(KILL cr);
8897
8898 format %{ "salq $dst, $shift" %}
8899 opcode(0xD1, 0x4); /* D1 /4 */
8900 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8901 ins_pipe(ialu_reg);
8902 %}
8903
8904 // Shift Left by one
8905 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8906 %{
8907 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8908 effect(KILL cr);
8909
8910 format %{ "salq $dst, $shift" %}
8911 opcode(0xD1, 0x4); /* D1 /4 */
8912 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8913 ins_pipe(ialu_mem_imm);
8914 %}
8915
8916 // Shift Left by 8-bit immediate
8917 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8918 %{
8919 match(Set dst (LShiftL dst shift));
8920 effect(KILL cr);
8921
8922 format %{ "salq $dst, $shift" %}
8923 opcode(0xC1, 0x4); /* C1 /4 ib */
8924 ins_encode(reg_opc_imm_wide(dst, shift));
8925 ins_pipe(ialu_reg);
8926 %}
8927
8928 // Shift Left by 8-bit immediate
8929 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8930 %{
8931 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8932 effect(KILL cr);
8933
8934 format %{ "salq $dst, $shift" %}
8935 opcode(0xC1, 0x4); /* C1 /4 ib */
8936 ins_encode(REX_mem_wide(dst), OpcP,
8937 RM_opc_mem(secondary, dst), Con8or32(shift));
8938 ins_pipe(ialu_mem_imm);
8939 %}
8940
8941 // Shift Left by variable
8942 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8943 %{
8944 match(Set dst (LShiftL dst shift));
8945 effect(KILL cr);
8946
8947 format %{ "salq $dst, $shift" %}
8948 opcode(0xD3, 0x4); /* D3 /4 */
8949 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8950 ins_pipe(ialu_reg_reg);
8951 %}
8952
8953 // Shift Left by variable
8954 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8955 %{
8956 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8957 effect(KILL cr);
8958
8959 format %{ "salq $dst, $shift" %}
8960 opcode(0xD3, 0x4); /* D3 /4 */
8961 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8962 ins_pipe(ialu_mem_reg);
8963 %}
8964
8965 // Arithmetic shift right by one
8966 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8967 %{
8968 match(Set dst (RShiftL dst shift));
8969 effect(KILL cr);
8970
8971 format %{ "sarq $dst, $shift" %}
8972 opcode(0xD1, 0x7); /* D1 /7 */
8973 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8974 ins_pipe(ialu_reg);
8975 %}
8976
8977 // Arithmetic shift right by one
8978 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8979 %{
8980 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8981 effect(KILL cr);
8982
8983 format %{ "sarq $dst, $shift" %}
8984 opcode(0xD1, 0x7); /* D1 /7 */
8985 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8986 ins_pipe(ialu_mem_imm);
8987 %}
8988
8989 // Arithmetic Shift Right by 8-bit immediate
8990 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8991 %{
8992 match(Set dst (RShiftL dst shift));
8993 effect(KILL cr);
8994
8995 format %{ "sarq $dst, $shift" %}
8996 opcode(0xC1, 0x7); /* C1 /7 ib */
8997 ins_encode(reg_opc_imm_wide(dst, shift));
8998 ins_pipe(ialu_mem_imm);
8999 %}
9000
9001 // Arithmetic Shift Right by 8-bit immediate
9002 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9003 %{
9004 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9005 effect(KILL cr);
9006
9007 format %{ "sarq $dst, $shift" %}
9008 opcode(0xC1, 0x7); /* C1 /7 ib */
9009 ins_encode(REX_mem_wide(dst), OpcP,
9010 RM_opc_mem(secondary, dst), Con8or32(shift));
9011 ins_pipe(ialu_mem_imm);
9012 %}
9013
9014 // Arithmetic Shift Right by variable
9015 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9016 %{
9017 match(Set dst (RShiftL dst shift));
9018 effect(KILL cr);
9019
9020 format %{ "sarq $dst, $shift" %}
9021 opcode(0xD3, 0x7); /* D3 /7 */
9022 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9023 ins_pipe(ialu_reg_reg);
9024 %}
9025
9026 // Arithmetic Shift Right by variable
9027 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9028 %{
9029 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9030 effect(KILL cr);
9031
9032 format %{ "sarq $dst, $shift" %}
9033 opcode(0xD3, 0x7); /* D3 /7 */
9034 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9035 ins_pipe(ialu_mem_reg);
9036 %}
9037
9038 // Logical shift right by one
9039 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9040 %{
9041 match(Set dst (URShiftL dst shift));
9042 effect(KILL cr);
9043
9044 format %{ "shrq $dst, $shift" %}
9045 opcode(0xD1, 0x5); /* D1 /5 */
9046 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9047 ins_pipe(ialu_reg);
9048 %}
9049
9050 // Logical shift right by one
9051 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9052 %{
9053 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9054 effect(KILL cr);
9055
9056 format %{ "shrq $dst, $shift" %}
9057 opcode(0xD1, 0x5); /* D1 /5 */
9058 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9059 ins_pipe(ialu_mem_imm);
9060 %}
9061
9062 // Logical Shift Right by 8-bit immediate
9063 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9064 %{
9065 match(Set dst (URShiftL dst shift));
9066 effect(KILL cr);
9067
9068 format %{ "shrq $dst, $shift" %}
9069 opcode(0xC1, 0x5); /* C1 /5 ib */
9070 ins_encode(reg_opc_imm_wide(dst, shift));
9071 ins_pipe(ialu_reg);
9072 %}
9073
9074
9075 // Logical Shift Right by 8-bit immediate
9076 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9077 %{
9078 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9079 effect(KILL cr);
9080
9081 format %{ "shrq $dst, $shift" %}
9082 opcode(0xC1, 0x5); /* C1 /5 ib */
9083 ins_encode(REX_mem_wide(dst), OpcP,
9084 RM_opc_mem(secondary, dst), Con8or32(shift));
9085 ins_pipe(ialu_mem_imm);
9086 %}
9087
9088 // Logical Shift Right by variable
9089 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9090 %{
9091 match(Set dst (URShiftL dst shift));
9092 effect(KILL cr);
9093
9094 format %{ "shrq $dst, $shift" %}
9095 opcode(0xD3, 0x5); /* D3 /5 */
9096 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9097 ins_pipe(ialu_reg_reg);
9098 %}
9099
9100 // Logical Shift Right by variable
9101 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9102 %{
9103 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9104 effect(KILL cr);
9105
9106 format %{ "shrq $dst, $shift" %}
9107 opcode(0xD3, 0x5); /* D3 /5 */
9108 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9109 ins_pipe(ialu_mem_reg);
9110 %}
9111
9112 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9113 // This idiom is used by the compiler for the i2b bytecode.
9114 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9115 %{
9116 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9117
9118 format %{ "movsbl $dst, $src\t# i2b" %}
9119 opcode(0x0F, 0xBE);
9120 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9121 ins_pipe(ialu_reg_reg);
9122 %}
9123
9124 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9125 // This idiom is used by the compiler the i2s bytecode.
9126 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9127 %{
9128 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9129
9130 format %{ "movswl $dst, $src\t# i2s" %}
9131 opcode(0x0F, 0xBF);
9132 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9133 ins_pipe(ialu_reg_reg);
9134 %}
9135
9136 // ROL/ROR instructions
9137
9138 // ROL expand
9139 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9140 effect(KILL cr, USE_DEF dst);
9141
9142 format %{ "roll $dst" %}
9143 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9144 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9145 ins_pipe(ialu_reg);
9146 %}
9147
9148 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9149 effect(USE_DEF dst, USE shift, KILL cr);
9150
9151 format %{ "roll $dst, $shift" %}
9152 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9153 ins_encode( reg_opc_imm(dst, shift) );
9154 ins_pipe(ialu_reg);
9155 %}
9156
9157 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9158 %{
9159 effect(USE_DEF dst, USE shift, KILL cr);
9160
9161 format %{ "roll $dst, $shift" %}
9162 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9163 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9164 ins_pipe(ialu_reg_reg);
9165 %}
9166 // end of ROL expand
9167
9168 // Rotate Left by one
9169 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9170 %{
9171 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9172
9173 expand %{
9174 rolI_rReg_imm1(dst, cr);
9175 %}
9176 %}
9177
9178 // Rotate Left by 8-bit immediate
9179 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9180 %{
9181 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9182 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9183
9184 expand %{
9185 rolI_rReg_imm8(dst, lshift, cr);
9186 %}
9187 %}
9188
9189 // Rotate Left by variable
9190 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9191 %{
9192 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9193
9194 expand %{
9195 rolI_rReg_CL(dst, shift, cr);
9196 %}
9197 %}
9198
9199 // Rotate Left by variable
9200 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9201 %{
9202 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9203
9204 expand %{
9205 rolI_rReg_CL(dst, shift, cr);
9206 %}
9207 %}
9208
9209 // ROR expand
9210 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9211 %{
9212 effect(USE_DEF dst, KILL cr);
9213
9214 format %{ "rorl $dst" %}
9215 opcode(0xD1, 0x1); /* D1 /1 */
9216 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9217 ins_pipe(ialu_reg);
9218 %}
9219
9220 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9221 %{
9222 effect(USE_DEF dst, USE shift, KILL cr);
9223
9224 format %{ "rorl $dst, $shift" %}
9225 opcode(0xC1, 0x1); /* C1 /1 ib */
9226 ins_encode(reg_opc_imm(dst, shift));
9227 ins_pipe(ialu_reg);
9228 %}
9229
9230 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9231 %{
9232 effect(USE_DEF dst, USE shift, KILL cr);
9233
9234 format %{ "rorl $dst, $shift" %}
9235 opcode(0xD3, 0x1); /* D3 /1 */
9236 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9237 ins_pipe(ialu_reg_reg);
9238 %}
9239 // end of ROR expand
9240
9241 // Rotate Right by one
9242 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9243 %{
9244 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9245
9246 expand %{
9247 rorI_rReg_imm1(dst, cr);
9248 %}
9249 %}
9250
9251 // Rotate Right by 8-bit immediate
9252 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9253 %{
9254 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9255 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9256
9257 expand %{
9258 rorI_rReg_imm8(dst, rshift, cr);
9259 %}
9260 %}
9261
9262 // Rotate Right by variable
9263 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9264 %{
9265 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9266
9267 expand %{
9268 rorI_rReg_CL(dst, shift, cr);
9269 %}
9270 %}
9271
9272 // Rotate Right by variable
9273 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9274 %{
9275 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9276
9277 expand %{
9278 rorI_rReg_CL(dst, shift, cr);
9279 %}
9280 %}
9281
9282 // for long rotate
9283 // ROL expand
9284 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9285 effect(USE_DEF dst, KILL cr);
9286
9287 format %{ "rolq $dst" %}
9288 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9289 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9290 ins_pipe(ialu_reg);
9291 %}
9292
9293 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9294 effect(USE_DEF dst, USE shift, KILL cr);
9295
9296 format %{ "rolq $dst, $shift" %}
9297 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9298 ins_encode( reg_opc_imm_wide(dst, shift) );
9299 ins_pipe(ialu_reg);
9300 %}
9301
9302 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9303 %{
9304 effect(USE_DEF dst, USE shift, KILL cr);
9305
9306 format %{ "rolq $dst, $shift" %}
9307 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9308 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9309 ins_pipe(ialu_reg_reg);
9310 %}
9311 // end of ROL expand
9312
9313 // Rotate Left by one
9314 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9315 %{
9316 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9317
9318 expand %{
9319 rolL_rReg_imm1(dst, cr);
9320 %}
9321 %}
9322
9323 // Rotate Left by 8-bit immediate
9324 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9325 %{
9326 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9327 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9328
9329 expand %{
9330 rolL_rReg_imm8(dst, lshift, cr);
9331 %}
9332 %}
9333
9334 // Rotate Left by variable
9335 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9336 %{
9337 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9338
9339 expand %{
9340 rolL_rReg_CL(dst, shift, cr);
9341 %}
9342 %}
9343
9344 // Rotate Left by variable
9345 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9346 %{
9347 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9348
9349 expand %{
9350 rolL_rReg_CL(dst, shift, cr);
9351 %}
9352 %}
9353
9354 // ROR expand
9355 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9356 %{
9357 effect(USE_DEF dst, KILL cr);
9358
9359 format %{ "rorq $dst" %}
9360 opcode(0xD1, 0x1); /* D1 /1 */
9361 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9362 ins_pipe(ialu_reg);
9363 %}
9364
9365 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9366 %{
9367 effect(USE_DEF dst, USE shift, KILL cr);
9368
9369 format %{ "rorq $dst, $shift" %}
9370 opcode(0xC1, 0x1); /* C1 /1 ib */
9371 ins_encode(reg_opc_imm_wide(dst, shift));
9372 ins_pipe(ialu_reg);
9373 %}
9374
9375 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9376 %{
9377 effect(USE_DEF dst, USE shift, KILL cr);
9378
9379 format %{ "rorq $dst, $shift" %}
9380 opcode(0xD3, 0x1); /* D3 /1 */
9381 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9382 ins_pipe(ialu_reg_reg);
9383 %}
9384 // end of ROR expand
9385
9386 // Rotate Right by one
9387 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9388 %{
9389 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9390
9391 expand %{
9392 rorL_rReg_imm1(dst, cr);
9393 %}
9394 %}
9395
9396 // Rotate Right by 8-bit immediate
9397 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9398 %{
9399 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9400 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9401
9402 expand %{
9403 rorL_rReg_imm8(dst, rshift, cr);
9404 %}
9405 %}
9406
9407 // Rotate Right by variable
9408 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9409 %{
9410 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9411
9412 expand %{
9413 rorL_rReg_CL(dst, shift, cr);
9414 %}
9415 %}
9416
9417 // Rotate Right by variable
9418 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9419 %{
9420 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9421
9422 expand %{
9423 rorL_rReg_CL(dst, shift, cr);
9424 %}
9425 %}
9426
9427 // Logical Instructions
9428
9429 // Integer Logical Instructions
9430
9431 // And Instructions
9432 // And Register with Register
9433 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9434 %{
9435 match(Set dst (AndI dst src));
9436 effect(KILL cr);
9437
9438 format %{ "andl $dst, $src\t# int" %}
9439 opcode(0x23);
9440 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9441 ins_pipe(ialu_reg_reg);
9442 %}
9443
9444 // And Register with Immediate 255
9445 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9446 %{
9447 match(Set dst (AndI dst src));
9448
9449 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9450 opcode(0x0F, 0xB6);
9451 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9452 ins_pipe(ialu_reg);
9453 %}
9454
9455 // And Register with Immediate 255 and promote to long
9456 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9457 %{
9458 match(Set dst (ConvI2L (AndI src mask)));
9459
9460 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9461 opcode(0x0F, 0xB6);
9462 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9463 ins_pipe(ialu_reg);
9464 %}
9465
9466 // And Register with Immediate 65535
9467 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9468 %{
9469 match(Set dst (AndI dst src));
9470
9471 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9472 opcode(0x0F, 0xB7);
9473 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9474 ins_pipe(ialu_reg);
9475 %}
9476
9477 // And Register with Immediate 65535 and promote to long
9478 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9479 %{
9480 match(Set dst (ConvI2L (AndI src mask)));
9481
9482 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9483 opcode(0x0F, 0xB7);
9484 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9485 ins_pipe(ialu_reg);
9486 %}
9487
9488 // And Register with Immediate
9489 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9490 %{
9491 match(Set dst (AndI dst src));
9492 effect(KILL cr);
9493
9494 format %{ "andl $dst, $src\t# int" %}
9495 opcode(0x81, 0x04); /* Opcode 81 /4 */
9496 ins_encode(OpcSErm(dst, src), Con8or32(src));
9497 ins_pipe(ialu_reg);
9498 %}
9499
9500 // And Register with Memory
9501 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9502 %{
9503 match(Set dst (AndI dst (LoadI src)));
9504 effect(KILL cr);
9505
9506 ins_cost(125);
9507 format %{ "andl $dst, $src\t# int" %}
9508 opcode(0x23);
9509 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9510 ins_pipe(ialu_reg_mem);
9511 %}
9512
9513 // And Memory with Register
9514 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9515 %{
9516 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9517 effect(KILL cr);
9518
9519 ins_cost(150);
9520 format %{ "andb $dst, $src\t# byte" %}
9521 opcode(0x20);
9522 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9523 ins_pipe(ialu_mem_reg);
9524 %}
9525
9526 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9527 %{
9528 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9529 effect(KILL cr);
9530
9531 ins_cost(150);
9532 format %{ "andl $dst, $src\t# int" %}
9533 opcode(0x21); /* Opcode 21 /r */
9534 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9535 ins_pipe(ialu_mem_reg);
9536 %}
9537
9538 // And Memory with Immediate
9539 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9540 %{
9541 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9542 effect(KILL cr);
9543
9544 ins_cost(125);
9545 format %{ "andl $dst, $src\t# int" %}
9546 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9547 ins_encode(REX_mem(dst), OpcSE(src),
9548 RM_opc_mem(secondary, dst), Con8or32(src));
9549 ins_pipe(ialu_mem_imm);
9550 %}
9551
9552 // BMI1 instructions
9553 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9554 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9555 predicate(UseBMI1Instructions);
9556 effect(KILL cr);
9557
9558 ins_cost(125);
9559 format %{ "andnl $dst, $src1, $src2" %}
9560
9561 ins_encode %{
9562 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9563 %}
9564 ins_pipe(ialu_reg_mem);
9565 %}
9566
9567 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9568 match(Set dst (AndI (XorI src1 minus_1) src2));
9569 predicate(UseBMI1Instructions);
9570 effect(KILL cr);
9571
9572 format %{ "andnl $dst, $src1, $src2" %}
9573
9574 ins_encode %{
9575 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9576 %}
9577 ins_pipe(ialu_reg);
9578 %}
9579
9580 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9581 match(Set dst (AndI (SubI imm_zero src) src));
9582 predicate(UseBMI1Instructions);
9583 effect(KILL cr);
9584
9585 format %{ "blsil $dst, $src" %}
9586
9587 ins_encode %{
9588 __ blsil($dst$$Register, $src$$Register);
9589 %}
9590 ins_pipe(ialu_reg);
9591 %}
9592
9593 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9594 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9595 predicate(UseBMI1Instructions);
9596 effect(KILL cr);
9597
9598 ins_cost(125);
9599 format %{ "blsil $dst, $src" %}
9600
9601 ins_encode %{
9602 __ blsil($dst$$Register, $src$$Address);
9603 %}
9604 ins_pipe(ialu_reg_mem);
9605 %}
9606
9607 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9608 %{
9609 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9610 predicate(UseBMI1Instructions);
9611 effect(KILL cr);
9612
9613 ins_cost(125);
9614 format %{ "blsmskl $dst, $src" %}
9615
9616 ins_encode %{
9617 __ blsmskl($dst$$Register, $src$$Address);
9618 %}
9619 ins_pipe(ialu_reg_mem);
9620 %}
9621
9622 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9623 %{
9624 match(Set dst (XorI (AddI src minus_1) src));
9625 predicate(UseBMI1Instructions);
9626 effect(KILL cr);
9627
9628 format %{ "blsmskl $dst, $src" %}
9629
9630 ins_encode %{
9631 __ blsmskl($dst$$Register, $src$$Register);
9632 %}
9633
9634 ins_pipe(ialu_reg);
9635 %}
9636
9637 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9638 %{
9639 match(Set dst (AndI (AddI src minus_1) src) );
9640 predicate(UseBMI1Instructions);
9641 effect(KILL cr);
9642
9643 format %{ "blsrl $dst, $src" %}
9644
9645 ins_encode %{
9646 __ blsrl($dst$$Register, $src$$Register);
9647 %}
9648
9649 ins_pipe(ialu_reg_mem);
9650 %}
9651
9652 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9653 %{
9654 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9655 predicate(UseBMI1Instructions);
9656 effect(KILL cr);
9657
9658 ins_cost(125);
9659 format %{ "blsrl $dst, $src" %}
9660
9661 ins_encode %{
9662 __ blsrl($dst$$Register, $src$$Address);
9663 %}
9664
9665 ins_pipe(ialu_reg);
9666 %}
9667
9668 // Or Instructions
9669 // Or Register with Register
9670 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9671 %{
9672 match(Set dst (OrI dst src));
9673 effect(KILL cr);
9674
9675 format %{ "orl $dst, $src\t# int" %}
9676 opcode(0x0B);
9677 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9678 ins_pipe(ialu_reg_reg);
9679 %}
9680
9681 // Or Register with Immediate
9682 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9683 %{
9684 match(Set dst (OrI dst src));
9685 effect(KILL cr);
9686
9687 format %{ "orl $dst, $src\t# int" %}
9688 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9689 ins_encode(OpcSErm(dst, src), Con8or32(src));
9690 ins_pipe(ialu_reg);
9691 %}
9692
9693 // Or Register with Memory
9694 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9695 %{
9696 match(Set dst (OrI dst (LoadI src)));
9697 effect(KILL cr);
9698
9699 ins_cost(125);
9700 format %{ "orl $dst, $src\t# int" %}
9701 opcode(0x0B);
9702 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9703 ins_pipe(ialu_reg_mem);
9704 %}
9705
9706 // Or Memory with Register
9707 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9708 %{
9709 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9710 effect(KILL cr);
9711
9712 ins_cost(150);
9713 format %{ "orb $dst, $src\t# byte" %}
9714 opcode(0x08);
9715 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9716 ins_pipe(ialu_mem_reg);
9717 %}
9718
9719 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9720 %{
9721 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9722 effect(KILL cr);
9723
9724 ins_cost(150);
9725 format %{ "orl $dst, $src\t# int" %}
9726 opcode(0x09); /* Opcode 09 /r */
9727 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9728 ins_pipe(ialu_mem_reg);
9729 %}
9730
9731 // Or Memory with Immediate
9732 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9733 %{
9734 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9735 effect(KILL cr);
9736
9737 ins_cost(125);
9738 format %{ "orl $dst, $src\t# int" %}
9739 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9740 ins_encode(REX_mem(dst), OpcSE(src),
9741 RM_opc_mem(secondary, dst), Con8or32(src));
9742 ins_pipe(ialu_mem_imm);
9743 %}
9744
9745 // Xor Instructions
9746 // Xor Register with Register
9747 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9748 %{
9749 match(Set dst (XorI dst src));
9750 effect(KILL cr);
9751
9752 format %{ "xorl $dst, $src\t# int" %}
9753 opcode(0x33);
9754 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9755 ins_pipe(ialu_reg_reg);
9756 %}
9757
9758 // Xor Register with Immediate -1
9759 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9760 match(Set dst (XorI dst imm));
9761
9762 format %{ "not $dst" %}
9763 ins_encode %{
9764 __ notl($dst$$Register);
9765 %}
9766 ins_pipe(ialu_reg);
9767 %}
9768
9769 // Xor Register with Immediate
9770 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9771 %{
9772 match(Set dst (XorI dst src));
9773 effect(KILL cr);
9774
9775 format %{ "xorl $dst, $src\t# int" %}
9776 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9777 ins_encode(OpcSErm(dst, src), Con8or32(src));
9778 ins_pipe(ialu_reg);
9779 %}
9780
9781 // Xor Register with Memory
9782 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9783 %{
9784 match(Set dst (XorI dst (LoadI src)));
9785 effect(KILL cr);
9786
9787 ins_cost(125);
9788 format %{ "xorl $dst, $src\t# int" %}
9789 opcode(0x33);
9790 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9791 ins_pipe(ialu_reg_mem);
9792 %}
9793
9794 // Xor Memory with Register
9795 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9796 %{
9797 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9798 effect(KILL cr);
9799
9800 ins_cost(150);
9801 format %{ "xorb $dst, $src\t# byte" %}
9802 opcode(0x30);
9803 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9804 ins_pipe(ialu_mem_reg);
9805 %}
9806
9807 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9808 %{
9809 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9810 effect(KILL cr);
9811
9812 ins_cost(150);
9813 format %{ "xorl $dst, $src\t# int" %}
9814 opcode(0x31); /* Opcode 31 /r */
9815 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9816 ins_pipe(ialu_mem_reg);
9817 %}
9818
9819 // Xor Memory with Immediate
9820 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9821 %{
9822 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9823 effect(KILL cr);
9824
9825 ins_cost(125);
9826 format %{ "xorl $dst, $src\t# int" %}
9827 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9828 ins_encode(REX_mem(dst), OpcSE(src),
9829 RM_opc_mem(secondary, dst), Con8or32(src));
9830 ins_pipe(ialu_mem_imm);
9831 %}
9832
9833
9834 // Long Logical Instructions
9835
9836 // And Instructions
9837 // And Register with Register
9838 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9839 %{
9840 match(Set dst (AndL dst src));
9841 effect(KILL cr);
9842
9843 format %{ "andq $dst, $src\t# long" %}
9844 opcode(0x23);
9845 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9846 ins_pipe(ialu_reg_reg);
9847 %}
9848
9849 // And Register with Immediate 255
9850 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9851 %{
9852 match(Set dst (AndL dst src));
9853
9854 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9855 opcode(0x0F, 0xB6);
9856 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9857 ins_pipe(ialu_reg);
9858 %}
9859
9860 // And Register with Immediate 65535
9861 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9862 %{
9863 match(Set dst (AndL dst src));
9864
9865 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9866 opcode(0x0F, 0xB7);
9867 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9868 ins_pipe(ialu_reg);
9869 %}
9870
9871 // And Register with Immediate
9872 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9873 %{
9874 match(Set dst (AndL dst src));
9875 effect(KILL cr);
9876
9877 format %{ "andq $dst, $src\t# long" %}
9878 opcode(0x81, 0x04); /* Opcode 81 /4 */
9879 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9880 ins_pipe(ialu_reg);
9881 %}
9882
9883 // And Register with Memory
9884 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9885 %{
9886 match(Set dst (AndL dst (LoadL src)));
9887 effect(KILL cr);
9888
9889 ins_cost(125);
9890 format %{ "andq $dst, $src\t# long" %}
9891 opcode(0x23);
9892 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9893 ins_pipe(ialu_reg_mem);
9894 %}
9895
9896 // And Memory with Register
9897 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9898 %{
9899 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9900 effect(KILL cr);
9901
9902 ins_cost(150);
9903 format %{ "andq $dst, $src\t# long" %}
9904 opcode(0x21); /* Opcode 21 /r */
9905 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9906 ins_pipe(ialu_mem_reg);
9907 %}
9908
9909 // And Memory with Immediate
9910 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9911 %{
9912 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9913 effect(KILL cr);
9914
9915 ins_cost(125);
9916 format %{ "andq $dst, $src\t# long" %}
9917 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9918 ins_encode(REX_mem_wide(dst), OpcSE(src),
9919 RM_opc_mem(secondary, dst), Con8or32(src));
9920 ins_pipe(ialu_mem_imm);
9921 %}
9922
9923 // BMI1 instructions
9924 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9925 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9926 predicate(UseBMI1Instructions);
9927 effect(KILL cr);
9928
9929 ins_cost(125);
9930 format %{ "andnq $dst, $src1, $src2" %}
9931
9932 ins_encode %{
9933 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9934 %}
9935 ins_pipe(ialu_reg_mem);
9936 %}
9937
9938 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9939 match(Set dst (AndL (XorL src1 minus_1) src2));
9940 predicate(UseBMI1Instructions);
9941 effect(KILL cr);
9942
9943 format %{ "andnq $dst, $src1, $src2" %}
9944
9945 ins_encode %{
9946 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9947 %}
9948 ins_pipe(ialu_reg_mem);
9949 %}
9950
9951 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9952 match(Set dst (AndL (SubL imm_zero src) src));
9953 predicate(UseBMI1Instructions);
9954 effect(KILL cr);
9955
9956 format %{ "blsiq $dst, $src" %}
9957
9958 ins_encode %{
9959 __ blsiq($dst$$Register, $src$$Register);
9960 %}
9961 ins_pipe(ialu_reg);
9962 %}
9963
9964 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9965 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9966 predicate(UseBMI1Instructions);
9967 effect(KILL cr);
9968
9969 ins_cost(125);
9970 format %{ "blsiq $dst, $src" %}
9971
9972 ins_encode %{
9973 __ blsiq($dst$$Register, $src$$Address);
9974 %}
9975 ins_pipe(ialu_reg_mem);
9976 %}
9977
9978 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9979 %{
9980 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9981 predicate(UseBMI1Instructions);
9982 effect(KILL cr);
9983
9984 ins_cost(125);
9985 format %{ "blsmskq $dst, $src" %}
9986
9987 ins_encode %{
9988 __ blsmskq($dst$$Register, $src$$Address);
9989 %}
9990 ins_pipe(ialu_reg_mem);
9991 %}
9992
9993 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9994 %{
9995 match(Set dst (XorL (AddL src minus_1) src));
9996 predicate(UseBMI1Instructions);
9997 effect(KILL cr);
9998
9999 format %{ "blsmskq $dst, $src" %}
10000
10001 ins_encode %{
10002 __ blsmskq($dst$$Register, $src$$Register);
10003 %}
10004
10005 ins_pipe(ialu_reg);
10006 %}
10007
10008 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10009 %{
10010 match(Set dst (AndL (AddL src minus_1) src) );
10011 predicate(UseBMI1Instructions);
10012 effect(KILL cr);
10013
10014 format %{ "blsrq $dst, $src" %}
10015
10016 ins_encode %{
10017 __ blsrq($dst$$Register, $src$$Register);
10018 %}
10019
10020 ins_pipe(ialu_reg);
10021 %}
10022
10023 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10024 %{
10025 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
10026 predicate(UseBMI1Instructions);
10027 effect(KILL cr);
10028
10029 ins_cost(125);
10030 format %{ "blsrq $dst, $src" %}
10031
10032 ins_encode %{
10033 __ blsrq($dst$$Register, $src$$Address);
10034 %}
10035
10036 ins_pipe(ialu_reg);
10037 %}
10038
10039 // Or Instructions
10040 // Or Register with Register
10041 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10042 %{
10043 match(Set dst (OrL dst src));
10044 effect(KILL cr);
10045
10046 format %{ "orq $dst, $src\t# long" %}
10047 opcode(0x0B);
10048 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10049 ins_pipe(ialu_reg_reg);
10050 %}
10051
10052 // Use any_RegP to match R15 (TLS register) without spilling.
10053 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10054 match(Set dst (OrL dst (CastP2X src)));
10055 effect(KILL cr);
10056
10057 format %{ "orq $dst, $src\t# long" %}
10058 opcode(0x0B);
10059 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10060 ins_pipe(ialu_reg_reg);
10061 %}
10062
10063
10064 // Or Register with Immediate
10065 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10066 %{
10067 match(Set dst (OrL dst src));
10068 effect(KILL cr);
10069
10070 format %{ "orq $dst, $src\t# long" %}
10071 opcode(0x81, 0x01); /* Opcode 81 /1 id */
10072 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10073 ins_pipe(ialu_reg);
10074 %}
10075
10076 // Or Register with Memory
10077 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10078 %{
10079 match(Set dst (OrL dst (LoadL src)));
10080 effect(KILL cr);
10081
10082 ins_cost(125);
10083 format %{ "orq $dst, $src\t# long" %}
10084 opcode(0x0B);
10085 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10086 ins_pipe(ialu_reg_mem);
10087 %}
10088
10089 // Or Memory with Register
10090 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10091 %{
10092 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10093 effect(KILL cr);
10094
10095 ins_cost(150);
10096 format %{ "orq $dst, $src\t# long" %}
10097 opcode(0x09); /* Opcode 09 /r */
10098 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10099 ins_pipe(ialu_mem_reg);
10100 %}
10101
10102 // Or Memory with Immediate
10103 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10104 %{
10105 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10106 effect(KILL cr);
10107
10108 ins_cost(125);
10109 format %{ "orq $dst, $src\t# long" %}
10110 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10111 ins_encode(REX_mem_wide(dst), OpcSE(src),
10112 RM_opc_mem(secondary, dst), Con8or32(src));
10113 ins_pipe(ialu_mem_imm);
10114 %}
10115
10116 // Xor Instructions
10117 // Xor Register with Register
10118 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10119 %{
10120 match(Set dst (XorL dst src));
10121 effect(KILL cr);
10122
10123 format %{ "xorq $dst, $src\t# long" %}
10124 opcode(0x33);
10125 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10126 ins_pipe(ialu_reg_reg);
10127 %}
10128
10129 // Xor Register with Immediate -1
10130 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10131 match(Set dst (XorL dst imm));
10132
10133 format %{ "notq $dst" %}
10134 ins_encode %{
10135 __ notq($dst$$Register);
10136 %}
10137 ins_pipe(ialu_reg);
10138 %}
10139
10140 // Xor Register with Immediate
10141 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10142 %{
10143 match(Set dst (XorL dst src));
10144 effect(KILL cr);
10145
10146 format %{ "xorq $dst, $src\t# long" %}
10147 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10148 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10149 ins_pipe(ialu_reg);
10150 %}
10151
10152 // Xor Register with Memory
10153 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10154 %{
10155 match(Set dst (XorL dst (LoadL src)));
10156 effect(KILL cr);
10157
10158 ins_cost(125);
10159 format %{ "xorq $dst, $src\t# long" %}
10160 opcode(0x33);
10161 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10162 ins_pipe(ialu_reg_mem);
10163 %}
10164
10165 // Xor Memory with Register
10166 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10167 %{
10168 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10169 effect(KILL cr);
10170
10171 ins_cost(150);
10172 format %{ "xorq $dst, $src\t# long" %}
10173 opcode(0x31); /* Opcode 31 /r */
10174 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10175 ins_pipe(ialu_mem_reg);
10176 %}
10177
10178 // Xor Memory with Immediate
10179 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10180 %{
10181 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10182 effect(KILL cr);
10183
10184 ins_cost(125);
10185 format %{ "xorq $dst, $src\t# long" %}
10186 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10187 ins_encode(REX_mem_wide(dst), OpcSE(src),
10188 RM_opc_mem(secondary, dst), Con8or32(src));
10189 ins_pipe(ialu_mem_imm);
10190 %}
10191
10192 // Convert Int to Boolean
10193 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10194 %{
10195 match(Set dst (Conv2B src));
10196 effect(KILL cr);
10197
10198 format %{ "testl $src, $src\t# ci2b\n\t"
10199 "setnz $dst\n\t"
10200 "movzbl $dst, $dst" %}
10201 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10202 setNZ_reg(dst),
10203 REX_reg_breg(dst, dst), // movzbl
10204 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10205 ins_pipe(pipe_slow); // XXX
10206 %}
10207
10208 // Convert Pointer to Boolean
10209 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10210 %{
10211 match(Set dst (Conv2B src));
10212 effect(KILL cr);
10213
10214 format %{ "testq $src, $src\t# cp2b\n\t"
10215 "setnz $dst\n\t"
10216 "movzbl $dst, $dst" %}
10217 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10218 setNZ_reg(dst),
10219 REX_reg_breg(dst, dst), // movzbl
10220 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10221 ins_pipe(pipe_slow); // XXX
10222 %}
10223
10224 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10225 %{
10226 match(Set dst (CmpLTMask p q));
10227 effect(KILL cr);
10228
10229 ins_cost(400);
10230 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10231 "setlt $dst\n\t"
10232 "movzbl $dst, $dst\n\t"
10233 "negl $dst" %}
10234 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10235 setLT_reg(dst),
10236 REX_reg_breg(dst, dst), // movzbl
10237 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10238 neg_reg(dst));
10239 ins_pipe(pipe_slow);
10240 %}
10241
10242 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10243 %{
10244 match(Set dst (CmpLTMask dst zero));
10245 effect(KILL cr);
10246
10247 ins_cost(100);
10248 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10249 ins_encode %{
10250 __ sarl($dst$$Register, 31);
10251 %}
10252 ins_pipe(ialu_reg);
10253 %}
10254
10255 /* Better to save a register than avoid a branch */
10256 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10257 %{
10258 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10259 effect(KILL cr);
10260 ins_cost(300);
10261 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10262 "jge done\n\t"
10263 "addl $p,$y\n"
10264 "done: " %}
10265 ins_encode %{
10266 Register Rp = $p$$Register;
10267 Register Rq = $q$$Register;
10268 Register Ry = $y$$Register;
10269 Label done;
10270 __ subl(Rp, Rq);
10271 __ jccb(Assembler::greaterEqual, done);
10272 __ addl(Rp, Ry);
10273 __ bind(done);
10274 %}
10275 ins_pipe(pipe_cmplt);
10276 %}
10277
10278 /* Better to save a register than avoid a branch */
10279 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10280 %{
10281 match(Set y (AndI (CmpLTMask p q) y));
10282 effect(KILL cr);
10283
10284 ins_cost(300);
10285
10286 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10287 "jlt done\n\t"
10288 "xorl $y, $y\n"
10289 "done: " %}
10290 ins_encode %{
10291 Register Rp = $p$$Register;
10292 Register Rq = $q$$Register;
10293 Register Ry = $y$$Register;
10294 Label done;
10295 __ cmpl(Rp, Rq);
10296 __ jccb(Assembler::less, done);
10297 __ xorl(Ry, Ry);
10298 __ bind(done);
10299 %}
10300 ins_pipe(pipe_cmplt);
10301 %}
10302
10303
10304 //---------- FP Instructions------------------------------------------------
10305
10306 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10307 %{
10308 match(Set cr (CmpF src1 src2));
10309
10310 ins_cost(145);
10311 format %{ "ucomiss $src1, $src2\n\t"
10312 "jnp,s exit\n\t"
10313 "pushfq\t# saw NaN, set CF\n\t"
10314 "andq [rsp], #0xffffff2b\n\t"
10315 "popfq\n"
10316 "exit:" %}
10317 ins_encode %{
10318 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10319 emit_cmpfp_fixup(_masm);
10320 %}
10321 ins_pipe(pipe_slow);
10322 %}
10323
10324 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10325 match(Set cr (CmpF src1 src2));
10326
10327 ins_cost(100);
10328 format %{ "ucomiss $src1, $src2" %}
10329 ins_encode %{
10330 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10331 %}
10332 ins_pipe(pipe_slow);
10333 %}
10334
10335 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10336 %{
10337 match(Set cr (CmpF src1 (LoadF src2)));
10338
10339 ins_cost(145);
10340 format %{ "ucomiss $src1, $src2\n\t"
10341 "jnp,s exit\n\t"
10342 "pushfq\t# saw NaN, set CF\n\t"
10343 "andq [rsp], #0xffffff2b\n\t"
10344 "popfq\n"
10345 "exit:" %}
10346 ins_encode %{
10347 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10348 emit_cmpfp_fixup(_masm);
10349 %}
10350 ins_pipe(pipe_slow);
10351 %}
10352
10353 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10354 match(Set cr (CmpF src1 (LoadF src2)));
10355
10356 ins_cost(100);
10357 format %{ "ucomiss $src1, $src2" %}
10358 ins_encode %{
10359 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10360 %}
10361 ins_pipe(pipe_slow);
10362 %}
10363
10364 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10365 match(Set cr (CmpF src con));
10366
10367 ins_cost(145);
10368 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10369 "jnp,s exit\n\t"
10370 "pushfq\t# saw NaN, set CF\n\t"
10371 "andq [rsp], #0xffffff2b\n\t"
10372 "popfq\n"
10373 "exit:" %}
10374 ins_encode %{
10375 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10376 emit_cmpfp_fixup(_masm);
10377 %}
10378 ins_pipe(pipe_slow);
10379 %}
10380
10381 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10382 match(Set cr (CmpF src con));
10383 ins_cost(100);
10384 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10385 ins_encode %{
10386 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10387 %}
10388 ins_pipe(pipe_slow);
10389 %}
10390
10391 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10392 %{
10393 match(Set cr (CmpD src1 src2));
10394
10395 ins_cost(145);
10396 format %{ "ucomisd $src1, $src2\n\t"
10397 "jnp,s exit\n\t"
10398 "pushfq\t# saw NaN, set CF\n\t"
10399 "andq [rsp], #0xffffff2b\n\t"
10400 "popfq\n"
10401 "exit:" %}
10402 ins_encode %{
10403 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10404 emit_cmpfp_fixup(_masm);
10405 %}
10406 ins_pipe(pipe_slow);
10407 %}
10408
10409 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10410 match(Set cr (CmpD src1 src2));
10411
10412 ins_cost(100);
10413 format %{ "ucomisd $src1, $src2 test" %}
10414 ins_encode %{
10415 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10416 %}
10417 ins_pipe(pipe_slow);
10418 %}
10419
10420 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10421 %{
10422 match(Set cr (CmpD src1 (LoadD src2)));
10423
10424 ins_cost(145);
10425 format %{ "ucomisd $src1, $src2\n\t"
10426 "jnp,s exit\n\t"
10427 "pushfq\t# saw NaN, set CF\n\t"
10428 "andq [rsp], #0xffffff2b\n\t"
10429 "popfq\n"
10430 "exit:" %}
10431 ins_encode %{
10432 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10433 emit_cmpfp_fixup(_masm);
10434 %}
10435 ins_pipe(pipe_slow);
10436 %}
10437
10438 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10439 match(Set cr (CmpD src1 (LoadD src2)));
10440
10441 ins_cost(100);
10442 format %{ "ucomisd $src1, $src2" %}
10443 ins_encode %{
10444 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10445 %}
10446 ins_pipe(pipe_slow);
10447 %}
10448
10449 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10450 match(Set cr (CmpD src con));
10451
10452 ins_cost(145);
10453 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10454 "jnp,s exit\n\t"
10455 "pushfq\t# saw NaN, set CF\n\t"
10456 "andq [rsp], #0xffffff2b\n\t"
10457 "popfq\n"
10458 "exit:" %}
10459 ins_encode %{
10460 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10461 emit_cmpfp_fixup(_masm);
10462 %}
10463 ins_pipe(pipe_slow);
10464 %}
10465
10466 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10467 match(Set cr (CmpD src con));
10468 ins_cost(100);
10469 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10470 ins_encode %{
10471 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10472 %}
10473 ins_pipe(pipe_slow);
10474 %}
10475
10476 // Compare into -1,0,1
10477 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10478 %{
10479 match(Set dst (CmpF3 src1 src2));
10480 effect(KILL cr);
10481
10482 ins_cost(275);
10483 format %{ "ucomiss $src1, $src2\n\t"
10484 "movl $dst, #-1\n\t"
10485 "jp,s done\n\t"
10486 "jb,s done\n\t"
10487 "setne $dst\n\t"
10488 "movzbl $dst, $dst\n"
10489 "done:" %}
10490 ins_encode %{
10491 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10492 emit_cmpfp3(_masm, $dst$$Register);
10493 %}
10494 ins_pipe(pipe_slow);
10495 %}
10496
10497 // Compare into -1,0,1
10498 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10499 %{
10500 match(Set dst (CmpF3 src1 (LoadF src2)));
10501 effect(KILL cr);
10502
10503 ins_cost(275);
10504 format %{ "ucomiss $src1, $src2\n\t"
10505 "movl $dst, #-1\n\t"
10506 "jp,s done\n\t"
10507 "jb,s done\n\t"
10508 "setne $dst\n\t"
10509 "movzbl $dst, $dst\n"
10510 "done:" %}
10511 ins_encode %{
10512 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10513 emit_cmpfp3(_masm, $dst$$Register);
10514 %}
10515 ins_pipe(pipe_slow);
10516 %}
10517
10518 // Compare into -1,0,1
10519 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10520 match(Set dst (CmpF3 src con));
10521 effect(KILL cr);
10522
10523 ins_cost(275);
10524 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10525 "movl $dst, #-1\n\t"
10526 "jp,s done\n\t"
10527 "jb,s done\n\t"
10528 "setne $dst\n\t"
10529 "movzbl $dst, $dst\n"
10530 "done:" %}
10531 ins_encode %{
10532 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10533 emit_cmpfp3(_masm, $dst$$Register);
10534 %}
10535 ins_pipe(pipe_slow);
10536 %}
10537
10538 // Compare into -1,0,1
10539 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10540 %{
10541 match(Set dst (CmpD3 src1 src2));
10542 effect(KILL cr);
10543
10544 ins_cost(275);
10545 format %{ "ucomisd $src1, $src2\n\t"
10546 "movl $dst, #-1\n\t"
10547 "jp,s done\n\t"
10548 "jb,s done\n\t"
10549 "setne $dst\n\t"
10550 "movzbl $dst, $dst\n"
10551 "done:" %}
10552 ins_encode %{
10553 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10554 emit_cmpfp3(_masm, $dst$$Register);
10555 %}
10556 ins_pipe(pipe_slow);
10557 %}
10558
10559 // Compare into -1,0,1
10560 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10561 %{
10562 match(Set dst (CmpD3 src1 (LoadD src2)));
10563 effect(KILL cr);
10564
10565 ins_cost(275);
10566 format %{ "ucomisd $src1, $src2\n\t"
10567 "movl $dst, #-1\n\t"
10568 "jp,s done\n\t"
10569 "jb,s done\n\t"
10570 "setne $dst\n\t"
10571 "movzbl $dst, $dst\n"
10572 "done:" %}
10573 ins_encode %{
10574 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10575 emit_cmpfp3(_masm, $dst$$Register);
10576 %}
10577 ins_pipe(pipe_slow);
10578 %}
10579
10580 // Compare into -1,0,1
10581 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10582 match(Set dst (CmpD3 src con));
10583 effect(KILL cr);
10584
10585 ins_cost(275);
10586 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10587 "movl $dst, #-1\n\t"
10588 "jp,s done\n\t"
10589 "jb,s done\n\t"
10590 "setne $dst\n\t"
10591 "movzbl $dst, $dst\n"
10592 "done:" %}
10593 ins_encode %{
10594 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10595 emit_cmpfp3(_masm, $dst$$Register);
10596 %}
10597 ins_pipe(pipe_slow);
10598 %}
10599
10600 //----------Arithmetic Conversion Instructions---------------------------------
10601
10602 instruct roundFloat_nop(regF dst)
10603 %{
10604 match(Set dst (RoundFloat dst));
10605
10606 ins_cost(0);
10607 ins_encode();
10608 ins_pipe(empty);
10609 %}
10610
10611 instruct roundDouble_nop(regD dst)
10612 %{
10613 match(Set dst (RoundDouble dst));
10614
10615 ins_cost(0);
10616 ins_encode();
10617 ins_pipe(empty);
10618 %}
10619
10620 instruct convF2D_reg_reg(regD dst, regF src)
10621 %{
10622 match(Set dst (ConvF2D src));
10623
10624 format %{ "cvtss2sd $dst, $src" %}
10625 ins_encode %{
10626 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10627 %}
10628 ins_pipe(pipe_slow); // XXX
10629 %}
10630
10631 instruct convF2D_reg_mem(regD dst, memory src)
10632 %{
10633 match(Set dst (ConvF2D (LoadF src)));
10634
10635 format %{ "cvtss2sd $dst, $src" %}
10636 ins_encode %{
10637 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10638 %}
10639 ins_pipe(pipe_slow); // XXX
10640 %}
10641
10642 instruct convD2F_reg_reg(regF dst, regD src)
10643 %{
10644 match(Set dst (ConvD2F src));
10645
10646 format %{ "cvtsd2ss $dst, $src" %}
10647 ins_encode %{
10648 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10649 %}
10650 ins_pipe(pipe_slow); // XXX
10651 %}
10652
10653 instruct convD2F_reg_mem(regF dst, memory src)
10654 %{
10655 match(Set dst (ConvD2F (LoadD src)));
10656
10657 format %{ "cvtsd2ss $dst, $src" %}
10658 ins_encode %{
10659 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10660 %}
10661 ins_pipe(pipe_slow); // XXX
10662 %}
10663
10664 // XXX do mem variants
10665 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10666 %{
10667 match(Set dst (ConvF2I src));
10668 effect(KILL cr);
10669
10670 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10671 "cmpl $dst, #0x80000000\n\t"
10672 "jne,s done\n\t"
10673 "subq rsp, #8\n\t"
10674 "movss [rsp], $src\n\t"
10675 "call f2i_fixup\n\t"
10676 "popq $dst\n"
10677 "done: "%}
10678 ins_encode %{
10679 Label done;
10680 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10681 __ cmpl($dst$$Register, 0x80000000);
10682 __ jccb(Assembler::notEqual, done);
10683 __ subptr(rsp, 8);
10684 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10685 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10686 __ pop($dst$$Register);
10687 __ bind(done);
10688 %}
10689 ins_pipe(pipe_slow);
10690 %}
10691
10692 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10693 %{
10694 match(Set dst (ConvF2L src));
10695 effect(KILL cr);
10696
10697 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10698 "cmpq $dst, [0x8000000000000000]\n\t"
10699 "jne,s done\n\t"
10700 "subq rsp, #8\n\t"
10701 "movss [rsp], $src\n\t"
10702 "call f2l_fixup\n\t"
10703 "popq $dst\n"
10704 "done: "%}
10705 ins_encode %{
10706 Label done;
10707 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10708 __ cmp64($dst$$Register,
10709 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10710 __ jccb(Assembler::notEqual, done);
10711 __ subptr(rsp, 8);
10712 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10713 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10714 __ pop($dst$$Register);
10715 __ bind(done);
10716 %}
10717 ins_pipe(pipe_slow);
10718 %}
10719
10720 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10721 %{
10722 match(Set dst (ConvD2I src));
10723 effect(KILL cr);
10724
10725 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10726 "cmpl $dst, #0x80000000\n\t"
10727 "jne,s done\n\t"
10728 "subq rsp, #8\n\t"
10729 "movsd [rsp], $src\n\t"
10730 "call d2i_fixup\n\t"
10731 "popq $dst\n"
10732 "done: "%}
10733 ins_encode %{
10734 Label done;
10735 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10736 __ cmpl($dst$$Register, 0x80000000);
10737 __ jccb(Assembler::notEqual, done);
10738 __ subptr(rsp, 8);
10739 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10740 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10741 __ pop($dst$$Register);
10742 __ bind(done);
10743 %}
10744 ins_pipe(pipe_slow);
10745 %}
10746
10747 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10748 %{
10749 match(Set dst (ConvD2L src));
10750 effect(KILL cr);
10751
10752 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10753 "cmpq $dst, [0x8000000000000000]\n\t"
10754 "jne,s done\n\t"
10755 "subq rsp, #8\n\t"
10756 "movsd [rsp], $src\n\t"
10757 "call d2l_fixup\n\t"
10758 "popq $dst\n"
10759 "done: "%}
10760 ins_encode %{
10761 Label done;
10762 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10763 __ cmp64($dst$$Register,
10764 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10765 __ jccb(Assembler::notEqual, done);
10766 __ subptr(rsp, 8);
10767 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10768 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10769 __ pop($dst$$Register);
10770 __ bind(done);
10771 %}
10772 ins_pipe(pipe_slow);
10773 %}
10774
10775 instruct convI2F_reg_reg(regF dst, rRegI src)
10776 %{
10777 predicate(!UseXmmI2F);
10778 match(Set dst (ConvI2F src));
10779
10780 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10781 ins_encode %{
10782 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10783 %}
10784 ins_pipe(pipe_slow); // XXX
10785 %}
10786
10787 instruct convI2F_reg_mem(regF dst, memory src)
10788 %{
10789 match(Set dst (ConvI2F (LoadI src)));
10790
10791 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10792 ins_encode %{
10793 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10794 %}
10795 ins_pipe(pipe_slow); // XXX
10796 %}
10797
10798 instruct convI2D_reg_reg(regD dst, rRegI src)
10799 %{
10800 predicate(!UseXmmI2D);
10801 match(Set dst (ConvI2D src));
10802
10803 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10804 ins_encode %{
10805 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10806 %}
10807 ins_pipe(pipe_slow); // XXX
10808 %}
10809
10810 instruct convI2D_reg_mem(regD dst, memory src)
10811 %{
10812 match(Set dst (ConvI2D (LoadI src)));
10813
10814 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10815 ins_encode %{
10816 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10817 %}
10818 ins_pipe(pipe_slow); // XXX
10819 %}
10820
10821 instruct convXI2F_reg(regF dst, rRegI src)
10822 %{
10823 predicate(UseXmmI2F);
10824 match(Set dst (ConvI2F src));
10825
10826 format %{ "movdl $dst, $src\n\t"
10827 "cvtdq2psl $dst, $dst\t# i2f" %}
10828 ins_encode %{
10829 __ movdl($dst$$XMMRegister, $src$$Register);
10830 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10831 %}
10832 ins_pipe(pipe_slow); // XXX
10833 %}
10834
10835 instruct convXI2D_reg(regD dst, rRegI src)
10836 %{
10837 predicate(UseXmmI2D);
10838 match(Set dst (ConvI2D src));
10839
10840 format %{ "movdl $dst, $src\n\t"
10841 "cvtdq2pdl $dst, $dst\t# i2d" %}
10842 ins_encode %{
10843 __ movdl($dst$$XMMRegister, $src$$Register);
10844 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10845 %}
10846 ins_pipe(pipe_slow); // XXX
10847 %}
10848
10849 instruct convL2F_reg_reg(regF dst, rRegL src)
10850 %{
10851 match(Set dst (ConvL2F src));
10852
10853 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10854 ins_encode %{
10855 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10856 %}
10857 ins_pipe(pipe_slow); // XXX
10858 %}
10859
10860 instruct convL2F_reg_mem(regF dst, memory src)
10861 %{
10862 match(Set dst (ConvL2F (LoadL src)));
10863
10864 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10865 ins_encode %{
10866 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10867 %}
10868 ins_pipe(pipe_slow); // XXX
10869 %}
10870
10871 instruct convL2D_reg_reg(regD dst, rRegL src)
10872 %{
10873 match(Set dst (ConvL2D src));
10874
10875 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10876 ins_encode %{
10877 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10878 %}
10879 ins_pipe(pipe_slow); // XXX
10880 %}
10881
10882 instruct convL2D_reg_mem(regD dst, memory src)
10883 %{
10884 match(Set dst (ConvL2D (LoadL src)));
10885
10886 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10887 ins_encode %{
10888 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10889 %}
10890 ins_pipe(pipe_slow); // XXX
10891 %}
10892
10893 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10894 %{
10895 match(Set dst (ConvI2L src));
10896
10897 ins_cost(125);
10898 format %{ "movslq $dst, $src\t# i2l" %}
10899 ins_encode %{
10900 __ movslq($dst$$Register, $src$$Register);
10901 %}
10902 ins_pipe(ialu_reg_reg);
10903 %}
10904
10905 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10906 // %{
10907 // match(Set dst (ConvI2L src));
10908 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10909 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10910 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10911 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10912 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10913 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10914
10915 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10916 // ins_encode(enc_copy(dst, src));
10917 // // opcode(0x63); // needs REX.W
10918 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10919 // ins_pipe(ialu_reg_reg);
10920 // %}
10921
10922 // Zero-extend convert int to long
10923 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10924 %{
10925 match(Set dst (AndL (ConvI2L src) mask));
10926
10927 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10928 ins_encode %{
10929 if ($dst$$reg != $src$$reg) {
10930 __ movl($dst$$Register, $src$$Register);
10931 }
10932 %}
10933 ins_pipe(ialu_reg_reg);
10934 %}
10935
10936 // Zero-extend convert int to long
10937 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10938 %{
10939 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10940
10941 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10942 ins_encode %{
10943 __ movl($dst$$Register, $src$$Address);
10944 %}
10945 ins_pipe(ialu_reg_mem);
10946 %}
10947
10948 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10949 %{
10950 match(Set dst (AndL src mask));
10951
10952 format %{ "movl $dst, $src\t# zero-extend long" %}
10953 ins_encode %{
10954 __ movl($dst$$Register, $src$$Register);
10955 %}
10956 ins_pipe(ialu_reg_reg);
10957 %}
10958
10959 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10960 %{
10961 match(Set dst (ConvL2I src));
10962
10963 format %{ "movl $dst, $src\t# l2i" %}
10964 ins_encode %{
10965 __ movl($dst$$Register, $src$$Register);
10966 %}
10967 ins_pipe(ialu_reg_reg);
10968 %}
10969
10970
10971 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10972 match(Set dst (MoveF2I src));
10973 effect(DEF dst, USE src);
10974
10975 ins_cost(125);
10976 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10977 ins_encode %{
10978 __ movl($dst$$Register, Address(rsp, $src$$disp));
10979 %}
10980 ins_pipe(ialu_reg_mem);
10981 %}
10982
10983 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10984 match(Set dst (MoveI2F src));
10985 effect(DEF dst, USE src);
10986
10987 ins_cost(125);
10988 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10989 ins_encode %{
10990 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10991 %}
10992 ins_pipe(pipe_slow);
10993 %}
10994
10995 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10996 match(Set dst (MoveD2L src));
10997 effect(DEF dst, USE src);
10998
10999 ins_cost(125);
11000 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11001 ins_encode %{
11002 __ movq($dst$$Register, Address(rsp, $src$$disp));
11003 %}
11004 ins_pipe(ialu_reg_mem);
11005 %}
11006
11007 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11008 predicate(!UseXmmLoadAndClearUpper);
11009 match(Set dst (MoveL2D src));
11010 effect(DEF dst, USE src);
11011
11012 ins_cost(125);
11013 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11014 ins_encode %{
11015 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11016 %}
11017 ins_pipe(pipe_slow);
11018 %}
11019
11020 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11021 predicate(UseXmmLoadAndClearUpper);
11022 match(Set dst (MoveL2D src));
11023 effect(DEF dst, USE src);
11024
11025 ins_cost(125);
11026 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11027 ins_encode %{
11028 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11029 %}
11030 ins_pipe(pipe_slow);
11031 %}
11032
11033
11034 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11035 match(Set dst (MoveF2I src));
11036 effect(DEF dst, USE src);
11037
11038 ins_cost(95); // XXX
11039 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11040 ins_encode %{
11041 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11042 %}
11043 ins_pipe(pipe_slow);
11044 %}
11045
11046 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11047 match(Set dst (MoveI2F src));
11048 effect(DEF dst, USE src);
11049
11050 ins_cost(100);
11051 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11052 ins_encode %{
11053 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11054 %}
11055 ins_pipe( ialu_mem_reg );
11056 %}
11057
11058 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11059 match(Set dst (MoveD2L src));
11060 effect(DEF dst, USE src);
11061
11062 ins_cost(95); // XXX
11063 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11064 ins_encode %{
11065 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11066 %}
11067 ins_pipe(pipe_slow);
11068 %}
11069
11070 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11071 match(Set dst (MoveL2D src));
11072 effect(DEF dst, USE src);
11073
11074 ins_cost(100);
11075 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11076 ins_encode %{
11077 __ movq(Address(rsp, $dst$$disp), $src$$Register);
11078 %}
11079 ins_pipe(ialu_mem_reg);
11080 %}
11081
11082 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11083 match(Set dst (MoveF2I src));
11084 effect(DEF dst, USE src);
11085 ins_cost(85);
11086 format %{ "movd $dst,$src\t# MoveF2I" %}
11087 ins_encode %{
11088 __ movdl($dst$$Register, $src$$XMMRegister);
11089 %}
11090 ins_pipe( pipe_slow );
11091 %}
11092
11093 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11094 match(Set dst (MoveD2L src));
11095 effect(DEF dst, USE src);
11096 ins_cost(85);
11097 format %{ "movd $dst,$src\t# MoveD2L" %}
11098 ins_encode %{
11099 __ movdq($dst$$Register, $src$$XMMRegister);
11100 %}
11101 ins_pipe( pipe_slow );
11102 %}
11103
11104 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11105 match(Set dst (MoveI2F src));
11106 effect(DEF dst, USE src);
11107 ins_cost(100);
11108 format %{ "movd $dst,$src\t# MoveI2F" %}
11109 ins_encode %{
11110 __ movdl($dst$$XMMRegister, $src$$Register);
11111 %}
11112 ins_pipe( pipe_slow );
11113 %}
11114
11115 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11116 match(Set dst (MoveL2D src));
11117 effect(DEF dst, USE src);
11118 ins_cost(100);
11119 format %{ "movd $dst,$src\t# MoveL2D" %}
11120 ins_encode %{
11121 __ movdq($dst$$XMMRegister, $src$$Register);
11122 %}
11123 ins_pipe( pipe_slow );
11124 %}
11125
11126
11127 // =======================================================================
11128 // fast clearing of an array
11129 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11130 Universe dummy, rFlagsReg cr)
11131 %{
11132 predicate(!((ClearArrayNode*)n)->is_large());
11133 match(Set dummy (ClearArray cnt base));
11134 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11135
11136 format %{ $$template
11137 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11138 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11139 $$emit$$"jg LARGE\n\t"
11140 $$emit$$"dec rcx\n\t"
11141 $$emit$$"js DONE\t# Zero length\n\t"
11142 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11143 $$emit$$"dec rcx\n\t"
11144 $$emit$$"jge LOOP\n\t"
11145 $$emit$$"jmp DONE\n\t"
11146 $$emit$$"# LARGE:\n\t"
11147 if (UseFastStosb) {
11148 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11149 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11150 } else if (UseXMMForObjInit) {
11151 $$emit$$"mov rdi,rax\n\t"
11152 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11153 $$emit$$"jmpq L_zero_64_bytes\n\t"
11154 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11155 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11156 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11157 $$emit$$"add 0x40,rax\n\t"
11158 $$emit$$"# L_zero_64_bytes:\n\t"
11159 $$emit$$"sub 0x8,rcx\n\t"
11160 $$emit$$"jge L_loop\n\t"
11161 $$emit$$"add 0x4,rcx\n\t"
11162 $$emit$$"jl L_tail\n\t"
11163 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11164 $$emit$$"add 0x20,rax\n\t"
11165 $$emit$$"sub 0x4,rcx\n\t"
11166 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11167 $$emit$$"add 0x4,rcx\n\t"
11168 $$emit$$"jle L_end\n\t"
11169 $$emit$$"dec rcx\n\t"
11170 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11171 $$emit$$"vmovq xmm0,(rax)\n\t"
11172 $$emit$$"add 0x8,rax\n\t"
11173 $$emit$$"dec rcx\n\t"
11174 $$emit$$"jge L_sloop\n\t"
11175 $$emit$$"# L_end:\n\t"
11176 } else {
11177 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11178 }
11179 $$emit$$"# DONE"
11180 %}
11181 ins_encode %{
11182 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11183 $tmp$$XMMRegister, false);
11184 %}
11185 ins_pipe(pipe_slow);
11186 %}
11187
11188 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11189 Universe dummy, rFlagsReg cr)
11190 %{
11191 predicate(((ClearArrayNode*)n)->is_large());
11192 match(Set dummy (ClearArray cnt base));
11193 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11194
11195 format %{ $$template
11196 if (UseFastStosb) {
11197 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11198 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11199 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11200 } else if (UseXMMForObjInit) {
11201 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11202 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11203 $$emit$$"jmpq L_zero_64_bytes\n\t"
11204 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11205 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11206 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11207 $$emit$$"add 0x40,rax\n\t"
11208 $$emit$$"# L_zero_64_bytes:\n\t"
11209 $$emit$$"sub 0x8,rcx\n\t"
11210 $$emit$$"jge L_loop\n\t"
11211 $$emit$$"add 0x4,rcx\n\t"
11212 $$emit$$"jl L_tail\n\t"
11213 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11214 $$emit$$"add 0x20,rax\n\t"
11215 $$emit$$"sub 0x4,rcx\n\t"
11216 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11217 $$emit$$"add 0x4,rcx\n\t"
11218 $$emit$$"jle L_end\n\t"
11219 $$emit$$"dec rcx\n\t"
11220 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11221 $$emit$$"vmovq xmm0,(rax)\n\t"
11222 $$emit$$"add 0x8,rax\n\t"
11223 $$emit$$"dec rcx\n\t"
11224 $$emit$$"jge L_sloop\n\t"
11225 $$emit$$"# L_end:\n\t"
11226 } else {
11227 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11228 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11229 }
11230 %}
11231 ins_encode %{
11232 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11233 $tmp$$XMMRegister, true);
11234 %}
11235 ins_pipe(pipe_slow);
11236 %}
11237
11238 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11239 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11240 %{
11241 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11242 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11243 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11244
11245 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11246 ins_encode %{
11247 __ string_compare($str1$$Register, $str2$$Register,
11248 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11249 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11250 %}
11251 ins_pipe( pipe_slow );
11252 %}
11253
11254 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11255 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11256 %{
11257 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11258 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11259 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11260
11261 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11262 ins_encode %{
11263 __ string_compare($str1$$Register, $str2$$Register,
11264 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11265 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11266 %}
11267 ins_pipe( pipe_slow );
11268 %}
11269
11270 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11271 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11272 %{
11273 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11274 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11275 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11276
11277 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11278 ins_encode %{
11279 __ string_compare($str1$$Register, $str2$$Register,
11280 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11281 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11282 %}
11283 ins_pipe( pipe_slow );
11284 %}
11285
11286 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11287 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11288 %{
11289 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11290 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11291 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11292
11293 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11294 ins_encode %{
11295 __ string_compare($str2$$Register, $str1$$Register,
11296 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11297 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11298 %}
11299 ins_pipe( pipe_slow );
11300 %}
11301
11302 // fast search of substring with known size.
11303 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11304 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11305 %{
11306 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11307 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11308 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11309
11310 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11311 ins_encode %{
11312 int icnt2 = (int)$int_cnt2$$constant;
11313 if (icnt2 >= 16) {
11314 // IndexOf for constant substrings with size >= 16 elements
11315 // which don't need to be loaded through stack.
11316 __ string_indexofC8($str1$$Register, $str2$$Register,
11317 $cnt1$$Register, $cnt2$$Register,
11318 icnt2, $result$$Register,
11319 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11320 } else {
11321 // Small strings are loaded through stack if they cross page boundary.
11322 __ string_indexof($str1$$Register, $str2$$Register,
11323 $cnt1$$Register, $cnt2$$Register,
11324 icnt2, $result$$Register,
11325 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11326 }
11327 %}
11328 ins_pipe( pipe_slow );
11329 %}
11330
11331 // fast search of substring with known size.
11332 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11333 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11334 %{
11335 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11336 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11337 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11338
11339 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11340 ins_encode %{
11341 int icnt2 = (int)$int_cnt2$$constant;
11342 if (icnt2 >= 8) {
11343 // IndexOf for constant substrings with size >= 8 elements
11344 // which don't need to be loaded through stack.
11345 __ string_indexofC8($str1$$Register, $str2$$Register,
11346 $cnt1$$Register, $cnt2$$Register,
11347 icnt2, $result$$Register,
11348 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11349 } else {
11350 // Small strings are loaded through stack if they cross page boundary.
11351 __ string_indexof($str1$$Register, $str2$$Register,
11352 $cnt1$$Register, $cnt2$$Register,
11353 icnt2, $result$$Register,
11354 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11355 }
11356 %}
11357 ins_pipe( pipe_slow );
11358 %}
11359
11360 // fast search of substring with known size.
11361 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11362 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11363 %{
11364 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11365 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11366 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11367
11368 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11369 ins_encode %{
11370 int icnt2 = (int)$int_cnt2$$constant;
11371 if (icnt2 >= 8) {
11372 // IndexOf for constant substrings with size >= 8 elements
11373 // which don't need to be loaded through stack.
11374 __ string_indexofC8($str1$$Register, $str2$$Register,
11375 $cnt1$$Register, $cnt2$$Register,
11376 icnt2, $result$$Register,
11377 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11378 } else {
11379 // Small strings are loaded through stack if they cross page boundary.
11380 __ string_indexof($str1$$Register, $str2$$Register,
11381 $cnt1$$Register, $cnt2$$Register,
11382 icnt2, $result$$Register,
11383 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11384 }
11385 %}
11386 ins_pipe( pipe_slow );
11387 %}
11388
11389 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11390 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11391 %{
11392 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11393 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11394 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11395
11396 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11397 ins_encode %{
11398 __ string_indexof($str1$$Register, $str2$$Register,
11399 $cnt1$$Register, $cnt2$$Register,
11400 (-1), $result$$Register,
11401 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11402 %}
11403 ins_pipe( pipe_slow );
11404 %}
11405
11406 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11407 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11408 %{
11409 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11410 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11411 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11412
11413 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11414 ins_encode %{
11415 __ string_indexof($str1$$Register, $str2$$Register,
11416 $cnt1$$Register, $cnt2$$Register,
11417 (-1), $result$$Register,
11418 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11419 %}
11420 ins_pipe( pipe_slow );
11421 %}
11422
11423 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11424 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11425 %{
11426 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11427 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11428 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11429
11430 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11431 ins_encode %{
11432 __ string_indexof($str1$$Register, $str2$$Register,
11433 $cnt1$$Register, $cnt2$$Register,
11434 (-1), $result$$Register,
11435 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11436 %}
11437 ins_pipe( pipe_slow );
11438 %}
11439
11440 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11441 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11442 %{
11443 predicate(UseSSE42Intrinsics);
11444 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11445 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11446 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11447 ins_encode %{
11448 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11449 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11450 %}
11451 ins_pipe( pipe_slow );
11452 %}
11453
11454 // fast string equals
11455 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11456 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11457 %{
11458 match(Set result (StrEquals (Binary str1 str2) cnt));
11459 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11460
11461 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11462 ins_encode %{
11463 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11464 $cnt$$Register, $result$$Register, $tmp3$$Register,
11465 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11466 %}
11467 ins_pipe( pipe_slow );
11468 %}
11469
11470 // fast array equals
11471 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11472 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11473 %{
11474 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11475 match(Set result (AryEq ary1 ary2));
11476 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11477
11478 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11479 ins_encode %{
11480 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11481 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11482 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11483 %}
11484 ins_pipe( pipe_slow );
11485 %}
11486
11487 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11488 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11489 %{
11490 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11491 match(Set result (AryEq ary1 ary2));
11492 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11493
11494 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11495 ins_encode %{
11496 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11497 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11498 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11499 %}
11500 ins_pipe( pipe_slow );
11501 %}
11502
11503 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11504 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11505 %{
11506 match(Set result (HasNegatives ary1 len));
11507 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11508
11509 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11510 ins_encode %{
11511 __ has_negatives($ary1$$Register, $len$$Register,
11512 $result$$Register, $tmp3$$Register,
11513 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11514 %}
11515 ins_pipe( pipe_slow );
11516 %}
11517
11518 // fast char[] to byte[] compression
11519 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11520 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11521 match(Set result (StrCompressedCopy src (Binary dst len)));
11522 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11523
11524 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11525 ins_encode %{
11526 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11527 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11528 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11529 %}
11530 ins_pipe( pipe_slow );
11531 %}
11532
11533 // fast byte[] to char[] inflation
11534 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11535 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11536 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11537 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11538
11539 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11540 ins_encode %{
11541 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11542 $tmp1$$XMMRegister, $tmp2$$Register);
11543 %}
11544 ins_pipe( pipe_slow );
11545 %}
11546
11547 // encode char[] to byte[] in ISO_8859_1
11548 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11549 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11550 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11551 match(Set result (EncodeISOArray src (Binary dst len)));
11552 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11553
11554 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11555 ins_encode %{
11556 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11557 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11558 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11559 %}
11560 ins_pipe( pipe_slow );
11561 %}
11562
11563 //----------Overflow Math Instructions-----------------------------------------
11564
11565 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11566 %{
11567 match(Set cr (OverflowAddI op1 op2));
11568 effect(DEF cr, USE_KILL op1, USE op2);
11569
11570 format %{ "addl $op1, $op2\t# overflow check int" %}
11571
11572 ins_encode %{
11573 __ addl($op1$$Register, $op2$$Register);
11574 %}
11575 ins_pipe(ialu_reg_reg);
11576 %}
11577
11578 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11579 %{
11580 match(Set cr (OverflowAddI op1 op2));
11581 effect(DEF cr, USE_KILL op1, USE op2);
11582
11583 format %{ "addl $op1, $op2\t# overflow check int" %}
11584
11585 ins_encode %{
11586 __ addl($op1$$Register, $op2$$constant);
11587 %}
11588 ins_pipe(ialu_reg_reg);
11589 %}
11590
11591 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11592 %{
11593 match(Set cr (OverflowAddL op1 op2));
11594 effect(DEF cr, USE_KILL op1, USE op2);
11595
11596 format %{ "addq $op1, $op2\t# overflow check long" %}
11597 ins_encode %{
11598 __ addq($op1$$Register, $op2$$Register);
11599 %}
11600 ins_pipe(ialu_reg_reg);
11601 %}
11602
11603 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11604 %{
11605 match(Set cr (OverflowAddL op1 op2));
11606 effect(DEF cr, USE_KILL op1, USE op2);
11607
11608 format %{ "addq $op1, $op2\t# overflow check long" %}
11609 ins_encode %{
11610 __ addq($op1$$Register, $op2$$constant);
11611 %}
11612 ins_pipe(ialu_reg_reg);
11613 %}
11614
11615 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11616 %{
11617 match(Set cr (OverflowSubI op1 op2));
11618
11619 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11620 ins_encode %{
11621 __ cmpl($op1$$Register, $op2$$Register);
11622 %}
11623 ins_pipe(ialu_reg_reg);
11624 %}
11625
11626 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11627 %{
11628 match(Set cr (OverflowSubI op1 op2));
11629
11630 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11631 ins_encode %{
11632 __ cmpl($op1$$Register, $op2$$constant);
11633 %}
11634 ins_pipe(ialu_reg_reg);
11635 %}
11636
11637 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11638 %{
11639 match(Set cr (OverflowSubL op1 op2));
11640
11641 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11642 ins_encode %{
11643 __ cmpq($op1$$Register, $op2$$Register);
11644 %}
11645 ins_pipe(ialu_reg_reg);
11646 %}
11647
11648 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11649 %{
11650 match(Set cr (OverflowSubL op1 op2));
11651
11652 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11653 ins_encode %{
11654 __ cmpq($op1$$Register, $op2$$constant);
11655 %}
11656 ins_pipe(ialu_reg_reg);
11657 %}
11658
11659 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11660 %{
11661 match(Set cr (OverflowSubI zero op2));
11662 effect(DEF cr, USE_KILL op2);
11663
11664 format %{ "negl $op2\t# overflow check int" %}
11665 ins_encode %{
11666 __ negl($op2$$Register);
11667 %}
11668 ins_pipe(ialu_reg_reg);
11669 %}
11670
11671 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11672 %{
11673 match(Set cr (OverflowSubL zero op2));
11674 effect(DEF cr, USE_KILL op2);
11675
11676 format %{ "negq $op2\t# overflow check long" %}
11677 ins_encode %{
11678 __ negq($op2$$Register);
11679 %}
11680 ins_pipe(ialu_reg_reg);
11681 %}
11682
11683 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11684 %{
11685 match(Set cr (OverflowMulI op1 op2));
11686 effect(DEF cr, USE_KILL op1, USE op2);
11687
11688 format %{ "imull $op1, $op2\t# overflow check int" %}
11689 ins_encode %{
11690 __ imull($op1$$Register, $op2$$Register);
11691 %}
11692 ins_pipe(ialu_reg_reg_alu0);
11693 %}
11694
11695 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11696 %{
11697 match(Set cr (OverflowMulI op1 op2));
11698 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11699
11700 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11701 ins_encode %{
11702 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11703 %}
11704 ins_pipe(ialu_reg_reg_alu0);
11705 %}
11706
11707 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11708 %{
11709 match(Set cr (OverflowMulL op1 op2));
11710 effect(DEF cr, USE_KILL op1, USE op2);
11711
11712 format %{ "imulq $op1, $op2\t# overflow check long" %}
11713 ins_encode %{
11714 __ imulq($op1$$Register, $op2$$Register);
11715 %}
11716 ins_pipe(ialu_reg_reg_alu0);
11717 %}
11718
11719 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11720 %{
11721 match(Set cr (OverflowMulL op1 op2));
11722 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11723
11724 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11725 ins_encode %{
11726 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11727 %}
11728 ins_pipe(ialu_reg_reg_alu0);
11729 %}
11730
11731
11732 //----------Control Flow Instructions------------------------------------------
11733 // Signed compare Instructions
11734
11735 // XXX more variants!!
11736 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11737 %{
11738 match(Set cr (CmpI op1 op2));
11739 effect(DEF cr, USE op1, USE op2);
11740
11741 format %{ "cmpl $op1, $op2" %}
11742 opcode(0x3B); /* Opcode 3B /r */
11743 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11744 ins_pipe(ialu_cr_reg_reg);
11745 %}
11746
11747 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11748 %{
11749 match(Set cr (CmpI op1 op2));
11750
11751 format %{ "cmpl $op1, $op2" %}
11752 opcode(0x81, 0x07); /* Opcode 81 /7 */
11753 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11754 ins_pipe(ialu_cr_reg_imm);
11755 %}
11756
11757 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11758 %{
11759 match(Set cr (CmpI op1 (LoadI op2)));
11760
11761 ins_cost(500); // XXX
11762 format %{ "cmpl $op1, $op2" %}
11763 opcode(0x3B); /* Opcode 3B /r */
11764 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11765 ins_pipe(ialu_cr_reg_mem);
11766 %}
11767
11768 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11769 %{
11770 match(Set cr (CmpI src zero));
11771
11772 format %{ "testl $src, $src" %}
11773 opcode(0x85);
11774 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11775 ins_pipe(ialu_cr_reg_imm);
11776 %}
11777
11778 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11779 %{
11780 match(Set cr (CmpI (AndI src con) zero));
11781
11782 format %{ "testl $src, $con" %}
11783 opcode(0xF7, 0x00);
11784 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11785 ins_pipe(ialu_cr_reg_imm);
11786 %}
11787
11788 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11789 %{
11790 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11791
11792 format %{ "testl $src, $mem" %}
11793 opcode(0x85);
11794 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11795 ins_pipe(ialu_cr_reg_mem);
11796 %}
11797
11798 // Unsigned compare Instructions; really, same as signed except they
11799 // produce an rFlagsRegU instead of rFlagsReg.
11800 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11801 %{
11802 match(Set cr (CmpU op1 op2));
11803
11804 format %{ "cmpl $op1, $op2\t# unsigned" %}
11805 opcode(0x3B); /* Opcode 3B /r */
11806 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11807 ins_pipe(ialu_cr_reg_reg);
11808 %}
11809
11810 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11811 %{
11812 match(Set cr (CmpU op1 op2));
11813
11814 format %{ "cmpl $op1, $op2\t# unsigned" %}
11815 opcode(0x81,0x07); /* Opcode 81 /7 */
11816 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11817 ins_pipe(ialu_cr_reg_imm);
11818 %}
11819
11820 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11821 %{
11822 match(Set cr (CmpU op1 (LoadI op2)));
11823
11824 ins_cost(500); // XXX
11825 format %{ "cmpl $op1, $op2\t# unsigned" %}
11826 opcode(0x3B); /* Opcode 3B /r */
11827 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11828 ins_pipe(ialu_cr_reg_mem);
11829 %}
11830
11831 // // // Cisc-spilled version of cmpU_rReg
11832 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11833 // //%{
11834 // // match(Set cr (CmpU (LoadI op1) op2));
11835 // //
11836 // // format %{ "CMPu $op1,$op2" %}
11837 // // ins_cost(500);
11838 // // opcode(0x39); /* Opcode 39 /r */
11839 // // ins_encode( OpcP, reg_mem( op1, op2) );
11840 // //%}
11841
11842 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11843 %{
11844 match(Set cr (CmpU src zero));
11845
11846 format %{ "testl $src, $src\t# unsigned" %}
11847 opcode(0x85);
11848 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11849 ins_pipe(ialu_cr_reg_imm);
11850 %}
11851
11852 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11853 %{
11854 match(Set cr (CmpP op1 op2));
11855
11856 format %{ "cmpq $op1, $op2\t# ptr" %}
11857 opcode(0x3B); /* Opcode 3B /r */
11858 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11859 ins_pipe(ialu_cr_reg_reg);
11860 %}
11861
11862 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11863 %{
11864 match(Set cr (CmpP op1 (LoadP op2)));
11865
11866 ins_cost(500); // XXX
11867 format %{ "cmpq $op1, $op2\t# ptr" %}
11868 opcode(0x3B); /* Opcode 3B /r */
11869 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11870 ins_pipe(ialu_cr_reg_mem);
11871 %}
11872
11873 // // // Cisc-spilled version of cmpP_rReg
11874 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11875 // //%{
11876 // // match(Set cr (CmpP (LoadP op1) op2));
11877 // //
11878 // // format %{ "CMPu $op1,$op2" %}
11879 // // ins_cost(500);
11880 // // opcode(0x39); /* Opcode 39 /r */
11881 // // ins_encode( OpcP, reg_mem( op1, op2) );
11882 // //%}
11883
11884 // XXX this is generalized by compP_rReg_mem???
11885 // Compare raw pointer (used in out-of-heap check).
11886 // Only works because non-oop pointers must be raw pointers
11887 // and raw pointers have no anti-dependencies.
11888 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11889 %{
11890 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11891 match(Set cr (CmpP op1 (LoadP op2)));
11892
11893 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11894 opcode(0x3B); /* Opcode 3B /r */
11895 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11896 ins_pipe(ialu_cr_reg_mem);
11897 %}
11898
11899 // This will generate a signed flags result. This should be OK since
11900 // any compare to a zero should be eq/neq.
11901 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11902 %{
11903 match(Set cr (CmpP src zero));
11904
11905 format %{ "testq $src, $src\t# ptr" %}
11906 opcode(0x85);
11907 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11908 ins_pipe(ialu_cr_reg_imm);
11909 %}
11910
11911 // This will generate a signed flags result. This should be OK since
11912 // any compare to a zero should be eq/neq.
11913 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11914 %{
11915 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11916 match(Set cr (CmpP (LoadP op) zero));
11917
11918 ins_cost(500); // XXX
11919 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11920 opcode(0xF7); /* Opcode F7 /0 */
11921 ins_encode(REX_mem_wide(op),
11922 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11923 ins_pipe(ialu_cr_reg_imm);
11924 %}
11925
11926 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11927 %{
11928 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11929 match(Set cr (CmpP (LoadP mem) zero));
11930
11931 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11932 ins_encode %{
11933 __ cmpq(r12, $mem$$Address);
11934 %}
11935 ins_pipe(ialu_cr_reg_mem);
11936 %}
11937
11938 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11939 %{
11940 match(Set cr (CmpN op1 op2));
11941
11942 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11943 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11944 ins_pipe(ialu_cr_reg_reg);
11945 %}
11946
11947 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11948 %{
11949 match(Set cr (CmpN src (LoadN mem)));
11950
11951 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11952 ins_encode %{
11953 __ cmpl($src$$Register, $mem$$Address);
11954 %}
11955 ins_pipe(ialu_cr_reg_mem);
11956 %}
11957
11958 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11959 match(Set cr (CmpN op1 op2));
11960
11961 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11962 ins_encode %{
11963 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11964 %}
11965 ins_pipe(ialu_cr_reg_imm);
11966 %}
11967
11968 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11969 %{
11970 match(Set cr (CmpN src (LoadN mem)));
11971
11972 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11973 ins_encode %{
11974 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11975 %}
11976 ins_pipe(ialu_cr_reg_mem);
11977 %}
11978
11979 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11980 match(Set cr (CmpN op1 op2));
11981
11982 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11983 ins_encode %{
11984 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11985 %}
11986 ins_pipe(ialu_cr_reg_imm);
11987 %}
11988
11989 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11990 %{
11991 match(Set cr (CmpN src (LoadNKlass mem)));
11992
11993 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11994 ins_encode %{
11995 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11996 %}
11997 ins_pipe(ialu_cr_reg_mem);
11998 %}
11999
12000 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12001 match(Set cr (CmpN src zero));
12002
12003 format %{ "testl $src, $src\t# compressed ptr" %}
12004 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12005 ins_pipe(ialu_cr_reg_imm);
12006 %}
12007
12008 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12009 %{
12010 predicate(Universe::narrow_oop_base() != NULL);
12011 match(Set cr (CmpN (LoadN mem) zero));
12012
12013 ins_cost(500); // XXX
12014 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12015 ins_encode %{
12016 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12017 %}
12018 ins_pipe(ialu_cr_reg_mem);
12019 %}
12020
12021 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12022 %{
12023 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
12024 match(Set cr (CmpN (LoadN mem) zero));
12025
12026 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12027 ins_encode %{
12028 __ cmpl(r12, $mem$$Address);
12029 %}
12030 ins_pipe(ialu_cr_reg_mem);
12031 %}
12032
12033 // Yanked all unsigned pointer compare operations.
12034 // Pointer compares are done with CmpP which is already unsigned.
12035
12036 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12037 %{
12038 match(Set cr (CmpL op1 op2));
12039
12040 format %{ "cmpq $op1, $op2" %}
12041 opcode(0x3B); /* Opcode 3B /r */
12042 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12043 ins_pipe(ialu_cr_reg_reg);
12044 %}
12045
12046 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12047 %{
12048 match(Set cr (CmpL op1 op2));
12049
12050 format %{ "cmpq $op1, $op2" %}
12051 opcode(0x81, 0x07); /* Opcode 81 /7 */
12052 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12053 ins_pipe(ialu_cr_reg_imm);
12054 %}
12055
12056 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12057 %{
12058 match(Set cr (CmpL op1 (LoadL op2)));
12059
12060 format %{ "cmpq $op1, $op2" %}
12061 opcode(0x3B); /* Opcode 3B /r */
12062 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12063 ins_pipe(ialu_cr_reg_mem);
12064 %}
12065
12066 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12067 %{
12068 match(Set cr (CmpL src zero));
12069
12070 format %{ "testq $src, $src" %}
12071 opcode(0x85);
12072 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12073 ins_pipe(ialu_cr_reg_imm);
12074 %}
12075
12076 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12077 %{
12078 match(Set cr (CmpL (AndL src con) zero));
12079
12080 format %{ "testq $src, $con\t# long" %}
12081 opcode(0xF7, 0x00);
12082 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12083 ins_pipe(ialu_cr_reg_imm);
12084 %}
12085
12086 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12087 %{
12088 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12089
12090 format %{ "testq $src, $mem" %}
12091 opcode(0x85);
12092 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12093 ins_pipe(ialu_cr_reg_mem);
12094 %}
12095
12096 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12097 %{
12098 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12099
12100 format %{ "testq $src, $mem" %}
12101 opcode(0x85);
12102 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12103 ins_pipe(ialu_cr_reg_mem);
12104 %}
12105
12106 // Manifest a CmpL result in an integer register. Very painful.
12107 // This is the test to avoid.
12108 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12109 %{
12110 match(Set dst (CmpL3 src1 src2));
12111 effect(KILL flags);
12112
12113 ins_cost(275); // XXX
12114 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12115 "movl $dst, -1\n\t"
12116 "jl,s done\n\t"
12117 "setne $dst\n\t"
12118 "movzbl $dst, $dst\n\t"
12119 "done:" %}
12120 ins_encode(cmpl3_flag(src1, src2, dst));
12121 ins_pipe(pipe_slow);
12122 %}
12123
12124 // Unsigned long compare Instructions; really, same as signed long except they
12125 // produce an rFlagsRegU instead of rFlagsReg.
12126 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12127 %{
12128 match(Set cr (CmpUL op1 op2));
12129
12130 format %{ "cmpq $op1, $op2\t# unsigned" %}
12131 opcode(0x3B); /* Opcode 3B /r */
12132 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12133 ins_pipe(ialu_cr_reg_reg);
12134 %}
12135
12136 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12137 %{
12138 match(Set cr (CmpUL op1 op2));
12139
12140 format %{ "cmpq $op1, $op2\t# unsigned" %}
12141 opcode(0x81, 0x07); /* Opcode 81 /7 */
12142 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12143 ins_pipe(ialu_cr_reg_imm);
12144 %}
12145
12146 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12147 %{
12148 match(Set cr (CmpUL op1 (LoadL op2)));
12149
12150 format %{ "cmpq $op1, $op2\t# unsigned" %}
12151 opcode(0x3B); /* Opcode 3B /r */
12152 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12153 ins_pipe(ialu_cr_reg_mem);
12154 %}
12155
12156 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12157 %{
12158 match(Set cr (CmpUL src zero));
12159
12160 format %{ "testq $src, $src\t# unsigned" %}
12161 opcode(0x85);
12162 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12163 ins_pipe(ialu_cr_reg_imm);
12164 %}
12165
12166 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12167 %{
12168 match(Set cr (CmpI (LoadB mem) imm));
12169
12170 ins_cost(125);
12171 format %{ "cmpb $mem, $imm" %}
12172 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12173 ins_pipe(ialu_cr_reg_mem);
12174 %}
12175
12176 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12177 %{
12178 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12179
12180 ins_cost(125);
12181 format %{ "testb $mem, $imm\t# ubyte" %}
12182 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12183 ins_pipe(ialu_cr_reg_mem);
12184 %}
12185
12186 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12187 %{
12188 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12189
12190 ins_cost(125);
12191 format %{ "testb $mem, $imm\t# byte" %}
12192 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12193 ins_pipe(ialu_cr_reg_mem);
12194 %}
12195
12196 //----------Max and Min--------------------------------------------------------
12197 // Min Instructions
12198
12199 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12200 %{
12201 effect(USE_DEF dst, USE src, USE cr);
12202
12203 format %{ "cmovlgt $dst, $src\t# min" %}
12204 opcode(0x0F, 0x4F);
12205 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12206 ins_pipe(pipe_cmov_reg);
12207 %}
12208
12209
12210 instruct minI_rReg(rRegI dst, rRegI src)
12211 %{
12212 match(Set dst (MinI dst src));
12213
12214 ins_cost(200);
12215 expand %{
12216 rFlagsReg cr;
12217 compI_rReg(cr, dst, src);
12218 cmovI_reg_g(dst, src, cr);
12219 %}
12220 %}
12221
12222 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12223 %{
12224 effect(USE_DEF dst, USE src, USE cr);
12225
12226 format %{ "cmovllt $dst, $src\t# max" %}
12227 opcode(0x0F, 0x4C);
12228 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12229 ins_pipe(pipe_cmov_reg);
12230 %}
12231
12232
12233 instruct maxI_rReg(rRegI dst, rRegI src)
12234 %{
12235 match(Set dst (MaxI dst src));
12236
12237 ins_cost(200);
12238 expand %{
12239 rFlagsReg cr;
12240 compI_rReg(cr, dst, src);
12241 cmovI_reg_l(dst, src, cr);
12242 %}
12243 %}
12244
12245 // ============================================================================
12246 // Branch Instructions
12247
12248 // Jump Direct - Label defines a relative address from JMP+1
12249 instruct jmpDir(label labl)
12250 %{
12251 match(Goto);
12252 effect(USE labl);
12253
12254 ins_cost(300);
12255 format %{ "jmp $labl" %}
12256 size(5);
12257 ins_encode %{
12258 Label* L = $labl$$label;
12259 __ jmp(*L, false); // Always long jump
12260 %}
12261 ins_pipe(pipe_jmp);
12262 %}
12263
12264 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12265 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12266 %{
12267 match(If cop cr);
12268 effect(USE labl);
12269
12270 ins_cost(300);
12271 format %{ "j$cop $labl" %}
12272 size(6);
12273 ins_encode %{
12274 Label* L = $labl$$label;
12275 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12276 %}
12277 ins_pipe(pipe_jcc);
12278 %}
12279
12280 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12281 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12282 %{
12283 predicate(!n->has_vector_mask_set());
12284 match(CountedLoopEnd cop cr);
12285 effect(USE labl);
12286
12287 ins_cost(300);
12288 format %{ "j$cop $labl\t# loop end" %}
12289 size(6);
12290 ins_encode %{
12291 Label* L = $labl$$label;
12292 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12293 %}
12294 ins_pipe(pipe_jcc);
12295 %}
12296
12297 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12298 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12299 predicate(!n->has_vector_mask_set());
12300 match(CountedLoopEnd cop cmp);
12301 effect(USE labl);
12302
12303 ins_cost(300);
12304 format %{ "j$cop,u $labl\t# loop end" %}
12305 size(6);
12306 ins_encode %{
12307 Label* L = $labl$$label;
12308 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12309 %}
12310 ins_pipe(pipe_jcc);
12311 %}
12312
12313 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12314 predicate(!n->has_vector_mask_set());
12315 match(CountedLoopEnd cop cmp);
12316 effect(USE labl);
12317
12318 ins_cost(200);
12319 format %{ "j$cop,u $labl\t# loop end" %}
12320 size(6);
12321 ins_encode %{
12322 Label* L = $labl$$label;
12323 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12324 %}
12325 ins_pipe(pipe_jcc);
12326 %}
12327
12328 // mask version
12329 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12330 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12331 %{
12332 predicate(n->has_vector_mask_set());
12333 match(CountedLoopEnd cop cr);
12334 effect(USE labl);
12335
12336 ins_cost(400);
12337 format %{ "j$cop $labl\t# loop end\n\t"
12338 "restorevectmask \t# vector mask restore for loops" %}
12339 size(10);
12340 ins_encode %{
12341 Label* L = $labl$$label;
12342 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12343 __ restorevectmask();
12344 %}
12345 ins_pipe(pipe_jcc);
12346 %}
12347
12348 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12349 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12350 predicate(n->has_vector_mask_set());
12351 match(CountedLoopEnd cop cmp);
12352 effect(USE labl);
12353
12354 ins_cost(400);
12355 format %{ "j$cop,u $labl\t# loop end\n\t"
12356 "restorevectmask \t# vector mask restore for loops" %}
12357 size(10);
12358 ins_encode %{
12359 Label* L = $labl$$label;
12360 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12361 __ restorevectmask();
12362 %}
12363 ins_pipe(pipe_jcc);
12364 %}
12365
12366 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12367 predicate(n->has_vector_mask_set());
12368 match(CountedLoopEnd cop cmp);
12369 effect(USE labl);
12370
12371 ins_cost(300);
12372 format %{ "j$cop,u $labl\t# loop end\n\t"
12373 "restorevectmask \t# vector mask restore for loops" %}
12374 size(10);
12375 ins_encode %{
12376 Label* L = $labl$$label;
12377 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12378 __ restorevectmask();
12379 %}
12380 ins_pipe(pipe_jcc);
12381 %}
12382
12383 // Jump Direct Conditional - using unsigned comparison
12384 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12385 match(If cop cmp);
12386 effect(USE labl);
12387
12388 ins_cost(300);
12389 format %{ "j$cop,u $labl" %}
12390 size(6);
12391 ins_encode %{
12392 Label* L = $labl$$label;
12393 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12394 %}
12395 ins_pipe(pipe_jcc);
12396 %}
12397
12398 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12399 match(If cop cmp);
12400 effect(USE labl);
12401
12402 ins_cost(200);
12403 format %{ "j$cop,u $labl" %}
12404 size(6);
12405 ins_encode %{
12406 Label* L = $labl$$label;
12407 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12408 %}
12409 ins_pipe(pipe_jcc);
12410 %}
12411
12412 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12413 match(If cop cmp);
12414 effect(USE labl);
12415
12416 ins_cost(200);
12417 format %{ $$template
12418 if ($cop$$cmpcode == Assembler::notEqual) {
12419 $$emit$$"jp,u $labl\n\t"
12420 $$emit$$"j$cop,u $labl"
12421 } else {
12422 $$emit$$"jp,u done\n\t"
12423 $$emit$$"j$cop,u $labl\n\t"
12424 $$emit$$"done:"
12425 }
12426 %}
12427 ins_encode %{
12428 Label* l = $labl$$label;
12429 if ($cop$$cmpcode == Assembler::notEqual) {
12430 __ jcc(Assembler::parity, *l, false);
12431 __ jcc(Assembler::notEqual, *l, false);
12432 } else if ($cop$$cmpcode == Assembler::equal) {
12433 Label done;
12434 __ jccb(Assembler::parity, done);
12435 __ jcc(Assembler::equal, *l, false);
12436 __ bind(done);
12437 } else {
12438 ShouldNotReachHere();
12439 }
12440 %}
12441 ins_pipe(pipe_jcc);
12442 %}
12443
12444 // ============================================================================
12445 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12446 // superklass array for an instance of the superklass. Set a hidden
12447 // internal cache on a hit (cache is checked with exposed code in
12448 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12449 // encoding ALSO sets flags.
12450
12451 instruct partialSubtypeCheck(rdi_RegP result,
12452 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12453 rFlagsReg cr)
12454 %{
12455 match(Set result (PartialSubtypeCheck sub super));
12456 effect(KILL rcx, KILL cr);
12457
12458 ins_cost(1100); // slightly larger than the next version
12459 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12460 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12461 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12462 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12463 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12464 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12465 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12466 "miss:\t" %}
12467
12468 opcode(0x1); // Force a XOR of RDI
12469 ins_encode(enc_PartialSubtypeCheck());
12470 ins_pipe(pipe_slow);
12471 %}
12472
12473 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12474 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12475 immP0 zero,
12476 rdi_RegP result)
12477 %{
12478 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12479 effect(KILL rcx, KILL result);
12480
12481 ins_cost(1000);
12482 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12483 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12484 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12485 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12486 "jne,s miss\t\t# Missed: flags nz\n\t"
12487 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12488 "miss:\t" %}
12489
12490 opcode(0x0); // No need to XOR RDI
12491 ins_encode(enc_PartialSubtypeCheck());
12492 ins_pipe(pipe_slow);
12493 %}
12494
12495 // ============================================================================
12496 // Branch Instructions -- short offset versions
12497 //
12498 // These instructions are used to replace jumps of a long offset (the default
12499 // match) with jumps of a shorter offset. These instructions are all tagged
12500 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12501 // match rules in general matching. Instead, the ADLC generates a conversion
12502 // method in the MachNode which can be used to do in-place replacement of the
12503 // long variant with the shorter variant. The compiler will determine if a
12504 // branch can be taken by the is_short_branch_offset() predicate in the machine
12505 // specific code section of the file.
12506
12507 // Jump Direct - Label defines a relative address from JMP+1
12508 instruct jmpDir_short(label labl) %{
12509 match(Goto);
12510 effect(USE labl);
12511
12512 ins_cost(300);
12513 format %{ "jmp,s $labl" %}
12514 size(2);
12515 ins_encode %{
12516 Label* L = $labl$$label;
12517 __ jmpb(*L);
12518 %}
12519 ins_pipe(pipe_jmp);
12520 ins_short_branch(1);
12521 %}
12522
12523 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12524 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12525 match(If cop cr);
12526 effect(USE labl);
12527
12528 ins_cost(300);
12529 format %{ "j$cop,s $labl" %}
12530 size(2);
12531 ins_encode %{
12532 Label* L = $labl$$label;
12533 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12534 %}
12535 ins_pipe(pipe_jcc);
12536 ins_short_branch(1);
12537 %}
12538
12539 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12540 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12541 match(CountedLoopEnd cop cr);
12542 effect(USE labl);
12543
12544 ins_cost(300);
12545 format %{ "j$cop,s $labl\t# loop end" %}
12546 size(2);
12547 ins_encode %{
12548 Label* L = $labl$$label;
12549 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12550 %}
12551 ins_pipe(pipe_jcc);
12552 ins_short_branch(1);
12553 %}
12554
12555 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12556 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12557 match(CountedLoopEnd cop cmp);
12558 effect(USE labl);
12559
12560 ins_cost(300);
12561 format %{ "j$cop,us $labl\t# loop end" %}
12562 size(2);
12563 ins_encode %{
12564 Label* L = $labl$$label;
12565 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12566 %}
12567 ins_pipe(pipe_jcc);
12568 ins_short_branch(1);
12569 %}
12570
12571 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12572 match(CountedLoopEnd cop cmp);
12573 effect(USE labl);
12574
12575 ins_cost(300);
12576 format %{ "j$cop,us $labl\t# loop end" %}
12577 size(2);
12578 ins_encode %{
12579 Label* L = $labl$$label;
12580 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12581 %}
12582 ins_pipe(pipe_jcc);
12583 ins_short_branch(1);
12584 %}
12585
12586 // Jump Direct Conditional - using unsigned comparison
12587 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12588 match(If cop cmp);
12589 effect(USE labl);
12590
12591 ins_cost(300);
12592 format %{ "j$cop,us $labl" %}
12593 size(2);
12594 ins_encode %{
12595 Label* L = $labl$$label;
12596 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12597 %}
12598 ins_pipe(pipe_jcc);
12599 ins_short_branch(1);
12600 %}
12601
12602 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12603 match(If cop cmp);
12604 effect(USE labl);
12605
12606 ins_cost(300);
12607 format %{ "j$cop,us $labl" %}
12608 size(2);
12609 ins_encode %{
12610 Label* L = $labl$$label;
12611 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12612 %}
12613 ins_pipe(pipe_jcc);
12614 ins_short_branch(1);
12615 %}
12616
12617 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12618 match(If cop cmp);
12619 effect(USE labl);
12620
12621 ins_cost(300);
12622 format %{ $$template
12623 if ($cop$$cmpcode == Assembler::notEqual) {
12624 $$emit$$"jp,u,s $labl\n\t"
12625 $$emit$$"j$cop,u,s $labl"
12626 } else {
12627 $$emit$$"jp,u,s done\n\t"
12628 $$emit$$"j$cop,u,s $labl\n\t"
12629 $$emit$$"done:"
12630 }
12631 %}
12632 size(4);
12633 ins_encode %{
12634 Label* l = $labl$$label;
12635 if ($cop$$cmpcode == Assembler::notEqual) {
12636 __ jccb(Assembler::parity, *l);
12637 __ jccb(Assembler::notEqual, *l);
12638 } else if ($cop$$cmpcode == Assembler::equal) {
12639 Label done;
12640 __ jccb(Assembler::parity, done);
12641 __ jccb(Assembler::equal, *l);
12642 __ bind(done);
12643 } else {
12644 ShouldNotReachHere();
12645 }
12646 %}
12647 ins_pipe(pipe_jcc);
12648 ins_short_branch(1);
12649 %}
12650
12651 // ============================================================================
12652 // inlined locking and unlocking
12653
12654 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12655 predicate(Compile::current()->use_rtm());
12656 match(Set cr (FastLock object box));
12657 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12658 ins_cost(300);
12659 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12660 ins_encode %{
12661 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12662 $scr$$Register, $cx1$$Register, $cx2$$Register,
12663 _counters, _rtm_counters, _stack_rtm_counters,
12664 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12665 true, ra_->C->profile_rtm());
12666 %}
12667 ins_pipe(pipe_slow);
12668 %}
12669
12670 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12671 predicate(!Compile::current()->use_rtm());
12672 match(Set cr (FastLock object box));
12673 effect(TEMP tmp, TEMP scr, USE_KILL box);
12674 ins_cost(300);
12675 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12676 ins_encode %{
12677 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12678 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12679 %}
12680 ins_pipe(pipe_slow);
12681 %}
12682
12683 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12684 match(Set cr (FastUnlock object box));
12685 effect(TEMP tmp, USE_KILL box);
12686 ins_cost(300);
12687 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12688 ins_encode %{
12689 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12690 %}
12691 ins_pipe(pipe_slow);
12692 %}
12693
12694
12695 // ============================================================================
12696 // Safepoint Instructions
12697 instruct safePoint_poll(rFlagsReg cr)
12698 %{
12699 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12700 match(SafePoint);
12701 effect(KILL cr);
12702
12703 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12704 "# Safepoint: poll for GC" %}
12705 ins_cost(125);
12706 ins_encode %{
12707 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12708 __ testl(rax, addr);
12709 %}
12710 ins_pipe(ialu_reg_mem);
12711 %}
12712
12713 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12714 %{
12715 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12716 match(SafePoint poll);
12717 effect(KILL cr, USE poll);
12718
12719 format %{ "testl rax, [$poll]\t"
12720 "# Safepoint: poll for GC" %}
12721 ins_cost(125);
12722 ins_encode %{
12723 __ relocate(relocInfo::poll_type);
12724 __ testl(rax, Address($poll$$Register, 0));
12725 %}
12726 ins_pipe(ialu_reg_mem);
12727 %}
12728
12729 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12730 %{
12731 predicate(SafepointMechanism::uses_thread_local_poll());
12732 match(SafePoint poll);
12733 effect(KILL cr, USE poll);
12734
12735 format %{ "testl rax, [$poll]\t"
12736 "# Safepoint: poll for GC" %}
12737 ins_cost(125);
12738 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12739 ins_encode %{
12740 __ relocate(relocInfo::poll_type);
12741 address pre_pc = __ pc();
12742 __ testl(rax, Address($poll$$Register, 0));
12743 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12744 %}
12745 ins_pipe(ialu_reg_mem);
12746 %}
12747
12748 // ============================================================================
12749 // Procedure Call/Return Instructions
12750 // Call Java Static Instruction
12751 // Note: If this code changes, the corresponding ret_addr_offset() and
12752 // compute_padding() functions will have to be adjusted.
12753 instruct CallStaticJavaDirect(method meth) %{
12754 match(CallStaticJava);
12755 effect(USE meth);
12756
12757 ins_cost(300);
12758 format %{ "call,static " %}
12759 opcode(0xE8); /* E8 cd */
12760 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12761 ins_pipe(pipe_slow);
12762 ins_alignment(4);
12763 %}
12764
12765 // Call Java Dynamic Instruction
12766 // Note: If this code changes, the corresponding ret_addr_offset() and
12767 // compute_padding() functions will have to be adjusted.
12768 instruct CallDynamicJavaDirect(method meth)
12769 %{
12770 match(CallDynamicJava);
12771 effect(USE meth);
12772
12773 ins_cost(300);
12774 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12775 "call,dynamic " %}
12776 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12777 ins_pipe(pipe_slow);
12778 ins_alignment(4);
12779 %}
12780
12781 // Call Runtime Instruction
12782 instruct CallRuntimeDirect(method meth)
12783 %{
12784 match(CallRuntime);
12785 effect(USE meth);
12786
12787 ins_cost(300);
12788 format %{ "call,runtime " %}
12789 ins_encode(clear_avx, Java_To_Runtime(meth));
12790 ins_pipe(pipe_slow);
12791 %}
12792
12793 // Call runtime without safepoint
12794 instruct CallLeafDirect(method meth)
12795 %{
12796 match(CallLeaf);
12797 effect(USE meth);
12798
12799 ins_cost(300);
12800 format %{ "call_leaf,runtime " %}
12801 ins_encode(clear_avx, Java_To_Runtime(meth));
12802 ins_pipe(pipe_slow);
12803 %}
12804
12805 // Call runtime without safepoint
12806 instruct CallLeafNoFPDirect(method meth)
12807 %{
12808 match(CallLeafNoFP);
12809 effect(USE meth);
12810
12811 ins_cost(300);
12812 format %{ "call_leaf_nofp,runtime " %}
12813 ins_encode(clear_avx, Java_To_Runtime(meth));
12814 ins_pipe(pipe_slow);
12815 %}
12816
12817 // Return Instruction
12818 // Remove the return address & jump to it.
12819 // Notice: We always emit a nop after a ret to make sure there is room
12820 // for safepoint patching
12821 instruct Ret()
12822 %{
12823 match(Return);
12824
12825 format %{ "ret" %}
12826 opcode(0xC3);
12827 ins_encode(OpcP);
12828 ins_pipe(pipe_jmp);
12829 %}
12830
12831 // Tail Call; Jump from runtime stub to Java code.
12832 // Also known as an 'interprocedural jump'.
12833 // Target of jump will eventually return to caller.
12834 // TailJump below removes the return address.
12835 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12836 %{
12837 match(TailCall jump_target method_oop);
12838
12839 ins_cost(300);
12840 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12841 opcode(0xFF, 0x4); /* Opcode FF /4 */
12842 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12843 ins_pipe(pipe_jmp);
12844 %}
12845
12846 // Tail Jump; remove the return address; jump to target.
12847 // TailCall above leaves the return address around.
12848 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12849 %{
12850 match(TailJump jump_target ex_oop);
12851
12852 ins_cost(300);
12853 format %{ "popq rdx\t# pop return address\n\t"
12854 "jmp $jump_target" %}
12855 opcode(0xFF, 0x4); /* Opcode FF /4 */
12856 ins_encode(Opcode(0x5a), // popq rdx
12857 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12858 ins_pipe(pipe_jmp);
12859 %}
12860
12861 // Create exception oop: created by stack-crawling runtime code.
12862 // Created exception is now available to this handler, and is setup
12863 // just prior to jumping to this handler. No code emitted.
12864 instruct CreateException(rax_RegP ex_oop)
12865 %{
12866 match(Set ex_oop (CreateEx));
12867
12868 size(0);
12869 // use the following format syntax
12870 format %{ "# exception oop is in rax; no code emitted" %}
12871 ins_encode();
12872 ins_pipe(empty);
12873 %}
12874
12875 // Rethrow exception:
12876 // The exception oop will come in the first argument position.
12877 // Then JUMP (not call) to the rethrow stub code.
12878 instruct RethrowException()
12879 %{
12880 match(Rethrow);
12881
12882 // use the following format syntax
12883 format %{ "jmp rethrow_stub" %}
12884 ins_encode(enc_rethrow);
12885 ins_pipe(pipe_jmp);
12886 %}
12887
12888 // ============================================================================
12889 // This name is KNOWN by the ADLC and cannot be changed.
12890 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12891 // for this guy.
12892 instruct tlsLoadP(r15_RegP dst) %{
12893 match(Set dst (ThreadLocal));
12894 effect(DEF dst);
12895
12896 size(0);
12897 format %{ "# TLS is in R15" %}
12898 ins_encode( /*empty encoding*/ );
12899 ins_pipe(ialu_reg_reg);
12900 %}
12901
12902
12903 //----------PEEPHOLE RULES-----------------------------------------------------
12904 // These must follow all instruction definitions as they use the names
12905 // defined in the instructions definitions.
12906 //
12907 // peepmatch ( root_instr_name [preceding_instruction]* );
12908 //
12909 // peepconstraint %{
12910 // (instruction_number.operand_name relational_op instruction_number.operand_name
12911 // [, ...] );
12912 // // instruction numbers are zero-based using left to right order in peepmatch
12913 //
12914 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12915 // // provide an instruction_number.operand_name for each operand that appears
12916 // // in the replacement instruction's match rule
12917 //
12918 // ---------VM FLAGS---------------------------------------------------------
12919 //
12920 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12921 //
12922 // Each peephole rule is given an identifying number starting with zero and
12923 // increasing by one in the order seen by the parser. An individual peephole
12924 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12925 // on the command-line.
12926 //
12927 // ---------CURRENT LIMITATIONS----------------------------------------------
12928 //
12929 // Only match adjacent instructions in same basic block
12930 // Only equality constraints
12931 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12932 // Only one replacement instruction
12933 //
12934 // ---------EXAMPLE----------------------------------------------------------
12935 //
12936 // // pertinent parts of existing instructions in architecture description
12937 // instruct movI(rRegI dst, rRegI src)
12938 // %{
12939 // match(Set dst (CopyI src));
12940 // %}
12941 //
12942 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12943 // %{
12944 // match(Set dst (AddI dst src));
12945 // effect(KILL cr);
12946 // %}
12947 //
12948 // // Change (inc mov) to lea
12949 // peephole %{
12950 // // increment preceeded by register-register move
12951 // peepmatch ( incI_rReg movI );
12952 // // require that the destination register of the increment
12953 // // match the destination register of the move
12954 // peepconstraint ( 0.dst == 1.dst );
12955 // // construct a replacement instruction that sets
12956 // // the destination to ( move's source register + one )
12957 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12958 // %}
12959 //
12960
12961 // Implementation no longer uses movX instructions since
12962 // machine-independent system no longer uses CopyX nodes.
12963 //
12964 // peephole
12965 // %{
12966 // peepmatch (incI_rReg movI);
12967 // peepconstraint (0.dst == 1.dst);
12968 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12969 // %}
12970
12971 // peephole
12972 // %{
12973 // peepmatch (decI_rReg movI);
12974 // peepconstraint (0.dst == 1.dst);
12975 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12976 // %}
12977
12978 // peephole
12979 // %{
12980 // peepmatch (addI_rReg_imm movI);
12981 // peepconstraint (0.dst == 1.dst);
12982 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12983 // %}
12984
12985 // peephole
12986 // %{
12987 // peepmatch (incL_rReg movL);
12988 // peepconstraint (0.dst == 1.dst);
12989 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12990 // %}
12991
12992 // peephole
12993 // %{
12994 // peepmatch (decL_rReg movL);
12995 // peepconstraint (0.dst == 1.dst);
12996 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12997 // %}
12998
12999 // peephole
13000 // %{
13001 // peepmatch (addL_rReg_imm movL);
13002 // peepconstraint (0.dst == 1.dst);
13003 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13004 // %}
13005
13006 // peephole
13007 // %{
13008 // peepmatch (addP_rReg_imm movP);
13009 // peepconstraint (0.dst == 1.dst);
13010 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13011 // %}
13012
13013 // // Change load of spilled value to only a spill
13014 // instruct storeI(memory mem, rRegI src)
13015 // %{
13016 // match(Set mem (StoreI mem src));
13017 // %}
13018 //
13019 // instruct loadI(rRegI dst, memory mem)
13020 // %{
13021 // match(Set dst (LoadI mem));
13022 // %}
13023 //
13024
13025 peephole
13026 %{
13027 peepmatch (loadI storeI);
13028 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13029 peepreplace (storeI(1.mem 1.mem 1.src));
13030 %}
13031
13032 peephole
13033 %{
13034 peepmatch (loadL storeL);
13035 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13036 peepreplace (storeL(1.mem 1.mem 1.src));
13037 %}
13038
13039 //----------SMARTSPILL RULES---------------------------------------------------
13040 // These must follow all instruction definitions as they use the names
13041 // defined in the instructions definitions.