417     emit_int32(cond << 28 | 0x06bf0f30 | rd->encoding() << 12 | rm->encoding());
 418   }
 419 
 420   void rev16(Register rd, Register rm, AsmCondition cond = al) {
 421     emit_int32(cond << 28 | 0x6bf0fb0 | rd->encoding() << 12 | rm->encoding());
 422   }
 423 
 424   void revsh(Register rd, Register rm, AsmCondition cond = al) {
 425     emit_int32(cond << 28 | 0x6ff0fb0 | rd->encoding() << 12 | rm->encoding());
 426   }
 427 
 428   void rbit(Register rd, Register rm, AsmCondition cond = al) {
 429     emit_int32(cond << 28 | 0x6ff0f30 | rd->encoding() << 12 | rm->encoding());
 430   }
 431 
 432   void pld(Address addr) {
 433     emit_int32(0xf550f000 | addr.encoding2());
 434   }
 435 
 436   void pldw(Address addr) {
 437     assert(VM_Version::arm_arch() >= 7 && os::is_MP(), "no pldw on this processor");
 438     emit_int32(0xf510f000 | addr.encoding2());
 439   }
 440 
 441   void svc(int imm_24, AsmCondition cond = al) {
 442     assert((imm_24 >> 24) == 0, "encoding constraint");
 443     emit_int32(cond << 28 | 0xf << 24 | imm_24);
 444   }
 445 
 446   void ubfx(Register rd, Register rn, unsigned int lsb, unsigned int width, AsmCondition cond = al) {
 447     assert(VM_Version::arm_arch() >= 7, "no ubfx on this processor");
 448     assert(width > 0, "must be");
 449     assert(lsb < 32, "must be");
 450     emit_int32(cond << 28 | 0x3f << 21 | (width - 1)  << 16 | rd->encoding() << 12 |
 451               lsb << 7 | 0x5 << 4 | rn->encoding());
 452   }
 453 
 454   void uxtb(Register rd, Register rm, unsigned int rotation = 0, AsmCondition cond = al) {
 455     assert(VM_Version::arm_arch() >= 7, "no uxtb on this processor");
 456     assert((rotation % 8) == 0 && (rotation <= 24), "encoding constraint");
 457     emit_int32(cond << 28 | 0x6e << 20 | 0xf << 16 | rd->encoding() << 12 |

 417     emit_int32(cond << 28 | 0x06bf0f30 | rd->encoding() << 12 | rm->encoding());
 418   }
 419 
 420   void rev16(Register rd, Register rm, AsmCondition cond = al) {
 421     emit_int32(cond << 28 | 0x6bf0fb0 | rd->encoding() << 12 | rm->encoding());
 422   }
 423 
 424   void revsh(Register rd, Register rm, AsmCondition cond = al) {
 425     emit_int32(cond << 28 | 0x6ff0fb0 | rd->encoding() << 12 | rm->encoding());
 426   }
 427 
 428   void rbit(Register rd, Register rm, AsmCondition cond = al) {
 429     emit_int32(cond << 28 | 0x6ff0f30 | rd->encoding() << 12 | rm->encoding());
 430   }
 431 
 432   void pld(Address addr) {
 433     emit_int32(0xf550f000 | addr.encoding2());
 434   }
 435 
 436   void pldw(Address addr) {
 437     assert(VM_Version::arm_arch() >= 7, "no pldw on this processor");
 438     emit_int32(0xf510f000 | addr.encoding2());
 439   }
 440 
 441   void svc(int imm_24, AsmCondition cond = al) {
 442     assert((imm_24 >> 24) == 0, "encoding constraint");
 443     emit_int32(cond << 28 | 0xf << 24 | imm_24);
 444   }
 445 
 446   void ubfx(Register rd, Register rn, unsigned int lsb, unsigned int width, AsmCondition cond = al) {
 447     assert(VM_Version::arm_arch() >= 7, "no ubfx on this processor");
 448     assert(width > 0, "must be");
 449     assert(lsb < 32, "must be");
 450     emit_int32(cond << 28 | 0x3f << 21 | (width - 1)  << 16 | rd->encoding() << 12 |
 451               lsb << 7 | 0x5 << 4 | rn->encoding());
 452   }
 453 
 454   void uxtb(Register rd, Register rm, unsigned int rotation = 0, AsmCondition cond = al) {
 455     assert(VM_Version::arm_arch() >= 7, "no uxtb on this processor");
 456     assert((rotation % 8) == 0 && (rotation <= 24), "encoding constraint");
 457     emit_int32(cond << 28 | 0x6e << 20 | 0xf << 16 | rd->encoding() << 12 |