496 return slot;
497
498 #else // AARCH64
499
500 int slot = 0;
501 int ireg = 0;
502 #ifdef __ABI_HARD__
503 int fp_slot = 0;
504 int single_fpr_slot = 0;
505 #endif // __ABI_HARD__
506 for (int i = 0; i < total_args_passed; i++) {
507 switch (sig_bt[i]) {
508 case T_SHORT:
509 case T_CHAR:
510 case T_BYTE:
511 case T_BOOLEAN:
512 case T_INT:
513 case T_ARRAY:
514 case T_OBJECT:
515 case T_ADDRESS:
516 #ifndef __ABI_HARD__
517 case T_FLOAT:
518 #endif // !__ABI_HARD__
519 if (ireg < 4) {
520 Register r = as_Register(ireg);
521 regs[i].set1(r->as_VMReg());
522 ireg++;
523 } else {
524 regs[i].set1(VMRegImpl::stack2reg(slot));
525 slot++;
526 }
527 break;
528 case T_LONG:
529 #ifndef __ABI_HARD__
530 case T_DOUBLE:
531 #endif // !__ABI_HARD__
532 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
533 if (ireg <= 2) {
534 #if (ALIGN_WIDE_ARGUMENTS == 1)
535 if(ireg & 1) ireg++; // Aligned location required
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496 return slot;
497
498 #else // AARCH64
499
500 int slot = 0;
501 int ireg = 0;
502 #ifdef __ABI_HARD__
503 int fp_slot = 0;
504 int single_fpr_slot = 0;
505 #endif // __ABI_HARD__
506 for (int i = 0; i < total_args_passed; i++) {
507 switch (sig_bt[i]) {
508 case T_SHORT:
509 case T_CHAR:
510 case T_BYTE:
511 case T_BOOLEAN:
512 case T_INT:
513 case T_ARRAY:
514 case T_OBJECT:
515 case T_ADDRESS:
516 case T_METADATA:
517 #ifndef __ABI_HARD__
518 case T_FLOAT:
519 #endif // !__ABI_HARD__
520 if (ireg < 4) {
521 Register r = as_Register(ireg);
522 regs[i].set1(r->as_VMReg());
523 ireg++;
524 } else {
525 regs[i].set1(VMRegImpl::stack2reg(slot));
526 slot++;
527 }
528 break;
529 case T_LONG:
530 #ifndef __ABI_HARD__
531 case T_DOUBLE:
532 #endif // !__ABI_HARD__
533 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
534 if (ireg <= 2) {
535 #if (ALIGN_WIDE_ARGUMENTS == 1)
536 if(ireg & 1) ireg++; // Aligned location required
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