/* * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef CPU_AARCH64_ICACHE_AARCH64_HPP #define CPU_AARCH64_ICACHE_AARCH64_HPP // Interface for updating the instruction cache. Whenever the VM // modifies code, part of the processor instruction cache potentially // has to be flushed. class ICache : public AbstractICache { private: #ifdef _WIN64 // __builtin___clear_cache is a GCC intrinsic, and is then not available in // MSVC. Define an equivalent method which calls the right Win32/MSVC // intrinsic. static void __builtin___clear_cache(char *start, char *end) { FlushInstructionCache((HANDLE)GetCurrentProcess(), start, (SIZE_T)(end - start)); } #endif public: static void initialize(); static void invalidate_word(address addr) { __builtin___clear_cache((char *)addr, (char *)(addr + 3)); } static void invalidate_range(address start, int nbytes) { __builtin___clear_cache((char *)start, (char *)(start + nbytes)); } }; #endif // CPU_AARCH64_ICACHE_AARCH64_HPP