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8248238: Adding Windows support to OpenJDK on AArch64
Summary: LP64 vs LLP64 changes to add Windows support
Contributed-by: Monica Beckwith <monica.beckwith@microsoft.com>, Ludovic Henry <luhenry@microsoft.com>
Reviewed-by:
8248238: Adding Windows support to OpenJDK on AArch64
Summary: Adding Windows support for AArch64
Contributed-by: Ludovic Henry <luhenry@microsoft.com>, Monica Beckwith <monica.beckwith@microsoft.com>
Reviewed-by:
*** 530,546 ****
--- 530,564 ----
return _ANY_REG_mask;
%}
// Class for non-allocatable 32 bit registers
reg_class non_allocatable_reg32(
+ #ifdef _WIN64
+ // On Windows-aarch64, R18 is used to store the pointer to the current
+ // thread's TEB which is itself used to store TLS variables.
+ // An alternative to simply never allocate it would be to save/restore it
+ // at key places. However, because the OS/Win32 exception handling (for
+ // segmentation faults for example) does use TLS to unwind the stack for
+ // Structured Exception Handling. If R18 were to be used for any other
+ // purpose at the time of the exception, the OS/Win32 would not be able to
+ // unwind the stack, and it would result in a crash. Because there are so
+ // many places where such an exception may happen, it's simpler and more
+ // efficient to never allocate R18.
+ //
+ // See https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019#integer-registers
+ R18, // tls on Windows
+ #endif
R28, // thread
R30, // lr
R31 // sp
);
// Class for non-allocatable 64 bit registers
reg_class non_allocatable_reg(
+ #ifdef _WIN64
+ R18, R18_H, // tls on Windows
+ #endif
R28, R28_H, // thread
R30, R30_H, // lr
R31, R31_H // sp
);
*** 980,989 ****
--- 998,1009 ----
#include "asm/macroAssembler.hpp"
#include "gc/shared/cardTable.hpp"
#include "gc/shared/cardTableBarrierSet.hpp"
#include "gc/shared/collectedHeap.hpp"
+ #include "gc/shared/barrierSet.hpp"
+ #include "gc/shared/barrierSetAssembler.hpp"
#include "opto/addnode.hpp"
#include "opto/convertnode.hpp"
extern RegMask _ANY_REG32_mask;
extern RegMask _ANY_REG_mask;
*** 1624,1634 ****
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
Compile* C = ra_->C;
C2_MacroAssembler _masm(&cbuf);
// n.b. frame size includes space for return pc and rfp
! const long framesize = C->output()->frame_size_in_bytes();
assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
// insert a nop at the start of the prolog so we can patch in a
// branch if we need to invalidate the method later
__ nop();
--- 1644,1654 ----
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
Compile* C = ra_->C;
C2_MacroAssembler _masm(&cbuf);
// n.b. frame size includes space for return pc and rfp
! const int64_t framesize = C->output()->frame_size_in_bytes();
assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
// insert a nop at the start of the prolog so we can patch in a
// branch if we need to invalidate the method later
__ nop();
*** 3116,3126 ****
/// mov envcodings
enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
C2_MacroAssembler _masm(&cbuf);
! u_int32_t con = (u_int32_t)$src$$constant;
Register dst_reg = as_Register($dst$$reg);
if (con == 0) {
__ movw(dst_reg, zr);
} else {
__ movw(dst_reg, con);
--- 3136,3146 ----
/// mov envcodings
enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
C2_MacroAssembler _masm(&cbuf);
! uint32_t con = (uint32_t)$src$$constant;
Register dst_reg = as_Register($dst$$reg);
if (con == 0) {
__ movw(dst_reg, zr);
} else {
__ movw(dst_reg, con);
*** 3128,3138 ****
%}
enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
C2_MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
! u_int64_t con = (u_int64_t)$src$$constant;
if (con == 0) {
__ mov(dst_reg, zr);
} else {
__ mov(dst_reg, con);
}
--- 3148,3158 ----
%}
enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
C2_MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
! uint64_t con = (uint64_t)$src$$constant;
if (con == 0) {
__ mov(dst_reg, zr);
} else {
__ mov(dst_reg, con);
}
*** 3153,3163 ****
} else {
assert(rtype == relocInfo::none, "unexpected reloc type");
if (con < (address)(uintptr_t)os::vm_page_size()) {
__ mov(dst_reg, con);
} else {
! unsigned long offset;
__ adrp(dst_reg, con, offset);
__ add(dst_reg, dst_reg, offset);
}
}
}
--- 3173,3183 ----
} else {
assert(rtype == relocInfo::none, "unexpected reloc type");
if (con < (address)(uintptr_t)os::vm_page_size()) {
__ mov(dst_reg, con);
} else {
! uint64_t offset;
__ adrp(dst_reg, con, offset);
__ add(dst_reg, dst_reg, offset);
}
}
}
*** 3170,3180 ****
%}
enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
C2_MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
! __ mov(dst_reg, (u_int64_t)1);
%}
enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
C2_MacroAssembler _masm(&cbuf);
__ load_byte_map_base($dst$$Register);
--- 3190,3200 ----
%}
enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
C2_MacroAssembler _masm(&cbuf);
Register dst_reg = as_Register($dst$$reg);
! __ mov(dst_reg, (uint64_t)1);
%}
enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
C2_MacroAssembler _masm(&cbuf);
__ load_byte_map_base($dst$$Register);
*** 3295,3305 ****
%}
enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
C2_MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
! u_int32_t val = (u_int32_t)$src2$$constant;
__ movw(rscratch1, val);
__ cmpw(reg1, rscratch1);
%}
enc_class aarch64_enc_cmp(iRegL src1, iRegL src2) %{
--- 3315,3325 ----
%}
enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
C2_MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
! uint32_t val = (uint32_t)$src2$$constant;
__ movw(rscratch1, val);
__ cmpw(reg1, rscratch1);
%}
enc_class aarch64_enc_cmp(iRegL src1, iRegL src2) %{
*** 3317,3335 ****
__ subs(zr, reg, val);
} else if (val != -val) {
__ adds(zr, reg, -val);
} else {
// aargh, Long.MIN_VALUE is a special case
! __ orr(rscratch1, zr, (u_int64_t)val);
__ subs(zr, reg, rscratch1);
}
%}
enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
C2_MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
! u_int64_t val = (u_int64_t)$src2$$constant;
__ mov(rscratch1, val);
__ cmp(reg1, rscratch1);
%}
enc_class aarch64_enc_cmpp(iRegP src1, iRegP src2) %{
--- 3337,3355 ----
__ subs(zr, reg, val);
} else if (val != -val) {
__ adds(zr, reg, -val);
} else {
// aargh, Long.MIN_VALUE is a special case
! __ orr(rscratch1, zr, (uint64_t)val);
__ subs(zr, reg, rscratch1);
}
%}
enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
C2_MacroAssembler _masm(&cbuf);
Register reg1 = as_Register($src1$$reg);
! uint64_t val = (uint64_t)$src2$$constant;
__ mov(rscratch1, val);
__ cmp(reg1, rscratch1);
%}
enc_class aarch64_enc_cmpp(iRegP src1, iRegP src2) %{
*** 4225,4246 ****
%}
// 32 bit integer valid for add sub immediate
operand immIAddSub()
%{
! predicate(Assembler::operand_valid_for_add_sub_immediate((long)n->get_int()));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// 32 bit unsigned integer valid for logical immediate
// TODO -- check this is right when e.g the mask is 0x80000000
operand immILog()
%{
! predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (unsigned long)n->get_int()));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
--- 4245,4266 ----
%}
// 32 bit integer valid for add sub immediate
operand immIAddSub()
%{
! predicate(Assembler::operand_valid_for_add_sub_immediate((int64_t)n->get_int()));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// 32 bit unsigned integer valid for logical immediate
// TODO -- check this is right when e.g the mask is 0x80000000
operand immILog()
%{
! predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (uint64_t)n->get_int()));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
*** 4314,4324 ****
%}
// 64 bit integer valid for logical immediate
operand immLLog()
%{
! predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (unsigned long)n->get_long()));
match(ConL);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
--- 4334,4344 ----
%}
// 64 bit integer valid for logical immediate
operand immLLog()
%{
! predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (uint64_t)n->get_long()));
match(ConL);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
*** 5874,5884 ****
pipeline %{
attributes %{
// ARM instructions are of fixed length
fixed_size_instructions; // Fixed size instructions TODO does
! max_instructions_per_bundle = 2; // A53 = 2, A57 = 4
// ARM instructions come in 32-bit word units
instruction_unit_size = 4; // An instruction is 4 bytes long
instruction_fetch_unit_size = 64; // The processor fetches one line
instruction_fetch_units = 1; // of 64 bytes
--- 5894,5904 ----
pipeline %{
attributes %{
// ARM instructions are of fixed length
fixed_size_instructions; // Fixed size instructions TODO does
! max_instructions_per_bundle = 4; // A53 = 2, A57 = 4
// ARM instructions come in 32-bit word units
instruction_unit_size = 4; // An instruction is 4 bytes long
instruction_fetch_unit_size = 64; // The processor fetches one line
instruction_fetch_units = 1; // of 64 bytes
*** 7110,7120 ****
instruct loadConL(iRegLNoSp dst, immL src)
%{
match(Set dst src);
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# long" %}
ins_encode( aarch64_enc_mov_imm(dst, src) );
ins_pipe(ialu_imm);
%}
--- 7130,7140 ----
instruct loadConL(iRegLNoSp dst, immL src)
%{
match(Set dst src);
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# int64_t" %}
ins_encode( aarch64_enc_mov_imm(dst, src) );
ins_pipe(ialu_imm);
%}
*** 8246,8256 ****
instruct castX2P(iRegPNoSp dst, iRegL src) %{
match(Set dst (CastX2P src));
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# long -> ptr" %}
ins_encode %{
if ($dst$$reg != $src$$reg) {
__ mov(as_Register($dst$$reg), as_Register($src$$reg));
}
--- 8266,8276 ----
instruct castX2P(iRegPNoSp dst, iRegL src) %{
match(Set dst (CastX2P src));
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# int64_t -> ptr" %}
ins_encode %{
if ($dst$$reg != $src$$reg) {
__ mov(as_Register($dst$$reg), as_Register($src$$reg));
}
*** 8261,8271 ****
instruct castP2X(iRegLNoSp dst, iRegP src) %{
match(Set dst (CastP2X src));
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# ptr -> long" %}
ins_encode %{
if ($dst$$reg != $src$$reg) {
__ mov(as_Register($dst$$reg), as_Register($src$$reg));
}
--- 8281,8291 ----
instruct castP2X(iRegLNoSp dst, iRegP src) %{
match(Set dst (CastP2X src));
ins_cost(INSN_COST);
! format %{ "mov $dst, $src\t# ptr -> int64_t" %}
ins_encode %{
if ($dst$$reg != $src$$reg) {
__ mov(as_Register($dst$$reg), as_Register($src$$reg));
}
*** 8599,8609 ****
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
aarch64_enc_cset_eq(res));
--- 8619,8629 ----
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg $mem, $oldval, $newval\t# (int64_t) if $mem == $oldval then $mem <-- $newval"
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
aarch64_enc_cset_eq(res));
*** 8714,8724 ****
ins_cost(VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
aarch64_enc_cset_eq(res));
--- 8734,8744 ----
ins_cost(VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg_acq $mem, $oldval, $newval\t# (int64_t) if $mem == $oldval then $mem <-- $newval"
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
aarch64_enc_cset_eq(res));
*** 8831,8841 ****
instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
format %{
! "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ false, /*release*/ true,
/*weak*/ false, $res$$Register);
--- 8851,8861 ----
instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
format %{
! "cmpxchg $res = $mem, $oldval, $newval\t# (int64_t, weak) if $mem == $oldval then $mem <-- $newval"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ false, /*release*/ true,
/*weak*/ false, $res$$Register);
*** 8929,8939 ****
predicate(needs_acquiring_load_exclusive(n));
match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
format %{
! "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ true, /*release*/ true,
/*weak*/ false, $res$$Register);
--- 8949,8959 ----
predicate(needs_acquiring_load_exclusive(n));
match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
effect(TEMP_DEF res, KILL cr);
format %{
! "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int64_t, weak) if $mem == $oldval then $mem <-- $newval"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ true, /*release*/ true,
/*weak*/ false, $res$$Register);
*** 9028,9038 ****
instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ false, /*release*/ true,
--- 9048,9058 ----
instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
ins_cost(2 * VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg $res = $mem, $oldval, $newval\t# (int64_t, weak) if $mem == $oldval then $mem <-- $newval"
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ false, /*release*/ true,
*** 9135,9145 ****
predicate(needs_acquiring_load_exclusive(n));
match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ true, /*release*/ true,
--- 9155,9165 ----
predicate(needs_acquiring_load_exclusive(n));
match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
ins_cost(VOLATILE_REF_COST);
effect(KILL cr);
format %{
! "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int64_t, weak) if $mem == $oldval then $mem <-- $newval"
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
%}
ins_encode %{
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
Assembler::xword, /*acquire*/ true, /*release*/ true,
*** 9657,9667 ****
instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src2$$reg),
as_Register($src1$$reg),
--- 9677,9687 ----
instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src2, $src1 $cmp\t# signed, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src2$$reg),
as_Register($src1$$reg),
*** 9673,9683 ****
instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src2$$reg),
as_Register($src1$$reg),
--- 9693,9703 ----
instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src2$$reg),
as_Register($src1$$reg),
*** 9691,9701 ****
instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, zr, $src $cmp\t# signed, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
zr,
as_Register($src$$reg),
--- 9711,9721 ----
instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, zr, $src $cmp\t# signed, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
zr,
as_Register($src$$reg),
*** 9707,9717 ****
instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, zr, $src $cmp\t# unsigned, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
zr,
as_Register($src$$reg),
--- 9727,9737 ----
instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, zr, $src $cmp\t# unsigned, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
zr,
as_Register($src$$reg),
*** 9723,9733 ****
instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src, zr $cmp\t# signed, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src$$reg),
zr,
--- 9743,9753 ----
instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src, zr $cmp\t# signed, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src$$reg),
zr,
*** 9739,9749 ****
instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src, zr $cmp\t# unsigned, long" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src$$reg),
zr,
--- 9759,9769 ----
instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
ins_cost(INSN_COST * 2);
! format %{ "csel $dst, $src, zr $cmp\t# unsigned, int64_t" %}
ins_encode %{
__ csel(as_Register($dst$$reg),
as_Register($src$$reg),
zr,
*** 10144,10154 ****
format %{ "sbfiz $dst, $src, $scale & 63, -$scale & 63\t" %}
ins_encode %{
__ sbfiz(as_Register($dst$$reg),
as_Register($src$$reg),
! $scale$$constant & 63, MIN(32, (-$scale$$constant) & 63));
%}
ins_pipe(ialu_reg_shift);
%}
--- 10164,10174 ----
format %{ "sbfiz $dst, $src, $scale & 63, -$scale & 63\t" %}
ins_encode %{
__ sbfiz(as_Register($dst$$reg),
as_Register($src$$reg),
! $scale$$constant & 63, MIN2(32, (int)((-$scale$$constant) & 63)));
%}
ins_pipe(ialu_reg_shift);
%}
*** 10284,10294 ****
instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero, rFlagsReg cr) %{
match(Set dst (SubL zero src));
ins_cost(INSN_COST);
! format %{ "neg $dst, $src\t# long" %}
ins_encode %{
__ neg(as_Register($dst$$reg),
as_Register($src$$reg));
%}
--- 10304,10314 ----
instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero, rFlagsReg cr) %{
match(Set dst (SubL zero src));
ins_cost(INSN_COST);
! format %{ "neg $dst, $src\t# int64_t" %}
ins_encode %{
__ neg(as_Register($dst$$reg),
as_Register($src$$reg));
%}
*** 11918,11928 ****
ins_cost(INSN_COST);
format %{ "ubfxw $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
! long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfxw(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 11938,11948 ----
ins_cost(INSN_COST);
format %{ "ubfxw $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
! int64_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfxw(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 11935,11945 ****
ins_cost(INSN_COST);
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 63;
! long mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 11955,11965 ----
ins_cost(INSN_COST);
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 63;
! int64_t mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 11955,11965 ****
ins_cost(INSN_COST * 2);
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
! long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 11975,11985 ----
ins_cost(INSN_COST * 2);
format %{ "ubfx $dst, $src, $rshift, $mask" %}
ins_encode %{
int rshift = $rshift$$constant & 31;
! int64_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 11974,11984 ****
ins_cost(INSN_COST);
format %{ "ubfizw $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 31;
! long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfizw(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 11994,12004 ----
ins_cost(INSN_COST);
format %{ "ubfizw $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 31;
! int64_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfizw(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 11992,12002 ****
ins_cost(INSN_COST);
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
! long mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 12012,12022 ----
ins_cost(INSN_COST);
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
! int64_t mask = $mask$$constant;
int width = exact_log2_long(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 12010,12020 ****
ins_cost(INSN_COST);
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
! long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
--- 12030,12040 ----
ins_cost(INSN_COST);
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
ins_encode %{
int lshift = $lshift$$constant & 63;
! int64_t mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfiz(as_Register($dst$$reg),
as_Register($src$$reg), lshift, width);
%}
ins_pipe(ialu_reg_shift);
*** 13247,13257 ****
ins_cost(INSN_COST);
ins_encode %{
__ andw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13267,13277 ----
ins_cost(INSN_COST);
ins_encode %{
__ andw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13279,13289 ****
ins_cost(INSN_COST);
ins_encode %{
__ orrw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13299,13309 ----
ins_cost(INSN_COST);
ins_encode %{
__ orrw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13311,13321 ****
ins_cost(INSN_COST);
ins_encode %{
__ eorw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13331,13341 ----
ins_cost(INSN_COST);
ins_encode %{
__ eorw(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13344,13354 ****
ins_cost(INSN_COST);
ins_encode %{
__ andr(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13364,13374 ----
ins_cost(INSN_COST);
ins_encode %{
__ andr(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13376,13386 ****
ins_cost(INSN_COST);
ins_encode %{
__ orr(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13396,13406 ----
ins_cost(INSN_COST);
ins_encode %{
__ orr(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13408,13418 ****
format %{ "eor $dst, $src1, $src2\t# int" %}
ins_encode %{
__ eor(as_Register($dst$$reg),
as_Register($src1$$reg),
! (unsigned long)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
--- 13428,13438 ----
format %{ "eor $dst, $src1, $src2\t# int" %}
ins_encode %{
__ eor(as_Register($dst$$reg),
as_Register($src1$$reg),
! (uint64_t)($src2$$constant));
%}
ins_pipe(ialu_reg_imm);
%}
*** 13857,13876 ****
ins_pipe(pipe_class_memory);
%}
instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
%{
! predicate((u_int64_t)n->in(2)->get_long()
! < (u_int64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
match(Set dummy (ClearArray cnt base));
effect(USE_KILL base);
ins_cost(4 * INSN_COST);
format %{ "ClearArray $cnt, $base" %}
ins_encode %{
! __ zero_words($base$$Register, (u_int64_t)$cnt$$constant);
%}
ins_pipe(pipe_class_memory);
%}
--- 13877,13896 ----
ins_pipe(pipe_class_memory);
%}
instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
%{
! predicate((uint64_t)n->in(2)->get_long()
! < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
match(Set dummy (ClearArray cnt base));
effect(USE_KILL base);
ins_cost(4 * INSN_COST);
format %{ "ClearArray $cnt, $base" %}
ins_encode %{
! __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
%}
ins_pipe(pipe_class_memory);
%}
*** 13905,13915 ****
instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowAddL op1 op2));
! format %{ "cmn $op1, $op2\t# overflow check long" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmn($op1$$Register, $op2$$Register);
%}
--- 13925,13935 ----
instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowAddL op1 op2));
! format %{ "cmn $op1, $op2\t# overflow check int64_t" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmn($op1$$Register, $op2$$Register);
%}
*** 13918,13928 ****
instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
%{
match(Set cr (OverflowAddL op1 op2));
! format %{ "cmn $op1, $op2\t# overflow check long" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmn($op1$$Register, $op2$$constant);
%}
--- 13938,13948 ----
instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
%{
match(Set cr (OverflowAddL op1 op2));
! format %{ "cmn $op1, $op2\t# overflow check int64_t" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmn($op1$$Register, $op2$$constant);
%}
*** 13957,13967 ****
instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowSubL op1 op2));
! format %{ "cmp $op1, $op2\t# overflow check long" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmp($op1$$Register, $op2$$Register);
%}
--- 13977,13987 ----
instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowSubL op1 op2));
! format %{ "cmp $op1, $op2\t# overflow check int64_t" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmp($op1$$Register, $op2$$Register);
%}
*** 13970,13980 ****
instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
%{
match(Set cr (OverflowSubL op1 op2));
! format %{ "cmp $op1, $op2\t# overflow check long" %}
ins_cost(INSN_COST);
ins_encode %{
__ subs(zr, $op1$$Register, $op2$$constant);
%}
--- 13990,14000 ----
instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
%{
match(Set cr (OverflowSubL op1 op2));
! format %{ "cmp $op1, $op2\t# overflow check int64_t" %}
ins_cost(INSN_COST);
ins_encode %{
__ subs(zr, $op1$$Register, $op2$$constant);
%}
*** 13996,14006 ****
instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op1)
%{
match(Set cr (OverflowSubL zero op1));
! format %{ "cmp zr, $op1\t# overflow check long" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmp(zr, $op1$$Register);
%}
--- 14016,14026 ----
instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op1)
%{
match(Set cr (OverflowSubL zero op1));
! format %{ "cmp zr, $op1\t# overflow check int64_t" %}
ins_cost(INSN_COST);
ins_encode %{
__ cmp(zr, $op1$$Register);
%}
*** 14052,14062 ****
instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowMulL op1 op2));
! format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"movw rscratch1, #0x80000000\n\t"
"cselw rscratch1, rscratch1, zr, NE\n\t"
"cmpw rscratch1, #1" %}
--- 14072,14082 ----
instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
%{
match(Set cr (OverflowMulL op1 op2));
! format %{ "mul rscratch1, $op1, $op2\t#overflow check int64_t\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"movw rscratch1, #0x80000000\n\t"
"cselw rscratch1, rscratch1, zr, NE\n\t"
"cmpw rscratch1, #1" %}
*** 14078,14088 ****
match(If cmp (OverflowMulL op1 op2));
predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
|| n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
effect(USE labl, KILL cr);
! format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"b$cmp $labl" %}
ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
ins_encode %{
--- 14098,14108 ----
match(If cmp (OverflowMulL op1 op2));
predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
|| n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
effect(USE labl, KILL cr);
! format %{ "mul rscratch1, $op1, $op2\t#overflow check int64_t\n\t"
"smulh rscratch2, $op1, $op2\n\t"
"cmp rscratch2, rscratch1, ASR #63\n\t"
"b$cmp $labl" %}
ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
ins_encode %{
*** 14842,14852 ****
instruct cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
match(If cmp (CmpL op1 op2));
effect(USE labl);
ins_cost(BRANCH_COST);
! format %{ "cb$cmp $op1, $labl # long" %}
ins_encode %{
Label* L = $labl$$label;
Assembler::Condition cond =
((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
__ tbr(cond, $op1$$Register, 63, *L);
--- 14862,14872 ----
instruct cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
match(If cmp (CmpL op1 op2));
effect(USE labl);
ins_cost(BRANCH_COST);
! format %{ "cb$cmp $op1, $labl # int64_t" %}
ins_encode %{
Label* L = $labl$$label;
Assembler::Condition cond =
((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
__ tbr(cond, $op1$$Register, 63, *L);
*** 14909,14919 ****
instruct far_cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
match(If cmp (CmpL op1 op2));
effect(USE labl);
ins_cost(BRANCH_COST);
! format %{ "cb$cmp $op1, $labl # long" %}
ins_encode %{
Label* L = $labl$$label;
Assembler::Condition cond =
((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
__ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
--- 14929,14939 ----
instruct far_cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
match(If cmp (CmpL op1 op2));
effect(USE labl);
ins_cost(BRANCH_COST);
! format %{ "cb$cmp $op1, $labl # int64_t" %}
ins_encode %{
Label* L = $labl$$label;
Assembler::Condition cond =
((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
__ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
*** 14974,14984 ****
match(Set cr (CmpL (AndL op1 op2) op3));
predicate(Assembler::operand_valid_for_logical_immediate
(/*is_32*/false, n->in(1)->in(2)->get_long()));
ins_cost(INSN_COST);
! format %{ "tst $op1, $op2 # long" %}
ins_encode %{
__ tst($op1$$Register, $op2$$constant);
%}
ins_pipe(ialu_reg_reg);
%}
--- 14994,15004 ----
match(Set cr (CmpL (AndL op1 op2) op3));
predicate(Assembler::operand_valid_for_logical_immediate
(/*is_32*/false, n->in(1)->in(2)->get_long()));
ins_cost(INSN_COST);
! format %{ "tst $op1, $op2 # int64_t" %}
ins_encode %{
__ tst($op1$$Register, $op2$$constant);
%}
ins_pipe(ialu_reg_reg);
%}
*** 14998,15008 ****
instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
match(Set cr (CmpL (AndL op1 op2) op3));
ins_cost(INSN_COST);
! format %{ "tst $op1, $op2 # long" %}
ins_encode %{
__ tst($op1$$Register, $op2$$Register);
%}
ins_pipe(ialu_reg_reg);
%}
--- 15018,15028 ----
instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
match(Set cr (CmpL (AndL op1 op2) op3));
ins_cost(INSN_COST);
! format %{ "tst $op1, $op2 # int64_t" %}
ins_encode %{
__ tst($op1$$Register, $op2$$Register);
%}
ins_pipe(ialu_reg_reg);
%}
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