1 /*
   2  * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
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  24  */
  25 
  26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 // definitions of various symbolic names for machine registers
  32 
  33 // First intercalls between C and Java which use 8 general registers
  34 // and 8 floating registers
  35 
  36 // we also have to copy between x86 and ARM registers but that's a
  37 // secondary complication -- not all code employing C call convention
  38 // executes as x86 code though -- we generate some of it
  39 
  40 class Argument {
  41  public:
  42   enum {
  43     n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
  44     n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )
  45 
  46     n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
  47     n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...
  48   };
  49 };
  50 
  51 REGISTER_DECLARATION(Register, c_rarg0, r0);
  52 REGISTER_DECLARATION(Register, c_rarg1, r1);
  53 REGISTER_DECLARATION(Register, c_rarg2, r2);
  54 REGISTER_DECLARATION(Register, c_rarg3, r3);
  55 REGISTER_DECLARATION(Register, c_rarg4, r4);
  56 REGISTER_DECLARATION(Register, c_rarg5, r5);
  57 REGISTER_DECLARATION(Register, c_rarg6, r6);
  58 REGISTER_DECLARATION(Register, c_rarg7, r7);
  59 
  60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
  61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
  62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
  63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
  64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
  65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
  66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
  67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
  68 
  69 // Symbolically name the register arguments used by the Java calling convention.
  70 // We have control over the convention for java so we can do what we please.
  71 // What pleases us is to offset the java calling convention so that when
  72 // we call a suitable jni method the arguments are lined up and we don't
  73 // have to do much shuffling. A suitable jni method is non-static and a
  74 // small number of arguments
  75 //
  76 //  |--------------------------------------------------------------------|
  77 //  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |
  78 //  |--------------------------------------------------------------------|
  79 //  | r0       r1       r2      r3      r4      r5      r6      r7       |
  80 //  |--------------------------------------------------------------------|
  81 //  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |
  82 //  |--------------------------------------------------------------------|
  83 
  84 
  85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
  86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
  87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
  88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
  89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
  90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
  91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
  92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
  93 
  94 // Java floating args are passed as per C
  95 
  96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
  97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
  98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
  99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
 104 
 105 // registers used to hold VM data either temporarily within a method
 106 // or across method calls
 107 
 108 // volatile (caller-save) registers
 109 
 110 // r8 is used for indirect result location return
 111 // we use it and r9 as scratch registers
 112 REGISTER_DECLARATION(Register, rscratch1, r8);
 113 REGISTER_DECLARATION(Register, rscratch2, r9);
 114 
 115 // current method -- must be in a call-clobbered register
 116 REGISTER_DECLARATION(Register, rmethod,   r12);
 117 
 118 // non-volatile (callee-save) registers are r16-29
 119 // of which the following are dedicated global state
 120 
 121 // link register
 122 REGISTER_DECLARATION(Register, lr,        r30);
 123 // frame pointer
 124 REGISTER_DECLARATION(Register, rfp,       r29);
 125 // current thread
 126 REGISTER_DECLARATION(Register, rthread,   r28);
 127 // base of heap
 128 REGISTER_DECLARATION(Register, rheapbase, r27);
 129 // constant pool cache
 130 REGISTER_DECLARATION(Register, rcpool,    r26);
 131 // monitors allocated on stack
 132 REGISTER_DECLARATION(Register, rmonitors, r25);
 133 // locals on stack
 134 REGISTER_DECLARATION(Register, rlocals,   r24);
 135 // bytecode pointer
 136 REGISTER_DECLARATION(Register, rbcp,      r22);
 137 // Dispatch table base
 138 REGISTER_DECLARATION(Register, rdispatch, r21);
 139 // Java stack pointer
 140 REGISTER_DECLARATION(Register, esp,      r20);
 141 
 142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
 143 
 144 namespace asm_util {
 145   uint32_t encode_logical_immediate(bool is32, uint64_t imm);
 146 };
 147 
 148 using namespace asm_util;
 149 
 150 
 151 class Assembler;
 152 
 153 class Instruction_aarch64 {
 154   unsigned insn;
 155 #ifdef ASSERT
 156   unsigned bits;
 157 #endif
 158   Assembler *assem;
 159 
 160 public:
 161 
 162   Instruction_aarch64(class Assembler *as) {
 163 #ifdef ASSERT
 164     bits = 0;
 165 #endif
 166     insn = 0;
 167     assem = as;
 168   }
 169 
 170   inline ~Instruction_aarch64();
 171 
 172   unsigned &get_insn() { return insn; }
 173 #ifdef ASSERT
 174   unsigned &get_bits() { return bits; }
 175 #endif
 176 
 177   static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
 178     union {
 179       unsigned u;
 180       int n;
 181     };
 182 
 183     u = val << (31 - hi);
 184     n = n >> (31 - hi + lo);
 185     return n;
 186   }
 187 
 188   static inline uint32_t extract(uint32_t val, int msb, int lsb) {
 189     int nbits = msb - lsb + 1;
 190     assert_cond(msb >= lsb);
 191     uint32_t mask = (1U << nbits) - 1;
 192     uint32_t result = val >> lsb;
 193     result &= mask;
 194     return result;
 195   }
 196 
 197   static inline int32_t sextract(uint32_t val, int msb, int lsb) {
 198     uint32_t uval = extract(val, msb, lsb);
 199     return extend(uval, msb - lsb);
 200   }
 201 
 202   static void patch(address a, int msb, int lsb, uint64_t val) {
 203     int nbits = msb - lsb + 1;
 204     guarantee(val < (1U << nbits), "Field too big for insn");
 205     assert_cond(msb >= lsb);
 206     unsigned mask = (1U << nbits) - 1;
 207     val <<= lsb;
 208     mask <<= lsb;
 209     unsigned target = *(unsigned *)a;
 210     target &= ~mask;
 211     target |= val;
 212     *(unsigned *)a = target;
 213   }
 214 
 215   static void spatch(address a, int msb, int lsb, int64_t val) {
 216     int nbits = msb - lsb + 1;
 217     int64_t chk = val >> (nbits - 1);
 218     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 219     unsigned uval = val;
 220     unsigned mask = (1U << nbits) - 1;
 221     uval &= mask;
 222     uval <<= lsb;
 223     mask <<= lsb;
 224     unsigned target = *(unsigned *)a;
 225     target &= ~mask;
 226     target |= uval;
 227     *(unsigned *)a = target;
 228   }
 229 
 230   void f(unsigned val, int msb, int lsb) {
 231     int nbits = msb - lsb + 1;
 232     guarantee(val < (1U << nbits), "Field too big for insn");
 233     assert_cond(msb >= lsb);
 234     unsigned mask = (1U << nbits) - 1;
 235     val <<= lsb;
 236     mask <<= lsb;
 237     insn |= val;
 238     assert_cond((bits & mask) == 0);
 239 #ifdef ASSERT
 240     bits |= mask;
 241 #endif
 242   }
 243 
 244   void f(unsigned val, int bit) {
 245     f(val, bit, bit);
 246   }
 247 
 248   void sf(int64_t val, int msb, int lsb) {
 249     int nbits = msb - lsb + 1;
 250     int64_t chk = val >> (nbits - 1);
 251     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 252     unsigned uval = val;
 253     unsigned mask = (1U << nbits) - 1;
 254     uval &= mask;
 255     f(uval, lsb + nbits - 1, lsb);
 256   }
 257 
 258   void rf(Register r, int lsb) {
 259     f(r->encoding_nocheck(), lsb + 4, lsb);
 260   }
 261 
 262   // reg|ZR
 263   void zrf(Register r, int lsb) {
 264     f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
 265   }
 266 
 267   // reg|SP
 268   void srf(Register r, int lsb) {
 269     f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
 270   }
 271 
 272   void rf(FloatRegister r, int lsb) {
 273     f(r->encoding_nocheck(), lsb + 4, lsb);
 274   }
 275 
 276   unsigned get(int msb = 31, int lsb = 0) {
 277     int nbits = msb - lsb + 1;
 278     unsigned mask = ((1U << nbits) - 1) << lsb;
 279     assert_cond((bits & mask) == mask);
 280     return (insn & mask) >> lsb;
 281   }
 282 
 283   void fixed(unsigned value, unsigned mask) {
 284     assert_cond ((mask & bits) == 0);
 285 #ifdef ASSERT
 286     bits |= mask;
 287 #endif
 288     insn |= value;
 289   }
 290 };
 291 
 292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
 293 
 294 class PrePost {
 295   int _offset;
 296   Register _r;
 297 public:
 298   PrePost(Register reg, int o) : _offset(o), _r(reg) { }
 299   int offset() { return _offset; }
 300   Register reg() { return _r; }
 301 };
 302 
 303 class Pre : public PrePost {
 304 public:
 305   Pre(Register reg, int o) : PrePost(reg, o) { }
 306 };
 307 class Post : public PrePost {
 308   Register _idx;
 309   bool _is_postreg;
 310 public:
 311   Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
 312   Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
 313   Register idx_reg() { return _idx; }
 314   bool is_postreg() {return _is_postreg; }
 315 };
 316 
 317 namespace ext
 318 {
 319   enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
 320 };
 321 
 322 // Addressing modes
 323 class Address {
 324  public:
 325 
 326   enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
 327               base_plus_offset_reg, literal };
 328 
 329   // Shift and extend for base reg + reg offset addressing
 330   class extend {
 331     int _option, _shift;
 332     ext::operation _op;
 333   public:
 334     extend() { }
 335     extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
 336     int option() const{ return _option; }
 337     int shift() const { return _shift; }
 338     ext::operation op() const { return _op; }
 339   };
 340   class uxtw : public extend {
 341   public:
 342     uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
 343   };
 344   class lsl : public extend {
 345   public:
 346     lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
 347   };
 348   class sxtw : public extend {
 349   public:
 350     sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
 351   };
 352   class sxtx : public extend {
 353   public:
 354     sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
 355   };
 356 
 357  private:
 358   Register _base;
 359   Register _index;
 360   int64_t _offset;
 361   enum mode _mode;
 362   extend _ext;
 363 
 364   RelocationHolder _rspec;
 365 
 366   // Typically we use AddressLiterals we want to use their rval
 367   // However in some situations we want the lval (effect address) of
 368   // the item.  We provide a special factory for making those lvals.
 369   bool _is_lval;
 370 
 371   // If the target is far we'll need to load the ea of this to a
 372   // register to reach it. Otherwise if near we can do PC-relative
 373   // addressing.
 374   address          _target;
 375 
 376  public:
 377   Address()
 378     : _mode(no_mode) { }
 379   Address(Register r)
 380     : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
 381   Address(Register r, int o)
 382     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 383   Address(Register r, int64_t o)
 384     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 385   Address(Register r, uint64_t o)
 386     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 387 #ifdef ASSERT
 388   Address(Register r, ByteSize disp)
 389     : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
 390 #endif
 391   Address(Register r, Register r1, extend ext = lsl())
 392     : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
 393       _ext(ext), _target(0) { }
 394   Address(Pre p)
 395     : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
 396   Address(Post p)
 397     : _base(p.reg()),  _index(p.idx_reg()), _offset(p.offset()),
 398       _mode(p.is_postreg() ? post_reg : post), _target(0) { }
 399   Address(address target, RelocationHolder const& rspec)
 400     : _mode(literal),
 401       _rspec(rspec),
 402       _is_lval(false),
 403       _target(target)  { }
 404   Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
 405   Address(Register base, RegisterOrConstant index, extend ext = lsl())
 406     : _base (base),
 407       _offset(0), _ext(ext), _target(0) {
 408     if (index.is_register()) {
 409       _mode = base_plus_offset_reg;
 410       _index = index.as_register();
 411     } else {
 412       guarantee(ext.option() == ext::uxtx, "should be");
 413       assert(index.is_constant(), "should be");
 414       _mode = base_plus_offset;
 415       _offset = index.as_constant() << ext.shift();
 416     }
 417   }
 418 
 419   Register base() const {
 420     guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
 421                | _mode == post | _mode == post_reg),
 422               "wrong mode");
 423     return _base;
 424   }
 425   int64_t offset() const {
 426     return _offset;
 427   }
 428   Register index() const {
 429     return _index;
 430   }
 431   mode getMode() const {
 432     return _mode;
 433   }
 434   bool uses(Register reg) const { return _base == reg || _index == reg; }
 435   address target() const { return _target; }
 436   const RelocationHolder& rspec() const { return _rspec; }
 437 
 438   void encode(Instruction_aarch64 *i) const {
 439     i->f(0b111, 29, 27);
 440     i->srf(_base, 5);
 441 
 442     switch(_mode) {
 443     case base_plus_offset:
 444       {
 445         unsigned size = i->get(31, 30);
 446         if (i->get(26, 26) && i->get(23, 23)) {
 447           // SIMD Q Type - Size = 128 bits
 448           assert(size == 0, "bad size");
 449           size = 0b100;
 450         }
 451         unsigned mask = (1 << size) - 1;
 452         if (_offset < 0 || _offset & mask)
 453           {
 454             i->f(0b00, 25, 24);
 455             i->f(0, 21), i->f(0b00, 11, 10);
 456             i->sf(_offset, 20, 12);
 457           } else {
 458             i->f(0b01, 25, 24);
 459             i->f(_offset >> size, 21, 10);
 460           }
 461       }
 462       break;
 463 
 464     case base_plus_offset_reg:
 465       {
 466         i->f(0b00, 25, 24);
 467         i->f(1, 21);
 468         i->rf(_index, 16);
 469         i->f(_ext.option(), 15, 13);
 470         unsigned size = i->get(31, 30);
 471         if (i->get(26, 26) && i->get(23, 23)) {
 472           // SIMD Q Type - Size = 128 bits
 473           assert(size == 0, "bad size");
 474           size = 0b100;
 475         }
 476         if (size == 0) // It's a byte
 477           i->f(_ext.shift() >= 0, 12);
 478         else {
 479           if (_ext.shift() > 0)
 480             assert(_ext.shift() == (int)size, "bad shift");
 481           i->f(_ext.shift() > 0, 12);
 482         }
 483         i->f(0b10, 11, 10);
 484       }
 485       break;
 486 
 487     case pre:
 488       i->f(0b00, 25, 24);
 489       i->f(0, 21), i->f(0b11, 11, 10);
 490       i->sf(_offset, 20, 12);
 491       break;
 492 
 493     case post:
 494       i->f(0b00, 25, 24);
 495       i->f(0, 21), i->f(0b01, 11, 10);
 496       i->sf(_offset, 20, 12);
 497       break;
 498 
 499     default:
 500       ShouldNotReachHere();
 501     }
 502   }
 503 
 504   void encode_pair(Instruction_aarch64 *i) const {
 505     switch(_mode) {
 506     case base_plus_offset:
 507       i->f(0b010, 25, 23);
 508       break;
 509     case pre:
 510       i->f(0b011, 25, 23);
 511       break;
 512     case post:
 513       i->f(0b001, 25, 23);
 514       break;
 515     default:
 516       ShouldNotReachHere();
 517     }
 518 
 519     unsigned size; // Operand shift in 32-bit words
 520 
 521     if (i->get(26, 26)) { // float
 522       switch(i->get(31, 30)) {
 523       case 0b10:
 524         size = 2; break;
 525       case 0b01:
 526         size = 1; break;
 527       case 0b00:
 528         size = 0; break;
 529       default:
 530         ShouldNotReachHere();
 531         size = 0;  // unreachable
 532       }
 533     } else {
 534       size = i->get(31, 31);
 535     }
 536 
 537     size = 4 << size;
 538     guarantee(_offset % size == 0, "bad offset");
 539     i->sf(_offset / size, 21, 15);
 540     i->srf(_base, 5);
 541   }
 542 
 543   void encode_nontemporal_pair(Instruction_aarch64 *i) const {
 544     // Only base + offset is allowed
 545     i->f(0b000, 25, 23);
 546     unsigned size = i->get(31, 31);
 547     size = 4 << size;
 548     guarantee(_offset % size == 0, "bad offset");
 549     i->sf(_offset / size, 21, 15);
 550     i->srf(_base, 5);
 551     guarantee(_mode == Address::base_plus_offset,
 552               "Bad addressing mode for non-temporal op");
 553   }
 554 
 555   void lea(MacroAssembler *, Register) const;
 556 
 557   static bool offset_ok_for_immed(int64_t offset, int shift) {
 558     unsigned mask = (1 << shift) - 1;
 559     if (offset < 0 || offset & mask) {
 560       return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
 561     } else {
 562       return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
 563     }
 564   }
 565 };
 566 
 567 // Convience classes
 568 class RuntimeAddress: public Address {
 569 
 570   public:
 571 
 572   RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
 573 
 574 };
 575 
 576 class OopAddress: public Address {
 577 
 578   public:
 579 
 580   OopAddress(address target) : Address(target, relocInfo::oop_type){}
 581 
 582 };
 583 
 584 class ExternalAddress: public Address {
 585  private:
 586   static relocInfo::relocType reloc_for_target(address target) {
 587     // Sometimes ExternalAddress is used for values which aren't
 588     // exactly addresses, like the card table base.
 589     // external_word_type can't be used for values in the first page
 590     // so just skip the reloc in that case.
 591     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 592   }
 593 
 594  public:
 595 
 596   ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
 597 
 598 };
 599 
 600 class InternalAddress: public Address {
 601 
 602   public:
 603 
 604   InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
 605 };
 606 
 607 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
 608                                 FloatRegisterImpl::save_slots_per_register;
 609 
 610 typedef enum {
 611   PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
 612   PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
 613   PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
 614 } prfop;
 615 
 616 class Assembler : public AbstractAssembler {
 617 
 618 #ifndef PRODUCT
 619   static const uint64_t asm_bp;
 620 
 621   void emit_long(jint x) {
 622     if ((uint64_t)pc() == asm_bp) {
 623 #ifdef _WIN64
 624       // MSVC built-in: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
 625       __nop();
 626 #else
 627       asm volatile ("nop");
 628 #endif
 629     }
 630     AbstractAssembler::emit_int32(x);
 631   }
 632 #else
 633   void emit_long(jint x) {
 634     AbstractAssembler::emit_int32(x);
 635   }
 636 #endif
 637 
 638 public:
 639 
 640   enum { instruction_size = 4 };
 641 
 642   //---<  calculate length of instruction  >---
 643   // We just use the values set above.
 644   // instruction must start at passed address
 645   static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
 646 
 647   //---<  longest instructions  >---
 648   static unsigned int instr_maxlen() { return instruction_size; }
 649 
 650   Address adjust(Register base, int offset, bool preIncrement) {
 651     if (preIncrement)
 652       return Address(Pre(base, offset));
 653     else
 654       return Address(Post(base, offset));
 655   }
 656 
 657   Address pre(Register base, int offset) {
 658     return adjust(base, offset, true);
 659   }
 660 
 661   Address post(Register base, int offset) {
 662     return adjust(base, offset, false);
 663   }
 664 
 665   Address post(Register base, Register idx) {
 666     return Address(Post(base, idx));
 667   }
 668 
 669   static address locate_next_instruction(address inst);
 670 
 671   Instruction_aarch64* current;
 672 
 673   void set_current(Instruction_aarch64* i) { current = i; }
 674 
 675   void f(unsigned val, int msb, int lsb) {
 676     current->f(val, msb, lsb);
 677   }
 678   void f(unsigned val, int msb) {
 679     current->f(val, msb, msb);
 680   }
 681   void sf(int64_t val, int msb, int lsb) {
 682     current->sf(val, msb, lsb);
 683   }
 684   void rf(Register reg, int lsb) {
 685     current->rf(reg, lsb);
 686   }
 687   void srf(Register reg, int lsb) {
 688     current->srf(reg, lsb);
 689   }
 690   void zrf(Register reg, int lsb) {
 691     current->zrf(reg, lsb);
 692   }
 693   void rf(FloatRegister reg, int lsb) {
 694     current->rf(reg, lsb);
 695   }
 696   void fixed(unsigned value, unsigned mask) {
 697     current->fixed(value, mask);
 698   }
 699 
 700   void emit() {
 701     emit_long(current->get_insn());
 702     assert_cond(current->get_bits() == 0xffffffff);
 703     current = NULL;
 704   }
 705 
 706   typedef void (Assembler::* uncond_branch_insn)(address dest);
 707   typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
 708   typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
 709   typedef void (Assembler::* prefetch_insn)(address target, prfop);
 710 
 711   void wrap_label(Label &L, uncond_branch_insn insn);
 712   void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
 713   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 714   void wrap_label(Label &L, prfop, prefetch_insn insn);
 715 
 716   // PC-rel. addressing
 717 
 718   void adr(Register Rd, address dest);
 719   void _adrp(Register Rd, address dest);
 720 
 721   void adr(Register Rd, const Address &dest);
 722   void _adrp(Register Rd, const Address &dest);
 723 
 724   void adr(Register Rd, Label &L) {
 725     wrap_label(Rd, L, &Assembler::Assembler::adr);
 726   }
 727   void _adrp(Register Rd, Label &L) {
 728     wrap_label(Rd, L, &Assembler::_adrp);
 729   }
 730 
 731   void adrp(Register Rd, const Address &dest, uint64_t &offset);
 732 
 733 #undef INSN
 734 
 735   void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
 736                          int negated_op);
 737 
 738   // Add/subtract (immediate)
 739 #define INSN(NAME, decode, negated)                                     \
 740   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 741     starti;                                                             \
 742     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 743     zrf(Rd, 0), srf(Rn, 5);                                             \
 744   }                                                                     \
 745                                                                         \
 746   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 747     starti;                                                             \
 748     add_sub_immediate(Rd, Rn, imm, decode, negated);                    \
 749   }
 750 
 751   INSN(addsw, 0b001, 0b011);
 752   INSN(subsw, 0b011, 0b001);
 753   INSN(adds,  0b101, 0b111);
 754   INSN(subs,  0b111, 0b101);
 755 
 756 #undef INSN
 757 
 758 #define INSN(NAME, decode, negated)                     \
 759   void NAME(Register Rd, Register Rn, unsigned imm) {   \
 760     starti;                                             \
 761     add_sub_immediate(Rd, Rn, imm, decode, negated);    \
 762   }
 763 
 764   INSN(addw, 0b000, 0b010);
 765   INSN(subw, 0b010, 0b000);
 766   INSN(add,  0b100, 0b110);
 767   INSN(sub,  0b110, 0b100);
 768 
 769 #undef INSN
 770 
 771  // Logical (immediate)
 772 #define INSN(NAME, decode, is32)                                \
 773   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 774     starti;                                                     \
 775     uint32_t val = encode_logical_immediate(is32, imm);         \
 776     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 777     srf(Rd, 0), zrf(Rn, 5);                                     \
 778   }
 779 
 780   INSN(andw, 0b000, true);
 781   INSN(orrw, 0b001, true);
 782   INSN(eorw, 0b010, true);
 783   INSN(andr,  0b100, false);
 784   INSN(orr,  0b101, false);
 785   INSN(eor,  0b110, false);
 786 
 787 #undef INSN
 788 
 789 #define INSN(NAME, decode, is32)                                \
 790   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 791     starti;                                                     \
 792     uint32_t val = encode_logical_immediate(is32, imm);         \
 793     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 794     zrf(Rd, 0), zrf(Rn, 5);                                     \
 795   }
 796 
 797   INSN(ands, 0b111, false);
 798   INSN(andsw, 0b011, true);
 799 
 800 #undef INSN
 801 
 802   // Move wide (immediate)
 803 #define INSN(NAME, opcode)                                              \
 804   void NAME(Register Rd, unsigned imm, unsigned shift = 0) {            \
 805     assert_cond((shift/16)*16 == shift);                                \
 806     starti;                                                             \
 807     f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
 808       f(imm, 20, 5);                                                    \
 809     rf(Rd, 0);                                                          \
 810   }
 811 
 812   INSN(movnw, 0b000);
 813   INSN(movzw, 0b010);
 814   INSN(movkw, 0b011);
 815   INSN(movn, 0b100);
 816   INSN(movz, 0b110);
 817   INSN(movk, 0b111);
 818 
 819 #undef INSN
 820 
 821   // Bitfield
 822 #define INSN(NAME, opcode, size)                                        \
 823   void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
 824     starti;                                                             \
 825     guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
 826     f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
 827     zrf(Rn, 5), rf(Rd, 0);                                              \
 828   }
 829 
 830   INSN(sbfmw, 0b0001001100, 0);
 831   INSN(bfmw,  0b0011001100, 0);
 832   INSN(ubfmw, 0b0101001100, 0);
 833   INSN(sbfm,  0b1001001101, 1);
 834   INSN(bfm,   0b1011001101, 1);
 835   INSN(ubfm,  0b1101001101, 1);
 836 
 837 #undef INSN
 838 
 839   // Extract
 840 #define INSN(NAME, opcode, size)                                        \
 841   void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) {     \
 842     starti;                                                             \
 843     guarantee(size == 1 || imms < 32, "incorrect imms");                \
 844     f(opcode, 31, 21), f(imms, 15, 10);                                 \
 845     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
 846   }
 847 
 848   INSN(extrw, 0b00010011100, 0);
 849   INSN(extr,  0b10010011110, 1);
 850 
 851 #undef INSN
 852 
 853   // The maximum range of a branch is fixed for the AArch64
 854   // architecture.  In debug mode we shrink it in order to test
 855   // trampolines, but not so small that branches in the interpreter
 856   // are out of range.
 857   static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
 858 
 859   static bool reachable_from_branch_at(address branch, address target) {
 860     return uabs(target - branch) < branch_range;
 861   }
 862 
 863   // Unconditional branch (immediate)
 864 #define INSN(NAME, opcode)                                              \
 865   void NAME(address dest) {                                             \
 866     starti;                                                             \
 867     int64_t offset = (dest - pc()) >> 2;                                   \
 868     DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
 869     f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0);               \
 870   }                                                                     \
 871   void NAME(Label &L) {                                                 \
 872     wrap_label(L, &Assembler::NAME);                                    \
 873   }                                                                     \
 874   void NAME(const Address &dest);
 875 
 876   INSN(b, 0);
 877   INSN(bl, 1);
 878 
 879 #undef INSN
 880 
 881   // Compare & branch (immediate)
 882 #define INSN(NAME, opcode)                              \
 883   void NAME(Register Rt, address dest) {                \
 884     int64_t offset = (dest - pc()) >> 2;                   \
 885     starti;                                             \
 886     f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0);    \
 887   }                                                     \
 888   void NAME(Register Rt, Label &L) {                    \
 889     wrap_label(Rt, L, &Assembler::NAME);                \
 890   }
 891 
 892   INSN(cbzw,  0b00110100);
 893   INSN(cbnzw, 0b00110101);
 894   INSN(cbz,   0b10110100);
 895   INSN(cbnz,  0b10110101);
 896 
 897 #undef INSN
 898 
 899   // Test & branch (immediate)
 900 #define INSN(NAME, opcode)                                              \
 901   void NAME(Register Rt, int bitpos, address dest) {                    \
 902     int64_t offset = (dest - pc()) >> 2;                                   \
 903     int b5 = bitpos >> 5;                                               \
 904     bitpos &= 0x1f;                                                     \
 905     starti;                                                             \
 906     f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
 907     rf(Rt, 0);                                                          \
 908   }                                                                     \
 909   void NAME(Register Rt, int bitpos, Label &L) {                        \
 910     wrap_label(Rt, bitpos, L, &Assembler::NAME);                        \
 911   }
 912 
 913   INSN(tbz,  0b0110110);
 914   INSN(tbnz, 0b0110111);
 915 
 916 #undef INSN
 917 
 918   // Conditional branch (immediate)
 919   enum Condition
 920     {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
 921 
 922   void br(Condition  cond, address dest) {
 923     int64_t offset = (dest - pc()) >> 2;
 924     starti;
 925     f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
 926   }
 927 
 928 #define INSN(NAME, cond)                        \
 929   void NAME(address dest) {                     \
 930     br(cond, dest);                             \
 931   }
 932 
 933   INSN(beq, EQ);
 934   INSN(bne, NE);
 935   INSN(bhs, HS);
 936   INSN(bcs, CS);
 937   INSN(blo, LO);
 938   INSN(bcc, CC);
 939   INSN(bmi, MI);
 940   INSN(bpl, PL);
 941   INSN(bvs, VS);
 942   INSN(bvc, VC);
 943   INSN(bhi, HI);
 944   INSN(bls, LS);
 945   INSN(bge, GE);
 946   INSN(blt, LT);
 947   INSN(bgt, GT);
 948   INSN(ble, LE);
 949   INSN(bal, AL);
 950   INSN(bnv, NV);
 951 
 952   void br(Condition cc, Label &L);
 953 
 954 #undef INSN
 955 
 956   // Exception generation
 957   void generate_exception(int opc, int op2, int LL, unsigned imm) {
 958     starti;
 959     f(0b11010100, 31, 24);
 960     f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
 961   }
 962 
 963 #define INSN(NAME, opc, op2, LL)                \
 964   void NAME(unsigned imm) {                     \
 965     generate_exception(opc, op2, LL, imm);      \
 966   }
 967 
 968   INSN(svc, 0b000, 0, 0b01);
 969   INSN(hvc, 0b000, 0, 0b10);
 970   INSN(smc, 0b000, 0, 0b11);
 971   INSN(brk, 0b001, 0, 0b00);
 972   INSN(hlt, 0b010, 0, 0b00);
 973   INSN(dcps1, 0b101, 0, 0b01);
 974   INSN(dcps2, 0b101, 0, 0b10);
 975   INSN(dcps3, 0b101, 0, 0b11);
 976 
 977 #undef INSN
 978 
 979   // System
 980   void system(int op0, int op1, int CRn, int CRm, int op2,
 981               Register rt = dummy_reg)
 982   {
 983     starti;
 984     f(0b11010101000, 31, 21);
 985     f(op0, 20, 19);
 986     f(op1, 18, 16);
 987     f(CRn, 15, 12);
 988     f(CRm, 11, 8);
 989     f(op2, 7, 5);
 990     rf(rt, 0);
 991   }
 992 
 993   void hint(int imm) {
 994     system(0b00, 0b011, 0b0010, 0b0000, imm);
 995   }
 996 
 997   void nop() {
 998     hint(0);
 999   }
1000 
1001   void yield() {
1002     hint(1);
1003   }
1004 
1005   void wfe() {
1006     hint(2);
1007   }
1008 
1009   void wfi() {
1010     hint(3);
1011   }
1012 
1013   void sev() {
1014     hint(4);
1015   }
1016 
1017   void sevl() {
1018     hint(5);
1019   }
1020 
1021   // we only provide mrs and msr for the special purpose system
1022   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1023   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1024 
1025   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1026     starti;
1027     f(0b1101010100011, 31, 19);
1028     f(op1, 18, 16);
1029     f(CRn, 15, 12);
1030     f(CRm, 11, 8);
1031     f(op2, 7, 5);
1032     // writing zr is ok
1033     zrf(rt, 0);
1034   }
1035 
1036   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1037     starti;
1038     f(0b1101010100111, 31, 19);
1039     f(op1, 18, 16);
1040     f(CRn, 15, 12);
1041     f(CRm, 11, 8);
1042     f(op2, 7, 5);
1043     // reading to zr is a mistake
1044     rf(rt, 0);
1045   }
1046 
1047   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1048                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1049 
1050   void dsb(barrier imm) {
1051     system(0b00, 0b011, 0b00011, imm, 0b100);
1052   }
1053 
1054   void dmb(barrier imm) {
1055     system(0b00, 0b011, 0b00011, imm, 0b101);
1056   }
1057 
1058   void isb() {
1059     system(0b00, 0b011, 0b00011, SY, 0b110);
1060   }
1061 
1062   void sys(int op1, int CRn, int CRm, int op2,
1063            Register rt = (Register)0b11111) {
1064     system(0b01, op1, CRn, CRm, op2, rt);
1065   }
1066 
1067   // Only implement operations accessible from EL0 or higher, i.e.,
1068   //            op1    CRn    CRm    op2
1069   // IC IVAU     3      7      5      1
1070   // DC CVAC     3      7      10     1
1071   // DC CVAP     3      7      12     1
1072   // DC CVAU     3      7      11     1
1073   // DC CIVAC    3      7      14     1
1074   // DC ZVA      3      7      4      1
1075   // So only deal with the CRm field.
1076   enum icache_maintenance {IVAU = 0b0101};
1077   enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1078 
1079   void dc(dcache_maintenance cm, Register Rt) {
1080     sys(0b011, 0b0111, cm, 0b001, Rt);
1081   }
1082 
1083   void ic(icache_maintenance cm, Register Rt) {
1084     sys(0b011, 0b0111, cm, 0b001, Rt);
1085   }
1086 
1087   // A more convenient access to dmb for our purposes
1088   enum Membar_mask_bits {
1089     // We can use ISH for a barrier because the ARM ARM says "This
1090     // architecture assumes that all Processing Elements that use the
1091     // same operating system or hypervisor are in the same Inner
1092     // Shareable shareability domain."
1093     StoreStore = ISHST,
1094     LoadStore  = ISHLD,
1095     LoadLoad   = ISHLD,
1096     StoreLoad  = ISH,
1097     AnyAny     = ISH
1098   };
1099 
1100   void membar(Membar_mask_bits order_constraint) {
1101     dmb(Assembler::barrier(order_constraint));
1102   }
1103 
1104   // Unconditional branch (register)
1105   void branch_reg(Register R, int opc) {
1106     starti;
1107     f(0b1101011, 31, 25);
1108     f(opc, 24, 21);
1109     f(0b11111000000, 20, 10);
1110     rf(R, 5);
1111     f(0b00000, 4, 0);
1112   }
1113 
1114 #define INSN(NAME, opc)                         \
1115   void NAME(Register R) {                       \
1116     branch_reg(R, opc);                         \
1117   }
1118 
1119   INSN(br, 0b0000);
1120   INSN(blr, 0b0001);
1121   INSN(ret, 0b0010);
1122 
1123   void ret(void *p); // This forces a compile-time error for ret(0)
1124 
1125 #undef INSN
1126 
1127 #define INSN(NAME, opc)                         \
1128   void NAME() {                 \
1129     branch_reg(dummy_reg, opc);         \
1130   }
1131 
1132   INSN(eret, 0b0100);
1133   INSN(drps, 0b0101);
1134 
1135 #undef INSN
1136 
1137   // Load/store exclusive
1138   enum operand_size { byte, halfword, word, xword };
1139 
1140   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1141     Register Rn, enum operand_size sz, int op, bool ordered) {
1142     starti;
1143     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1144     rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1145   }
1146 
1147   void load_exclusive(Register dst, Register addr,
1148                       enum operand_size sz, bool ordered) {
1149     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1150                          sz, 0b010, ordered);
1151   }
1152 
1153   void store_exclusive(Register status, Register new_val, Register addr,
1154                        enum operand_size sz, bool ordered) {
1155     load_store_exclusive(status, new_val, dummy_reg, addr,
1156                          sz, 0b000, ordered);
1157   }
1158 
1159 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1160   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1161     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1162     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1163   }
1164 
1165 #define INSN3(NAME, sz, op, o0) /* Three registers */                   \
1166   void NAME(Register Rs, Register Rt, Register Rn) {                    \
1167     guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction");       \
1168     load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1169   }
1170 
1171 #define INSN2(NAME, sz, op, o0) /* Two registers */                     \
1172   void NAME(Register Rt, Register Rn) {                                 \
1173     load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1174                          Rn, sz, op, o0);                               \
1175   }
1176 
1177 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1178   void NAME(Register Rt1, Register Rt2, Register Rn) {                  \
1179     guarantee(Rt1 != Rt2, "unpredictable instruction");                 \
1180     load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0);          \
1181   }
1182 
1183   // bytes
1184   INSN3(stxrb, byte, 0b000, 0);
1185   INSN3(stlxrb, byte, 0b000, 1);
1186   INSN2(ldxrb, byte, 0b010, 0);
1187   INSN2(ldaxrb, byte, 0b010, 1);
1188   INSN2(stlrb, byte, 0b100, 1);
1189   INSN2(ldarb, byte, 0b110, 1);
1190 
1191   // halfwords
1192   INSN3(stxrh, halfword, 0b000, 0);
1193   INSN3(stlxrh, halfword, 0b000, 1);
1194   INSN2(ldxrh, halfword, 0b010, 0);
1195   INSN2(ldaxrh, halfword, 0b010, 1);
1196   INSN2(stlrh, halfword, 0b100, 1);
1197   INSN2(ldarh, halfword, 0b110, 1);
1198 
1199   // words
1200   INSN3(stxrw, word, 0b000, 0);
1201   INSN3(stlxrw, word, 0b000, 1);
1202   INSN4(stxpw, word, 0b001, 0);
1203   INSN4(stlxpw, word, 0b001, 1);
1204   INSN2(ldxrw, word, 0b010, 0);
1205   INSN2(ldaxrw, word, 0b010, 1);
1206   INSN_FOO(ldxpw, word, 0b011, 0);
1207   INSN_FOO(ldaxpw, word, 0b011, 1);
1208   INSN2(stlrw, word, 0b100, 1);
1209   INSN2(ldarw, word, 0b110, 1);
1210 
1211   // xwords
1212   INSN3(stxr, xword, 0b000, 0);
1213   INSN3(stlxr, xword, 0b000, 1);
1214   INSN4(stxp, xword, 0b001, 0);
1215   INSN4(stlxp, xword, 0b001, 1);
1216   INSN2(ldxr, xword, 0b010, 0);
1217   INSN2(ldaxr, xword, 0b010, 1);
1218   INSN_FOO(ldxp, xword, 0b011, 0);
1219   INSN_FOO(ldaxp, xword, 0b011, 1);
1220   INSN2(stlr, xword, 0b100, 1);
1221   INSN2(ldar, xword, 0b110, 1);
1222 
1223 #undef INSN2
1224 #undef INSN3
1225 #undef INSN4
1226 #undef INSN_FOO
1227 
1228   // 8.1 Compare and swap extensions
1229   void lse_cas(Register Rs, Register Rt, Register Rn,
1230                         enum operand_size sz, bool a, bool r, bool not_pair) {
1231     starti;
1232     if (! not_pair) { // Pair
1233       assert(sz == word || sz == xword, "invalid size");
1234       /* The size bit is in bit 30, not 31 */
1235       sz = (operand_size)(sz == word ? 0b00:0b01);
1236     }
1237     f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1238     zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1239   }
1240 
1241   // CAS
1242 #define INSN(NAME, a, r)                                                \
1243   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1244     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1245     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1246   }
1247   INSN(cas,    false, false)
1248   INSN(casa,   true,  false)
1249   INSN(casl,   false, true)
1250   INSN(casal,  true,  true)
1251 #undef INSN
1252 
1253   // CASP
1254 #define INSN(NAME, a, r)                                                \
1255   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1256             Register Rt, Register Rt1, Register Rn) {                   \
1257     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1258            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \
1259            Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers");     \
1260     lse_cas(Rs, Rt, Rn, sz, a, r, false);                               \
1261   }
1262   INSN(casp,    false, false)
1263   INSN(caspa,   true,  false)
1264   INSN(caspl,   false, true)
1265   INSN(caspal,  true,  true)
1266 #undef INSN
1267 
1268   // 8.1 Atomic operations
1269   void lse_atomic(Register Rs, Register Rt, Register Rn,
1270                   enum operand_size sz, int op1, int op2, bool a, bool r) {
1271     starti;
1272     f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1273     zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1274   }
1275 
1276 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2)                   \
1277   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1278     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false);                 \
1279   }                                                                     \
1280   void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1281     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false);                  \
1282   }                                                                     \
1283   void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1284     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true);                  \
1285   }                                                                     \
1286   void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1287     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true);                   \
1288   }
1289   INSN(ldadd,  ldadda,  ldaddl,  ldaddal,  0, 0b000);
1290   INSN(ldbic,  ldbica,  ldbicl,  ldbical,  0, 0b001);
1291   INSN(ldeor,  ldeora,  ldeorl,  ldeoral,  0, 0b010);
1292   INSN(ldorr,  ldorra,  ldorrl,  ldorral,  0, 0b011);
1293   INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1294   INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1295   INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1296   INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1297   INSN(swp,    swpa,    swpl,    swpal,    1, 0b000);
1298 #undef INSN
1299 
1300   // Load register (literal)
1301 #define INSN(NAME, opc, V)                                              \
1302   void NAME(Register Rt, address dest) {                                \
1303     int64_t offset = (dest - pc()) >> 2;                                   \
1304     starti;                                                             \
1305     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1306       sf(offset, 23, 5);                                                \
1307     rf(Rt, 0);                                                          \
1308   }                                                                     \
1309   void NAME(Register Rt, address dest, relocInfo::relocType rtype) {    \
1310     InstructionMark im(this);                                           \
1311     guarantee(rtype == relocInfo::internal_word_type,                   \
1312               "only internal_word_type relocs make sense here");        \
1313     code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1314     NAME(Rt, dest);                                                     \
1315   }                                                                     \
1316   void NAME(Register Rt, Label &L) {                                    \
1317     wrap_label(Rt, L, &Assembler::NAME);                                \
1318   }
1319 
1320   INSN(ldrw, 0b00, 0);
1321   INSN(ldr, 0b01, 0);
1322   INSN(ldrsw, 0b10, 0);
1323 
1324 #undef INSN
1325 
1326 #define INSN(NAME, opc, V)                                              \
1327   void NAME(FloatRegister Rt, address dest) {                           \
1328     int64_t offset = (dest - pc()) >> 2;                                   \
1329     starti;                                                             \
1330     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1331       sf(offset, 23, 5);                                                \
1332     rf((Register)Rt, 0);                                                \
1333   }
1334 
1335   INSN(ldrs, 0b00, 1);
1336   INSN(ldrd, 0b01, 1);
1337   INSN(ldrq, 0b10, 1);
1338 
1339 #undef INSN
1340 
1341 #define INSN(NAME, opc, V)                                              \
1342   void NAME(address dest, prfop op = PLDL1KEEP) {                       \
1343     int64_t offset = (dest - pc()) >> 2;                                   \
1344     starti;                                                             \
1345     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1346       sf(offset, 23, 5);                                                \
1347     f(op, 4, 0);                                                        \
1348   }                                                                     \
1349   void NAME(Label &L, prfop op = PLDL1KEEP) {                           \
1350     wrap_label(L, op, &Assembler::NAME);                                \
1351   }
1352 
1353   INSN(prfm, 0b11, 0);
1354 
1355 #undef INSN
1356 
1357   // Load/store
1358   void ld_st1(int opc, int p1, int V, int L,
1359               Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1360     starti;
1361     f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1362     zrf(Rt2, 10), zrf(Rt1, 0);
1363     if (no_allocate) {
1364       adr.encode_nontemporal_pair(current);
1365     } else {
1366       adr.encode_pair(current);
1367     }
1368   }
1369 
1370   // Load/store register pair (offset)
1371 #define INSN(NAME, size, p1, V, L, no_allocate)         \
1372   void NAME(Register Rt1, Register Rt2, Address adr) {  \
1373     ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1374    }
1375 
1376   INSN(stpw, 0b00, 0b101, 0, 0, false);
1377   INSN(ldpw, 0b00, 0b101, 0, 1, false);
1378   INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1379   INSN(stp, 0b10, 0b101, 0, 0, false);
1380   INSN(ldp, 0b10, 0b101, 0, 1, false);
1381 
1382   // Load/store no-allocate pair (offset)
1383   INSN(stnpw, 0b00, 0b101, 0, 0, true);
1384   INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1385   INSN(stnp, 0b10, 0b101, 0, 0, true);
1386   INSN(ldnp, 0b10, 0b101, 0, 1, true);
1387 
1388 #undef INSN
1389 
1390 #define INSN(NAME, size, p1, V, L, no_allocate)                         \
1391   void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) {        \
1392     ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1393    }
1394 
1395   INSN(stps, 0b00, 0b101, 1, 0, false);
1396   INSN(ldps, 0b00, 0b101, 1, 1, false);
1397   INSN(stpd, 0b01, 0b101, 1, 0, false);
1398   INSN(ldpd, 0b01, 0b101, 1, 1, false);
1399   INSN(stpq, 0b10, 0b101, 1, 0, false);
1400   INSN(ldpq, 0b10, 0b101, 1, 1, false);
1401 
1402 #undef INSN
1403 
1404   // Load/store register (all modes)
1405   void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1406     starti;
1407 
1408     f(V, 26); // general reg?
1409     zrf(Rt, 0);
1410 
1411     // Encoding for literal loads is done here (rather than pushed
1412     // down into Address::encode) because the encoding of this
1413     // instruction is too different from all of the other forms to
1414     // make it worth sharing.
1415     if (adr.getMode() == Address::literal) {
1416       assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1417       assert(op == 0b01, "literal form can only be used with loads");
1418       f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1419       int64_t offset = (adr.target() - pc()) >> 2;
1420       sf(offset, 23, 5);
1421       code_section()->relocate(pc(), adr.rspec());
1422       return;
1423     }
1424 
1425     f(size, 31, 30);
1426     f(op, 23, 22); // str
1427     adr.encode(current);
1428   }
1429 
1430 #define INSN(NAME, size, op)                            \
1431   void NAME(Register Rt, const Address &adr) {          \
1432     ld_st2(Rt, adr, size, op);                          \
1433   }                                                     \
1434 
1435   INSN(str, 0b11, 0b00);
1436   INSN(strw, 0b10, 0b00);
1437   INSN(strb, 0b00, 0b00);
1438   INSN(strh, 0b01, 0b00);
1439 
1440   INSN(ldr, 0b11, 0b01);
1441   INSN(ldrw, 0b10, 0b01);
1442   INSN(ldrb, 0b00, 0b01);
1443   INSN(ldrh, 0b01, 0b01);
1444 
1445   INSN(ldrsb, 0b00, 0b10);
1446   INSN(ldrsbw, 0b00, 0b11);
1447   INSN(ldrsh, 0b01, 0b10);
1448   INSN(ldrshw, 0b01, 0b11);
1449   INSN(ldrsw, 0b10, 0b10);
1450 
1451 #undef INSN
1452 
1453 #define INSN(NAME, size, op)                                    \
1454   void NAME(const Address &adr, prfop pfop = PLDL1KEEP) {       \
1455     ld_st2((Register)pfop, adr, size, op);                      \
1456   }
1457 
1458   INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1459                           // writeback modes, but the assembler
1460                           // doesn't enfore that.
1461 
1462 #undef INSN
1463 
1464 #define INSN(NAME, size, op)                            \
1465   void NAME(FloatRegister Rt, const Address &adr) {     \
1466     ld_st2((Register)Rt, adr, size, op, 1);             \
1467   }
1468 
1469   INSN(strd, 0b11, 0b00);
1470   INSN(strs, 0b10, 0b00);
1471   INSN(ldrd, 0b11, 0b01);
1472   INSN(ldrs, 0b10, 0b01);
1473   INSN(strq, 0b00, 0b10);
1474   INSN(ldrq, 0x00, 0b11);
1475 
1476 #undef INSN
1477 
1478   enum shift_kind { LSL, LSR, ASR, ROR };
1479 
1480   void op_shifted_reg(unsigned decode,
1481                       enum shift_kind kind, unsigned shift,
1482                       unsigned size, unsigned op) {
1483     f(size, 31);
1484     f(op, 30, 29);
1485     f(decode, 28, 24);
1486     f(shift, 15, 10);
1487     f(kind, 23, 22);
1488   }
1489 
1490   // Logical (shifted register)
1491 #define INSN(NAME, size, op, N)                                 \
1492   void NAME(Register Rd, Register Rn, Register Rm,              \
1493             enum shift_kind kind = LSL, unsigned shift = 0) {   \
1494     starti;                                                     \
1495     guarantee(size == 1 || shift < 32, "incorrect shift");      \
1496     f(N, 21);                                                   \
1497     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                        \
1498     op_shifted_reg(0b01010, kind, shift, size, op);             \
1499   }
1500 
1501   INSN(andr, 1, 0b00, 0);
1502   INSN(orr, 1, 0b01, 0);
1503   INSN(eor, 1, 0b10, 0);
1504   INSN(ands, 1, 0b11, 0);
1505   INSN(andw, 0, 0b00, 0);
1506   INSN(orrw, 0, 0b01, 0);
1507   INSN(eorw, 0, 0b10, 0);
1508   INSN(andsw, 0, 0b11, 0);
1509 
1510 #undef INSN
1511 
1512 #define INSN(NAME, size, op, N)                                         \
1513   void NAME(Register Rd, Register Rn, Register Rm,                      \
1514             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1515     starti;                                                             \
1516     f(N, 21);                                                           \
1517     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
1518     op_shifted_reg(0b01010, kind, shift, size, op);                     \
1519   }                                                                     \
1520                                                                         \
1521   /* These instructions have no immediate form. Provide an overload so  \
1522      that if anyone does try to use an immediate operand -- this has    \
1523      happened! -- we'll get a compile-time error. */                    \
1524   void NAME(Register Rd, Register Rn, unsigned imm,                     \
1525             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1526     assert(false, " can't be used with immediate operand");             \
1527   }
1528 
1529   INSN(bic, 1, 0b00, 1);
1530   INSN(orn, 1, 0b01, 1);
1531   INSN(eon, 1, 0b10, 1);
1532   INSN(bics, 1, 0b11, 1);
1533   INSN(bicw, 0, 0b00, 1);
1534   INSN(ornw, 0, 0b01, 1);
1535   INSN(eonw, 0, 0b10, 1);
1536   INSN(bicsw, 0, 0b11, 1);
1537 
1538 #undef INSN
1539 
1540 #ifdef _WIN64
1541 // In MSVC, `mvn` is defined as a macro and it screws up compilation
1542 #undef mvn
1543 #endif
1544 
1545   // Aliases for short forms of orn
1546 void mvn(Register Rd, Register Rm,
1547             enum shift_kind kind = LSL, unsigned shift = 0) {
1548   orn(Rd, zr, Rm, kind, shift);
1549 }
1550 
1551 void mvnw(Register Rd, Register Rm,
1552             enum shift_kind kind = LSL, unsigned shift = 0) {
1553   ornw(Rd, zr, Rm, kind, shift);
1554 }
1555 
1556   // Add/subtract (shifted register)
1557 #define INSN(NAME, size, op)                            \
1558   void NAME(Register Rd, Register Rn, Register Rm,      \
1559             enum shift_kind kind, unsigned shift = 0) { \
1560     starti;                                             \
1561     f(0, 21);                                           \
1562     assert_cond(kind != ROR);                           \
1563     guarantee(size == 1 || shift < 32, "incorrect shift");\
1564     zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16);                \
1565     op_shifted_reg(0b01011, kind, shift, size, op);     \
1566   }
1567 
1568   INSN(add, 1, 0b000);
1569   INSN(sub, 1, 0b10);
1570   INSN(addw, 0, 0b000);
1571   INSN(subw, 0, 0b10);
1572 
1573   INSN(adds, 1, 0b001);
1574   INSN(subs, 1, 0b11);
1575   INSN(addsw, 0, 0b001);
1576   INSN(subsw, 0, 0b11);
1577 
1578 #undef INSN
1579 
1580   // Add/subtract (extended register)
1581 #define INSN(NAME, op)                                                  \
1582   void NAME(Register Rd, Register Rn, Register Rm,                      \
1583            ext::operation option, int amount = 0) {                     \
1584     starti;                                                             \
1585     zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0);                                \
1586     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1587   }
1588 
1589   void add_sub_extended_reg(unsigned op, unsigned decode,
1590     Register Rd, Register Rn, Register Rm,
1591     unsigned opt, ext::operation option, unsigned imm) {
1592     guarantee(imm <= 4, "shift amount must be <= 4");
1593     f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1594     f(option, 15, 13), f(imm, 12, 10);
1595   }
1596 
1597   INSN(addw, 0b000);
1598   INSN(subw, 0b010);
1599   INSN(add, 0b100);
1600   INSN(sub, 0b110);
1601 
1602 #undef INSN
1603 
1604 #define INSN(NAME, op)                                                  \
1605   void NAME(Register Rd, Register Rn, Register Rm,                      \
1606            ext::operation option, int amount = 0) {                     \
1607     starti;                                                             \
1608     zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0);                                \
1609     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1610   }
1611 
1612   INSN(addsw, 0b001);
1613   INSN(subsw, 0b011);
1614   INSN(adds, 0b101);
1615   INSN(subs, 0b111);
1616 
1617 #undef INSN
1618 
1619   // Aliases for short forms of add and sub
1620 #define INSN(NAME)                                      \
1621   void NAME(Register Rd, Register Rn, Register Rm) {    \
1622     if (Rd == sp || Rn == sp)                           \
1623       NAME(Rd, Rn, Rm, ext::uxtx);                      \
1624     else                                                \
1625       NAME(Rd, Rn, Rm, LSL);                            \
1626   }
1627 
1628   INSN(addw);
1629   INSN(subw);
1630   INSN(add);
1631   INSN(sub);
1632 
1633   INSN(addsw);
1634   INSN(subsw);
1635   INSN(adds);
1636   INSN(subs);
1637 
1638 #undef INSN
1639 
1640   // Add/subtract (with carry)
1641   void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1642     starti;
1643     f(op, 31, 29);
1644     f(0b11010000, 28, 21);
1645     f(0b000000, 15, 10);
1646     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1647   }
1648 
1649   #define INSN(NAME, op)                                \
1650     void NAME(Register Rd, Register Rn, Register Rm) {  \
1651       add_sub_carry(op, Rd, Rn, Rm);                    \
1652     }
1653 
1654   INSN(adcw, 0b000);
1655   INSN(adcsw, 0b001);
1656   INSN(sbcw, 0b010);
1657   INSN(sbcsw, 0b011);
1658   INSN(adc, 0b100);
1659   INSN(adcs, 0b101);
1660   INSN(sbc,0b110);
1661   INSN(sbcs, 0b111);
1662 
1663 #undef INSN
1664 
1665   // Conditional compare (both kinds)
1666   void conditional_compare(unsigned op, int o1, int o2, int o3,
1667                            Register Rn, unsigned imm5, unsigned nzcv,
1668                            unsigned cond) {
1669     starti;
1670     f(op, 31, 29);
1671     f(0b11010010, 28, 21);
1672     f(cond, 15, 12);
1673     f(o1, 11);
1674     f(o2, 10);
1675     f(o3, 4);
1676     f(nzcv, 3, 0);
1677     f(imm5, 20, 16), zrf(Rn, 5);
1678   }
1679 
1680 #define INSN(NAME, op)                                                  \
1681   void NAME(Register Rn, Register Rm, int imm, Condition cond) {        \
1682     int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm);                    \
1683     conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond);         \
1684   }                                                                     \
1685                                                                         \
1686   void NAME(Register Rn, int imm5, int imm, Condition cond) {           \
1687     conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond);              \
1688   }
1689 
1690   INSN(ccmnw, 0b001);
1691   INSN(ccmpw, 0b011);
1692   INSN(ccmn, 0b101);
1693   INSN(ccmp, 0b111);
1694 
1695 #undef INSN
1696 
1697   // Conditional select
1698   void conditional_select(unsigned op, unsigned op2,
1699                           Register Rd, Register Rn, Register Rm,
1700                           unsigned cond) {
1701     starti;
1702     f(op, 31, 29);
1703     f(0b11010100, 28, 21);
1704     f(cond, 15, 12);
1705     f(op2, 11, 10);
1706     zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1707   }
1708 
1709 #define INSN(NAME, op, op2)                                             \
1710   void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1711     conditional_select(op, op2, Rd, Rn, Rm, cond);                      \
1712   }
1713 
1714   INSN(cselw, 0b000, 0b00);
1715   INSN(csincw, 0b000, 0b01);
1716   INSN(csinvw, 0b010, 0b00);
1717   INSN(csnegw, 0b010, 0b01);
1718   INSN(csel, 0b100, 0b00);
1719   INSN(csinc, 0b100, 0b01);
1720   INSN(csinv, 0b110, 0b00);
1721   INSN(csneg, 0b110, 0b01);
1722 
1723 #undef INSN
1724 
1725   // Data processing
1726   void data_processing(unsigned op29, unsigned opcode,
1727                        Register Rd, Register Rn) {
1728     f(op29, 31, 29), f(0b11010110, 28, 21);
1729     f(opcode, 15, 10);
1730     rf(Rn, 5), rf(Rd, 0);
1731   }
1732 
1733   // (1 source)
1734 #define INSN(NAME, op29, opcode2, opcode)       \
1735   void NAME(Register Rd, Register Rn) {         \
1736     starti;                                     \
1737     f(opcode2, 20, 16);                         \
1738     data_processing(op29, opcode, Rd, Rn);      \
1739   }
1740 
1741   INSN(rbitw,  0b010, 0b00000, 0b00000);
1742   INSN(rev16w, 0b010, 0b00000, 0b00001);
1743   INSN(revw,   0b010, 0b00000, 0b00010);
1744   INSN(clzw,   0b010, 0b00000, 0b00100);
1745   INSN(clsw,   0b010, 0b00000, 0b00101);
1746 
1747   INSN(rbit,   0b110, 0b00000, 0b00000);
1748   INSN(rev16,  0b110, 0b00000, 0b00001);
1749   INSN(rev32,  0b110, 0b00000, 0b00010);
1750   INSN(rev,    0b110, 0b00000, 0b00011);
1751   INSN(clz,    0b110, 0b00000, 0b00100);
1752   INSN(cls,    0b110, 0b00000, 0b00101);
1753 
1754 #undef INSN
1755 
1756   // (2 sources)
1757 #define INSN(NAME, op29, opcode)                        \
1758   void NAME(Register Rd, Register Rn, Register Rm) {    \
1759     starti;                                             \
1760     rf(Rm, 16);                                         \
1761     data_processing(op29, opcode, Rd, Rn);              \
1762   }
1763 
1764   INSN(udivw, 0b000, 0b000010);
1765   INSN(sdivw, 0b000, 0b000011);
1766   INSN(lslvw, 0b000, 0b001000);
1767   INSN(lsrvw, 0b000, 0b001001);
1768   INSN(asrvw, 0b000, 0b001010);
1769   INSN(rorvw, 0b000, 0b001011);
1770 
1771   INSN(udiv, 0b100, 0b000010);
1772   INSN(sdiv, 0b100, 0b000011);
1773   INSN(lslv, 0b100, 0b001000);
1774   INSN(lsrv, 0b100, 0b001001);
1775   INSN(asrv, 0b100, 0b001010);
1776   INSN(rorv, 0b100, 0b001011);
1777 
1778 #undef INSN
1779 
1780   // (3 sources)
1781   void data_processing(unsigned op54, unsigned op31, unsigned o0,
1782                        Register Rd, Register Rn, Register Rm,
1783                        Register Ra) {
1784     starti;
1785     f(op54, 31, 29), f(0b11011, 28, 24);
1786     f(op31, 23, 21), f(o0, 15);
1787     zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1788   }
1789 
1790 #define INSN(NAME, op54, op31, o0)                                      \
1791   void NAME(Register Rd, Register Rn, Register Rm, Register Ra) {       \
1792     data_processing(op54, op31, o0, Rd, Rn, Rm, Ra);                    \
1793   }
1794 
1795   INSN(maddw, 0b000, 0b000, 0);
1796   INSN(msubw, 0b000, 0b000, 1);
1797   INSN(madd, 0b100, 0b000, 0);
1798   INSN(msub, 0b100, 0b000, 1);
1799   INSN(smaddl, 0b100, 0b001, 0);
1800   INSN(smsubl, 0b100, 0b001, 1);
1801   INSN(umaddl, 0b100, 0b101, 0);
1802   INSN(umsubl, 0b100, 0b101, 1);
1803 
1804 #undef INSN
1805 
1806 #define INSN(NAME, op54, op31, o0)                      \
1807   void NAME(Register Rd, Register Rn, Register Rm) {    \
1808     data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31);  \
1809   }
1810 
1811   INSN(smulh, 0b100, 0b010, 0);
1812   INSN(umulh, 0b100, 0b110, 0);
1813 
1814 #undef INSN
1815 
1816   // Floating-point data-processing (1 source)
1817   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1818                        FloatRegister Vd, FloatRegister Vn) {
1819     starti;
1820     f(op31, 31, 29);
1821     f(0b11110, 28, 24);
1822     f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1823     rf(Vn, 5), rf(Vd, 0);
1824   }
1825 
1826 #define INSN(NAME, op31, type, opcode)                  \
1827   void NAME(FloatRegister Vd, FloatRegister Vn) {       \
1828     data_processing(op31, type, opcode, Vd, Vn);        \
1829   }
1830 
1831 private:
1832   INSN(i_fmovs, 0b000, 0b00, 0b000000);
1833 public:
1834   INSN(fabss, 0b000, 0b00, 0b000001);
1835   INSN(fnegs, 0b000, 0b00, 0b000010);
1836   INSN(fsqrts, 0b000, 0b00, 0b000011);
1837   INSN(fcvts, 0b000, 0b00, 0b000101);   // Single-precision to double-precision
1838 
1839 private:
1840   INSN(i_fmovd, 0b000, 0b01, 0b000000);
1841 public:
1842   INSN(fabsd, 0b000, 0b01, 0b000001);
1843   INSN(fnegd, 0b000, 0b01, 0b000010);
1844   INSN(fsqrtd, 0b000, 0b01, 0b000011);
1845   INSN(fcvtd, 0b000, 0b01, 0b000100);   // Double-precision to single-precision
1846 
1847   void fmovd(FloatRegister Vd, FloatRegister Vn) {
1848     assert(Vd != Vn, "should be");
1849     i_fmovd(Vd, Vn);
1850   }
1851 
1852   void fmovs(FloatRegister Vd, FloatRegister Vn) {
1853     assert(Vd != Vn, "should be");
1854     i_fmovs(Vd, Vn);
1855   }
1856 
1857 #undef INSN
1858 
1859   // Floating-point data-processing (2 source)
1860   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1861                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1862     starti;
1863     f(op31, 31, 29);
1864     f(0b11110, 28, 24);
1865     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1866     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1867   }
1868 
1869 #define INSN(NAME, op31, type, opcode)                  \
1870   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1871     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1872   }
1873 
1874   INSN(fmuls, 0b000, 0b00, 0b0000);
1875   INSN(fdivs, 0b000, 0b00, 0b0001);
1876   INSN(fadds, 0b000, 0b00, 0b0010);
1877   INSN(fsubs, 0b000, 0b00, 0b0011);
1878   INSN(fmaxs, 0b000, 0b00, 0b0100);
1879   INSN(fmins, 0b000, 0b00, 0b0101);
1880   INSN(fnmuls, 0b000, 0b00, 0b1000);
1881 
1882   INSN(fmuld, 0b000, 0b01, 0b0000);
1883   INSN(fdivd, 0b000, 0b01, 0b0001);
1884   INSN(faddd, 0b000, 0b01, 0b0010);
1885   INSN(fsubd, 0b000, 0b01, 0b0011);
1886   INSN(fmaxd, 0b000, 0b01, 0b0100);
1887   INSN(fmind, 0b000, 0b01, 0b0101);
1888   INSN(fnmuld, 0b000, 0b01, 0b1000);
1889 
1890 #undef INSN
1891 
1892    // Floating-point data-processing (3 source)
1893   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1894                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1895                        FloatRegister Va) {
1896     starti;
1897     f(op31, 31, 29);
1898     f(0b11111, 28, 24);
1899     f(type, 23, 22), f(o1, 21), f(o0, 15);
1900     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1901   }
1902 
1903 #define INSN(NAME, op31, type, o1, o0)                                  \
1904   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1905             FloatRegister Va) {                                         \
1906     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1907   }
1908 
1909   INSN(fmadds, 0b000, 0b00, 0, 0);
1910   INSN(fmsubs, 0b000, 0b00, 0, 1);
1911   INSN(fnmadds, 0b000, 0b00, 1, 0);
1912   INSN(fnmsubs, 0b000, 0b00, 1, 1);
1913 
1914   INSN(fmaddd, 0b000, 0b01, 0, 0);
1915   INSN(fmsubd, 0b000, 0b01, 0, 1);
1916   INSN(fnmaddd, 0b000, 0b01, 1, 0);
1917   INSN(fnmsub, 0b000, 0b01, 1, 1);
1918 
1919 #undef INSN
1920 
1921    // Floating-point conditional select
1922   void fp_conditional_select(unsigned op31, unsigned type,
1923                              unsigned op1, unsigned op2,
1924                              Condition cond, FloatRegister Vd,
1925                              FloatRegister Vn, FloatRegister Vm) {
1926     starti;
1927     f(op31, 31, 29);
1928     f(0b11110, 28, 24);
1929     f(type, 23, 22);
1930     f(op1, 21, 21);
1931     f(op2, 11, 10);
1932     f(cond, 15, 12);
1933     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1934   }
1935 
1936 #define INSN(NAME, op31, type, op1, op2)                                \
1937   void NAME(FloatRegister Vd, FloatRegister Vn,                         \
1938             FloatRegister Vm, Condition cond) {                         \
1939     fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm);      \
1940   }
1941 
1942   INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1943   INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1944 
1945 #undef INSN
1946 
1947    // Floating-point<->integer conversions
1948   void float_int_convert(unsigned op31, unsigned type,
1949                          unsigned rmode, unsigned opcode,
1950                          Register Rd, Register Rn) {
1951     starti;
1952     f(op31, 31, 29);
1953     f(0b11110, 28, 24);
1954     f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1955     f(opcode, 18, 16), f(0b000000, 15, 10);
1956     zrf(Rn, 5), zrf(Rd, 0);
1957   }
1958 
1959 #define INSN(NAME, op31, type, rmode, opcode)                           \
1960   void NAME(Register Rd, FloatRegister Vn) {                            \
1961     float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn);     \
1962   }
1963 
1964   INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1965   INSN(fcvtzs,  0b100, 0b00, 0b11, 0b000);
1966   INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1967   INSN(fcvtzd,  0b100, 0b01, 0b11, 0b000);
1968 
1969   INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1970   INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1971 
1972   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1973 
1974 #undef INSN
1975 
1976 #define INSN(NAME, op31, type, rmode, opcode)                           \
1977   void NAME(FloatRegister Vd, Register Rn) {                            \
1978     float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn);     \
1979   }
1980 
1981   INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1982   INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1983 
1984   INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1985   INSN(scvtfs,  0b100, 0b00, 0b00, 0b010);
1986   INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1987   INSN(scvtfd,  0b100, 0b01, 0b00, 0b010);
1988 
1989   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1990 
1991 #undef INSN
1992 
1993   // Floating-point compare
1994   void float_compare(unsigned op31, unsigned type,
1995                      unsigned op, unsigned op2,
1996                      FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1997     starti;
1998     f(op31, 31, 29);
1999     f(0b11110, 28, 24);
2000     f(type, 23, 22), f(1, 21);
2001     f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
2002     rf(Vn, 5), rf(Vm, 16);
2003   }
2004 
2005 
2006 #define INSN(NAME, op31, type, op, op2)                 \
2007   void NAME(FloatRegister Vn, FloatRegister Vm) {       \
2008     float_compare(op31, type, op, op2, Vn, Vm);         \
2009   }
2010 
2011 #define INSN1(NAME, op31, type, op, op2)        \
2012   void NAME(FloatRegister Vn, double d) {       \
2013     assert_cond(d == 0.0);                      \
2014     float_compare(op31, type, op, op2, Vn);     \
2015   }
2016 
2017   INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2018   INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2019   // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2020   // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2021 
2022   INSN(fcmpd, 0b000,   0b01, 0b00, 0b00000);
2023   INSN1(fcmpd, 0b000,  0b01, 0b00, 0b01000);
2024   // INSN(fcmped, 0b000,  0b01, 0b00, 0b10000);
2025   // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2026 
2027 #undef INSN
2028 #undef INSN1
2029 
2030   // Floating-point Move (immediate)
2031 private:
2032   unsigned pack(double value);
2033 
2034   void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2035     starti;
2036     f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2037     f(pack(value), 20, 13), f(0b10000000, 12, 5);
2038     rf(Vn, 0);
2039   }
2040 
2041 public:
2042 
2043   void fmovs(FloatRegister Vn, double value) {
2044     if (value)
2045       fmov_imm(Vn, value, 0b00);
2046     else
2047       fmovs(Vn, zr);
2048   }
2049   void fmovd(FloatRegister Vn, double value) {
2050     if (value)
2051       fmov_imm(Vn, value, 0b01);
2052     else
2053       fmovd(Vn, zr);
2054   }
2055 
2056    // Floating-point rounding
2057    // type: half-precision = 11
2058    //       single         = 00
2059    //       double         = 01
2060    // rmode: A = Away     = 100
2061    //        I = current  = 111
2062    //        M = MinusInf = 010
2063    //        N = eveN     = 000
2064    //        P = PlusInf  = 001
2065    //        X = eXact    = 110
2066    //        Z = Zero     = 011
2067   void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2068     starti;
2069     f(0b00011110, 31, 24);
2070     f(type, 23, 22);
2071     f(0b1001, 21, 18);
2072     f(rmode, 17, 15);
2073     f(0b10000, 14, 10);
2074     rf(Rn, 5), rf(Rd, 0);
2075   }
2076 #define INSN(NAME, type, rmode)                   \
2077   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2078     float_round(type, rmode, Vd, Vn);             \
2079   }
2080 
2081 public:
2082   INSN(frintah, 0b11, 0b100);
2083   INSN(frintih, 0b11, 0b111);
2084   INSN(frintmh, 0b11, 0b010);
2085   INSN(frintnh, 0b11, 0b000);
2086   INSN(frintph, 0b11, 0b001);
2087   INSN(frintxh, 0b11, 0b110);
2088   INSN(frintzh, 0b11, 0b011);
2089 
2090   INSN(frintas, 0b00, 0b100);
2091   INSN(frintis, 0b00, 0b111);
2092   INSN(frintms, 0b00, 0b010);
2093   INSN(frintns, 0b00, 0b000);
2094   INSN(frintps, 0b00, 0b001);
2095   INSN(frintxs, 0b00, 0b110);
2096   INSN(frintzs, 0b00, 0b011);
2097 
2098   INSN(frintad, 0b01, 0b100);
2099   INSN(frintid, 0b01, 0b111);
2100   INSN(frintmd, 0b01, 0b010);
2101   INSN(frintnd, 0b01, 0b000);
2102   INSN(frintpd, 0b01, 0b001);
2103   INSN(frintxd, 0b01, 0b110);
2104   INSN(frintzd, 0b01, 0b011);
2105 #undef INSN
2106 
2107 /* SIMD extensions
2108  *
2109  * We just use FloatRegister in the following. They are exactly the same
2110  * as SIMD registers.
2111  */
2112  public:
2113 
2114   enum SIMD_Arrangement {
2115        T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2116   };
2117 
2118   enum SIMD_RegVariant {
2119        B, H, S, D, Q
2120   };
2121 
2122 private:
2123   static short SIMD_Size_in_bytes[];
2124 
2125 public:
2126 #define INSN(NAME, op)                                            \
2127   void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) {   \
2128     ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2129   }                                                                      \
2130 
2131   INSN(ldr, 1);
2132   INSN(str, 0);
2133 
2134 #undef INSN
2135 
2136  private:
2137 
2138   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2139     starti;
2140     f(0,31), f((int)T & 1, 30);
2141     f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2142     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2143   }
2144   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2145              int imm, int op1, int op2, int regs) {
2146 
2147     bool replicate = op2 >> 2 == 3;
2148     // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2149     int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2150     guarantee(T < T1Q , "incorrect arrangement");
2151     guarantee(imm == expectedImmediate, "bad offset");
2152     starti;
2153     f(0,31), f((int)T & 1, 30);
2154     f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2155     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2156   }
2157   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2158              Register Xm, int op1, int op2) {
2159     starti;
2160     f(0,31), f((int)T & 1, 30);
2161     f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2162     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2163   }
2164 
2165   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2166     switch (a.getMode()) {
2167     case Address::base_plus_offset:
2168       guarantee(a.offset() == 0, "no offset allowed here");
2169       ld_st(Vt, T, a.base(), op1, op2);
2170       break;
2171     case Address::post:
2172       ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2173       break;
2174     case Address::post_reg:
2175       ld_st(Vt, T, a.base(), a.index(), op1, op2);
2176       break;
2177     default:
2178       ShouldNotReachHere();
2179     }
2180   }
2181 
2182  public:
2183 
2184 #define INSN1(NAME, op1, op2)                                           \
2185   void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) {   \
2186     ld_st(Vt, T, a, op1, op2, 1);                                       \
2187  }
2188 
2189 #define INSN2(NAME, op1, op2)                                           \
2190   void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2191     assert(Vt->successor() == Vt2, "Registers must be ordered");        \
2192     ld_st(Vt, T, a, op1, op2, 2);                                       \
2193   }
2194 
2195 #define INSN3(NAME, op1, op2)                                           \
2196   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2197             SIMD_Arrangement T, const Address &a) {                     \
2198     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,           \
2199            "Registers must be ordered");                                \
2200     ld_st(Vt, T, a, op1, op2, 3);                                       \
2201   }
2202 
2203 #define INSN4(NAME, op1, op2)                                           \
2204   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2205             FloatRegister Vt4, SIMD_Arrangement T, const Address &a) {  \
2206     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&         \
2207            Vt3->successor() == Vt4, "Registers must be ordered");       \
2208     ld_st(Vt, T, a, op1, op2, 4);                                       \
2209   }
2210 
2211   INSN1(ld1,  0b001100010, 0b0111);
2212   INSN2(ld1,  0b001100010, 0b1010);
2213   INSN3(ld1,  0b001100010, 0b0110);
2214   INSN4(ld1,  0b001100010, 0b0010);
2215 
2216   INSN2(ld2,  0b001100010, 0b1000);
2217   INSN3(ld3,  0b001100010, 0b0100);
2218   INSN4(ld4,  0b001100010, 0b0000);
2219 
2220   INSN1(st1,  0b001100000, 0b0111);
2221   INSN2(st1,  0b001100000, 0b1010);
2222   INSN3(st1,  0b001100000, 0b0110);
2223   INSN4(st1,  0b001100000, 0b0010);
2224 
2225   INSN2(st2,  0b001100000, 0b1000);
2226   INSN3(st3,  0b001100000, 0b0100);
2227   INSN4(st4,  0b001100000, 0b0000);
2228 
2229   INSN1(ld1r, 0b001101010, 0b1100);
2230   INSN2(ld2r, 0b001101011, 0b1100);
2231   INSN3(ld3r, 0b001101010, 0b1110);
2232   INSN4(ld4r, 0b001101011, 0b1110);
2233 
2234 #undef INSN1
2235 #undef INSN2
2236 #undef INSN3
2237 #undef INSN4
2238 
2239 #define INSN(NAME, opc)                                                                 \
2240   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2241     starti;                                                                             \
2242     assert(T == T8B || T == T16B, "must be T8B or T16B");                               \
2243     f(0, 31), f((int)T & 1, 30), f(opc, 29, 21);                                        \
2244     rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);                              \
2245   }
2246 
2247   INSN(eor,  0b101110001);
2248   INSN(orr,  0b001110101);
2249   INSN(andr, 0b001110001);
2250   INSN(bic,  0b001110011);
2251   INSN(bif,  0b101110111);
2252   INSN(bit,  0b101110101);
2253   INSN(bsl,  0b101110011);
2254   INSN(orn,  0b001110111);
2255 
2256 #undef INSN
2257 
2258 #define INSN(NAME, opc, opc2, acceptT2D)                                                \
2259   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2260     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2261     if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement");                       \
2262     starti;                                                                             \
2263     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2264     f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10);                      \
2265     rf(Vn, 5), rf(Vd, 0);                                                               \
2266   }
2267 
2268   INSN(addv,   0, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2269   INSN(subv,   1, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2270   INSN(mulv,   0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2271   INSN(mlav,   0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2272   INSN(mlsv,   1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2273   INSN(sshl,   0, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2274   INSN(ushl,   1, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2275   INSN(addpv,  0, 0b101111, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2276   INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2277   INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2278   INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2279 
2280 #undef INSN
2281 
2282 #define INSN(NAME, opc, opc2, accepted) \
2283   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2284     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2285     if (accepted < 3) guarantee(T != T2D, "incorrect arrangement");                     \
2286     if (accepted < 2) guarantee(T != T2S, "incorrect arrangement");                     \
2287     if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement");        \
2288     starti;                                                                             \
2289     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2290     f((int)T >> 1, 23, 22), f(opc2, 21, 10);                                            \
2291     rf(Vn, 5), rf(Vd, 0);                                                               \
2292   }
2293 
2294   INSN(absr,   0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2295   INSN(negr,   1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2296   INSN(notr,   1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2297   INSN(addv,   0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2298   INSN(cls,    0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2299   INSN(clz,    1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2300   INSN(cnt,    0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2301   INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2302   INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2303 
2304 #undef INSN
2305 
2306 #define INSN(NAME, opc) \
2307   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                  \
2308     starti;                                                                            \
2309     assert(T == T4S, "arrangement must be T4S");                                       \
2310     f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23),                      \
2311     f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0);          \
2312   }
2313 
2314   INSN(fmaxv, 0);
2315   INSN(fminv, 1);
2316 
2317 #undef INSN
2318 
2319 #define INSN(NAME, op0, cmode0) \
2320   void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
2321     unsigned cmode = cmode0;                                                           \
2322     unsigned op = op0;                                                                 \
2323     starti;                                                                            \
2324     assert(lsl == 0 ||                                                                 \
2325            ((T == T4H || T == T8H) && lsl == 8) ||                                     \
2326            ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2327     cmode |= lsl >> 2;                                                                 \
2328     if (T == T4H || T == T8H) cmode |= 0b1000;                                         \
2329     if (!(T == T4H || T == T8H || T == T2S || T == T4S)) {                             \
2330       assert(op == 0 && cmode0 == 0, "must be MOVI");                                  \
2331       cmode = 0b1110;                                                                  \
2332       if (T == T1D || T == T2D) op = 1;                                                \
2333     }                                                                                  \
2334     f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);                   \
2335     f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5);  \
2336     rf(Vd, 0);                                                                         \
2337   }
2338 
2339   INSN(movi, 0, 0);
2340   INSN(orri, 0, 1);
2341   INSN(mvni, 1, 0);
2342   INSN(bici, 1, 1);
2343 
2344 #undef INSN
2345 
2346 #define INSN(NAME, op1, op2, op3) \
2347   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2348     starti;                                                                             \
2349     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                    \
2350     f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);            \
2351     f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0);    \
2352   }
2353 
2354   INSN(fadd, 0, 0, 0b110101);
2355   INSN(fdiv, 1, 0, 0b111111);
2356   INSN(fmul, 1, 0, 0b110111);
2357   INSN(fsub, 0, 1, 0b110101);
2358   INSN(fmla, 0, 0, 0b110011);
2359   INSN(fmls, 0, 1, 0b110011);
2360   INSN(fmax, 0, 0, 0b111101);
2361   INSN(fmin, 0, 1, 0b111101);
2362 
2363 #undef INSN
2364 
2365 #define INSN(NAME, opc)                                                                 \
2366   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2367     starti;                                                                             \
2368     assert(T == T4S, "arrangement must be T4S");                                        \
2369     f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
2370   }
2371 
2372   INSN(sha1c,     0b000000);
2373   INSN(sha1m,     0b001000);
2374   INSN(sha1p,     0b000100);
2375   INSN(sha1su0,   0b001100);
2376   INSN(sha256h2,  0b010100);
2377   INSN(sha256h,   0b010000);
2378   INSN(sha256su1, 0b011000);
2379 
2380 #undef INSN
2381 
2382 #define INSN(NAME, opc)                                                                 \
2383   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2384     starti;                                                                             \
2385     assert(T == T4S, "arrangement must be T4S");                                        \
2386     f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);                \
2387   }
2388 
2389   INSN(sha1h,     0b000010);
2390   INSN(sha1su1,   0b000110);
2391   INSN(sha256su0, 0b001010);
2392 
2393 #undef INSN
2394 
2395 #define INSN(NAME, opc)                           \
2396   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2397     starti;                                       \
2398     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
2399   }
2400 
2401   INSN(aese, 0b0100111000101000010010);
2402   INSN(aesd, 0b0100111000101000010110);
2403   INSN(aesmc, 0b0100111000101000011010);
2404   INSN(aesimc, 0b0100111000101000011110);
2405 
2406 #undef INSN
2407 
2408 #define INSN(NAME, op1, op2) \
2409   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2410     starti;                                                                                            \
2411     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                                   \
2412     assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index");     \
2413     f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23);                                      \
2414     f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16);                              \
2415     f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10);                                  \
2416     rf(Vn, 5), rf(Vd, 0);                                                                              \
2417   }
2418 
2419   // FMLA/FMLS - Vector - Scalar
2420   INSN(fmlavs, 0, 0b0001);
2421   INSN(fmlsvs, 0, 0b0101);
2422   // FMULX - Vector - Scalar
2423   INSN(fmulxvs, 1, 0b1001);
2424 
2425 #undef INSN
2426 
2427   // Floating-point Reciprocal Estimate
2428   void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2429     assert(type == D || type == S, "Wrong type for frecpe");
2430     starti;
2431     f(0b010111101, 31, 23);
2432     f(type == D ? 1 : 0, 22);
2433     f(0b100001110110, 21, 10);
2434     rf(Vn, 5), rf(Vd, 0);
2435   }
2436 
2437   // (double) {a, b} -> (a + b)
2438   void faddpd(FloatRegister Vd, FloatRegister Vn) {
2439     starti;
2440     f(0b0111111001110000110110, 31, 10);
2441     rf(Vn, 5), rf(Vd, 0);
2442   }
2443 
2444   void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2445     starti;
2446     assert(T != Q, "invalid register variant");
2447     f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2448     f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2449   }
2450 
2451   void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2452     starti;
2453     f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2454     f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2455     rf(Vn, 5), rf(Rd, 0);
2456   }
2457 
2458 #define INSN(NAME, opc, opc2, isSHR)                                    \
2459   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2460     starti;                                                             \
2461     /* The encodings for the immh:immb fields (bits 22:16) in *SHR are  \
2462      *   0001 xxx       8B/16B, shift = 16  - UInt(immh:immb)           \
2463      *   001x xxx       4H/8H,  shift = 32  - UInt(immh:immb)           \
2464      *   01xx xxx       2S/4S,  shift = 64  - UInt(immh:immb)           \
2465      *   1xxx xxx       1D/2D,  shift = 128 - UInt(immh:immb)           \
2466      *   (1D is RESERVED)                                               \
2467      * for SHL shift is calculated as:                                  \
2468      *   0001 xxx       8B/16B, shift = UInt(immh:immb) - 8             \
2469      *   001x xxx       4H/8H,  shift = UInt(immh:immb) - 16            \
2470      *   01xx xxx       2S/4S,  shift = UInt(immh:immb) - 32            \
2471      *   1xxx xxx       1D/2D,  shift = UInt(immh:immb) - 64            \
2472      *   (1D is RESERVED)                                               \
2473      */                                                                 \
2474     assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");           \
2475     int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0)));               \
2476     int encodedShift = isSHR ? cVal - shift : cVal + shift;             \
2477     f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23),            \
2478     f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);     \
2479   }
2480 
2481   INSN(shl,  0, 0b010101, /* isSHR = */ false);
2482   INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2483   INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2484 
2485 #undef INSN
2486 
2487 private:
2488   void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2489     starti;
2490     /* The encodings for the immh:immb fields (bits 22:16) are
2491      *   0001 xxx       8H, 8B/16b shift = xxx
2492      *   001x xxx       4S, 4H/8H  shift = xxxx
2493      *   01xx xxx       2D, 2S/4S  shift = xxxxx
2494      *   1xxx xxx       RESERVED
2495      */
2496     assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2497     assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2498     f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2499     f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2500   }
2501 
2502 public:
2503   void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
2504     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2505     _ushll(Vd, Ta, Vn, Tb, shift);
2506   }
2507 
2508   void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
2509     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2510     _ushll(Vd, Ta, Vn, Tb, shift);
2511   }
2512 
2513   // Move from general purpose register
2514   //   mov  Vd.T[index], Rn
2515   void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2516     starti;
2517     f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2518     f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2519   }
2520 
2521   // Move to general purpose register
2522   //   mov  Rd, Vn.T[index]
2523   void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2524     guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2525     starti;
2526     f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2527     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2528     f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2529   }
2530 
2531 private:
2532   void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2533     starti;
2534     assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2535            (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2536     int size = (Ta == T1Q) ? 0b11 : 0b00;
2537     f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2538     f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2539   }
2540 
2541 public:
2542   void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2543     assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2544     _pmull(Vd, Ta, Vn, Vm, Tb);
2545   }
2546 
2547   void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2548     assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2549     _pmull(Vd, Ta, Vn, Vm, Tb);
2550   }
2551 
2552   void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2553     starti;
2554     int size_b = (int)Tb >> 1;
2555     int size_a = (int)Ta >> 1;
2556     assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2557     f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2558     f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2559   }
2560 
2561   void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2562   {
2563     starti;
2564     assert(T != T1D, "reserved encoding");
2565     f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2566     f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2567   }
2568 
2569   void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2570   {
2571     starti;
2572     assert(T != T1D, "reserved encoding");
2573     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2574     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2575     f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2576   }
2577 
2578   // AdvSIMD ZIP/UZP/TRN
2579 #define INSN(NAME, opcode)                                              \
2580   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2581     guarantee(T != T1D && T != T1Q, "invalid arrangement");             \
2582     starti;                                                             \
2583     f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15);                  \
2584     f(opcode, 14, 12), f(0b10, 11, 10);                                 \
2585     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);                                   \
2586     f(T & 1, 30), f(T >> 1, 23, 22);                                    \
2587   }
2588 
2589   INSN(uzp1, 0b001);
2590   INSN(trn1, 0b010);
2591   INSN(zip1, 0b011);
2592   INSN(uzp2, 0b101);
2593   INSN(trn2, 0b110);
2594   INSN(zip2, 0b111);
2595 
2596 #undef INSN
2597 
2598   // CRC32 instructions
2599 #define INSN(NAME, c, sf, sz)                                             \
2600   void NAME(Register Rd, Register Rn, Register Rm) {                      \
2601     starti;                                                               \
2602     f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12);       \
2603     f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                      \
2604   }
2605 
2606   INSN(crc32b,  0, 0, 0b00);
2607   INSN(crc32h,  0, 0, 0b01);
2608   INSN(crc32w,  0, 0, 0b10);
2609   INSN(crc32x,  0, 1, 0b11);
2610   INSN(crc32cb, 1, 0, 0b00);
2611   INSN(crc32ch, 1, 0, 0b01);
2612   INSN(crc32cw, 1, 0, 0b10);
2613   INSN(crc32cx, 1, 1, 0b11);
2614 
2615 #undef INSN
2616 
2617   // Table vector lookup
2618 #define INSN(NAME, op)                                                  \
2619   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2620     starti;                                                             \
2621     assert(T == T8B || T == T16B, "invalid arrangement");               \
2622     assert(0 < registers && registers <= 4, "invalid number of registers"); \
2623     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2624     f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2625   }
2626 
2627   INSN(tbl, 0);
2628   INSN(tbx, 1);
2629 
2630 #undef INSN
2631 
2632   // AdvSIMD two-reg misc
2633   // In this instruction group, the 2 bits in the size field ([23:22]) may be
2634   // fixed or determined by the "SIMD_Arrangement T", or both. The additional
2635   // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
2636   // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
2637   // set to 1 if corresponding bit marked as "x" in the ArmARM.
2638 #define INSN(NAME, U, size, tmask, opcode)                                          \
2639   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
2640        starti;                                                                      \
2641        assert((ASSERTION), MSG);                                                    \
2642        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
2643        f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17);               \
2644        f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                    \
2645  }
2646 
2647 #define MSG "invalid arrangement"
2648 
2649 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2650   INSN(fsqrt,  1, 0b10, 0b01, 0b11111);
2651   INSN(fabs,   0, 0b10, 0b01, 0b01111);
2652   INSN(fneg,   1, 0b10, 0b01, 0b01111);
2653   INSN(frintn, 0, 0b00, 0b01, 0b11000);
2654   INSN(frintm, 0, 0b00, 0b01, 0b11001);
2655   INSN(frintp, 0, 0b10, 0b01, 0b11000);
2656 #undef ASSERTION
2657 
2658 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2659   INSN(rev64, 0, 0b00, 0b11, 0b00000);
2660 #undef ASSERTION
2661 
2662 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2663   INSN(rev32, 1, 0b00, 0b11, 0b00000);
2664 #undef ASSERTION
2665 
2666 #define ASSERTION (T == T8B || T == T16B)
2667   INSN(rev16, 0, 0b00, 0b11, 0b00001);
2668   INSN(rbit,  1, 0b01, 0b00, 0b00101);
2669 #undef ASSERTION
2670 
2671 #undef MSG
2672 
2673 #undef INSN
2674 
2675 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2676   {
2677     starti;
2678     assert(T == T8B || T == T16B, "invalid arrangement");
2679     assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2680     f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2681     rf(Vm, 16), f(0, 15), f(index, 14, 11);
2682     f(0, 10), rf(Vn, 5), rf(Vd, 0);
2683   }
2684 
2685   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2686   }
2687 
2688   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2689                                                 Register tmp,
2690                                                 int offset) {
2691     ShouldNotCallThis();
2692     return RegisterOrConstant();
2693   }
2694 
2695   // Stack overflow checking
2696   virtual void bang_stack_with_offset(int offset);
2697 
2698   static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2699   static bool operand_valid_for_add_sub_immediate(int64_t imm);
2700   static bool operand_valid_for_float_immediate(double imm);
2701 
2702   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2703   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2704 };
2705 
2706 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2707                                              Assembler::Membar_mask_bits b) {
2708   return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2709 }
2710 
2711 Instruction_aarch64::~Instruction_aarch64() {
2712   assem->emit();
2713 }
2714 
2715 #undef starti
2716 
2717 // Invert a condition
2718 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2719   return Assembler::Condition(int(cond) ^ 1);
2720 }
2721 
2722 class BiasedLockingCounters;
2723 
2724 extern "C" void das(uint64_t start, int len);
2725 
2726 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP