1 /*
2 * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_LIR.hpp"
29 #include "runtime/sharedRuntime.hpp"
30 #include "vmreg_aarch64.inline.hpp"
31
32 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
33 LIR_Opr opr = LIR_OprFact::illegalOpr;
34 VMReg r_1 = reg->first();
35 VMReg r_2 = reg->second();
36 if (r_1->is_stack()) {
37 // Convert stack slot to an SP offset
38 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
39 // so we must add it in here.
40 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
41 opr = LIR_OprFact::address(new LIR_Address(sp_opr, st_off, type));
42 } else if (r_1->is_Register()) {
43 Register reg = r_1->as_Register();
44 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
45 Register reg2 = r_2->as_Register();
46 assert(reg2 == reg, "must be same register");
47 opr = as_long_opr(reg);
48 } else if (is_reference_type(type)) {
49 opr = as_oop_opr(reg);
50 } else if (type == T_METADATA) {
51 opr = as_metadata_opr(reg);
52 } else if (type == T_ADDRESS) {
53 opr = as_address_opr(reg);
54 } else {
55 opr = as_opr(reg);
56 }
57 } else if (r_1->is_FloatRegister()) {
58 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
59 int num = r_1->as_FloatRegister()->encoding();
60 if (type == T_FLOAT) {
61 opr = LIR_OprFact::single_fpu(num);
62 } else {
63 opr = LIR_OprFact::double_fpu(num);
64 }
65 } else {
66 ShouldNotReachHere();
67 }
68 return opr;
69 }
70
71 LIR_Opr FrameMap::r0_opr;
72 LIR_Opr FrameMap::r1_opr;
73 LIR_Opr FrameMap::r2_opr;
74 LIR_Opr FrameMap::r3_opr;
75 LIR_Opr FrameMap::r4_opr;
76 LIR_Opr FrameMap::r5_opr;
77 LIR_Opr FrameMap::r6_opr;
78 LIR_Opr FrameMap::r7_opr;
79 LIR_Opr FrameMap::r8_opr;
80 LIR_Opr FrameMap::r9_opr;
81 LIR_Opr FrameMap::r10_opr;
82 LIR_Opr FrameMap::r11_opr;
83 LIR_Opr FrameMap::r12_opr;
84 LIR_Opr FrameMap::r13_opr;
85 LIR_Opr FrameMap::r14_opr;
86 LIR_Opr FrameMap::r15_opr;
87 LIR_Opr FrameMap::r16_opr;
88 LIR_Opr FrameMap::r17_opr;
89 LIR_Opr FrameMap::r18_opr;
90 LIR_Opr FrameMap::r19_opr;
91 LIR_Opr FrameMap::r20_opr;
92 LIR_Opr FrameMap::r21_opr;
93 LIR_Opr FrameMap::r22_opr;
94 LIR_Opr FrameMap::r23_opr;
95 LIR_Opr FrameMap::r24_opr;
96 LIR_Opr FrameMap::r25_opr;
97 LIR_Opr FrameMap::r26_opr;
98 LIR_Opr FrameMap::r27_opr;
99 LIR_Opr FrameMap::r28_opr;
100 LIR_Opr FrameMap::r29_opr;
101 LIR_Opr FrameMap::r30_opr;
102
103 LIR_Opr FrameMap::rfp_opr;
104 LIR_Opr FrameMap::sp_opr;
105
106 LIR_Opr FrameMap::receiver_opr;
107
108 LIR_Opr FrameMap::r0_oop_opr;
109 LIR_Opr FrameMap::r1_oop_opr;
110 LIR_Opr FrameMap::r2_oop_opr;
111 LIR_Opr FrameMap::r3_oop_opr;
112 LIR_Opr FrameMap::r4_oop_opr;
113 LIR_Opr FrameMap::r5_oop_opr;
114 LIR_Opr FrameMap::r6_oop_opr;
115 LIR_Opr FrameMap::r7_oop_opr;
116 LIR_Opr FrameMap::r8_oop_opr;
117 LIR_Opr FrameMap::r9_oop_opr;
118 LIR_Opr FrameMap::r10_oop_opr;
119 LIR_Opr FrameMap::r11_oop_opr;
120 LIR_Opr FrameMap::r12_oop_opr;
121 LIR_Opr FrameMap::r13_oop_opr;
122 LIR_Opr FrameMap::r14_oop_opr;
123 LIR_Opr FrameMap::r15_oop_opr;
124 LIR_Opr FrameMap::r16_oop_opr;
125 LIR_Opr FrameMap::r17_oop_opr;
126 LIR_Opr FrameMap::r18_oop_opr;
127 LIR_Opr FrameMap::r19_oop_opr;
128 LIR_Opr FrameMap::r20_oop_opr;
129 LIR_Opr FrameMap::r21_oop_opr;
130 LIR_Opr FrameMap::r22_oop_opr;
131 LIR_Opr FrameMap::r23_oop_opr;
132 LIR_Opr FrameMap::r24_oop_opr;
133 LIR_Opr FrameMap::r25_oop_opr;
134 LIR_Opr FrameMap::r26_oop_opr;
135 LIR_Opr FrameMap::r27_oop_opr;
136 LIR_Opr FrameMap::r28_oop_opr;
137 LIR_Opr FrameMap::r29_oop_opr;
138 LIR_Opr FrameMap::r30_oop_opr;
139
140 LIR_Opr FrameMap::rscratch1_opr;
141 LIR_Opr FrameMap::rscratch2_opr;
142 LIR_Opr FrameMap::rscratch1_long_opr;
143 LIR_Opr FrameMap::rscratch2_long_opr;
144
145 LIR_Opr FrameMap::r0_metadata_opr;
146 LIR_Opr FrameMap::r1_metadata_opr;
147 LIR_Opr FrameMap::r2_metadata_opr;
148 LIR_Opr FrameMap::r3_metadata_opr;
149 LIR_Opr FrameMap::r4_metadata_opr;
150 LIR_Opr FrameMap::r5_metadata_opr;
151
152 LIR_Opr FrameMap::long0_opr;
153 LIR_Opr FrameMap::long1_opr;
154 LIR_Opr FrameMap::fpu0_float_opr;
155 LIR_Opr FrameMap::fpu0_double_opr;
156
157 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
158 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
159
160 //--------------------------------------------------------
161 // FrameMap
162 //--------------------------------------------------------
163
164 void FrameMap::initialize() {
165 assert(!_init_done, "once");
166
167 int i=0;
168 map_register(i, r0); r0_opr = LIR_OprFact::single_cpu(i); i++;
169 map_register(i, r1); r1_opr = LIR_OprFact::single_cpu(i); i++;
170 map_register(i, r2); r2_opr = LIR_OprFact::single_cpu(i); i++;
171 map_register(i, r3); r3_opr = LIR_OprFact::single_cpu(i); i++;
172 map_register(i, r4); r4_opr = LIR_OprFact::single_cpu(i); i++;
173 map_register(i, r5); r5_opr = LIR_OprFact::single_cpu(i); i++;
174 map_register(i, r6); r6_opr = LIR_OprFact::single_cpu(i); i++;
175 map_register(i, r7); r7_opr = LIR_OprFact::single_cpu(i); i++;
176 map_register(i, r10); r10_opr = LIR_OprFact::single_cpu(i); i++;
177 map_register(i, r11); r11_opr = LIR_OprFact::single_cpu(i); i++;
178 map_register(i, r12); r12_opr = LIR_OprFact::single_cpu(i); i++;
179 map_register(i, r13); r13_opr = LIR_OprFact::single_cpu(i); i++;
180 map_register(i, r14); r14_opr = LIR_OprFact::single_cpu(i); i++;
181 map_register(i, r15); r15_opr = LIR_OprFact::single_cpu(i); i++;
182 map_register(i, r16); r16_opr = LIR_OprFact::single_cpu(i); i++;
183 map_register(i, r17); r17_opr = LIR_OprFact::single_cpu(i); i++;
184 #ifndef _WIN64
185 // See comment in aarch64.ad about R18 in non_allocatable_reg32
186 map_register(i, r18); r18_opr = LIR_OprFact::single_cpu(i); i++;
187 #endif
188 map_register(i, r19); r19_opr = LIR_OprFact::single_cpu(i); i++;
189 map_register(i, r20); r20_opr = LIR_OprFact::single_cpu(i); i++;
190 map_register(i, r21); r21_opr = LIR_OprFact::single_cpu(i); i++;
191 map_register(i, r22); r22_opr = LIR_OprFact::single_cpu(i); i++;
192 map_register(i, r23); r23_opr = LIR_OprFact::single_cpu(i); i++;
193 map_register(i, r24); r24_opr = LIR_OprFact::single_cpu(i); i++;
194 map_register(i, r25); r25_opr = LIR_OprFact::single_cpu(i); i++;
195 map_register(i, r26); r26_opr = LIR_OprFact::single_cpu(i); i++;
196
197 map_register(i, r27); r27_opr = LIR_OprFact::single_cpu(i); i++; // rheapbase
198 map_register(i, r28); r28_opr = LIR_OprFact::single_cpu(i); i++; // rthread
199 map_register(i, r29); r29_opr = LIR_OprFact::single_cpu(i); i++; // rfp
200 map_register(i, r30); r30_opr = LIR_OprFact::single_cpu(i); i++; // lr
201 map_register(i, r31_sp); sp_opr = LIR_OprFact::single_cpu(i); i++; // sp
202 map_register(i, r8); r8_opr = LIR_OprFact::single_cpu(i); i++; // rscratch1
203 map_register(i, r9); r9_opr = LIR_OprFact::single_cpu(i); i++; // rscratch2
204
205 #ifdef _WIN64
206 // See comment in aarch64.ad about R18 in non_allocatable_reg32
207 map_register(i, r18); r18_opr = LIR_OprFact::single_cpu(i); i++; // TLS for Win
208 #endif
209
210 rscratch1_opr = r8_opr;
211 rscratch2_opr = r9_opr;
212 rscratch1_long_opr = LIR_OprFact::double_cpu(r8_opr->cpu_regnr(), r8_opr->cpu_regnr());
213 rscratch2_long_opr = LIR_OprFact::double_cpu(r9_opr->cpu_regnr(), r9_opr->cpu_regnr());
214
215 long0_opr = LIR_OprFact::double_cpu(0, 0);
216 long1_opr = LIR_OprFact::double_cpu(1, 1);
217
218 fpu0_float_opr = LIR_OprFact::single_fpu(0);
219 fpu0_double_opr = LIR_OprFact::double_fpu(0);
220
221 _caller_save_cpu_regs[0] = r0_opr;
222 _caller_save_cpu_regs[1] = r1_opr;
223 _caller_save_cpu_regs[2] = r2_opr;
224 _caller_save_cpu_regs[3] = r3_opr;
225 _caller_save_cpu_regs[4] = r4_opr;
226 _caller_save_cpu_regs[5] = r5_opr;
227 _caller_save_cpu_regs[6] = r6_opr;
228 _caller_save_cpu_regs[7] = r7_opr;
229 // rscratch1, rscratch 2 not included
230 _caller_save_cpu_regs[8] = r10_opr;
231 _caller_save_cpu_regs[9] = r11_opr;
232 _caller_save_cpu_regs[10] = r12_opr;
233 _caller_save_cpu_regs[11] = r13_opr;
234 _caller_save_cpu_regs[12] = r14_opr;
235 _caller_save_cpu_regs[13] = r15_opr;
236 _caller_save_cpu_regs[14] = r16_opr;
237 _caller_save_cpu_regs[15] = r17_opr;
238 #ifndef _WIN64
239 // R18 used for TLS on Windows
240 _caller_save_cpu_regs[16] = r18_opr;
241 #endif
242
243 for (int i = 0; i < 8; i++) {
244 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
245 }
246
247 _init_done = true;
248
249 r0_oop_opr = as_oop_opr(r0);
250 r1_oop_opr = as_oop_opr(r1);
251 r2_oop_opr = as_oop_opr(r2);
252 r3_oop_opr = as_oop_opr(r3);
253 r4_oop_opr = as_oop_opr(r4);
254 r5_oop_opr = as_oop_opr(r5);
255 r6_oop_opr = as_oop_opr(r6);
256 r7_oop_opr = as_oop_opr(r7);
257 r8_oop_opr = as_oop_opr(r8);
258 r9_oop_opr = as_oop_opr(r9);
259 r10_oop_opr = as_oop_opr(r10);
260 r11_oop_opr = as_oop_opr(r11);
261 r12_oop_opr = as_oop_opr(r12);
262 r13_oop_opr = as_oop_opr(r13);
263 r14_oop_opr = as_oop_opr(r14);
264 r15_oop_opr = as_oop_opr(r15);
265 r16_oop_opr = as_oop_opr(r16);
266 r17_oop_opr = as_oop_opr(r17);
267 r18_oop_opr = as_oop_opr(r18);
268 r19_oop_opr = as_oop_opr(r19);
269 r20_oop_opr = as_oop_opr(r20);
270 r21_oop_opr = as_oop_opr(r21);
271 r22_oop_opr = as_oop_opr(r22);
272 r23_oop_opr = as_oop_opr(r23);
273 r24_oop_opr = as_oop_opr(r24);
274 r25_oop_opr = as_oop_opr(r25);
275 r26_oop_opr = as_oop_opr(r26);
276 r27_oop_opr = as_oop_opr(r27);
277 r28_oop_opr = as_oop_opr(r28);
278 r29_oop_opr = as_oop_opr(r29);
279 r30_oop_opr = as_oop_opr(r30);
280
281 r0_metadata_opr = as_metadata_opr(r0);
282 r1_metadata_opr = as_metadata_opr(r1);
283 r2_metadata_opr = as_metadata_opr(r2);
284 r3_metadata_opr = as_metadata_opr(r3);
285 r4_metadata_opr = as_metadata_opr(r4);
286 r5_metadata_opr = as_metadata_opr(r5);
287
288 sp_opr = as_pointer_opr(r31_sp);
289 rfp_opr = as_pointer_opr(rfp);
290
291 VMRegPair regs;
292 BasicType sig_bt = T_OBJECT;
293 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
294 receiver_opr = as_oop_opr(regs.first()->as_Register());
295
296 for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
297 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
298 }
299 }
300
301
302 Address FrameMap::make_new_address(ByteSize sp_offset) const {
303 // for rbp, based address use this:
304 // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
305 return Address(sp, in_bytes(sp_offset));
306 }
307
308
309 // ----------------mapping-----------------------
310 // all mapping is based on rfp addressing, except for simple leaf methods where we access
311 // the locals sp based (and no frame is built)
312
313
314 // Frame for simple leaf methods (quick entries)
315 //
316 // +----------+
317 // | ret addr | <- TOS
318 // +----------+
319 // | args |
320 // | ...... |
321
322 // Frame for standard methods
323 //
324 // | .........| <- TOS
325 // | locals |
326 // +----------+
327 // | old fp, | <- RFP
328 // +----------+
329 // | ret addr |
330 // +----------+
331 // | args |
332 // | .........|
333
334
335 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
336 // This is the offset from sp() in the frame of the slot for the index,
337 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
338 //
339 // framesize +
340 // stack0 stack0 0 <- VMReg
341 // | | <registers> |
342 // ...........|..............|.............|
343 // 0 1 2 3 x x 4 5 6 ... | <- local indices
344 // ^ ^ sp() ( x x indicate link
345 // | | and return addr)
346 // arguments non-argument locals
347
348
349 VMReg FrameMap::fpu_regname (int n) {
350 // Return the OptoReg name for the fpu stack slot "n"
351 // A spilled fpu stack slot comprises to two single-word OptoReg's.
352 return as_FloatRegister(n)->as_VMReg();
353 }
354
355 LIR_Opr FrameMap::stack_pointer() {
356 return FrameMap::sp_opr;
357 }
358
359
360 // JSR 292
361 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
362 return LIR_OprFact::illegalOpr; // Not needed on aarch64
363 }
364
365
366 bool FrameMap::validate_frame() {
367 return true;
368 }