1 /* 2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "jvm.h" 30 #include "asm/assembler.hpp" 31 #include "asm/assembler.inline.hpp" 32 #include "gc/shared/barrierSet.hpp" 33 #include "gc/shared/cardTable.hpp" 34 #include "gc/shared/barrierSetAssembler.hpp" 35 #include "gc/shared/cardTableBarrierSet.hpp" 36 #include "interpreter/interpreter.hpp" 37 #include "compiler/disassembler.hpp" 38 #include "memory/resourceArea.hpp" 39 #include "memory/universe.hpp" 40 #include "nativeInst_aarch64.hpp" 41 #include "oops/accessDecorators.hpp" 42 #include "oops/compressedOops.inline.hpp" 43 #include "oops/klass.inline.hpp" 44 #include "runtime/biasedLocking.hpp" 45 #include "runtime/icache.hpp" 46 #include "runtime/interfaceSupport.inline.hpp" 47 #include "runtime/jniHandles.inline.hpp" 48 #include "runtime/sharedRuntime.hpp" 49 #include "runtime/thread.hpp" 50 #include "utilities/powerOfTwo.hpp" 51 #ifdef COMPILER1 52 #include "c1/c1_LIRAssembler.hpp" 53 #endif 54 #ifdef COMPILER2 55 #include "oops/oop.hpp" 56 #include "opto/compile.hpp" 57 #include "opto/node.hpp" 58 #include "opto/output.hpp" 59 #endif 60 61 #ifdef PRODUCT 62 #define BLOCK_COMMENT(str) /* nothing */ 63 #else 64 #define BLOCK_COMMENT(str) block_comment(str) 65 #endif 66 #define STOP(str) stop(str); 67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 68 69 // Patch any kind of instruction; there may be several instructions. 70 // Return the total length (in bytes) of the instructions. 71 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 72 int instructions = 1; 73 assert((uint64_t)target < ((uint64_t)1 << 48), "48-bit overflow in address constant"); 74 int64_t offset = (target - branch) >> 2; 75 unsigned insn = *(unsigned*)branch; 76 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 77 // Load register (literal) 78 Instruction_aarch64::spatch(branch, 23, 5, offset); 79 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 80 // Unconditional branch (immediate) 81 Instruction_aarch64::spatch(branch, 25, 0, offset); 82 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 83 // Conditional branch (immediate) 84 Instruction_aarch64::spatch(branch, 23, 5, offset); 85 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 86 // Compare & branch (immediate) 87 Instruction_aarch64::spatch(branch, 23, 5, offset); 88 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 89 // Test & branch (immediate) 90 Instruction_aarch64::spatch(branch, 18, 5, offset); 91 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 92 // PC-rel. addressing 93 offset = target-branch; 94 int shift = Instruction_aarch64::extract(insn, 31, 31); 95 if (shift) { 96 uint64_t dest = (uint64_t)target; 97 uint64_t pc_page = (uint64_t)branch >> 12; 98 uint64_t adr_page = (uint64_t)target >> 12; 99 unsigned offset_lo = dest & 0xfff; 100 offset = adr_page - pc_page; 101 102 // We handle 4 types of PC relative addressing 103 // 1 - adrp Rx, target_page 104 // ldr/str Ry, [Rx, #offset_in_page] 105 // 2 - adrp Rx, target_page 106 // add Ry, Rx, #offset_in_page 107 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 108 // movk Rx, #imm16<<32 109 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 110 // In the first 3 cases we must check that Rx is the same in the adrp and the 111 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 112 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 113 // to be followed by a random unrelated ldr/str, add or movk instruction. 114 // 115 unsigned insn2 = ((unsigned*)branch)[1]; 116 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 117 Instruction_aarch64::extract(insn, 4, 0) == 118 Instruction_aarch64::extract(insn2, 9, 5)) { 119 // Load/store register (unsigned immediate) 120 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 121 Instruction_aarch64::patch(branch + sizeof (unsigned), 122 21, 10, offset_lo >> size); 123 guarantee(((dest >> size) << size) == dest, "misaligned target"); 124 instructions = 2; 125 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 126 Instruction_aarch64::extract(insn, 4, 0) == 127 Instruction_aarch64::extract(insn2, 4, 0)) { 128 // add (immediate) 129 Instruction_aarch64::patch(branch + sizeof (unsigned), 130 21, 10, offset_lo); 131 instructions = 2; 132 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 133 Instruction_aarch64::extract(insn, 4, 0) == 134 Instruction_aarch64::extract(insn2, 4, 0)) { 135 // movk #imm16<<32 136 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 137 int64_t dest = ((int64_t)target & 0xffffffffL) | ((int64_t)branch & 0xffff00000000L); 138 int64_t pc_page = (int64_t)branch >> 12; 139 int64_t adr_page = (int64_t)dest >> 12; 140 offset = adr_page - pc_page; 141 instructions = 2; 142 } 143 } 144 int offset_lo = offset & 3; 145 offset >>= 2; 146 Instruction_aarch64::spatch(branch, 23, 5, offset); 147 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 148 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 149 uint64_t dest = (uint64_t)target; 150 // Move wide constant 151 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 152 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 153 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 154 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 155 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 156 assert(target_addr_for_insn(branch) == target, "should be"); 157 instructions = 3; 158 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 159 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 160 // nothing to do 161 assert(target == 0, "did not expect to relocate target for polling page load"); 162 } else { 163 ShouldNotReachHere(); 164 } 165 return instructions * NativeInstruction::instruction_size; 166 } 167 168 int MacroAssembler::patch_oop(address insn_addr, address o) { 169 int instructions; 170 unsigned insn = *(unsigned*)insn_addr; 171 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 172 173 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 174 // narrow OOPs by setting the upper 16 bits in the first 175 // instruction. 176 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 177 // Move narrow OOP 178 narrowOop n = CompressedOops::encode((oop)o); 179 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 180 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 181 instructions = 2; 182 } else { 183 // Move wide OOP 184 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 185 uintptr_t dest = (uintptr_t)o; 186 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 187 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 188 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 189 instructions = 3; 190 } 191 return instructions * NativeInstruction::instruction_size; 192 } 193 194 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) { 195 // Metatdata pointers are either narrow (32 bits) or wide (48 bits). 196 // We encode narrow ones by setting the upper 16 bits in the first 197 // instruction. 198 NativeInstruction *insn = nativeInstruction_at(insn_addr); 199 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 && 200 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 201 202 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 203 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 204 return 2 * NativeInstruction::instruction_size; 205 } 206 207 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 208 int64_t offset = 0; 209 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 210 // Load register (literal) 211 offset = Instruction_aarch64::sextract(insn, 23, 5); 212 return address(((uint64_t)insn_addr + (offset << 2))); 213 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 214 // Unconditional branch (immediate) 215 offset = Instruction_aarch64::sextract(insn, 25, 0); 216 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 217 // Conditional branch (immediate) 218 offset = Instruction_aarch64::sextract(insn, 23, 5); 219 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 220 // Compare & branch (immediate) 221 offset = Instruction_aarch64::sextract(insn, 23, 5); 222 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 223 // Test & branch (immediate) 224 offset = Instruction_aarch64::sextract(insn, 18, 5); 225 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 226 // PC-rel. addressing 227 offset = Instruction_aarch64::extract(insn, 30, 29); 228 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 229 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 230 if (shift) { 231 offset <<= shift; 232 uint64_t target_page = ((uint64_t)insn_addr) + offset; 233 target_page &= ((uint64_t)-1) << shift; 234 // Return the target address for the following sequences 235 // 1 - adrp Rx, target_page 236 // ldr/str Ry, [Rx, #offset_in_page] 237 // 2 - adrp Rx, target_page 238 // add Ry, Rx, #offset_in_page 239 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 240 // movk Rx, #imm12<<32 241 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 242 // 243 // In the first two cases we check that the register is the same and 244 // return the target_page + the offset within the page. 245 // Otherwise we assume it is a page aligned relocation and return 246 // the target page only. 247 // 248 unsigned insn2 = ((unsigned*)insn_addr)[1]; 249 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 250 Instruction_aarch64::extract(insn, 4, 0) == 251 Instruction_aarch64::extract(insn2, 9, 5)) { 252 // Load/store register (unsigned immediate) 253 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 254 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 255 return address(target_page + (byte_offset << size)); 256 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 257 Instruction_aarch64::extract(insn, 4, 0) == 258 Instruction_aarch64::extract(insn2, 4, 0)) { 259 // add (immediate) 260 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 261 return address(target_page + byte_offset); 262 } else { 263 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 264 Instruction_aarch64::extract(insn, 4, 0) == 265 Instruction_aarch64::extract(insn2, 4, 0)) { 266 target_page = (target_page & 0xffffffff) | 267 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 268 } 269 return (address)target_page; 270 } 271 } else { 272 ShouldNotReachHere(); 273 } 274 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 275 uint32_t *insns = (uint32_t *)insn_addr; 276 // Move wide constant: movz, movk, movk. See movptr(). 277 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 278 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 279 return address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 280 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 281 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 282 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 283 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 284 return 0; 285 } else { 286 ShouldNotReachHere(); 287 } 288 return address(((uint64_t)insn_addr + (offset << 2))); 289 } 290 291 void MacroAssembler::safepoint_poll(Label& slow_path) { 292 ldr(rscratch1, Address(rthread, Thread::polling_page_offset())); 293 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); 294 } 295 296 // Just like safepoint_poll, but use an acquiring load for thread- 297 // local polling. 298 // 299 // We need an acquire here to ensure that any subsequent load of the 300 // global SafepointSynchronize::_state flag is ordered after this load 301 // of the local Thread::_polling page. We don't want this poll to 302 // return false (i.e. not safepointing) and a later poll of the global 303 // SafepointSynchronize::_state spuriously to return true. 304 // 305 // This is to avoid a race when we're in a native->Java transition 306 // racing the code which wakes up from a safepoint. 307 // 308 void MacroAssembler::safepoint_poll_acquire(Label& slow_path) { 309 lea(rscratch1, Address(rthread, Thread::polling_page_offset())); 310 ldar(rscratch1, rscratch1); 311 tbnz(rscratch1, exact_log2(SafepointMechanism::poll_bit()), slow_path); 312 } 313 314 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 315 // we must set sp to zero to clear frame 316 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 317 318 // must clear fp, so that compiled frames are not confused; it is 319 // possible that we need it only for debugging 320 if (clear_fp) { 321 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 322 } 323 324 // Always clear the pc because it could have been set by make_walkable() 325 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 326 } 327 328 // Calls to C land 329 // 330 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 331 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 332 // has to be reset to 0. This is required to allow proper stack traversal. 333 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 334 Register last_java_fp, 335 Register last_java_pc, 336 Register scratch) { 337 338 if (last_java_pc->is_valid()) { 339 str(last_java_pc, Address(rthread, 340 JavaThread::frame_anchor_offset() 341 + JavaFrameAnchor::last_Java_pc_offset())); 342 } 343 344 // determine last_java_sp register 345 if (last_java_sp == sp) { 346 mov(scratch, sp); 347 last_java_sp = scratch; 348 } else if (!last_java_sp->is_valid()) { 349 last_java_sp = esp; 350 } 351 352 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 353 354 // last_java_fp is optional 355 if (last_java_fp->is_valid()) { 356 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 357 } 358 } 359 360 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 361 Register last_java_fp, 362 address last_java_pc, 363 Register scratch) { 364 assert(last_java_pc != NULL, "must provide a valid PC"); 365 366 adr(scratch, last_java_pc); 367 str(scratch, Address(rthread, 368 JavaThread::frame_anchor_offset() 369 + JavaFrameAnchor::last_Java_pc_offset())); 370 371 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 372 } 373 374 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 375 Register last_java_fp, 376 Label &L, 377 Register scratch) { 378 if (L.is_bound()) { 379 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 380 } else { 381 InstructionMark im(this); 382 L.add_patch_at(code(), locator()); 383 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch); 384 } 385 } 386 387 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 388 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 389 assert(CodeCache::find_blob(entry.target()) != NULL, 390 "destination of far call not found in code cache"); 391 if (far_branches()) { 392 uint64_t offset; 393 // We can use ADRP here because we know that the total size of 394 // the code cache cannot exceed 2Gb. 395 adrp(tmp, entry, offset); 396 add(tmp, tmp, offset); 397 if (cbuf) cbuf->set_insts_mark(); 398 blr(tmp); 399 } else { 400 if (cbuf) cbuf->set_insts_mark(); 401 bl(entry); 402 } 403 } 404 405 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 406 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 407 assert(CodeCache::find_blob(entry.target()) != NULL, 408 "destination of far call not found in code cache"); 409 if (far_branches()) { 410 uint64_t offset; 411 // We can use ADRP here because we know that the total size of 412 // the code cache cannot exceed 2Gb. 413 adrp(tmp, entry, offset); 414 add(tmp, tmp, offset); 415 if (cbuf) cbuf->set_insts_mark(); 416 br(tmp); 417 } else { 418 if (cbuf) cbuf->set_insts_mark(); 419 b(entry); 420 } 421 } 422 423 void MacroAssembler::reserved_stack_check() { 424 // testing if reserved zone needs to be enabled 425 Label no_reserved_zone_enabling; 426 427 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); 428 cmp(sp, rscratch1); 429 br(Assembler::LO, no_reserved_zone_enabling); 430 431 enter(); // LR and FP are live. 432 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)); 433 mov(c_rarg0, rthread); 434 blr(rscratch1); 435 leave(); 436 437 // We have already removed our own frame. 438 // throw_delayed_StackOverflowError will think that it's been 439 // called by our caller. 440 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 441 br(rscratch1); 442 should_not_reach_here(); 443 444 bind(no_reserved_zone_enabling); 445 } 446 447 int MacroAssembler::biased_locking_enter(Register lock_reg, 448 Register obj_reg, 449 Register swap_reg, 450 Register tmp_reg, 451 bool swap_reg_contains_mark, 452 Label& done, 453 Label* slow_case, 454 BiasedLockingCounters* counters) { 455 assert(UseBiasedLocking, "why call this otherwise?"); 456 assert_different_registers(lock_reg, obj_reg, swap_reg); 457 458 if (PrintBiasedLockingStatistics && counters == NULL) 459 counters = BiasedLocking::counters(); 460 461 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 462 assert(markWord::age_shift == markWord::lock_bits + markWord::biased_lock_bits, "biased locking makes assumptions about bit layout"); 463 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 464 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 465 Address saved_mark_addr(lock_reg, 0); 466 467 // Biased locking 468 // See whether the lock is currently biased toward our thread and 469 // whether the epoch is still valid 470 // Note that the runtime guarantees sufficient alignment of JavaThread 471 // pointers to allow age to be placed into low bits 472 // First check to see whether biasing is even enabled for this object 473 Label cas_label; 474 int null_check_offset = -1; 475 if (!swap_reg_contains_mark) { 476 null_check_offset = offset(); 477 ldr(swap_reg, mark_addr); 478 } 479 andr(tmp_reg, swap_reg, markWord::biased_lock_mask_in_place); 480 cmp(tmp_reg, (u1)markWord::biased_lock_pattern); 481 br(Assembler::NE, cas_label); 482 // The bias pattern is present in the object's header. Need to check 483 // whether the bias owner and the epoch are both still current. 484 load_prototype_header(tmp_reg, obj_reg); 485 orr(tmp_reg, tmp_reg, rthread); 486 eor(tmp_reg, swap_reg, tmp_reg); 487 andr(tmp_reg, tmp_reg, ~((int) markWord::age_mask_in_place)); 488 if (counters != NULL) { 489 Label around; 490 cbnz(tmp_reg, around); 491 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 492 b(done); 493 bind(around); 494 } else { 495 cbz(tmp_reg, done); 496 } 497 498 Label try_revoke_bias; 499 Label try_rebias; 500 501 // At this point we know that the header has the bias pattern and 502 // that we are not the bias owner in the current epoch. We need to 503 // figure out more details about the state of the header in order to 504 // know what operations can be legally performed on the object's 505 // header. 506 507 // If the low three bits in the xor result aren't clear, that means 508 // the prototype header is no longer biased and we have to revoke 509 // the bias on this object. 510 andr(rscratch1, tmp_reg, markWord::biased_lock_mask_in_place); 511 cbnz(rscratch1, try_revoke_bias); 512 513 // Biasing is still enabled for this data type. See whether the 514 // epoch of the current bias is still valid, meaning that the epoch 515 // bits of the mark word are equal to the epoch bits of the 516 // prototype header. (Note that the prototype header's epoch bits 517 // only change at a safepoint.) If not, attempt to rebias the object 518 // toward the current thread. Note that we must be absolutely sure 519 // that the current epoch is invalid in order to do this because 520 // otherwise the manipulations it performs on the mark word are 521 // illegal. 522 andr(rscratch1, tmp_reg, markWord::epoch_mask_in_place); 523 cbnz(rscratch1, try_rebias); 524 525 // The epoch of the current bias is still valid but we know nothing 526 // about the owner; it might be set or it might be clear. Try to 527 // acquire the bias of the object using an atomic operation. If this 528 // fails we will go in to the runtime to revoke the object's bias. 529 // Note that we first construct the presumed unbiased header so we 530 // don't accidentally blow away another thread's valid bias. 531 { 532 Label here; 533 mov(rscratch1, markWord::biased_lock_mask_in_place | markWord::age_mask_in_place | markWord::epoch_mask_in_place); 534 andr(swap_reg, swap_reg, rscratch1); 535 orr(tmp_reg, swap_reg, rthread); 536 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 537 // If the biasing toward our thread failed, this means that 538 // another thread succeeded in biasing it toward itself and we 539 // need to revoke that bias. The revocation will occur in the 540 // interpreter runtime in the slow case. 541 bind(here); 542 if (counters != NULL) { 543 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 544 tmp_reg, rscratch1, rscratch2); 545 } 546 } 547 b(done); 548 549 bind(try_rebias); 550 // At this point we know the epoch has expired, meaning that the 551 // current "bias owner", if any, is actually invalid. Under these 552 // circumstances _only_, we are allowed to use the current header's 553 // value as the comparison value when doing the cas to acquire the 554 // bias in the current epoch. In other words, we allow transfer of 555 // the bias from one thread to another directly in this situation. 556 // 557 // FIXME: due to a lack of registers we currently blow away the age 558 // bits in this situation. Should attempt to preserve them. 559 { 560 Label here; 561 load_prototype_header(tmp_reg, obj_reg); 562 orr(tmp_reg, rthread, tmp_reg); 563 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 564 // If the biasing toward our thread failed, then another thread 565 // succeeded in biasing it toward itself and we need to revoke that 566 // bias. The revocation will occur in the runtime in the slow case. 567 bind(here); 568 if (counters != NULL) { 569 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 570 tmp_reg, rscratch1, rscratch2); 571 } 572 } 573 b(done); 574 575 bind(try_revoke_bias); 576 // The prototype mark in the klass doesn't have the bias bit set any 577 // more, indicating that objects of this data type are not supposed 578 // to be biased any more. We are going to try to reset the mark of 579 // this object to the prototype value and fall through to the 580 // CAS-based locking scheme. Note that if our CAS fails, it means 581 // that another thread raced us for the privilege of revoking the 582 // bias of this particular object, so it's okay to continue in the 583 // normal locking code. 584 // 585 // FIXME: due to a lack of registers we currently blow away the age 586 // bits in this situation. Should attempt to preserve them. 587 { 588 Label here, nope; 589 load_prototype_header(tmp_reg, obj_reg); 590 cmpxchg_obj_header(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 591 bind(here); 592 593 // Fall through to the normal CAS-based lock, because no matter what 594 // the result of the above CAS, some thread must have succeeded in 595 // removing the bias bit from the object's header. 596 if (counters != NULL) { 597 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 598 rscratch1, rscratch2); 599 } 600 bind(nope); 601 } 602 603 bind(cas_label); 604 605 return null_check_offset; 606 } 607 608 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 609 assert(UseBiasedLocking, "why call this otherwise?"); 610 611 // Check for biased locking unlock case, which is a no-op 612 // Note: we do not have to check the thread ID for two reasons. 613 // First, the interpreter checks for IllegalMonitorStateException at 614 // a higher level. Second, if the bias was revoked while we held the 615 // lock, the object could not be rebiased toward another thread, so 616 // the bias bit would be clear. 617 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 618 andr(temp_reg, temp_reg, markWord::biased_lock_mask_in_place); 619 cmp(temp_reg, (u1)markWord::biased_lock_pattern); 620 br(Assembler::EQ, done); 621 } 622 623 static void pass_arg0(MacroAssembler* masm, Register arg) { 624 if (c_rarg0 != arg ) { 625 masm->mov(c_rarg0, arg); 626 } 627 } 628 629 static void pass_arg1(MacroAssembler* masm, Register arg) { 630 if (c_rarg1 != arg ) { 631 masm->mov(c_rarg1, arg); 632 } 633 } 634 635 static void pass_arg2(MacroAssembler* masm, Register arg) { 636 if (c_rarg2 != arg ) { 637 masm->mov(c_rarg2, arg); 638 } 639 } 640 641 static void pass_arg3(MacroAssembler* masm, Register arg) { 642 if (c_rarg3 != arg ) { 643 masm->mov(c_rarg3, arg); 644 } 645 } 646 647 void MacroAssembler::call_VM_base(Register oop_result, 648 Register java_thread, 649 Register last_java_sp, 650 address entry_point, 651 int number_of_arguments, 652 bool check_exceptions) { 653 // determine java_thread register 654 if (!java_thread->is_valid()) { 655 java_thread = rthread; 656 } 657 658 // determine last_java_sp register 659 if (!last_java_sp->is_valid()) { 660 last_java_sp = esp; 661 } 662 663 // debugging support 664 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 665 assert(java_thread == rthread, "unexpected register"); 666 #ifdef ASSERT 667 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 668 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 669 #endif // ASSERT 670 671 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 672 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 673 674 // push java thread (becomes first argument of C function) 675 676 mov(c_rarg0, java_thread); 677 678 // set last Java frame before call 679 assert(last_java_sp != rfp, "can't use rfp"); 680 681 Label l; 682 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 683 684 // do the call, remove parameters 685 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 686 687 // reset last Java frame 688 // Only interpreter should have to clear fp 689 reset_last_Java_frame(true); 690 691 // C++ interp handles this in the interpreter 692 check_and_handle_popframe(java_thread); 693 check_and_handle_earlyret(java_thread); 694 695 if (check_exceptions) { 696 // check for pending exceptions (java_thread is set upon return) 697 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 698 Label ok; 699 cbz(rscratch1, ok); 700 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 701 br(rscratch1); 702 bind(ok); 703 } 704 705 // get oop result if there is one and reset the value in the thread 706 if (oop_result->is_valid()) { 707 get_vm_result(oop_result, java_thread); 708 } 709 } 710 711 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 712 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 713 } 714 715 // Maybe emit a call via a trampoline. If the code cache is small 716 // trampolines won't be emitted. 717 718 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 719 assert(JavaThread::current()->is_Compiler_thread(), "just checking"); 720 assert(entry.rspec().type() == relocInfo::runtime_call_type 721 || entry.rspec().type() == relocInfo::opt_virtual_call_type 722 || entry.rspec().type() == relocInfo::static_call_type 723 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 724 725 // We need a trampoline if branches are far. 726 if (far_branches()) { 727 bool in_scratch_emit_size = false; 728 #ifdef COMPILER2 729 // We don't want to emit a trampoline if C2 is generating dummy 730 // code during its branch shortening phase. 731 CompileTask* task = ciEnv::current()->task(); 732 in_scratch_emit_size = 733 (task != NULL && is_c2_compile(task->comp_level()) && 734 Compile::current()->output()->in_scratch_emit_size()); 735 #endif 736 if (!in_scratch_emit_size) { 737 address stub = emit_trampoline_stub(offset(), entry.target()); 738 if (stub == NULL) { 739 return NULL; // CodeCache is full 740 } 741 } 742 } 743 744 if (cbuf) cbuf->set_insts_mark(); 745 relocate(entry.rspec()); 746 if (!far_branches()) { 747 bl(entry.target()); 748 } else { 749 bl(pc()); 750 } 751 // just need to return a non-null address 752 return pc(); 753 } 754 755 756 // Emit a trampoline stub for a call to a target which is too far away. 757 // 758 // code sequences: 759 // 760 // call-site: 761 // branch-and-link to <destination> or <trampoline stub> 762 // 763 // Related trampoline stub for this call site in the stub section: 764 // load the call target from the constant pool 765 // branch (LR still points to the call site above) 766 767 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 768 address dest) { 769 // Max stub size: alignment nop, TrampolineStub. 770 address stub = start_a_stub(NativeInstruction::instruction_size 771 + NativeCallTrampolineStub::instruction_size); 772 if (stub == NULL) { 773 return NULL; // CodeBuffer::expand failed 774 } 775 776 // Create a trampoline stub relocation which relates this trampoline stub 777 // with the call instruction at insts_call_instruction_offset in the 778 // instructions code-section. 779 align(wordSize); 780 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 781 + insts_call_instruction_offset)); 782 const int stub_start_offset = offset(); 783 784 // Now, create the trampoline stub's code: 785 // - load the call 786 // - call 787 Label target; 788 ldr(rscratch1, target); 789 br(rscratch1); 790 bind(target); 791 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 792 "should be"); 793 emit_int64((int64_t)dest); 794 795 const address stub_start_addr = addr_at(stub_start_offset); 796 797 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 798 799 end_a_stub(); 800 return stub_start_addr; 801 } 802 803 void MacroAssembler::emit_static_call_stub() { 804 // CompiledDirectStaticCall::set_to_interpreted knows the 805 // exact layout of this stub. 806 807 isb(); 808 mov_metadata(rmethod, (Metadata*)NULL); 809 810 // Jump to the entry point of the i2c stub. 811 movptr(rscratch1, 0); 812 br(rscratch1); 813 } 814 815 void MacroAssembler::c2bool(Register x) { 816 // implements x == 0 ? 0 : 1 817 // note: must only look at least-significant byte of x 818 // since C-style booleans are stored in one byte 819 // only! (was bug) 820 tst(x, 0xff); 821 cset(x, Assembler::NE); 822 } 823 824 address MacroAssembler::ic_call(address entry, jint method_index) { 825 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 826 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 827 // uint64_t offset; 828 // ldr_constant(rscratch2, const_ptr); 829 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 830 return trampoline_call(Address(entry, rh)); 831 } 832 833 // Implementation of call_VM versions 834 835 void MacroAssembler::call_VM(Register oop_result, 836 address entry_point, 837 bool check_exceptions) { 838 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 839 } 840 841 void MacroAssembler::call_VM(Register oop_result, 842 address entry_point, 843 Register arg_1, 844 bool check_exceptions) { 845 pass_arg1(this, arg_1); 846 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 847 } 848 849 void MacroAssembler::call_VM(Register oop_result, 850 address entry_point, 851 Register arg_1, 852 Register arg_2, 853 bool check_exceptions) { 854 assert(arg_1 != c_rarg2, "smashed arg"); 855 pass_arg2(this, arg_2); 856 pass_arg1(this, arg_1); 857 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 858 } 859 860 void MacroAssembler::call_VM(Register oop_result, 861 address entry_point, 862 Register arg_1, 863 Register arg_2, 864 Register arg_3, 865 bool check_exceptions) { 866 assert(arg_1 != c_rarg3, "smashed arg"); 867 assert(arg_2 != c_rarg3, "smashed arg"); 868 pass_arg3(this, arg_3); 869 870 assert(arg_1 != c_rarg2, "smashed arg"); 871 pass_arg2(this, arg_2); 872 873 pass_arg1(this, arg_1); 874 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 875 } 876 877 void MacroAssembler::call_VM(Register oop_result, 878 Register last_java_sp, 879 address entry_point, 880 int number_of_arguments, 881 bool check_exceptions) { 882 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 883 } 884 885 void MacroAssembler::call_VM(Register oop_result, 886 Register last_java_sp, 887 address entry_point, 888 Register arg_1, 889 bool check_exceptions) { 890 pass_arg1(this, arg_1); 891 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 892 } 893 894 void MacroAssembler::call_VM(Register oop_result, 895 Register last_java_sp, 896 address entry_point, 897 Register arg_1, 898 Register arg_2, 899 bool check_exceptions) { 900 901 assert(arg_1 != c_rarg2, "smashed arg"); 902 pass_arg2(this, arg_2); 903 pass_arg1(this, arg_1); 904 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 905 } 906 907 void MacroAssembler::call_VM(Register oop_result, 908 Register last_java_sp, 909 address entry_point, 910 Register arg_1, 911 Register arg_2, 912 Register arg_3, 913 bool check_exceptions) { 914 assert(arg_1 != c_rarg3, "smashed arg"); 915 assert(arg_2 != c_rarg3, "smashed arg"); 916 pass_arg3(this, arg_3); 917 assert(arg_1 != c_rarg2, "smashed arg"); 918 pass_arg2(this, arg_2); 919 pass_arg1(this, arg_1); 920 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 921 } 922 923 924 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 925 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 926 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 927 verify_oop(oop_result, "broken oop in call_VM_base"); 928 } 929 930 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 931 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 932 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 933 } 934 935 void MacroAssembler::align(int modulus) { 936 while (offset() % modulus != 0) nop(); 937 } 938 939 // these are no-ops overridden by InterpreterMacroAssembler 940 941 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 942 943 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 944 945 946 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 947 Register tmp, 948 int offset) { 949 intptr_t value = *delayed_value_addr; 950 if (value != 0) 951 return RegisterOrConstant(value + offset); 952 953 // load indirectly to solve generation ordering problem 954 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 955 956 if (offset != 0) 957 add(tmp, tmp, offset); 958 959 return RegisterOrConstant(tmp); 960 } 961 962 // Look up the method for a megamorphic invokeinterface call. 963 // The target method is determined by <intf_klass, itable_index>. 964 // The receiver klass is in recv_klass. 965 // On success, the result will be in method_result, and execution falls through. 966 // On failure, execution transfers to the given label. 967 void MacroAssembler::lookup_interface_method(Register recv_klass, 968 Register intf_klass, 969 RegisterOrConstant itable_index, 970 Register method_result, 971 Register scan_temp, 972 Label& L_no_such_interface, 973 bool return_method) { 974 assert_different_registers(recv_klass, intf_klass, scan_temp); 975 assert_different_registers(method_result, intf_klass, scan_temp); 976 assert(recv_klass != method_result || !return_method, 977 "recv_klass can be destroyed when method isn't needed"); 978 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 979 "caller must use same register for non-constant itable index as for method"); 980 981 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 982 int vtable_base = in_bytes(Klass::vtable_start_offset()); 983 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 984 int scan_step = itableOffsetEntry::size() * wordSize; 985 int vte_size = vtableEntry::size_in_bytes(); 986 assert(vte_size == wordSize, "else adjust times_vte_scale"); 987 988 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 989 990 // %%% Could store the aligned, prescaled offset in the klassoop. 991 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 992 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 993 add(scan_temp, scan_temp, vtable_base); 994 995 if (return_method) { 996 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 997 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 998 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 999 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 1000 if (itentry_off) 1001 add(recv_klass, recv_klass, itentry_off); 1002 } 1003 1004 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 1005 // if (scan->interface() == intf) { 1006 // result = (klass + scan->offset() + itable_index); 1007 // } 1008 // } 1009 Label search, found_method; 1010 1011 for (int peel = 1; peel >= 0; peel--) { 1012 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 1013 cmp(intf_klass, method_result); 1014 1015 if (peel) { 1016 br(Assembler::EQ, found_method); 1017 } else { 1018 br(Assembler::NE, search); 1019 // (invert the test to fall through to found_method...) 1020 } 1021 1022 if (!peel) break; 1023 1024 bind(search); 1025 1026 // Check that the previous entry is non-null. A null entry means that 1027 // the receiver class doesn't implement the interface, and wasn't the 1028 // same as when the caller was compiled. 1029 cbz(method_result, L_no_such_interface); 1030 add(scan_temp, scan_temp, scan_step); 1031 } 1032 1033 bind(found_method); 1034 1035 // Got a hit. 1036 if (return_method) { 1037 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 1038 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0))); 1039 } 1040 } 1041 1042 // virtual method calling 1043 void MacroAssembler::lookup_virtual_method(Register recv_klass, 1044 RegisterOrConstant vtable_index, 1045 Register method_result) { 1046 const int base = in_bytes(Klass::vtable_start_offset()); 1047 assert(vtableEntry::size() * wordSize == 8, 1048 "adjust the scaling in the code below"); 1049 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 1050 1051 if (vtable_index.is_register()) { 1052 lea(method_result, Address(recv_klass, 1053 vtable_index.as_register(), 1054 Address::lsl(LogBytesPerWord))); 1055 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 1056 } else { 1057 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 1058 ldr(method_result, 1059 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0)); 1060 } 1061 } 1062 1063 void MacroAssembler::check_klass_subtype(Register sub_klass, 1064 Register super_klass, 1065 Register temp_reg, 1066 Label& L_success) { 1067 Label L_failure; 1068 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 1069 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 1070 bind(L_failure); 1071 } 1072 1073 1074 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 1075 Register super_klass, 1076 Register temp_reg, 1077 Label* L_success, 1078 Label* L_failure, 1079 Label* L_slow_path, 1080 RegisterOrConstant super_check_offset) { 1081 assert_different_registers(sub_klass, super_klass, temp_reg); 1082 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1083 if (super_check_offset.is_register()) { 1084 assert_different_registers(sub_klass, super_klass, 1085 super_check_offset.as_register()); 1086 } else if (must_load_sco) { 1087 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1088 } 1089 1090 Label L_fallthrough; 1091 int label_nulls = 0; 1092 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1093 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1094 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1095 assert(label_nulls <= 1, "at most one NULL in the batch"); 1096 1097 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1098 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1099 Address super_check_offset_addr(super_klass, sco_offset); 1100 1101 // Hacked jmp, which may only be used just before L_fallthrough. 1102 #define final_jmp(label) \ 1103 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1104 else b(label) /*omit semi*/ 1105 1106 // If the pointers are equal, we are done (e.g., String[] elements). 1107 // This self-check enables sharing of secondary supertype arrays among 1108 // non-primary types such as array-of-interface. Otherwise, each such 1109 // type would need its own customized SSA. 1110 // We move this check to the front of the fast path because many 1111 // type checks are in fact trivially successful in this manner, 1112 // so we get a nicely predicted branch right at the start of the check. 1113 cmp(sub_klass, super_klass); 1114 br(Assembler::EQ, *L_success); 1115 1116 // Check the supertype display: 1117 if (must_load_sco) { 1118 ldrw(temp_reg, super_check_offset_addr); 1119 super_check_offset = RegisterOrConstant(temp_reg); 1120 } 1121 Address super_check_addr(sub_klass, super_check_offset); 1122 ldr(rscratch1, super_check_addr); 1123 cmp(super_klass, rscratch1); // load displayed supertype 1124 1125 // This check has worked decisively for primary supers. 1126 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1127 // (Secondary supers are interfaces and very deeply nested subtypes.) 1128 // This works in the same check above because of a tricky aliasing 1129 // between the super_cache and the primary super display elements. 1130 // (The 'super_check_addr' can address either, as the case requires.) 1131 // Note that the cache is updated below if it does not help us find 1132 // what we need immediately. 1133 // So if it was a primary super, we can just fail immediately. 1134 // Otherwise, it's the slow path for us (no success at this point). 1135 1136 if (super_check_offset.is_register()) { 1137 br(Assembler::EQ, *L_success); 1138 subs(zr, super_check_offset.as_register(), sc_offset); 1139 if (L_failure == &L_fallthrough) { 1140 br(Assembler::EQ, *L_slow_path); 1141 } else { 1142 br(Assembler::NE, *L_failure); 1143 final_jmp(*L_slow_path); 1144 } 1145 } else if (super_check_offset.as_constant() == sc_offset) { 1146 // Need a slow path; fast failure is impossible. 1147 if (L_slow_path == &L_fallthrough) { 1148 br(Assembler::EQ, *L_success); 1149 } else { 1150 br(Assembler::NE, *L_slow_path); 1151 final_jmp(*L_success); 1152 } 1153 } else { 1154 // No slow path; it's a fast decision. 1155 if (L_failure == &L_fallthrough) { 1156 br(Assembler::EQ, *L_success); 1157 } else { 1158 br(Assembler::NE, *L_failure); 1159 final_jmp(*L_success); 1160 } 1161 } 1162 1163 bind(L_fallthrough); 1164 1165 #undef final_jmp 1166 } 1167 1168 // These two are taken from x86, but they look generally useful 1169 1170 // scans count pointer sized words at [addr] for occurence of value, 1171 // generic 1172 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1173 Register scratch) { 1174 Label Lloop, Lexit; 1175 cbz(count, Lexit); 1176 bind(Lloop); 1177 ldr(scratch, post(addr, wordSize)); 1178 cmp(value, scratch); 1179 br(EQ, Lexit); 1180 sub(count, count, 1); 1181 cbnz(count, Lloop); 1182 bind(Lexit); 1183 } 1184 1185 // scans count 4 byte words at [addr] for occurence of value, 1186 // generic 1187 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1188 Register scratch) { 1189 Label Lloop, Lexit; 1190 cbz(count, Lexit); 1191 bind(Lloop); 1192 ldrw(scratch, post(addr, wordSize)); 1193 cmpw(value, scratch); 1194 br(EQ, Lexit); 1195 sub(count, count, 1); 1196 cbnz(count, Lloop); 1197 bind(Lexit); 1198 } 1199 1200 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1201 Register super_klass, 1202 Register temp_reg, 1203 Register temp2_reg, 1204 Label* L_success, 1205 Label* L_failure, 1206 bool set_cond_codes) { 1207 assert_different_registers(sub_klass, super_klass, temp_reg); 1208 if (temp2_reg != noreg) 1209 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1210 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1211 1212 Label L_fallthrough; 1213 int label_nulls = 0; 1214 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1215 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1216 assert(label_nulls <= 1, "at most one NULL in the batch"); 1217 1218 // a couple of useful fields in sub_klass: 1219 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1220 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1221 Address secondary_supers_addr(sub_klass, ss_offset); 1222 Address super_cache_addr( sub_klass, sc_offset); 1223 1224 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1225 1226 // Do a linear scan of the secondary super-klass chain. 1227 // This code is rarely used, so simplicity is a virtue here. 1228 // The repne_scan instruction uses fixed registers, which we must spill. 1229 // Don't worry too much about pre-existing connections with the input regs. 1230 1231 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1232 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1233 1234 RegSet pushed_registers; 1235 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1236 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1237 1238 if (super_klass != r0 || UseCompressedOops) { 1239 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1240 } 1241 1242 push(pushed_registers, sp); 1243 1244 // Get super_klass value into r0 (even if it was in r5 or r2). 1245 if (super_klass != r0) { 1246 mov(r0, super_klass); 1247 } 1248 1249 #ifndef PRODUCT 1250 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1251 Address pst_counter_addr(rscratch2); 1252 ldr(rscratch1, pst_counter_addr); 1253 add(rscratch1, rscratch1, 1); 1254 str(rscratch1, pst_counter_addr); 1255 #endif //PRODUCT 1256 1257 // We will consult the secondary-super array. 1258 ldr(r5, secondary_supers_addr); 1259 // Load the array length. 1260 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1261 // Skip to start of data. 1262 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1263 1264 cmp(sp, zr); // Clear Z flag; SP is never zero 1265 // Scan R2 words at [R5] for an occurrence of R0. 1266 // Set NZ/Z based on last compare. 1267 repne_scan(r5, r0, r2, rscratch1); 1268 1269 // Unspill the temp. registers: 1270 pop(pushed_registers, sp); 1271 1272 br(Assembler::NE, *L_failure); 1273 1274 // Success. Cache the super we found and proceed in triumph. 1275 str(super_klass, super_cache_addr); 1276 1277 if (L_success != &L_fallthrough) { 1278 b(*L_success); 1279 } 1280 1281 #undef IS_A_TEMP 1282 1283 bind(L_fallthrough); 1284 } 1285 1286 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) { 1287 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required"); 1288 assert_different_registers(klass, rthread, scratch); 1289 1290 Label L_fallthrough, L_tmp; 1291 if (L_fast_path == NULL) { 1292 L_fast_path = &L_fallthrough; 1293 } else if (L_slow_path == NULL) { 1294 L_slow_path = &L_fallthrough; 1295 } 1296 // Fast path check: class is fully initialized 1297 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset())); 1298 subs(zr, scratch, InstanceKlass::fully_initialized); 1299 br(Assembler::EQ, *L_fast_path); 1300 1301 // Fast path check: current thread is initializer thread 1302 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset())); 1303 cmp(rthread, scratch); 1304 1305 if (L_slow_path == &L_fallthrough) { 1306 br(Assembler::EQ, *L_fast_path); 1307 bind(*L_slow_path); 1308 } else if (L_fast_path == &L_fallthrough) { 1309 br(Assembler::NE, *L_slow_path); 1310 bind(*L_fast_path); 1311 } else { 1312 Unimplemented(); 1313 } 1314 } 1315 1316 void MacroAssembler::verify_oop(Register reg, const char* s) { 1317 if (!VerifyOops) return; 1318 1319 // Pass register number to verify_oop_subroutine 1320 const char* b = NULL; 1321 { 1322 ResourceMark rm; 1323 stringStream ss; 1324 ss.print("verify_oop: %s: %s", reg->name(), s); 1325 b = code_string(ss.as_string()); 1326 } 1327 BLOCK_COMMENT("verify_oop {"); 1328 1329 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1330 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1331 1332 mov(r0, reg); 1333 movptr(rscratch1, (uintptr_t)(address)b); 1334 1335 // call indirectly to solve generation ordering problem 1336 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1337 ldr(rscratch2, Address(rscratch2)); 1338 blr(rscratch2); 1339 1340 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1341 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1342 1343 BLOCK_COMMENT("} verify_oop"); 1344 } 1345 1346 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1347 if (!VerifyOops) return; 1348 1349 const char* b = NULL; 1350 { 1351 ResourceMark rm; 1352 stringStream ss; 1353 ss.print("verify_oop_addr: %s", s); 1354 b = code_string(ss.as_string()); 1355 } 1356 BLOCK_COMMENT("verify_oop_addr {"); 1357 1358 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1359 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1360 1361 // addr may contain sp so we will have to adjust it based on the 1362 // pushes that we just did. 1363 if (addr.uses(sp)) { 1364 lea(r0, addr); 1365 ldr(r0, Address(r0, 4 * wordSize)); 1366 } else { 1367 ldr(r0, addr); 1368 } 1369 movptr(rscratch1, (uintptr_t)(address)b); 1370 1371 // call indirectly to solve generation ordering problem 1372 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1373 ldr(rscratch2, Address(rscratch2)); 1374 blr(rscratch2); 1375 1376 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1377 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1378 1379 BLOCK_COMMENT("} verify_oop_addr"); 1380 } 1381 1382 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1383 int extra_slot_offset) { 1384 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1385 int stackElementSize = Interpreter::stackElementSize; 1386 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1387 #ifdef ASSERT 1388 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1389 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1390 #endif 1391 if (arg_slot.is_constant()) { 1392 return Address(esp, arg_slot.as_constant() * stackElementSize 1393 + offset); 1394 } else { 1395 add(rscratch1, esp, arg_slot.as_register(), 1396 ext::uxtx, exact_log2(stackElementSize)); 1397 return Address(rscratch1, offset); 1398 } 1399 } 1400 1401 void MacroAssembler::call_VM_leaf_base(address entry_point, 1402 int number_of_arguments, 1403 Label *retaddr) { 1404 Label E, L; 1405 1406 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1407 1408 mov(rscratch1, entry_point); 1409 blr(rscratch1); 1410 if (retaddr) 1411 bind(*retaddr); 1412 1413 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1414 maybe_isb(); 1415 } 1416 1417 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1418 call_VM_leaf_base(entry_point, number_of_arguments); 1419 } 1420 1421 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1422 pass_arg0(this, arg_0); 1423 call_VM_leaf_base(entry_point, 1); 1424 } 1425 1426 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1427 pass_arg0(this, arg_0); 1428 pass_arg1(this, arg_1); 1429 call_VM_leaf_base(entry_point, 2); 1430 } 1431 1432 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1433 Register arg_1, Register arg_2) { 1434 pass_arg0(this, arg_0); 1435 pass_arg1(this, arg_1); 1436 pass_arg2(this, arg_2); 1437 call_VM_leaf_base(entry_point, 3); 1438 } 1439 1440 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1441 pass_arg0(this, arg_0); 1442 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1443 } 1444 1445 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1446 1447 assert(arg_0 != c_rarg1, "smashed arg"); 1448 pass_arg1(this, arg_1); 1449 pass_arg0(this, arg_0); 1450 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1451 } 1452 1453 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1454 assert(arg_0 != c_rarg2, "smashed arg"); 1455 assert(arg_1 != c_rarg2, "smashed arg"); 1456 pass_arg2(this, arg_2); 1457 assert(arg_0 != c_rarg1, "smashed arg"); 1458 pass_arg1(this, arg_1); 1459 pass_arg0(this, arg_0); 1460 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1461 } 1462 1463 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1464 assert(arg_0 != c_rarg3, "smashed arg"); 1465 assert(arg_1 != c_rarg3, "smashed arg"); 1466 assert(arg_2 != c_rarg3, "smashed arg"); 1467 pass_arg3(this, arg_3); 1468 assert(arg_0 != c_rarg2, "smashed arg"); 1469 assert(arg_1 != c_rarg2, "smashed arg"); 1470 pass_arg2(this, arg_2); 1471 assert(arg_0 != c_rarg1, "smashed arg"); 1472 pass_arg1(this, arg_1); 1473 pass_arg0(this, arg_0); 1474 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1475 } 1476 1477 void MacroAssembler::null_check(Register reg, int offset) { 1478 if (needs_explicit_null_check(offset)) { 1479 // provoke OS NULL exception if reg = NULL by 1480 // accessing M[reg] w/o changing any registers 1481 // NOTE: this is plenty to provoke a segv 1482 ldr(zr, Address(reg)); 1483 } else { 1484 // nothing to do, (later) access of M[reg + offset] 1485 // will provoke OS NULL exception if reg = NULL 1486 } 1487 } 1488 1489 // MacroAssembler protected routines needed to implement 1490 // public methods 1491 1492 void MacroAssembler::mov(Register r, Address dest) { 1493 code_section()->relocate(pc(), dest.rspec()); 1494 uint64_t imm64 = (uint64_t)dest.target(); 1495 movptr(r, imm64); 1496 } 1497 1498 // Move a constant pointer into r. In AArch64 mode the virtual 1499 // address space is 48 bits in size, so we only need three 1500 // instructions to create a patchable instruction sequence that can 1501 // reach anywhere. 1502 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1503 #ifndef PRODUCT 1504 { 1505 char buffer[64]; 1506 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, imm64); 1507 block_comment(buffer); 1508 } 1509 #endif 1510 assert(imm64 < (1ull << 48), "48-bit overflow in address constant"); 1511 movz(r, imm64 & 0xffff); 1512 imm64 >>= 16; 1513 movk(r, imm64 & 0xffff, 16); 1514 imm64 >>= 16; 1515 movk(r, imm64 & 0xffff, 32); 1516 } 1517 1518 // Macro to mov replicated immediate to vector register. 1519 // Vd will get the following values for different arrangements in T 1520 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1521 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1522 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1523 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1524 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1525 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1526 // T1D/T2D: invalid 1527 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32) { 1528 assert(T != T1D && T != T2D, "invalid arrangement"); 1529 if (T == T8B || T == T16B) { 1530 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1531 movi(Vd, T, imm32 & 0xff, 0); 1532 return; 1533 } 1534 uint32_t nimm32 = ~imm32; 1535 if (T == T4H || T == T8H) { 1536 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1537 imm32 &= 0xffff; 1538 nimm32 &= 0xffff; 1539 } 1540 uint32_t x = imm32; 1541 int movi_cnt = 0; 1542 int movn_cnt = 0; 1543 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1544 x = nimm32; 1545 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1546 if (movn_cnt < movi_cnt) imm32 = nimm32; 1547 unsigned lsl = 0; 1548 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1549 if (movn_cnt < movi_cnt) 1550 mvni(Vd, T, imm32 & 0xff, lsl); 1551 else 1552 movi(Vd, T, imm32 & 0xff, lsl); 1553 imm32 >>= 8; lsl += 8; 1554 while (imm32) { 1555 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1556 if (movn_cnt < movi_cnt) 1557 bici(Vd, T, imm32 & 0xff, lsl); 1558 else 1559 orri(Vd, T, imm32 & 0xff, lsl); 1560 lsl += 8; imm32 >>= 8; 1561 } 1562 } 1563 1564 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64) 1565 { 1566 #ifndef PRODUCT 1567 { 1568 char buffer[64]; 1569 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, imm64); 1570 block_comment(buffer); 1571 } 1572 #endif 1573 if (operand_valid_for_logical_immediate(false, imm64)) { 1574 orr(dst, zr, imm64); 1575 } else { 1576 // we can use a combination of MOVZ or MOVN with 1577 // MOVK to build up the constant 1578 uint64_t imm_h[4]; 1579 int zero_count = 0; 1580 int neg_count = 0; 1581 int i; 1582 for (i = 0; i < 4; i++) { 1583 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1584 if (imm_h[i] == 0) { 1585 zero_count++; 1586 } else if (imm_h[i] == 0xffffL) { 1587 neg_count++; 1588 } 1589 } 1590 if (zero_count == 4) { 1591 // one MOVZ will do 1592 movz(dst, 0); 1593 } else if (neg_count == 4) { 1594 // one MOVN will do 1595 movn(dst, 0); 1596 } else if (zero_count == 3) { 1597 for (i = 0; i < 4; i++) { 1598 if (imm_h[i] != 0L) { 1599 movz(dst, (uint32_t)imm_h[i], (i << 4)); 1600 break; 1601 } 1602 } 1603 } else if (neg_count == 3) { 1604 // one MOVN will do 1605 for (int i = 0; i < 4; i++) { 1606 if (imm_h[i] != 0xffffL) { 1607 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1608 break; 1609 } 1610 } 1611 } else if (zero_count == 2) { 1612 // one MOVZ and one MOVK will do 1613 for (i = 0; i < 3; i++) { 1614 if (imm_h[i] != 0L) { 1615 movz(dst, (uint32_t)imm_h[i], (i << 4)); 1616 i++; 1617 break; 1618 } 1619 } 1620 for (;i < 4; i++) { 1621 if (imm_h[i] != 0L) { 1622 movk(dst, (uint32_t)imm_h[i], (i << 4)); 1623 } 1624 } 1625 } else if (neg_count == 2) { 1626 // one MOVN and one MOVK will do 1627 for (i = 0; i < 4; i++) { 1628 if (imm_h[i] != 0xffffL) { 1629 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1630 i++; 1631 break; 1632 } 1633 } 1634 for (;i < 4; i++) { 1635 if (imm_h[i] != 0xffffL) { 1636 movk(dst, (uint32_t)imm_h[i], (i << 4)); 1637 } 1638 } 1639 } else if (zero_count == 1) { 1640 // one MOVZ and two MOVKs will do 1641 for (i = 0; i < 4; i++) { 1642 if (imm_h[i] != 0L) { 1643 movz(dst, (uint32_t)imm_h[i], (i << 4)); 1644 i++; 1645 break; 1646 } 1647 } 1648 for (;i < 4; i++) { 1649 if (imm_h[i] != 0x0L) { 1650 movk(dst, (uint32_t)imm_h[i], (i << 4)); 1651 } 1652 } 1653 } else if (neg_count == 1) { 1654 // one MOVN and two MOVKs will do 1655 for (i = 0; i < 4; i++) { 1656 if (imm_h[i] != 0xffffL) { 1657 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1658 i++; 1659 break; 1660 } 1661 } 1662 for (;i < 4; i++) { 1663 if (imm_h[i] != 0xffffL) { 1664 movk(dst, (uint32_t)imm_h[i], (i << 4)); 1665 } 1666 } 1667 } else { 1668 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1669 movz(dst, (uint32_t)imm_h[0], 0); 1670 for (i = 1; i < 4; i++) { 1671 movk(dst, (uint32_t)imm_h[i], (i << 4)); 1672 } 1673 } 1674 } 1675 } 1676 1677 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32) 1678 { 1679 #ifndef PRODUCT 1680 { 1681 char buffer[64]; 1682 snprintf(buffer, sizeof(buffer), "0x%" PRIX32, imm32); 1683 block_comment(buffer); 1684 } 1685 #endif 1686 if (operand_valid_for_logical_immediate(true, imm32)) { 1687 orrw(dst, zr, imm32); 1688 } else { 1689 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1690 // constant 1691 uint32_t imm_h[2]; 1692 imm_h[0] = imm32 & 0xffff; 1693 imm_h[1] = ((imm32 >> 16) & 0xffff); 1694 if (imm_h[0] == 0) { 1695 movzw(dst, imm_h[1], 16); 1696 } else if (imm_h[0] == 0xffff) { 1697 movnw(dst, imm_h[1] ^ 0xffff, 16); 1698 } else if (imm_h[1] == 0) { 1699 movzw(dst, imm_h[0], 0); 1700 } else if (imm_h[1] == 0xffff) { 1701 movnw(dst, imm_h[0] ^ 0xffff, 0); 1702 } else { 1703 // use a MOVZ and MOVK (makes it easier to debug) 1704 movzw(dst, imm_h[0], 0); 1705 movkw(dst, imm_h[1], 16); 1706 } 1707 } 1708 } 1709 1710 // Form an address from base + offset in Rd. Rd may or may 1711 // not actually be used: you must use the Address that is returned. 1712 // It is up to you to ensure that the shift provided matches the size 1713 // of your data. 1714 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) { 1715 if (Address::offset_ok_for_immed(byte_offset, shift)) 1716 // It fits; no need for any heroics 1717 return Address(base, byte_offset); 1718 1719 // Don't do anything clever with negative or misaligned offsets 1720 unsigned mask = (1 << shift) - 1; 1721 if (byte_offset < 0 || byte_offset & mask) { 1722 mov(Rd, byte_offset); 1723 add(Rd, base, Rd); 1724 return Address(Rd); 1725 } 1726 1727 // See if we can do this with two 12-bit offsets 1728 { 1729 uint64_t word_offset = byte_offset >> shift; 1730 uint64_t masked_offset = word_offset & 0xfff000; 1731 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0) 1732 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1733 add(Rd, base, masked_offset << shift); 1734 word_offset -= masked_offset; 1735 return Address(Rd, word_offset << shift); 1736 } 1737 } 1738 1739 // Do it the hard way 1740 mov(Rd, byte_offset); 1741 add(Rd, base, Rd); 1742 return Address(Rd); 1743 } 1744 1745 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1746 if (UseLSE) { 1747 mov(tmp, 1); 1748 ldadd(Assembler::word, tmp, zr, counter_addr); 1749 return; 1750 } 1751 Label retry_load; 1752 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 1753 prfm(Address(counter_addr), PSTL1STRM); 1754 bind(retry_load); 1755 // flush and load exclusive from the memory location 1756 ldxrw(tmp, counter_addr); 1757 addw(tmp, tmp, 1); 1758 // if we store+flush with no intervening write tmp wil be zero 1759 stxrw(tmp2, tmp, counter_addr); 1760 cbnzw(tmp2, retry_load); 1761 } 1762 1763 1764 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1765 bool want_remainder, Register scratch) 1766 { 1767 // Full implementation of Java idiv and irem. The function 1768 // returns the (pc) offset of the div instruction - may be needed 1769 // for implicit exceptions. 1770 // 1771 // constraint : ra/rb =/= scratch 1772 // normal case 1773 // 1774 // input : ra: dividend 1775 // rb: divisor 1776 // 1777 // result: either 1778 // quotient (= ra idiv rb) 1779 // remainder (= ra irem rb) 1780 1781 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1782 1783 int idivl_offset = offset(); 1784 if (! want_remainder) { 1785 sdivw(result, ra, rb); 1786 } else { 1787 sdivw(scratch, ra, rb); 1788 Assembler::msubw(result, scratch, rb, ra); 1789 } 1790 1791 return idivl_offset; 1792 } 1793 1794 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1795 bool want_remainder, Register scratch) 1796 { 1797 // Full implementation of Java ldiv and lrem. The function 1798 // returns the (pc) offset of the div instruction - may be needed 1799 // for implicit exceptions. 1800 // 1801 // constraint : ra/rb =/= scratch 1802 // normal case 1803 // 1804 // input : ra: dividend 1805 // rb: divisor 1806 // 1807 // result: either 1808 // quotient (= ra idiv rb) 1809 // remainder (= ra irem rb) 1810 1811 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1812 1813 int idivq_offset = offset(); 1814 if (! want_remainder) { 1815 sdiv(result, ra, rb); 1816 } else { 1817 sdiv(scratch, ra, rb); 1818 Assembler::msub(result, scratch, rb, ra); 1819 } 1820 1821 return idivq_offset; 1822 } 1823 1824 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1825 address prev = pc() - NativeMembar::instruction_size; 1826 address last = code()->last_insn(); 1827 if (last != NULL && nativeInstruction_at(last)->is_Membar() && prev == last) { 1828 NativeMembar *bar = NativeMembar_at(prev); 1829 // We are merging two memory barrier instructions. On AArch64 we 1830 // can do this simply by ORing them together. 1831 bar->set_kind(bar->get_kind() | order_constraint); 1832 BLOCK_COMMENT("merged membar"); 1833 } else { 1834 code()->set_last_insn(pc()); 1835 dmb(Assembler::barrier(order_constraint)); 1836 } 1837 } 1838 1839 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) { 1840 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) { 1841 merge_ldst(rt, adr, size_in_bytes, is_store); 1842 code()->clear_last_insn(); 1843 return true; 1844 } else { 1845 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported."); 1846 const unsigned mask = size_in_bytes - 1; 1847 if (adr.getMode() == Address::base_plus_offset && 1848 (adr.offset() & mask) == 0) { // only supports base_plus_offset. 1849 code()->set_last_insn(pc()); 1850 } 1851 return false; 1852 } 1853 } 1854 1855 void MacroAssembler::ldr(Register Rx, const Address &adr) { 1856 // We always try to merge two adjacent loads into one ldp. 1857 if (!try_merge_ldst(Rx, adr, 8, false)) { 1858 Assembler::ldr(Rx, adr); 1859 } 1860 } 1861 1862 void MacroAssembler::ldrw(Register Rw, const Address &adr) { 1863 // We always try to merge two adjacent loads into one ldp. 1864 if (!try_merge_ldst(Rw, adr, 4, false)) { 1865 Assembler::ldrw(Rw, adr); 1866 } 1867 } 1868 1869 void MacroAssembler::str(Register Rx, const Address &adr) { 1870 // We always try to merge two adjacent stores into one stp. 1871 if (!try_merge_ldst(Rx, adr, 8, true)) { 1872 Assembler::str(Rx, adr); 1873 } 1874 } 1875 1876 void MacroAssembler::strw(Register Rw, const Address &adr) { 1877 // We always try to merge two adjacent stores into one stp. 1878 if (!try_merge_ldst(Rw, adr, 4, true)) { 1879 Assembler::strw(Rw, adr); 1880 } 1881 } 1882 1883 // MacroAssembler routines found actually to be needed 1884 1885 void MacroAssembler::push(Register src) 1886 { 1887 str(src, Address(pre(esp, -1 * wordSize))); 1888 } 1889 1890 void MacroAssembler::pop(Register dst) 1891 { 1892 ldr(dst, Address(post(esp, 1 * wordSize))); 1893 } 1894 1895 // Note: load_unsigned_short used to be called load_unsigned_word. 1896 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1897 int off = offset(); 1898 ldrh(dst, src); 1899 return off; 1900 } 1901 1902 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1903 int off = offset(); 1904 ldrb(dst, src); 1905 return off; 1906 } 1907 1908 int MacroAssembler::load_signed_short(Register dst, Address src) { 1909 int off = offset(); 1910 ldrsh(dst, src); 1911 return off; 1912 } 1913 1914 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1915 int off = offset(); 1916 ldrsb(dst, src); 1917 return off; 1918 } 1919 1920 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1921 int off = offset(); 1922 ldrshw(dst, src); 1923 return off; 1924 } 1925 1926 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1927 int off = offset(); 1928 ldrsbw(dst, src); 1929 return off; 1930 } 1931 1932 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1933 switch (size_in_bytes) { 1934 case 8: ldr(dst, src); break; 1935 case 4: ldrw(dst, src); break; 1936 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1937 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1938 default: ShouldNotReachHere(); 1939 } 1940 } 1941 1942 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1943 switch (size_in_bytes) { 1944 case 8: str(src, dst); break; 1945 case 4: strw(src, dst); break; 1946 case 2: strh(src, dst); break; 1947 case 1: strb(src, dst); break; 1948 default: ShouldNotReachHere(); 1949 } 1950 } 1951 1952 void MacroAssembler::decrementw(Register reg, int value) 1953 { 1954 if (value < 0) { incrementw(reg, -value); return; } 1955 if (value == 0) { return; } 1956 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1957 /* else */ { 1958 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1959 movw(rscratch2, (unsigned)value); 1960 subw(reg, reg, rscratch2); 1961 } 1962 } 1963 1964 void MacroAssembler::decrement(Register reg, int value) 1965 { 1966 if (value < 0) { increment(reg, -value); return; } 1967 if (value == 0) { return; } 1968 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1969 /* else */ { 1970 assert(reg != rscratch2, "invalid dst for register decrement"); 1971 mov(rscratch2, (uint64_t) value); 1972 sub(reg, reg, rscratch2); 1973 } 1974 } 1975 1976 void MacroAssembler::decrementw(Address dst, int value) 1977 { 1978 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1979 if (dst.getMode() == Address::literal) { 1980 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 1981 lea(rscratch2, dst); 1982 dst = Address(rscratch2); 1983 } 1984 ldrw(rscratch1, dst); 1985 decrementw(rscratch1, value); 1986 strw(rscratch1, dst); 1987 } 1988 1989 void MacroAssembler::decrement(Address dst, int value) 1990 { 1991 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1992 if (dst.getMode() == Address::literal) { 1993 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 1994 lea(rscratch2, dst); 1995 dst = Address(rscratch2); 1996 } 1997 ldr(rscratch1, dst); 1998 decrement(rscratch1, value); 1999 str(rscratch1, dst); 2000 } 2001 2002 void MacroAssembler::incrementw(Register reg, int value) 2003 { 2004 if (value < 0) { decrementw(reg, -value); return; } 2005 if (value == 0) { return; } 2006 if (value < (1 << 12)) { addw(reg, reg, value); return; } 2007 /* else */ { 2008 assert(reg != rscratch2, "invalid dst for register increment"); 2009 movw(rscratch2, (unsigned)value); 2010 addw(reg, reg, rscratch2); 2011 } 2012 } 2013 2014 void MacroAssembler::increment(Register reg, int value) 2015 { 2016 if (value < 0) { decrement(reg, -value); return; } 2017 if (value == 0) { return; } 2018 if (value < (1 << 12)) { add(reg, reg, value); return; } 2019 /* else */ { 2020 assert(reg != rscratch2, "invalid dst for register increment"); 2021 movw(rscratch2, (unsigned)value); 2022 add(reg, reg, rscratch2); 2023 } 2024 } 2025 2026 void MacroAssembler::incrementw(Address dst, int value) 2027 { 2028 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 2029 if (dst.getMode() == Address::literal) { 2030 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 2031 lea(rscratch2, dst); 2032 dst = Address(rscratch2); 2033 } 2034 ldrw(rscratch1, dst); 2035 incrementw(rscratch1, value); 2036 strw(rscratch1, dst); 2037 } 2038 2039 void MacroAssembler::increment(Address dst, int value) 2040 { 2041 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 2042 if (dst.getMode() == Address::literal) { 2043 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 2044 lea(rscratch2, dst); 2045 dst = Address(rscratch2); 2046 } 2047 ldr(rscratch1, dst); 2048 increment(rscratch1, value); 2049 str(rscratch1, dst); 2050 } 2051 2052 2053 void MacroAssembler::pusha() { 2054 push(0x7fffffff, sp); 2055 } 2056 2057 void MacroAssembler::popa() { 2058 pop(0x7fffffff, sp); 2059 } 2060 2061 // Push lots of registers in the bit set supplied. Don't push sp. 2062 // Return the number of words pushed 2063 int MacroAssembler::push(unsigned int bitset, Register stack) { 2064 int words_pushed = 0; 2065 2066 // Scan bitset to accumulate register pairs 2067 unsigned char regs[32]; 2068 int count = 0; 2069 for (int reg = 0; reg <= 30; reg++) { 2070 if (1 & bitset) 2071 regs[count++] = reg; 2072 bitset >>= 1; 2073 } 2074 regs[count++] = zr->encoding_nocheck(); 2075 count &= ~1; // Only push an even nuber of regs 2076 2077 if (count) { 2078 stp(as_Register(regs[0]), as_Register(regs[1]), 2079 Address(pre(stack, -count * wordSize))); 2080 words_pushed += 2; 2081 } 2082 for (int i = 2; i < count; i += 2) { 2083 stp(as_Register(regs[i]), as_Register(regs[i+1]), 2084 Address(stack, i * wordSize)); 2085 words_pushed += 2; 2086 } 2087 2088 assert(words_pushed == count, "oops, pushed != count"); 2089 2090 return count; 2091 } 2092 2093 int MacroAssembler::pop(unsigned int bitset, Register stack) { 2094 int words_pushed = 0; 2095 2096 // Scan bitset to accumulate register pairs 2097 unsigned char regs[32]; 2098 int count = 0; 2099 for (int reg = 0; reg <= 30; reg++) { 2100 if (1 & bitset) 2101 regs[count++] = reg; 2102 bitset >>= 1; 2103 } 2104 regs[count++] = zr->encoding_nocheck(); 2105 count &= ~1; 2106 2107 for (int i = 2; i < count; i += 2) { 2108 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 2109 Address(stack, i * wordSize)); 2110 words_pushed += 2; 2111 } 2112 if (count) { 2113 ldp(as_Register(regs[0]), as_Register(regs[1]), 2114 Address(post(stack, count * wordSize))); 2115 words_pushed += 2; 2116 } 2117 2118 assert(words_pushed == count, "oops, pushed != count"); 2119 2120 return count; 2121 } 2122 2123 // Push lots of registers in the bit set supplied. Don't push sp. 2124 // Return the number of words pushed 2125 int MacroAssembler::push_fp(unsigned int bitset, Register stack) { 2126 int words_pushed = 0; 2127 2128 // Scan bitset to accumulate register pairs 2129 unsigned char regs[32]; 2130 int count = 0; 2131 for (int reg = 0; reg <= 31; reg++) { 2132 if (1 & bitset) 2133 regs[count++] = reg; 2134 bitset >>= 1; 2135 } 2136 regs[count++] = zr->encoding_nocheck(); 2137 count &= ~1; // Only push an even number of regs 2138 2139 // Always pushing full 128 bit registers. 2140 if (count) { 2141 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2))); 2142 words_pushed += 2; 2143 } 2144 for (int i = 2; i < count; i += 2) { 2145 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); 2146 words_pushed += 2; 2147 } 2148 2149 assert(words_pushed == count, "oops, pushed != count"); 2150 return count; 2151 } 2152 2153 int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { 2154 int words_pushed = 0; 2155 2156 // Scan bitset to accumulate register pairs 2157 unsigned char regs[32]; 2158 int count = 0; 2159 for (int reg = 0; reg <= 31; reg++) { 2160 if (1 & bitset) 2161 regs[count++] = reg; 2162 bitset >>= 1; 2163 } 2164 regs[count++] = zr->encoding_nocheck(); 2165 count &= ~1; 2166 2167 for (int i = 2; i < count; i += 2) { 2168 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); 2169 words_pushed += 2; 2170 } 2171 if (count) { 2172 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2))); 2173 words_pushed += 2; 2174 } 2175 2176 assert(words_pushed == count, "oops, pushed != count"); 2177 2178 return count; 2179 } 2180 2181 #ifdef ASSERT 2182 void MacroAssembler::verify_heapbase(const char* msg) { 2183 #if 0 2184 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 2185 assert (Universe::heap() != NULL, "java heap should be initialized"); 2186 if (!UseCompressedOops || Universe::ptr_base() == NULL) { 2187 // rheapbase is allocated as general register 2188 return; 2189 } 2190 if (CheckCompressedOops) { 2191 Label ok; 2192 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 2193 cmpptr(rheapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr())); 2194 br(Assembler::EQ, ok); 2195 stop(msg); 2196 bind(ok); 2197 pop(1 << rscratch1->encoding(), sp); 2198 } 2199 #endif 2200 } 2201 #endif 2202 2203 void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) { 2204 Label done, not_weak; 2205 cbz(value, done); // Use NULL as-is. 2206 2207 STATIC_ASSERT(JNIHandles::weak_tag_mask == 1u); 2208 tbz(r0, 0, not_weak); // Test for jweak tag. 2209 2210 // Resolve jweak. 2211 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, value, 2212 Address(value, -JNIHandles::weak_tag_value), tmp, thread); 2213 verify_oop(value); 2214 b(done); 2215 2216 bind(not_weak); 2217 // Resolve (untagged) jobject. 2218 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread); 2219 verify_oop(value); 2220 bind(done); 2221 } 2222 2223 void MacroAssembler::stop(const char* msg) { 2224 BLOCK_COMMENT(msg); 2225 dcps1(0xdeae); 2226 emit_int64((uintptr_t)msg); 2227 } 2228 2229 void MacroAssembler::unimplemented(const char* what) { 2230 const char* buf = NULL; 2231 { 2232 ResourceMark rm; 2233 stringStream ss; 2234 ss.print("unimplemented: %s", what); 2235 buf = code_string(ss.as_string()); 2236 } 2237 stop(buf); 2238 } 2239 2240 // If a constant does not fit in an immediate field, generate some 2241 // number of MOV instructions and then perform the operation. 2242 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 2243 add_sub_imm_insn insn1, 2244 add_sub_reg_insn insn2) { 2245 assert(Rd != zr, "Rd = zr and not setting flags?"); 2246 if (operand_valid_for_add_sub_immediate((int)imm)) { 2247 (this->*insn1)(Rd, Rn, imm); 2248 } else { 2249 if (uabs(imm) < (1 << 24)) { 2250 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 2251 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 2252 } else { 2253 assert_different_registers(Rd, Rn); 2254 mov(Rd, (uint64_t)imm); 2255 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2256 } 2257 } 2258 } 2259 2260 // Seperate vsn which sets the flags. Optimisations are more restricted 2261 // because we must set the flags correctly. 2262 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 2263 add_sub_imm_insn insn1, 2264 add_sub_reg_insn insn2) { 2265 if (operand_valid_for_add_sub_immediate((int)imm)) { 2266 (this->*insn1)(Rd, Rn, imm); 2267 } else { 2268 assert_different_registers(Rd, Rn); 2269 assert(Rd != zr, "overflow in immediate operand"); 2270 mov(Rd, (uint64_t)imm); 2271 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2272 } 2273 } 2274 2275 2276 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2277 if (increment.is_register()) { 2278 add(Rd, Rn, increment.as_register()); 2279 } else { 2280 add(Rd, Rn, increment.as_constant()); 2281 } 2282 } 2283 2284 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2285 if (increment.is_register()) { 2286 addw(Rd, Rn, increment.as_register()); 2287 } else { 2288 addw(Rd, Rn, increment.as_constant()); 2289 } 2290 } 2291 2292 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2293 if (decrement.is_register()) { 2294 sub(Rd, Rn, decrement.as_register()); 2295 } else { 2296 sub(Rd, Rn, decrement.as_constant()); 2297 } 2298 } 2299 2300 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2301 if (decrement.is_register()) { 2302 subw(Rd, Rn, decrement.as_register()); 2303 } else { 2304 subw(Rd, Rn, decrement.as_constant()); 2305 } 2306 } 2307 2308 void MacroAssembler::reinit_heapbase() 2309 { 2310 if (UseCompressedOops) { 2311 if (Universe::is_fully_initialized()) { 2312 mov(rheapbase, CompressedOops::ptrs_base()); 2313 } else { 2314 lea(rheapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr())); 2315 ldr(rheapbase, Address(rheapbase)); 2316 } 2317 } 2318 } 2319 2320 // this simulates the behaviour of the x86 cmpxchg instruction using a 2321 // load linked/store conditional pair. we use the acquire/release 2322 // versions of these instructions so that we flush pending writes as 2323 // per Java semantics. 2324 2325 // n.b the x86 version assumes the old value to be compared against is 2326 // in rax and updates rax with the value located in memory if the 2327 // cmpxchg fails. we supply a register for the old value explicitly 2328 2329 // the aarch64 load linked/store conditional instructions do not 2330 // accept an offset. so, unlike x86, we must provide a plain register 2331 // to identify the memory word to be compared/exchanged rather than a 2332 // register+offset Address. 2333 2334 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2335 Label &succeed, Label *fail) { 2336 // oldv holds comparison value 2337 // newv holds value to write in exchange 2338 // addr identifies memory word to compare against/update 2339 if (UseLSE) { 2340 mov(tmp, oldv); 2341 casal(Assembler::xword, oldv, newv, addr); 2342 cmp(tmp, oldv); 2343 br(Assembler::EQ, succeed); 2344 membar(AnyAny); 2345 } else { 2346 Label retry_load, nope; 2347 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2348 prfm(Address(addr), PSTL1STRM); 2349 bind(retry_load); 2350 // flush and load exclusive from the memory location 2351 // and fail if it is not what we expect 2352 ldaxr(tmp, addr); 2353 cmp(tmp, oldv); 2354 br(Assembler::NE, nope); 2355 // if we store+flush with no intervening write tmp wil be zero 2356 stlxr(tmp, newv, addr); 2357 cbzw(tmp, succeed); 2358 // retry so we only ever return after a load fails to compare 2359 // ensures we don't return a stale value after a failed write. 2360 b(retry_load); 2361 // if the memory word differs we return it in oldv and signal a fail 2362 bind(nope); 2363 membar(AnyAny); 2364 mov(oldv, tmp); 2365 } 2366 if (fail) 2367 b(*fail); 2368 } 2369 2370 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 2371 Label &succeed, Label *fail) { 2372 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption"); 2373 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail); 2374 } 2375 2376 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2377 Label &succeed, Label *fail) { 2378 // oldv holds comparison value 2379 // newv holds value to write in exchange 2380 // addr identifies memory word to compare against/update 2381 // tmp returns 0/1 for success/failure 2382 if (UseLSE) { 2383 mov(tmp, oldv); 2384 casal(Assembler::word, oldv, newv, addr); 2385 cmp(tmp, oldv); 2386 br(Assembler::EQ, succeed); 2387 membar(AnyAny); 2388 } else { 2389 Label retry_load, nope; 2390 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2391 prfm(Address(addr), PSTL1STRM); 2392 bind(retry_load); 2393 // flush and load exclusive from the memory location 2394 // and fail if it is not what we expect 2395 ldaxrw(tmp, addr); 2396 cmp(tmp, oldv); 2397 br(Assembler::NE, nope); 2398 // if we store+flush with no intervening write tmp wil be zero 2399 stlxrw(tmp, newv, addr); 2400 cbzw(tmp, succeed); 2401 // retry so we only ever return after a load fails to compare 2402 // ensures we don't return a stale value after a failed write. 2403 b(retry_load); 2404 // if the memory word differs we return it in oldv and signal a fail 2405 bind(nope); 2406 membar(AnyAny); 2407 mov(oldv, tmp); 2408 } 2409 if (fail) 2410 b(*fail); 2411 } 2412 2413 // A generic CAS; success or failure is in the EQ flag. A weak CAS 2414 // doesn't retry and may fail spuriously. If the oldval is wanted, 2415 // Pass a register for the result, otherwise pass noreg. 2416 2417 // Clobbers rscratch1 2418 void MacroAssembler::cmpxchg(Register addr, Register expected, 2419 Register new_val, 2420 enum operand_size size, 2421 bool acquire, bool release, 2422 bool weak, 2423 Register result) { 2424 if (result == noreg) result = rscratch1; 2425 BLOCK_COMMENT("cmpxchg {"); 2426 if (UseLSE) { 2427 mov(result, expected); 2428 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true); 2429 compare_eq(result, expected, size); 2430 } else { 2431 Label retry_load, done; 2432 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) 2433 prfm(Address(addr), PSTL1STRM); 2434 bind(retry_load); 2435 load_exclusive(result, addr, size, acquire); 2436 compare_eq(result, expected, size); 2437 br(Assembler::NE, done); 2438 store_exclusive(rscratch1, new_val, addr, size, release); 2439 if (weak) { 2440 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller. 2441 } else { 2442 cbnzw(rscratch1, retry_load); 2443 } 2444 bind(done); 2445 } 2446 BLOCK_COMMENT("} cmpxchg"); 2447 } 2448 2449 // A generic comparison. Only compares for equality, clobbers rscratch1. 2450 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) { 2451 if (size == xword) { 2452 cmp(rm, rn); 2453 } else if (size == word) { 2454 cmpw(rm, rn); 2455 } else if (size == halfword) { 2456 eorw(rscratch1, rm, rn); 2457 ands(zr, rscratch1, 0xffff); 2458 } else if (size == byte) { 2459 eorw(rscratch1, rm, rn); 2460 ands(zr, rscratch1, 0xff); 2461 } else { 2462 ShouldNotReachHere(); 2463 } 2464 } 2465 2466 2467 static bool different(Register a, RegisterOrConstant b, Register c) { 2468 if (b.is_constant()) 2469 return a != c; 2470 else 2471 return a != b.as_register() && a != c && b.as_register() != c; 2472 } 2473 2474 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \ 2475 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \ 2476 if (UseLSE) { \ 2477 prev = prev->is_valid() ? prev : zr; \ 2478 if (incr.is_register()) { \ 2479 AOP(sz, incr.as_register(), prev, addr); \ 2480 } else { \ 2481 mov(rscratch2, incr.as_constant()); \ 2482 AOP(sz, rscratch2, prev, addr); \ 2483 } \ 2484 return; \ 2485 } \ 2486 Register result = rscratch2; \ 2487 if (prev->is_valid()) \ 2488 result = different(prev, incr, addr) ? prev : rscratch2; \ 2489 \ 2490 Label retry_load; \ 2491 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2492 prfm(Address(addr), PSTL1STRM); \ 2493 bind(retry_load); \ 2494 LDXR(result, addr); \ 2495 OP(rscratch1, result, incr); \ 2496 STXR(rscratch2, rscratch1, addr); \ 2497 cbnzw(rscratch2, retry_load); \ 2498 if (prev->is_valid() && prev != result) { \ 2499 IOP(prev, rscratch1, incr); \ 2500 } \ 2501 } 2502 2503 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword) 2504 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word) 2505 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword) 2506 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word) 2507 2508 #undef ATOMIC_OP 2509 2510 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \ 2511 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2512 if (UseLSE) { \ 2513 prev = prev->is_valid() ? prev : zr; \ 2514 AOP(sz, newv, prev, addr); \ 2515 return; \ 2516 } \ 2517 Register result = rscratch2; \ 2518 if (prev->is_valid()) \ 2519 result = different(prev, newv, addr) ? prev : rscratch2; \ 2520 \ 2521 Label retry_load; \ 2522 if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH)) \ 2523 prfm(Address(addr), PSTL1STRM); \ 2524 bind(retry_load); \ 2525 LDXR(result, addr); \ 2526 STXR(rscratch1, newv, addr); \ 2527 cbnzw(rscratch1, retry_load); \ 2528 if (prev->is_valid() && prev != result) \ 2529 mov(prev, result); \ 2530 } 2531 2532 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) 2533 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) 2534 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) 2535 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) 2536 2537 #undef ATOMIC_XCHG 2538 2539 #ifndef PRODUCT 2540 extern "C" void findpc(intptr_t x); 2541 #endif 2542 2543 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2544 { 2545 // In order to get locks to work, we need to fake a in_VM state 2546 if (ShowMessageBoxOnError ) { 2547 JavaThread* thread = JavaThread::current(); 2548 JavaThreadState saved_state = thread->thread_state(); 2549 thread->set_thread_state(_thread_in_vm); 2550 #ifndef PRODUCT 2551 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2552 ttyLocker ttyl; 2553 BytecodeCounter::print(); 2554 } 2555 #endif 2556 if (os::message_box(msg, "Execution stopped, print registers?")) { 2557 ttyLocker ttyl; 2558 tty->print_cr(" pc = 0x%016lx", pc); 2559 #ifndef PRODUCT 2560 tty->cr(); 2561 findpc(pc); 2562 tty->cr(); 2563 #endif 2564 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2565 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2566 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2567 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2568 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2569 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2570 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2571 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2572 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2573 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2574 tty->print_cr("r10 = 0x%016lx", regs[10]); 2575 tty->print_cr("r11 = 0x%016lx", regs[11]); 2576 tty->print_cr("r12 = 0x%016lx", regs[12]); 2577 tty->print_cr("r13 = 0x%016lx", regs[13]); 2578 tty->print_cr("r14 = 0x%016lx", regs[14]); 2579 tty->print_cr("r15 = 0x%016lx", regs[15]); 2580 tty->print_cr("r16 = 0x%016lx", regs[16]); 2581 tty->print_cr("r17 = 0x%016lx", regs[17]); 2582 tty->print_cr("r18 = 0x%016lx", regs[18]); 2583 tty->print_cr("r19 = 0x%016lx", regs[19]); 2584 tty->print_cr("r20 = 0x%016lx", regs[20]); 2585 tty->print_cr("r21 = 0x%016lx", regs[21]); 2586 tty->print_cr("r22 = 0x%016lx", regs[22]); 2587 tty->print_cr("r23 = 0x%016lx", regs[23]); 2588 tty->print_cr("r24 = 0x%016lx", regs[24]); 2589 tty->print_cr("r25 = 0x%016lx", regs[25]); 2590 tty->print_cr("r26 = 0x%016lx", regs[26]); 2591 tty->print_cr("r27 = 0x%016lx", regs[27]); 2592 tty->print_cr("r28 = 0x%016lx", regs[28]); 2593 tty->print_cr("r30 = 0x%016lx", regs[30]); 2594 tty->print_cr("r31 = 0x%016lx", regs[31]); 2595 BREAKPOINT; 2596 } 2597 } 2598 fatal("DEBUG MESSAGE: %s", msg); 2599 } 2600 2601 void MacroAssembler::push_call_clobbered_registers() { 2602 int step = 4 * wordSize; 2603 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2) WIN64_ONLY(- r18), sp); 2604 sub(sp, sp, step); 2605 mov(rscratch1, -step); 2606 // Push v0-v7, v16-v31. 2607 for (int i = 31; i>= 4; i -= 4) { 2608 if (i <= v7->encoding() || i >= v16->encoding()) 2609 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1), 2610 as_FloatRegister(i), T1D, Address(post(sp, rscratch1))); 2611 } 2612 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2), 2613 as_FloatRegister(3), T1D, Address(sp)); 2614 } 2615 2616 void MacroAssembler::pop_call_clobbered_registers() { 2617 for (int i = 0; i < 32; i += 4) { 2618 if (i <= v7->encoding() || i >= v16->encoding()) 2619 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 2620 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize))); 2621 } 2622 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2) WIN64_ONLY(- r18), sp); 2623 } 2624 2625 void MacroAssembler::push_CPU_state(bool save_vectors) { 2626 int step = (save_vectors ? 8 : 4) * wordSize; 2627 push(0x3fffffff, sp); // integer registers except lr & sp 2628 mov(rscratch1, -step); 2629 sub(sp, sp, step); 2630 for (int i = 28; i >= 4; i -= 4) { 2631 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 2632 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1))); 2633 } 2634 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp); 2635 } 2636 2637 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2638 int step = (restore_vectors ? 8 : 4) * wordSize; 2639 for (int i = 0; i <= 28; i += 4) 2640 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 2641 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step))); 2642 pop(0x3fffffff, sp); // integer registers except lr & sp 2643 } 2644 2645 /** 2646 * Helpers for multiply_to_len(). 2647 */ 2648 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2649 Register src1, Register src2) { 2650 adds(dest_lo, dest_lo, src1); 2651 adc(dest_hi, dest_hi, zr); 2652 adds(dest_lo, dest_lo, src2); 2653 adc(final_dest_hi, dest_hi, zr); 2654 } 2655 2656 // Generate an address from (r + r1 extend offset). "size" is the 2657 // size of the operand. The result may be in rscratch2. 2658 Address MacroAssembler::offsetted_address(Register r, Register r1, 2659 Address::extend ext, int offset, int size) { 2660 if (offset || (ext.shift() % size != 0)) { 2661 lea(rscratch2, Address(r, r1, ext)); 2662 return Address(rscratch2, offset); 2663 } else { 2664 return Address(r, r1, ext); 2665 } 2666 } 2667 2668 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2669 { 2670 assert(offset >= 0, "spill to negative address?"); 2671 // Offset reachable ? 2672 // Not aligned - 9 bits signed offset 2673 // Aligned - 12 bits unsigned offset shifted 2674 Register base = sp; 2675 if ((offset & (size-1)) && offset >= (1<<8)) { 2676 add(tmp, base, offset & ((1<<12)-1)); 2677 base = tmp; 2678 offset &= -1u<<12; 2679 } 2680 2681 if (offset >= (1<<12) * size) { 2682 add(tmp, base, offset & (((1<<12)-1)<<12)); 2683 base = tmp; 2684 offset &= ~(((1<<12)-1)<<12); 2685 } 2686 2687 return Address(base, offset); 2688 } 2689 2690 // Checks whether offset is aligned. 2691 // Returns true if it is, else false. 2692 bool MacroAssembler::merge_alignment_check(Register base, 2693 size_t size, 2694 int64_t cur_offset, 2695 int64_t prev_offset) const { 2696 if (AvoidUnalignedAccesses) { 2697 if (base == sp) { 2698 // Checks whether low offset if aligned to pair of registers. 2699 int64_t pair_mask = size * 2 - 1; 2700 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset; 2701 return (offset & pair_mask) == 0; 2702 } else { // If base is not sp, we can't guarantee the access is aligned. 2703 return false; 2704 } 2705 } else { 2706 int64_t mask = size - 1; 2707 // Load/store pair instruction only supports element size aligned offset. 2708 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0; 2709 } 2710 } 2711 2712 // Checks whether current and previous loads/stores can be merged. 2713 // Returns true if it can be merged, else false. 2714 bool MacroAssembler::ldst_can_merge(Register rt, 2715 const Address &adr, 2716 size_t cur_size_in_bytes, 2717 bool is_store) const { 2718 address prev = pc() - NativeInstruction::instruction_size; 2719 address last = code()->last_insn(); 2720 2721 if (last == NULL || !nativeInstruction_at(last)->is_Imm_LdSt()) { 2722 return false; 2723 } 2724 2725 if (adr.getMode() != Address::base_plus_offset || prev != last) { 2726 return false; 2727 } 2728 2729 NativeLdSt* prev_ldst = NativeLdSt_at(prev); 2730 size_t prev_size_in_bytes = prev_ldst->size_in_bytes(); 2731 2732 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging."); 2733 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging."); 2734 2735 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) { 2736 return false; 2737 } 2738 2739 int64_t max_offset = 63 * prev_size_in_bytes; 2740 int64_t min_offset = -64 * prev_size_in_bytes; 2741 2742 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged."); 2743 2744 // Only same base can be merged. 2745 if (adr.base() != prev_ldst->base()) { 2746 return false; 2747 } 2748 2749 int64_t cur_offset = adr.offset(); 2750 int64_t prev_offset = prev_ldst->offset(); 2751 size_t diff = abs(cur_offset - prev_offset); 2752 if (diff != prev_size_in_bytes) { 2753 return false; 2754 } 2755 2756 // Following cases can not be merged: 2757 // ldr x2, [x2, #8] 2758 // ldr x3, [x2, #16] 2759 // or: 2760 // ldr x2, [x3, #8] 2761 // ldr x2, [x3, #16] 2762 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL. 2763 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) { 2764 return false; 2765 } 2766 2767 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset; 2768 // Offset range must be in ldp/stp instruction's range. 2769 if (low_offset > max_offset || low_offset < min_offset) { 2770 return false; 2771 } 2772 2773 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) { 2774 return true; 2775 } 2776 2777 return false; 2778 } 2779 2780 // Merge current load/store with previous load/store into ldp/stp. 2781 void MacroAssembler::merge_ldst(Register rt, 2782 const Address &adr, 2783 size_t cur_size_in_bytes, 2784 bool is_store) { 2785 2786 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged."); 2787 2788 Register rt_low, rt_high; 2789 address prev = pc() - NativeInstruction::instruction_size; 2790 NativeLdSt* prev_ldst = NativeLdSt_at(prev); 2791 2792 int64_t offset; 2793 2794 if (adr.offset() < prev_ldst->offset()) { 2795 offset = adr.offset(); 2796 rt_low = rt; 2797 rt_high = prev_ldst->target(); 2798 } else { 2799 offset = prev_ldst->offset(); 2800 rt_low = prev_ldst->target(); 2801 rt_high = rt; 2802 } 2803 2804 Address adr_p = Address(prev_ldst->base(), offset); 2805 // Overwrite previous generated binary. 2806 code_section()->set_end(prev); 2807 2808 const int sz = prev_ldst->size_in_bytes(); 2809 assert(sz == 8 || sz == 4, "only supports 64/32bit merging."); 2810 if (!is_store) { 2811 BLOCK_COMMENT("merged ldr pair"); 2812 if (sz == 8) { 2813 ldp(rt_low, rt_high, adr_p); 2814 } else { 2815 ldpw(rt_low, rt_high, adr_p); 2816 } 2817 } else { 2818 BLOCK_COMMENT("merged str pair"); 2819 if (sz == 8) { 2820 stp(rt_low, rt_high, adr_p); 2821 } else { 2822 stpw(rt_low, rt_high, adr_p); 2823 } 2824 } 2825 } 2826 2827 /** 2828 * Multiply 64 bit by 64 bit first loop. 2829 */ 2830 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2831 Register y, Register y_idx, Register z, 2832 Register carry, Register product, 2833 Register idx, Register kdx) { 2834 // 2835 // jlong carry, x[], y[], z[]; 2836 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2837 // huge_128 product = y[idx] * x[xstart] + carry; 2838 // z[kdx] = (jlong)product; 2839 // carry = (jlong)(product >>> 64); 2840 // } 2841 // z[xstart] = carry; 2842 // 2843 2844 Label L_first_loop, L_first_loop_exit; 2845 Label L_one_x, L_one_y, L_multiply; 2846 2847 subsw(xstart, xstart, 1); 2848 br(Assembler::MI, L_one_x); 2849 2850 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2851 ldr(x_xstart, Address(rscratch1)); 2852 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2853 2854 bind(L_first_loop); 2855 subsw(idx, idx, 1); 2856 br(Assembler::MI, L_first_loop_exit); 2857 subsw(idx, idx, 1); 2858 br(Assembler::MI, L_one_y); 2859 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2860 ldr(y_idx, Address(rscratch1)); 2861 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2862 bind(L_multiply); 2863 2864 // AArch64 has a multiply-accumulate instruction that we can't use 2865 // here because it has no way to process carries, so we have to use 2866 // separate add and adc instructions. Bah. 2867 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2868 mul(product, x_xstart, y_idx); 2869 adds(product, product, carry); 2870 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2871 2872 subw(kdx, kdx, 2); 2873 ror(product, product, 32); // back to big-endian 2874 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2875 2876 b(L_first_loop); 2877 2878 bind(L_one_y); 2879 ldrw(y_idx, Address(y, 0)); 2880 b(L_multiply); 2881 2882 bind(L_one_x); 2883 ldrw(x_xstart, Address(x, 0)); 2884 b(L_first_loop); 2885 2886 bind(L_first_loop_exit); 2887 } 2888 2889 /** 2890 * Multiply 128 bit by 128. Unrolled inner loop. 2891 * 2892 */ 2893 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2894 Register carry, Register carry2, 2895 Register idx, Register jdx, 2896 Register yz_idx1, Register yz_idx2, 2897 Register tmp, Register tmp3, Register tmp4, 2898 Register tmp6, Register product_hi) { 2899 2900 // jlong carry, x[], y[], z[]; 2901 // int kdx = ystart+1; 2902 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2903 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2904 // jlong carry2 = (jlong)(tmp3 >>> 64); 2905 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2906 // carry = (jlong)(tmp4 >>> 64); 2907 // z[kdx+idx+1] = (jlong)tmp3; 2908 // z[kdx+idx] = (jlong)tmp4; 2909 // } 2910 // idx += 2; 2911 // if (idx > 0) { 2912 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2913 // z[kdx+idx] = (jlong)yz_idx1; 2914 // carry = (jlong)(yz_idx1 >>> 64); 2915 // } 2916 // 2917 2918 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2919 2920 lsrw(jdx, idx, 2); 2921 2922 bind(L_third_loop); 2923 2924 subsw(jdx, jdx, 1); 2925 br(Assembler::MI, L_third_loop_exit); 2926 subw(idx, idx, 4); 2927 2928 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2929 2930 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2931 2932 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2933 2934 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2935 ror(yz_idx2, yz_idx2, 32); 2936 2937 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2938 2939 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2940 umulh(tmp4, product_hi, yz_idx1); 2941 2942 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2943 ror(rscratch2, rscratch2, 32); 2944 2945 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2946 umulh(carry2, product_hi, yz_idx2); 2947 2948 // propagate sum of both multiplications into carry:tmp4:tmp3 2949 adds(tmp3, tmp3, carry); 2950 adc(tmp4, tmp4, zr); 2951 adds(tmp3, tmp3, rscratch1); 2952 adcs(tmp4, tmp4, tmp); 2953 adc(carry, carry2, zr); 2954 adds(tmp4, tmp4, rscratch2); 2955 adc(carry, carry, zr); 2956 2957 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2958 ror(tmp4, tmp4, 32); 2959 stp(tmp4, tmp3, Address(tmp6, 0)); 2960 2961 b(L_third_loop); 2962 bind (L_third_loop_exit); 2963 2964 andw (idx, idx, 0x3); 2965 cbz(idx, L_post_third_loop_done); 2966 2967 Label L_check_1; 2968 subsw(idx, idx, 2); 2969 br(Assembler::MI, L_check_1); 2970 2971 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2972 ldr(yz_idx1, Address(rscratch1, 0)); 2973 ror(yz_idx1, yz_idx1, 32); 2974 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2975 umulh(tmp4, product_hi, yz_idx1); 2976 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2977 ldr(yz_idx2, Address(rscratch1, 0)); 2978 ror(yz_idx2, yz_idx2, 32); 2979 2980 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2981 2982 ror(tmp3, tmp3, 32); 2983 str(tmp3, Address(rscratch1, 0)); 2984 2985 bind (L_check_1); 2986 2987 andw (idx, idx, 0x1); 2988 subsw(idx, idx, 1); 2989 br(Assembler::MI, L_post_third_loop_done); 2990 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2991 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2992 umulh(carry2, tmp4, product_hi); 2993 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2994 2995 add2_with_carry(carry2, tmp3, tmp4, carry); 2996 2997 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2998 extr(carry, carry2, tmp3, 32); 2999 3000 bind(L_post_third_loop_done); 3001 } 3002 3003 /** 3004 * Code for BigInteger::multiplyToLen() instrinsic. 3005 * 3006 * r0: x 3007 * r1: xlen 3008 * r2: y 3009 * r3: ylen 3010 * r4: z 3011 * r5: zlen 3012 * r10: tmp1 3013 * r11: tmp2 3014 * r12: tmp3 3015 * r13: tmp4 3016 * r14: tmp5 3017 * r15: tmp6 3018 * r16: tmp7 3019 * 3020 */ 3021 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 3022 Register z, Register zlen, 3023 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 3024 Register tmp5, Register tmp6, Register product_hi) { 3025 3026 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 3027 3028 const Register idx = tmp1; 3029 const Register kdx = tmp2; 3030 const Register xstart = tmp3; 3031 3032 const Register y_idx = tmp4; 3033 const Register carry = tmp5; 3034 const Register product = xlen; 3035 const Register x_xstart = zlen; // reuse register 3036 3037 // First Loop. 3038 // 3039 // final static int64_t LONG_MASK = 0xffffffffL; 3040 // int xstart = xlen - 1; 3041 // int ystart = ylen - 1; 3042 // int64_t carry = 0; 3043 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 3044 // int64_t product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 3045 // z[kdx] = (int)product; 3046 // carry = product >>> 32; 3047 // } 3048 // z[xstart] = (int)carry; 3049 // 3050 3051 movw(idx, ylen); // idx = ylen; 3052 movw(kdx, zlen); // kdx = xlen+ylen; 3053 mov(carry, zr); // carry = 0; 3054 3055 Label L_done; 3056 3057 movw(xstart, xlen); 3058 subsw(xstart, xstart, 1); 3059 br(Assembler::MI, L_done); 3060 3061 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 3062 3063 Label L_second_loop; 3064 cbzw(kdx, L_second_loop); 3065 3066 Label L_carry; 3067 subw(kdx, kdx, 1); 3068 cbzw(kdx, L_carry); 3069 3070 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 3071 lsr(carry, carry, 32); 3072 subw(kdx, kdx, 1); 3073 3074 bind(L_carry); 3075 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 3076 3077 // Second and third (nested) loops. 3078 // 3079 // for (int i = xstart-1; i >= 0; i--) { // Second loop 3080 // carry = 0; 3081 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 3082 // int64_t product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 3083 // (z[k] & LONG_MASK) + carry; 3084 // z[k] = (int)product; 3085 // carry = product >>> 32; 3086 // } 3087 // z[i] = (int)carry; 3088 // } 3089 // 3090 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 3091 3092 const Register jdx = tmp1; 3093 3094 bind(L_second_loop); 3095 mov(carry, zr); // carry = 0; 3096 movw(jdx, ylen); // j = ystart+1 3097 3098 subsw(xstart, xstart, 1); // i = xstart-1; 3099 br(Assembler::MI, L_done); 3100 3101 str(z, Address(pre(sp, -4 * wordSize))); 3102 3103 Label L_last_x; 3104 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 3105 subsw(xstart, xstart, 1); // i = xstart-1; 3106 br(Assembler::MI, L_last_x); 3107 3108 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 3109 ldr(product_hi, Address(rscratch1)); 3110 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 3111 3112 Label L_third_loop_prologue; 3113 bind(L_third_loop_prologue); 3114 3115 str(ylen, Address(sp, wordSize)); 3116 stp(x, xstart, Address(sp, 2 * wordSize)); 3117 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 3118 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 3119 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 3120 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 3121 3122 addw(tmp3, xlen, 1); 3123 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 3124 subsw(tmp3, tmp3, 1); 3125 br(Assembler::MI, L_done); 3126 3127 lsr(carry, carry, 32); 3128 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 3129 b(L_second_loop); 3130 3131 // Next infrequent code is moved outside loops. 3132 bind(L_last_x); 3133 ldrw(product_hi, Address(x, 0)); 3134 b(L_third_loop_prologue); 3135 3136 bind(L_done); 3137 } 3138 3139 // Code for BigInteger::mulAdd instrinsic 3140 // out = r0 3141 // in = r1 3142 // offset = r2 (already out.length-offset) 3143 // len = r3 3144 // k = r4 3145 // 3146 // pseudo code from java implementation: 3147 // carry = 0; 3148 // offset = out.length-offset - 1; 3149 // for (int j=len-1; j >= 0; j--) { 3150 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry; 3151 // out[offset--] = (int)product; 3152 // carry = product >>> 32; 3153 // } 3154 // return (int)carry; 3155 void MacroAssembler::mul_add(Register out, Register in, Register offset, 3156 Register len, Register k) { 3157 Label LOOP, END; 3158 // pre-loop 3159 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches 3160 csel(out, zr, out, Assembler::EQ); 3161 br(Assembler::EQ, END); 3162 add(in, in, len, LSL, 2); // in[j+1] address 3163 add(offset, out, offset, LSL, 2); // out[offset + 1] address 3164 mov(out, zr); // used to keep carry now 3165 BIND(LOOP); 3166 ldrw(rscratch1, Address(pre(in, -4))); 3167 madd(rscratch1, rscratch1, k, out); 3168 ldrw(rscratch2, Address(pre(offset, -4))); 3169 add(rscratch1, rscratch1, rscratch2); 3170 strw(rscratch1, Address(offset)); 3171 lsr(out, rscratch1, 32); 3172 subs(len, len, 1); 3173 br(Assembler::NE, LOOP); 3174 BIND(END); 3175 } 3176 3177 /** 3178 * Emits code to update CRC-32 with a byte value according to constants in table 3179 * 3180 * @param [in,out]crc Register containing the crc. 3181 * @param [in]val Register containing the byte to fold into the CRC. 3182 * @param [in]table Register containing the table of crc constants. 3183 * 3184 * uint32_t crc; 3185 * val = crc_table[(val ^ crc) & 0xFF]; 3186 * crc = val ^ (crc >> 8); 3187 * 3188 */ 3189 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 3190 eor(val, val, crc); 3191 andr(val, val, 0xff); 3192 ldrw(val, Address(table, val, Address::lsl(2))); 3193 eor(crc, val, crc, Assembler::LSR, 8); 3194 } 3195 3196 /** 3197 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 3198 * 3199 * @param [in,out]crc Register containing the crc. 3200 * @param [in]v Register containing the 32-bit to fold into the CRC. 3201 * @param [in]table0 Register containing table 0 of crc constants. 3202 * @param [in]table1 Register containing table 1 of crc constants. 3203 * @param [in]table2 Register containing table 2 of crc constants. 3204 * @param [in]table3 Register containing table 3 of crc constants. 3205 * 3206 * uint32_t crc; 3207 * v = crc ^ v 3208 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 3209 * 3210 */ 3211 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 3212 Register table0, Register table1, Register table2, Register table3, 3213 bool upper) { 3214 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 3215 uxtb(tmp, v); 3216 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 3217 ubfx(tmp, v, 8, 8); 3218 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 3219 eor(crc, crc, tmp); 3220 ubfx(tmp, v, 16, 8); 3221 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 3222 eor(crc, crc, tmp); 3223 ubfx(tmp, v, 24, 8); 3224 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 3225 eor(crc, crc, tmp); 3226 } 3227 3228 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf, 3229 Register len, Register tmp0, Register tmp1, Register tmp2, 3230 Register tmp3) { 3231 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 3232 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 3233 3234 mvnw(crc, crc); 3235 3236 subs(len, len, 128); 3237 br(Assembler::GE, CRC_by64_pre); 3238 BIND(CRC_less64); 3239 adds(len, len, 128-32); 3240 br(Assembler::GE, CRC_by32_loop); 3241 BIND(CRC_less32); 3242 adds(len, len, 32-4); 3243 br(Assembler::GE, CRC_by4_loop); 3244 adds(len, len, 4); 3245 br(Assembler::GT, CRC_by1_loop); 3246 b(L_exit); 3247 3248 BIND(CRC_by32_loop); 3249 ldp(tmp0, tmp1, Address(post(buf, 16))); 3250 subs(len, len, 32); 3251 crc32x(crc, crc, tmp0); 3252 ldr(tmp2, Address(post(buf, 8))); 3253 crc32x(crc, crc, tmp1); 3254 ldr(tmp3, Address(post(buf, 8))); 3255 crc32x(crc, crc, tmp2); 3256 crc32x(crc, crc, tmp3); 3257 br(Assembler::GE, CRC_by32_loop); 3258 cmn(len, 32); 3259 br(Assembler::NE, CRC_less32); 3260 b(L_exit); 3261 3262 BIND(CRC_by4_loop); 3263 ldrw(tmp0, Address(post(buf, 4))); 3264 subs(len, len, 4); 3265 crc32w(crc, crc, tmp0); 3266 br(Assembler::GE, CRC_by4_loop); 3267 adds(len, len, 4); 3268 br(Assembler::LE, L_exit); 3269 BIND(CRC_by1_loop); 3270 ldrb(tmp0, Address(post(buf, 1))); 3271 subs(len, len, 1); 3272 crc32b(crc, crc, tmp0); 3273 br(Assembler::GT, CRC_by1_loop); 3274 b(L_exit); 3275 3276 BIND(CRC_by64_pre); 3277 sub(buf, buf, 8); 3278 ldp(tmp0, tmp1, Address(buf, 8)); 3279 crc32x(crc, crc, tmp0); 3280 ldr(tmp2, Address(buf, 24)); 3281 crc32x(crc, crc, tmp1); 3282 ldr(tmp3, Address(buf, 32)); 3283 crc32x(crc, crc, tmp2); 3284 ldr(tmp0, Address(buf, 40)); 3285 crc32x(crc, crc, tmp3); 3286 ldr(tmp1, Address(buf, 48)); 3287 crc32x(crc, crc, tmp0); 3288 ldr(tmp2, Address(buf, 56)); 3289 crc32x(crc, crc, tmp1); 3290 ldr(tmp3, Address(pre(buf, 64))); 3291 3292 b(CRC_by64_loop); 3293 3294 align(CodeEntryAlignment); 3295 BIND(CRC_by64_loop); 3296 subs(len, len, 64); 3297 crc32x(crc, crc, tmp2); 3298 ldr(tmp0, Address(buf, 8)); 3299 crc32x(crc, crc, tmp3); 3300 ldr(tmp1, Address(buf, 16)); 3301 crc32x(crc, crc, tmp0); 3302 ldr(tmp2, Address(buf, 24)); 3303 crc32x(crc, crc, tmp1); 3304 ldr(tmp3, Address(buf, 32)); 3305 crc32x(crc, crc, tmp2); 3306 ldr(tmp0, Address(buf, 40)); 3307 crc32x(crc, crc, tmp3); 3308 ldr(tmp1, Address(buf, 48)); 3309 crc32x(crc, crc, tmp0); 3310 ldr(tmp2, Address(buf, 56)); 3311 crc32x(crc, crc, tmp1); 3312 ldr(tmp3, Address(pre(buf, 64))); 3313 br(Assembler::GE, CRC_by64_loop); 3314 3315 // post-loop 3316 crc32x(crc, crc, tmp2); 3317 crc32x(crc, crc, tmp3); 3318 3319 sub(len, len, 64); 3320 add(buf, buf, 8); 3321 cmn(len, 128); 3322 br(Assembler::NE, CRC_less64); 3323 BIND(L_exit); 3324 mvnw(crc, crc); 3325 } 3326 3327 /** 3328 * @param crc register containing existing CRC (32-bit) 3329 * @param buf register pointing to input byte buffer (byte*) 3330 * @param len register containing number of bytes 3331 * @param table register that will contain address of CRC table 3332 * @param tmp scratch register 3333 */ 3334 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 3335 Register table0, Register table1, Register table2, Register table3, 3336 Register tmp, Register tmp2, Register tmp3) { 3337 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 3338 uint64_t offset; 3339 3340 if (UseCRC32) { 3341 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3); 3342 return; 3343 } 3344 3345 mvnw(crc, crc); 3346 3347 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 3348 if (offset) add(table0, table0, offset); 3349 add(table1, table0, 1*256*sizeof(juint)); 3350 add(table2, table0, 2*256*sizeof(juint)); 3351 add(table3, table0, 3*256*sizeof(juint)); 3352 3353 if (UseNeon) { 3354 cmp(len, (u1)64); 3355 br(Assembler::LT, L_by16); 3356 eor(v16, T16B, v16, v16); 3357 3358 Label L_fold; 3359 3360 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 3361 3362 ld1(v0, v1, T2D, post(buf, 32)); 3363 ld1r(v4, T2D, post(tmp, 8)); 3364 ld1r(v5, T2D, post(tmp, 8)); 3365 ld1r(v6, T2D, post(tmp, 8)); 3366 ld1r(v7, T2D, post(tmp, 8)); 3367 mov(v16, T4S, 0, crc); 3368 3369 eor(v0, T16B, v0, v16); 3370 sub(len, len, 64); 3371 3372 BIND(L_fold); 3373 pmull(v22, T8H, v0, v5, T8B); 3374 pmull(v20, T8H, v0, v7, T8B); 3375 pmull(v23, T8H, v0, v4, T8B); 3376 pmull(v21, T8H, v0, v6, T8B); 3377 3378 pmull2(v18, T8H, v0, v5, T16B); 3379 pmull2(v16, T8H, v0, v7, T16B); 3380 pmull2(v19, T8H, v0, v4, T16B); 3381 pmull2(v17, T8H, v0, v6, T16B); 3382 3383 uzp1(v24, T8H, v20, v22); 3384 uzp2(v25, T8H, v20, v22); 3385 eor(v20, T16B, v24, v25); 3386 3387 uzp1(v26, T8H, v16, v18); 3388 uzp2(v27, T8H, v16, v18); 3389 eor(v16, T16B, v26, v27); 3390 3391 ushll2(v22, T4S, v20, T8H, 8); 3392 ushll(v20, T4S, v20, T4H, 8); 3393 3394 ushll2(v18, T4S, v16, T8H, 8); 3395 ushll(v16, T4S, v16, T4H, 8); 3396 3397 eor(v22, T16B, v23, v22); 3398 eor(v18, T16B, v19, v18); 3399 eor(v20, T16B, v21, v20); 3400 eor(v16, T16B, v17, v16); 3401 3402 uzp1(v17, T2D, v16, v20); 3403 uzp2(v21, T2D, v16, v20); 3404 eor(v17, T16B, v17, v21); 3405 3406 ushll2(v20, T2D, v17, T4S, 16); 3407 ushll(v16, T2D, v17, T2S, 16); 3408 3409 eor(v20, T16B, v20, v22); 3410 eor(v16, T16B, v16, v18); 3411 3412 uzp1(v17, T2D, v20, v16); 3413 uzp2(v21, T2D, v20, v16); 3414 eor(v28, T16B, v17, v21); 3415 3416 pmull(v22, T8H, v1, v5, T8B); 3417 pmull(v20, T8H, v1, v7, T8B); 3418 pmull(v23, T8H, v1, v4, T8B); 3419 pmull(v21, T8H, v1, v6, T8B); 3420 3421 pmull2(v18, T8H, v1, v5, T16B); 3422 pmull2(v16, T8H, v1, v7, T16B); 3423 pmull2(v19, T8H, v1, v4, T16B); 3424 pmull2(v17, T8H, v1, v6, T16B); 3425 3426 ld1(v0, v1, T2D, post(buf, 32)); 3427 3428 uzp1(v24, T8H, v20, v22); 3429 uzp2(v25, T8H, v20, v22); 3430 eor(v20, T16B, v24, v25); 3431 3432 uzp1(v26, T8H, v16, v18); 3433 uzp2(v27, T8H, v16, v18); 3434 eor(v16, T16B, v26, v27); 3435 3436 ushll2(v22, T4S, v20, T8H, 8); 3437 ushll(v20, T4S, v20, T4H, 8); 3438 3439 ushll2(v18, T4S, v16, T8H, 8); 3440 ushll(v16, T4S, v16, T4H, 8); 3441 3442 eor(v22, T16B, v23, v22); 3443 eor(v18, T16B, v19, v18); 3444 eor(v20, T16B, v21, v20); 3445 eor(v16, T16B, v17, v16); 3446 3447 uzp1(v17, T2D, v16, v20); 3448 uzp2(v21, T2D, v16, v20); 3449 eor(v16, T16B, v17, v21); 3450 3451 ushll2(v20, T2D, v16, T4S, 16); 3452 ushll(v16, T2D, v16, T2S, 16); 3453 3454 eor(v20, T16B, v22, v20); 3455 eor(v16, T16B, v16, v18); 3456 3457 uzp1(v17, T2D, v20, v16); 3458 uzp2(v21, T2D, v20, v16); 3459 eor(v20, T16B, v17, v21); 3460 3461 shl(v16, T2D, v28, 1); 3462 shl(v17, T2D, v20, 1); 3463 3464 eor(v0, T16B, v0, v16); 3465 eor(v1, T16B, v1, v17); 3466 3467 subs(len, len, 32); 3468 br(Assembler::GE, L_fold); 3469 3470 mov(crc, 0); 3471 mov(tmp, v0, T1D, 0); 3472 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3473 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3474 mov(tmp, v0, T1D, 1); 3475 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3476 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3477 mov(tmp, v1, T1D, 0); 3478 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3479 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3480 mov(tmp, v1, T1D, 1); 3481 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3482 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3483 3484 add(len, len, 32); 3485 } 3486 3487 BIND(L_by16); 3488 subs(len, len, 16); 3489 br(Assembler::GE, L_by16_loop); 3490 adds(len, len, 16-4); 3491 br(Assembler::GE, L_by4_loop); 3492 adds(len, len, 4); 3493 br(Assembler::GT, L_by1_loop); 3494 b(L_exit); 3495 3496 BIND(L_by4_loop); 3497 ldrw(tmp, Address(post(buf, 4))); 3498 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 3499 subs(len, len, 4); 3500 br(Assembler::GE, L_by4_loop); 3501 adds(len, len, 4); 3502 br(Assembler::LE, L_exit); 3503 BIND(L_by1_loop); 3504 subs(len, len, 1); 3505 ldrb(tmp, Address(post(buf, 1))); 3506 update_byte_crc32(crc, tmp, table0); 3507 br(Assembler::GT, L_by1_loop); 3508 b(L_exit); 3509 3510 align(CodeEntryAlignment); 3511 BIND(L_by16_loop); 3512 subs(len, len, 16); 3513 ldp(tmp, tmp3, Address(post(buf, 16))); 3514 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3515 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3516 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 3517 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 3518 br(Assembler::GE, L_by16_loop); 3519 adds(len, len, 16-4); 3520 br(Assembler::GE, L_by4_loop); 3521 adds(len, len, 4); 3522 br(Assembler::GT, L_by1_loop); 3523 BIND(L_exit); 3524 mvnw(crc, crc); 3525 } 3526 3527 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf, 3528 Register len, Register tmp0, Register tmp1, Register tmp2, 3529 Register tmp3) { 3530 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 3531 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 3532 3533 subs(len, len, 128); 3534 br(Assembler::GE, CRC_by64_pre); 3535 BIND(CRC_less64); 3536 adds(len, len, 128-32); 3537 br(Assembler::GE, CRC_by32_loop); 3538 BIND(CRC_less32); 3539 adds(len, len, 32-4); 3540 br(Assembler::GE, CRC_by4_loop); 3541 adds(len, len, 4); 3542 br(Assembler::GT, CRC_by1_loop); 3543 b(L_exit); 3544 3545 BIND(CRC_by32_loop); 3546 ldp(tmp0, tmp1, Address(post(buf, 16))); 3547 subs(len, len, 32); 3548 crc32cx(crc, crc, tmp0); 3549 ldr(tmp2, Address(post(buf, 8))); 3550 crc32cx(crc, crc, tmp1); 3551 ldr(tmp3, Address(post(buf, 8))); 3552 crc32cx(crc, crc, tmp2); 3553 crc32cx(crc, crc, tmp3); 3554 br(Assembler::GE, CRC_by32_loop); 3555 cmn(len, 32); 3556 br(Assembler::NE, CRC_less32); 3557 b(L_exit); 3558 3559 BIND(CRC_by4_loop); 3560 ldrw(tmp0, Address(post(buf, 4))); 3561 subs(len, len, 4); 3562 crc32cw(crc, crc, tmp0); 3563 br(Assembler::GE, CRC_by4_loop); 3564 adds(len, len, 4); 3565 br(Assembler::LE, L_exit); 3566 BIND(CRC_by1_loop); 3567 ldrb(tmp0, Address(post(buf, 1))); 3568 subs(len, len, 1); 3569 crc32cb(crc, crc, tmp0); 3570 br(Assembler::GT, CRC_by1_loop); 3571 b(L_exit); 3572 3573 BIND(CRC_by64_pre); 3574 sub(buf, buf, 8); 3575 ldp(tmp0, tmp1, Address(buf, 8)); 3576 crc32cx(crc, crc, tmp0); 3577 ldr(tmp2, Address(buf, 24)); 3578 crc32cx(crc, crc, tmp1); 3579 ldr(tmp3, Address(buf, 32)); 3580 crc32cx(crc, crc, tmp2); 3581 ldr(tmp0, Address(buf, 40)); 3582 crc32cx(crc, crc, tmp3); 3583 ldr(tmp1, Address(buf, 48)); 3584 crc32cx(crc, crc, tmp0); 3585 ldr(tmp2, Address(buf, 56)); 3586 crc32cx(crc, crc, tmp1); 3587 ldr(tmp3, Address(pre(buf, 64))); 3588 3589 b(CRC_by64_loop); 3590 3591 align(CodeEntryAlignment); 3592 BIND(CRC_by64_loop); 3593 subs(len, len, 64); 3594 crc32cx(crc, crc, tmp2); 3595 ldr(tmp0, Address(buf, 8)); 3596 crc32cx(crc, crc, tmp3); 3597 ldr(tmp1, Address(buf, 16)); 3598 crc32cx(crc, crc, tmp0); 3599 ldr(tmp2, Address(buf, 24)); 3600 crc32cx(crc, crc, tmp1); 3601 ldr(tmp3, Address(buf, 32)); 3602 crc32cx(crc, crc, tmp2); 3603 ldr(tmp0, Address(buf, 40)); 3604 crc32cx(crc, crc, tmp3); 3605 ldr(tmp1, Address(buf, 48)); 3606 crc32cx(crc, crc, tmp0); 3607 ldr(tmp2, Address(buf, 56)); 3608 crc32cx(crc, crc, tmp1); 3609 ldr(tmp3, Address(pre(buf, 64))); 3610 br(Assembler::GE, CRC_by64_loop); 3611 3612 // post-loop 3613 crc32cx(crc, crc, tmp2); 3614 crc32cx(crc, crc, tmp3); 3615 3616 sub(len, len, 64); 3617 add(buf, buf, 8); 3618 cmn(len, 128); 3619 br(Assembler::NE, CRC_less64); 3620 BIND(L_exit); 3621 } 3622 3623 /** 3624 * @param crc register containing existing CRC (32-bit) 3625 * @param buf register pointing to input byte buffer (byte*) 3626 * @param len register containing number of bytes 3627 * @param table register that will contain address of CRC table 3628 * @param tmp scratch register 3629 */ 3630 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3631 Register table0, Register table1, Register table2, Register table3, 3632 Register tmp, Register tmp2, Register tmp3) { 3633 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3); 3634 } 3635 3636 3637 SkipIfEqual::SkipIfEqual( 3638 MacroAssembler* masm, const bool* flag_addr, bool value) { 3639 _masm = masm; 3640 uint64_t offset; 3641 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3642 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3643 _masm->cbzw(rscratch1, _label); 3644 } 3645 3646 SkipIfEqual::~SkipIfEqual() { 3647 _masm->bind(_label); 3648 } 3649 3650 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3651 Address adr; 3652 switch(dst.getMode()) { 3653 case Address::base_plus_offset: 3654 // This is the expected mode, although we allow all the other 3655 // forms below. 3656 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3657 break; 3658 default: 3659 lea(rscratch2, dst); 3660 adr = Address(rscratch2); 3661 break; 3662 } 3663 ldr(rscratch1, adr); 3664 add(rscratch1, rscratch1, src); 3665 str(rscratch1, adr); 3666 } 3667 3668 void MacroAssembler::cmpptr(Register src1, Address src2) { 3669 uint64_t offset; 3670 adrp(rscratch1, src2, offset); 3671 ldr(rscratch1, Address(rscratch1, offset)); 3672 cmp(src1, rscratch1); 3673 } 3674 3675 void MacroAssembler::cmpoop(Register obj1, Register obj2) { 3676 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3677 bs->obj_equals(this, obj1, obj2); 3678 } 3679 3680 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) { 3681 load_method_holder(rresult, rmethod); 3682 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset())); 3683 } 3684 3685 void MacroAssembler::load_method_holder(Register holder, Register method) { 3686 ldr(holder, Address(method, Method::const_offset())); // ConstMethod* 3687 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool* 3688 ldr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass* 3689 } 3690 3691 void MacroAssembler::load_klass(Register dst, Register src) { 3692 if (UseCompressedClassPointers) { 3693 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3694 decode_klass_not_null(dst); 3695 } else { 3696 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3697 } 3698 } 3699 3700 // ((OopHandle)result).resolve(); 3701 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { 3702 // OopHandle::resolve is an indirection. 3703 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp, noreg); 3704 } 3705 3706 // ((WeakHandle)result).resolve(); 3707 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) { 3708 assert_different_registers(rresult, rtmp); 3709 Label resolved; 3710 3711 // A null weak handle resolves to null. 3712 cbz(rresult, resolved); 3713 3714 // Only 64 bit platforms support GCs that require a tmp register 3715 // Only IN_HEAP loads require a thread_tmp register 3716 // WeakHandle::resolve is an indirection like jweak. 3717 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 3718 rresult, Address(rresult), rtmp, /*tmp_thread*/noreg); 3719 bind(resolved); 3720 } 3721 3722 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp) { 3723 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 3724 ldr(dst, Address(rmethod, Method::const_offset())); 3725 ldr(dst, Address(dst, ConstMethod::constants_offset())); 3726 ldr(dst, Address(dst, ConstantPool::pool_holder_offset_in_bytes())); 3727 ldr(dst, Address(dst, mirror_offset)); 3728 resolve_oop_handle(dst, tmp); 3729 } 3730 3731 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3732 if (UseCompressedClassPointers) { 3733 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3734 if (CompressedKlassPointers::base() == NULL) { 3735 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift()); 3736 return; 3737 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0 3738 && CompressedKlassPointers::shift() == 0) { 3739 // Only the bottom 32 bits matter 3740 cmpw(trial_klass, tmp); 3741 return; 3742 } 3743 decode_klass_not_null(tmp); 3744 } else { 3745 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3746 } 3747 cmp(trial_klass, tmp); 3748 } 3749 3750 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3751 load_klass(dst, src); 3752 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3753 } 3754 3755 void MacroAssembler::store_klass(Register dst, Register src) { 3756 // FIXME: Should this be a store release? concurrent gcs assumes 3757 // klass length is valid if klass field is not null. 3758 if (UseCompressedClassPointers) { 3759 encode_klass_not_null(src); 3760 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3761 } else { 3762 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3763 } 3764 } 3765 3766 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3767 if (UseCompressedClassPointers) { 3768 // Store to klass gap in destination 3769 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3770 } 3771 } 3772 3773 // Algorithm must match CompressedOops::encode. 3774 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3775 #ifdef ASSERT 3776 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3777 #endif 3778 verify_oop(s, "broken oop in encode_heap_oop"); 3779 if (CompressedOops::base() == NULL) { 3780 if (CompressedOops::shift() != 0) { 3781 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 3782 lsr(d, s, LogMinObjAlignmentInBytes); 3783 } else { 3784 mov(d, s); 3785 } 3786 } else { 3787 subs(d, s, rheapbase); 3788 csel(d, d, zr, Assembler::HS); 3789 lsr(d, d, LogMinObjAlignmentInBytes); 3790 3791 /* Old algorithm: is this any worse? 3792 Label nonnull; 3793 cbnz(r, nonnull); 3794 sub(r, r, rheapbase); 3795 bind(nonnull); 3796 lsr(r, r, LogMinObjAlignmentInBytes); 3797 */ 3798 } 3799 } 3800 3801 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3802 #ifdef ASSERT 3803 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3804 if (CheckCompressedOops) { 3805 Label ok; 3806 cbnz(r, ok); 3807 stop("null oop passed to encode_heap_oop_not_null"); 3808 bind(ok); 3809 } 3810 #endif 3811 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3812 if (CompressedOops::base() != NULL) { 3813 sub(r, r, rheapbase); 3814 } 3815 if (CompressedOops::shift() != 0) { 3816 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 3817 lsr(r, r, LogMinObjAlignmentInBytes); 3818 } 3819 } 3820 3821 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3822 #ifdef ASSERT 3823 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3824 if (CheckCompressedOops) { 3825 Label ok; 3826 cbnz(src, ok); 3827 stop("null oop passed to encode_heap_oop_not_null2"); 3828 bind(ok); 3829 } 3830 #endif 3831 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3832 3833 Register data = src; 3834 if (CompressedOops::base() != NULL) { 3835 sub(dst, src, rheapbase); 3836 data = dst; 3837 } 3838 if (CompressedOops::shift() != 0) { 3839 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 3840 lsr(dst, data, LogMinObjAlignmentInBytes); 3841 data = dst; 3842 } 3843 if (data == src) 3844 mov(dst, src); 3845 } 3846 3847 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3848 #ifdef ASSERT 3849 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3850 #endif 3851 if (CompressedOops::base() == NULL) { 3852 if (CompressedOops::shift() != 0 || d != s) { 3853 lsl(d, s, CompressedOops::shift()); 3854 } 3855 } else { 3856 Label done; 3857 if (d != s) 3858 mov(d, s); 3859 cbz(s, done); 3860 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3861 bind(done); 3862 } 3863 verify_oop(d, "broken oop in decode_heap_oop"); 3864 } 3865 3866 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3867 assert (UseCompressedOops, "should only be used for compressed headers"); 3868 assert (Universe::heap() != NULL, "java heap should be initialized"); 3869 // Cannot assert, unverified entry point counts instructions (see .ad file) 3870 // vtableStubs also counts instructions in pd_code_size_limit. 3871 // Also do not verify_oop as this is called by verify_oop. 3872 if (CompressedOops::shift() != 0) { 3873 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 3874 if (CompressedOops::base() != NULL) { 3875 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3876 } else { 3877 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3878 } 3879 } else { 3880 assert (CompressedOops::base() == NULL, "sanity"); 3881 } 3882 } 3883 3884 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3885 assert (UseCompressedOops, "should only be used for compressed headers"); 3886 assert (Universe::heap() != NULL, "java heap should be initialized"); 3887 // Cannot assert, unverified entry point counts instructions (see .ad file) 3888 // vtableStubs also counts instructions in pd_code_size_limit. 3889 // Also do not verify_oop as this is called by verify_oop. 3890 if (CompressedOops::shift() != 0) { 3891 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 3892 if (CompressedOops::base() != NULL) { 3893 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3894 } else { 3895 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3896 } 3897 } else { 3898 assert (CompressedOops::base() == NULL, "sanity"); 3899 if (dst != src) { 3900 mov(dst, src); 3901 } 3902 } 3903 } 3904 3905 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone); 3906 3907 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() { 3908 assert(UseCompressedClassPointers, "not using compressed class pointers"); 3909 assert(Metaspace::initialized(), "metaspace not initialized yet"); 3910 3911 if (_klass_decode_mode != KlassDecodeNone) { 3912 return _klass_decode_mode; 3913 } 3914 3915 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift() 3916 || 0 == CompressedKlassPointers::shift(), "decode alg wrong"); 3917 3918 if (CompressedKlassPointers::base() == NULL) { 3919 return (_klass_decode_mode = KlassDecodeZero); 3920 } 3921 3922 if (operand_valid_for_logical_immediate( 3923 /*is32*/false, (uint64_t)CompressedKlassPointers::base())) { 3924 const uint64_t range_mask = 3925 (1UL << log2_intptr(CompressedKlassPointers::range())) - 1; 3926 if (((uint64_t)CompressedKlassPointers::base() & range_mask) == 0) { 3927 return (_klass_decode_mode = KlassDecodeXor); 3928 } 3929 } 3930 3931 const uint64_t shifted_base = 3932 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift(); 3933 guarantee((shifted_base & 0xffff0000ffffffff) == 0, 3934 "compressed class base bad alignment"); 3935 3936 return (_klass_decode_mode = KlassDecodeMovk); 3937 } 3938 3939 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3940 switch (klass_decode_mode()) { 3941 case KlassDecodeZero: 3942 if (CompressedKlassPointers::shift() != 0) { 3943 lsr(dst, src, LogKlassAlignmentInBytes); 3944 } else { 3945 if (dst != src) mov(dst, src); 3946 } 3947 break; 3948 3949 case KlassDecodeXor: 3950 if (CompressedKlassPointers::shift() != 0) { 3951 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 3952 lsr(dst, dst, LogKlassAlignmentInBytes); 3953 } else { 3954 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 3955 } 3956 break; 3957 3958 case KlassDecodeMovk: 3959 if (CompressedKlassPointers::shift() != 0) { 3960 ubfx(dst, src, LogKlassAlignmentInBytes, 32); 3961 } else { 3962 movw(dst, src); 3963 } 3964 break; 3965 3966 case KlassDecodeNone: 3967 ShouldNotReachHere(); 3968 break; 3969 } 3970 } 3971 3972 void MacroAssembler::encode_klass_not_null(Register r) { 3973 encode_klass_not_null(r, r); 3974 } 3975 3976 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3977 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3978 3979 switch (klass_decode_mode()) { 3980 case KlassDecodeZero: 3981 if (CompressedKlassPointers::shift() != 0) { 3982 lsl(dst, src, LogKlassAlignmentInBytes); 3983 } else { 3984 if (dst != src) mov(dst, src); 3985 } 3986 break; 3987 3988 case KlassDecodeXor: 3989 if (CompressedKlassPointers::shift() != 0) { 3990 lsl(dst, src, LogKlassAlignmentInBytes); 3991 eor(dst, dst, (uint64_t)CompressedKlassPointers::base()); 3992 } else { 3993 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 3994 } 3995 break; 3996 3997 case KlassDecodeMovk: { 3998 const uint64_t shifted_base = 3999 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift(); 4000 4001 if (dst != src) movw(dst, src); 4002 movk(dst, shifted_base >> 32, 32); 4003 4004 if (CompressedKlassPointers::shift() != 0) { 4005 lsl(dst, dst, LogKlassAlignmentInBytes); 4006 } 4007 4008 break; 4009 } 4010 4011 case KlassDecodeNone: 4012 ShouldNotReachHere(); 4013 break; 4014 } 4015 } 4016 4017 void MacroAssembler::decode_klass_not_null(Register r) { 4018 decode_klass_not_null(r, r); 4019 } 4020 4021 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 4022 #ifdef ASSERT 4023 { 4024 ThreadInVMfromUnknown tiv; 4025 assert (UseCompressedOops, "should only be used for compressed oops"); 4026 assert (Universe::heap() != NULL, "java heap should be initialized"); 4027 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4028 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop"); 4029 } 4030 #endif 4031 int oop_index = oop_recorder()->find_index(obj); 4032 InstructionMark im(this); 4033 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4034 code_section()->relocate(inst_mark(), rspec); 4035 movz(dst, 0xDEAD, 16); 4036 movk(dst, 0xBEEF); 4037 } 4038 4039 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 4040 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4041 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4042 int index = oop_recorder()->find_index(k); 4043 assert(! Universe::heap()->is_in(k), "should not be an oop"); 4044 4045 InstructionMark im(this); 4046 RelocationHolder rspec = metadata_Relocation::spec(index); 4047 code_section()->relocate(inst_mark(), rspec); 4048 narrowKlass nk = CompressedKlassPointers::encode(k); 4049 movz(dst, (nk >> 16), 16); 4050 movk(dst, nk & 0xffff); 4051 } 4052 4053 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, 4054 Register dst, Address src, 4055 Register tmp1, Register thread_tmp) { 4056 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4057 decorators = AccessInternal::decorator_fixup(decorators); 4058 bool as_raw = (decorators & AS_RAW) != 0; 4059 if (as_raw) { 4060 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4061 } else { 4062 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4063 } 4064 } 4065 4066 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, 4067 Address dst, Register src, 4068 Register tmp1, Register thread_tmp) { 4069 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4070 decorators = AccessInternal::decorator_fixup(decorators); 4071 bool as_raw = (decorators & AS_RAW) != 0; 4072 if (as_raw) { 4073 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4074 } else { 4075 bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4076 } 4077 } 4078 4079 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) { 4080 // Use stronger ACCESS_WRITE|ACCESS_READ by default. 4081 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) { 4082 decorators |= ACCESS_READ | ACCESS_WRITE; 4083 } 4084 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4085 return bs->resolve(this, decorators, obj); 4086 } 4087 4088 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 4089 Register thread_tmp, DecoratorSet decorators) { 4090 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 4091 } 4092 4093 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 4094 Register thread_tmp, DecoratorSet decorators) { 4095 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); 4096 } 4097 4098 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1, 4099 Register thread_tmp, DecoratorSet decorators) { 4100 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 4101 } 4102 4103 // Used for storing NULLs. 4104 void MacroAssembler::store_heap_oop_null(Address dst) { 4105 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg); 4106 } 4107 4108 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 4109 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 4110 int index = oop_recorder()->allocate_metadata_index(obj); 4111 RelocationHolder rspec = metadata_Relocation::spec(index); 4112 return Address((address)obj, rspec); 4113 } 4114 4115 // Move an oop into a register. immediate is true if we want 4116 // immediate instructions and nmethod entry barriers are not enabled. 4117 // i.e. we are not going to patch this instruction while the code is being 4118 // executed by another thread. 4119 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 4120 int oop_index; 4121 if (obj == NULL) { 4122 oop_index = oop_recorder()->allocate_oop_index(obj); 4123 } else { 4124 #ifdef ASSERT 4125 { 4126 ThreadInVMfromUnknown tiv; 4127 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop"); 4128 } 4129 #endif 4130 oop_index = oop_recorder()->find_index(obj); 4131 } 4132 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4133 4134 // nmethod entry barrier necessitate using the constant pool. They have to be 4135 // ordered with respected to oop accesses. 4136 // Using immediate literals would necessitate ISBs. 4137 if (BarrierSet::barrier_set()->barrier_set_nmethod() != NULL || !immediate) { 4138 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 4139 ldr_constant(dst, Address(dummy, rspec)); 4140 } else 4141 mov(dst, Address((address)obj, rspec)); 4142 4143 } 4144 4145 // Move a metadata address into a register. 4146 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 4147 int oop_index; 4148 if (obj == NULL) { 4149 oop_index = oop_recorder()->allocate_metadata_index(obj); 4150 } else { 4151 oop_index = oop_recorder()->find_index(obj); 4152 } 4153 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 4154 mov(dst, Address((address)obj, rspec)); 4155 } 4156 4157 Address MacroAssembler::constant_oop_address(jobject obj) { 4158 #ifdef ASSERT 4159 { 4160 ThreadInVMfromUnknown tiv; 4161 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4162 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop"); 4163 } 4164 #endif 4165 int oop_index = oop_recorder()->find_index(obj); 4166 return Address((address)obj, oop_Relocation::spec(oop_index)); 4167 } 4168 4169 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 4170 void MacroAssembler::tlab_allocate(Register obj, 4171 Register var_size_in_bytes, 4172 int con_size_in_bytes, 4173 Register t1, 4174 Register t2, 4175 Label& slow_case) { 4176 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4177 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 4178 } 4179 4180 // Defines obj, preserves var_size_in_bytes 4181 void MacroAssembler::eden_allocate(Register obj, 4182 Register var_size_in_bytes, 4183 int con_size_in_bytes, 4184 Register t1, 4185 Label& slow_case) { 4186 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4187 bs->eden_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case); 4188 } 4189 4190 // Zero words; len is in bytes 4191 // Destroys all registers except addr 4192 // len must be a nonzero multiple of wordSize 4193 void MacroAssembler::zero_memory(Register addr, Register len, Register t1) { 4194 assert_different_registers(addr, len, t1, rscratch1, rscratch2); 4195 4196 #ifdef ASSERT 4197 { Label L; 4198 tst(len, BytesPerWord - 1); 4199 br(Assembler::EQ, L); 4200 stop("len is not a multiple of BytesPerWord"); 4201 bind(L); 4202 } 4203 #endif 4204 4205 #ifndef PRODUCT 4206 block_comment("zero memory"); 4207 #endif 4208 4209 Label loop; 4210 Label entry; 4211 4212 // Algorithm: 4213 // 4214 // scratch1 = cnt & 7; 4215 // cnt -= scratch1; 4216 // p += scratch1; 4217 // switch (scratch1) { 4218 // do { 4219 // cnt -= 8; 4220 // p[-8] = 0; 4221 // case 7: 4222 // p[-7] = 0; 4223 // case 6: 4224 // p[-6] = 0; 4225 // // ... 4226 // case 1: 4227 // p[-1] = 0; 4228 // case 0: 4229 // p += 8; 4230 // } while (cnt); 4231 // } 4232 4233 const int unroll = 8; // Number of str(zr) instructions we'll unroll 4234 4235 lsr(len, len, LogBytesPerWord); 4236 andr(rscratch1, len, unroll - 1); // tmp1 = cnt % unroll 4237 sub(len, len, rscratch1); // cnt -= unroll 4238 // t1 always points to the end of the region we're about to zero 4239 add(t1, addr, rscratch1, Assembler::LSL, LogBytesPerWord); 4240 adr(rscratch2, entry); 4241 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2); 4242 br(rscratch2); 4243 bind(loop); 4244 sub(len, len, unroll); 4245 for (int i = -unroll; i < 0; i++) 4246 Assembler::str(zr, Address(t1, i * wordSize)); 4247 bind(entry); 4248 add(t1, t1, unroll * wordSize); 4249 cbnz(len, loop); 4250 } 4251 4252 void MacroAssembler::verify_tlab() { 4253 #ifdef ASSERT 4254 if (UseTLAB && VerifyOops) { 4255 Label next, ok; 4256 4257 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 4258 4259 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4260 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 4261 cmp(rscratch2, rscratch1); 4262 br(Assembler::HS, next); 4263 STOP("assert(top >= start)"); 4264 should_not_reach_here(); 4265 4266 bind(next); 4267 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 4268 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 4269 cmp(rscratch2, rscratch1); 4270 br(Assembler::HS, ok); 4271 STOP("assert(top <= end)"); 4272 should_not_reach_here(); 4273 4274 bind(ok); 4275 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 4276 } 4277 #endif 4278 } 4279 4280 // Writes to stack successive pages until offset reached to check for 4281 // stack overflow + shadow pages. This clobbers tmp. 4282 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 4283 assert_different_registers(tmp, size, rscratch1); 4284 mov(tmp, sp); 4285 // Bang stack for total size given plus shadow page size. 4286 // Bang one page at a time because large size can bang beyond yellow and 4287 // red zones. 4288 Label loop; 4289 mov(rscratch1, os::vm_page_size()); 4290 bind(loop); 4291 lea(tmp, Address(tmp, -os::vm_page_size())); 4292 subsw(size, size, rscratch1); 4293 str(size, Address(tmp)); 4294 br(Assembler::GT, loop); 4295 4296 // Bang down shadow pages too. 4297 // At this point, (tmp-0) is the last address touched, so don't 4298 // touch it again. (It was touched as (tmp-pagesize) but then tmp 4299 // was post-decremented.) Skip this address by starting at i=1, and 4300 // touch a few more pages below. N.B. It is important to touch all 4301 // the way down to and including i=StackShadowPages. 4302 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { 4303 // this could be any sized move but this is can be a debugging crumb 4304 // so the bigger the better. 4305 lea(tmp, Address(tmp, -os::vm_page_size())); 4306 str(size, Address(tmp)); 4307 } 4308 } 4309 4310 // Move the address of the polling page into dest. 4311 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) { 4312 ldr(dest, Address(rthread, Thread::polling_page_offset())); 4313 } 4314 4315 // Move the address of the polling page into r, then read the polling 4316 // page. 4317 address MacroAssembler::fetch_and_read_polling_page(Register r, relocInfo::relocType rtype) { 4318 get_polling_page(r, rtype); 4319 return read_polling_page(r, rtype); 4320 } 4321 4322 // Read the polling page. The address of the polling page must 4323 // already be in r. 4324 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 4325 InstructionMark im(this); 4326 code_section()->relocate(inst_mark(), rtype); 4327 ldrw(zr, Address(r, 0)); 4328 return inst_mark(); 4329 } 4330 4331 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) { 4332 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 4333 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12; 4334 uint64_t high_page = (uint64_t)(CodeCache::high_bound() - 1) >> 12; 4335 uint64_t dest_page = (uint64_t)dest.target() >> 12; 4336 int64_t offset_low = dest_page - low_page; 4337 int64_t offset_high = dest_page - high_page; 4338 4339 assert(is_valid_AArch64_address(dest.target()), "bad address"); 4340 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 4341 4342 InstructionMark im(this); 4343 code_section()->relocate(inst_mark(), dest.rspec()); 4344 // 8143067: Ensure that the adrp can reach the dest from anywhere within 4345 // the code cache so that if it is relocated we know it will still reach 4346 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 4347 _adrp(reg1, dest.target()); 4348 } else { 4349 uint64_t target = (uint64_t)dest.target(); 4350 uint64_t adrp_target 4351 = (target & 0xffffffffUL) | ((uint64_t)pc() & 0xffff00000000UL); 4352 4353 _adrp(reg1, (address)adrp_target); 4354 movk(reg1, target >> 32, 32); 4355 } 4356 byte_offset = (uint64_t)dest.target() & 0xfff; 4357 } 4358 4359 void MacroAssembler::load_byte_map_base(Register reg) { 4360 CardTable::CardValue* byte_map_base = 4361 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base(); 4362 4363 if (is_valid_AArch64_address((address)byte_map_base)) { 4364 // Strictly speaking the byte_map_base isn't an address at all, 4365 // and it might even be negative. 4366 uint64_t offset; 4367 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4368 // We expect offset to be zero with most collectors. 4369 if (offset != 0) { 4370 add(reg, reg, offset); 4371 } 4372 } else { 4373 mov(reg, (uint64_t)byte_map_base); 4374 } 4375 } 4376 4377 void MacroAssembler::build_frame(int framesize) { 4378 assert(framesize > 0, "framesize must be > 0"); 4379 if (framesize < ((1 << 9) + 2 * wordSize)) { 4380 sub(sp, sp, framesize); 4381 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4382 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4383 } else { 4384 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4385 if (PreserveFramePointer) mov(rfp, sp); 4386 if (framesize < ((1 << 12) + 2 * wordSize)) 4387 sub(sp, sp, framesize - 2 * wordSize); 4388 else { 4389 mov(rscratch1, framesize - 2 * wordSize); 4390 sub(sp, sp, rscratch1); 4391 } 4392 } 4393 } 4394 4395 void MacroAssembler::remove_frame(int framesize) { 4396 assert(framesize > 0, "framesize must be > 0"); 4397 if (framesize < ((1 << 9) + 2 * wordSize)) { 4398 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4399 add(sp, sp, framesize); 4400 } else { 4401 if (framesize < ((1 << 12) + 2 * wordSize)) 4402 add(sp, sp, framesize - 2 * wordSize); 4403 else { 4404 mov(rscratch1, framesize - 2 * wordSize); 4405 add(sp, sp, rscratch1); 4406 } 4407 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4408 } 4409 } 4410 4411 // This method checks if provided byte array contains byte with highest bit set. 4412 void MacroAssembler::has_negatives(Register ary1, Register len, Register result) { 4413 // Simple and most common case of aligned small array which is not at the 4414 // end of memory page is placed here. All other cases are in stub. 4415 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; 4416 const uint64_t UPPER_BIT_MASK=0x8080808080808080; 4417 assert_different_registers(ary1, len, result); 4418 4419 cmpw(len, 0); 4420 br(LE, SET_RESULT); 4421 cmpw(len, 4 * wordSize); 4422 br(GE, STUB_LONG); // size > 32 then go to stub 4423 4424 int shift = 64 - exact_log2(os::vm_page_size()); 4425 lsl(rscratch1, ary1, shift); 4426 mov(rscratch2, (size_t)(4 * wordSize) << shift); 4427 adds(rscratch2, rscratch1, rscratch2); // At end of page? 4428 br(CS, STUB); // at the end of page then go to stub 4429 subs(len, len, wordSize); 4430 br(LT, END); 4431 4432 BIND(LOOP); 4433 ldr(rscratch1, Address(post(ary1, wordSize))); 4434 tst(rscratch1, UPPER_BIT_MASK); 4435 br(NE, SET_RESULT); 4436 subs(len, len, wordSize); 4437 br(GE, LOOP); 4438 cmpw(len, -wordSize); 4439 br(EQ, SET_RESULT); 4440 4441 BIND(END); 4442 ldr(result, Address(ary1)); 4443 sub(len, zr, len, LSL, 3); // LSL 3 is to get bits from bytes 4444 lslv(result, result, len); 4445 tst(result, UPPER_BIT_MASK); 4446 b(SET_RESULT); 4447 4448 BIND(STUB); 4449 RuntimeAddress has_neg = RuntimeAddress(StubRoutines::aarch64::has_negatives()); 4450 assert(has_neg.target() != NULL, "has_negatives stub has not been generated"); 4451 trampoline_call(has_neg); 4452 b(DONE); 4453 4454 BIND(STUB_LONG); 4455 RuntimeAddress has_neg_long = RuntimeAddress( 4456 StubRoutines::aarch64::has_negatives_long()); 4457 assert(has_neg_long.target() != NULL, "has_negatives stub has not been generated"); 4458 trampoline_call(has_neg_long); 4459 b(DONE); 4460 4461 BIND(SET_RESULT); 4462 cset(result, NE); // set true or false 4463 4464 BIND(DONE); 4465 } 4466 4467 void MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3, 4468 Register tmp4, Register tmp5, Register result, 4469 Register cnt1, int elem_size) { 4470 Label DONE, SAME; 4471 Register tmp1 = rscratch1; 4472 Register tmp2 = rscratch2; 4473 Register cnt2 = tmp2; // cnt2 only used in array length compare 4474 int elem_per_word = wordSize/elem_size; 4475 int log_elem_size = exact_log2(elem_size); 4476 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4477 int base_offset 4478 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); 4479 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16); 4480 4481 assert(elem_size == 1 || elem_size == 2, "must be char or byte"); 4482 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 4483 4484 #ifndef PRODUCT 4485 { 4486 const char kind = (elem_size == 2) ? 'U' : 'L'; 4487 char comment[64]; 4488 snprintf(comment, sizeof comment, "array_equals%c{", kind); 4489 BLOCK_COMMENT(comment); 4490 } 4491 #endif 4492 4493 // if (a1 == a2) 4494 // return true; 4495 cmpoop(a1, a2); // May have read barriers for a1 and a2. 4496 br(EQ, SAME); 4497 4498 if (UseSimpleArrayEquals) { 4499 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL; 4500 // if (a1 == null || a2 == null) 4501 // return false; 4502 // a1 & a2 == 0 means (some-pointer is null) or 4503 // (very-rare-or-even-probably-impossible-pointer-values) 4504 // so, we can save one branch in most cases 4505 tst(a1, a2); 4506 mov(result, false); 4507 br(EQ, A_MIGHT_BE_NULL); 4508 // if (a1.length != a2.length) 4509 // return false; 4510 bind(A_IS_NOT_NULL); 4511 ldrw(cnt1, Address(a1, length_offset)); 4512 ldrw(cnt2, Address(a2, length_offset)); 4513 eorw(tmp5, cnt1, cnt2); 4514 cbnzw(tmp5, DONE); 4515 lea(a1, Address(a1, base_offset)); 4516 lea(a2, Address(a2, base_offset)); 4517 // Check for short strings, i.e. smaller than wordSize. 4518 subs(cnt1, cnt1, elem_per_word); 4519 br(Assembler::LT, SHORT); 4520 // Main 8 byte comparison loop. 4521 bind(NEXT_WORD); { 4522 ldr(tmp1, Address(post(a1, wordSize))); 4523 ldr(tmp2, Address(post(a2, wordSize))); 4524 subs(cnt1, cnt1, elem_per_word); 4525 eor(tmp5, tmp1, tmp2); 4526 cbnz(tmp5, DONE); 4527 } br(GT, NEXT_WORD); 4528 // Last longword. In the case where length == 4 we compare the 4529 // same longword twice, but that's still faster than another 4530 // conditional branch. 4531 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 4532 // length == 4. 4533 if (log_elem_size > 0) 4534 lsl(cnt1, cnt1, log_elem_size); 4535 ldr(tmp3, Address(a1, cnt1)); 4536 ldr(tmp4, Address(a2, cnt1)); 4537 eor(tmp5, tmp3, tmp4); 4538 cbnz(tmp5, DONE); 4539 b(SAME); 4540 bind(A_MIGHT_BE_NULL); 4541 // in case both a1 and a2 are not-null, proceed with loads 4542 cbz(a1, DONE); 4543 cbz(a2, DONE); 4544 b(A_IS_NOT_NULL); 4545 bind(SHORT); 4546 4547 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. 4548 { 4549 ldrw(tmp1, Address(post(a1, 4))); 4550 ldrw(tmp2, Address(post(a2, 4))); 4551 eorw(tmp5, tmp1, tmp2); 4552 cbnzw(tmp5, DONE); 4553 } 4554 bind(TAIL03); 4555 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. 4556 { 4557 ldrh(tmp3, Address(post(a1, 2))); 4558 ldrh(tmp4, Address(post(a2, 2))); 4559 eorw(tmp5, tmp3, tmp4); 4560 cbnzw(tmp5, DONE); 4561 } 4562 bind(TAIL01); 4563 if (elem_size == 1) { // Only needed when comparing byte arrays. 4564 tbz(cnt1, 0, SAME); // 0-1 bytes left. 4565 { 4566 ldrb(tmp1, a1); 4567 ldrb(tmp2, a2); 4568 eorw(tmp5, tmp1, tmp2); 4569 cbnzw(tmp5, DONE); 4570 } 4571 } 4572 } else { 4573 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB, EARLY_OUT, 4574 CSET_EQ, LAST_CHECK; 4575 mov(result, false); 4576 cbz(a1, DONE); 4577 ldrw(cnt1, Address(a1, length_offset)); 4578 cbz(a2, DONE); 4579 ldrw(cnt2, Address(a2, length_offset)); 4580 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's 4581 // faster to perform another branch before comparing a1 and a2 4582 cmp(cnt1, (u1)elem_per_word); 4583 br(LE, SHORT); // short or same 4584 ldr(tmp3, Address(pre(a1, base_offset))); 4585 subs(zr, cnt1, stubBytesThreshold); 4586 br(GE, STUB); 4587 ldr(tmp4, Address(pre(a2, base_offset))); 4588 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); 4589 cmp(cnt2, cnt1); 4590 br(NE, DONE); 4591 4592 // Main 16 byte comparison loop with 2 exits 4593 bind(NEXT_DWORD); { 4594 ldr(tmp1, Address(pre(a1, wordSize))); 4595 ldr(tmp2, Address(pre(a2, wordSize))); 4596 subs(cnt1, cnt1, 2 * elem_per_word); 4597 br(LE, TAIL); 4598 eor(tmp4, tmp3, tmp4); 4599 cbnz(tmp4, DONE); 4600 ldr(tmp3, Address(pre(a1, wordSize))); 4601 ldr(tmp4, Address(pre(a2, wordSize))); 4602 cmp(cnt1, (u1)elem_per_word); 4603 br(LE, TAIL2); 4604 cmp(tmp1, tmp2); 4605 } br(EQ, NEXT_DWORD); 4606 b(DONE); 4607 4608 bind(TAIL); 4609 eor(tmp4, tmp3, tmp4); 4610 eor(tmp2, tmp1, tmp2); 4611 lslv(tmp2, tmp2, tmp5); 4612 orr(tmp5, tmp4, tmp2); 4613 cmp(tmp5, zr); 4614 b(CSET_EQ); 4615 4616 bind(TAIL2); 4617 eor(tmp2, tmp1, tmp2); 4618 cbnz(tmp2, DONE); 4619 b(LAST_CHECK); 4620 4621 bind(STUB); 4622 ldr(tmp4, Address(pre(a2, base_offset))); 4623 cmp(cnt2, cnt1); 4624 br(NE, DONE); 4625 if (elem_size == 2) { // convert to byte counter 4626 lsl(cnt1, cnt1, 1); 4627 } 4628 eor(tmp5, tmp3, tmp4); 4629 cbnz(tmp5, DONE); 4630 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals()); 4631 assert(stub.target() != NULL, "array_equals_long stub has not been generated"); 4632 trampoline_call(stub); 4633 b(DONE); 4634 4635 bind(EARLY_OUT); 4636 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2) 4637 // so, if a2 == null => return false(0), else return true, so we can return a2 4638 mov(result, a2); 4639 b(DONE); 4640 bind(SHORT); 4641 cmp(cnt2, cnt1); 4642 br(NE, DONE); 4643 cbz(cnt1, SAME); 4644 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); 4645 ldr(tmp3, Address(a1, base_offset)); 4646 ldr(tmp4, Address(a2, base_offset)); 4647 bind(LAST_CHECK); 4648 eor(tmp4, tmp3, tmp4); 4649 lslv(tmp5, tmp4, tmp5); 4650 cmp(tmp5, zr); 4651 bind(CSET_EQ); 4652 cset(result, EQ); 4653 b(DONE); 4654 } 4655 4656 bind(SAME); 4657 mov(result, true); 4658 // That's it. 4659 bind(DONE); 4660 4661 BLOCK_COMMENT("} array_equals"); 4662 } 4663 4664 // Compare Strings 4665 4666 // For Strings we're passed the address of the first characters in a1 4667 // and a2 and the length in cnt1. 4668 // elem_size is the element size in bytes: either 1 or 2. 4669 // There are two implementations. For arrays >= 8 bytes, all 4670 // comparisons (including the final one, which may overlap) are 4671 // performed 8 bytes at a time. For strings < 8 bytes, we compare a 4672 // halfword, then a short, and then a byte. 4673 4674 void MacroAssembler::string_equals(Register a1, Register a2, 4675 Register result, Register cnt1, int elem_size) 4676 { 4677 Label SAME, DONE, SHORT, NEXT_WORD; 4678 Register tmp1 = rscratch1; 4679 Register tmp2 = rscratch2; 4680 Register cnt2 = tmp2; // cnt2 only used in array length compare 4681 4682 assert(elem_size == 1 || elem_size == 2, "must be 2 or 1 byte"); 4683 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 4684 4685 #ifndef PRODUCT 4686 { 4687 const char kind = (elem_size == 2) ? 'U' : 'L'; 4688 char comment[64]; 4689 snprintf(comment, sizeof comment, "{string_equals%c", kind); 4690 BLOCK_COMMENT(comment); 4691 } 4692 #endif 4693 4694 mov(result, false); 4695 4696 // Check for short strings, i.e. smaller than wordSize. 4697 subs(cnt1, cnt1, wordSize); 4698 br(Assembler::LT, SHORT); 4699 // Main 8 byte comparison loop. 4700 bind(NEXT_WORD); { 4701 ldr(tmp1, Address(post(a1, wordSize))); 4702 ldr(tmp2, Address(post(a2, wordSize))); 4703 subs(cnt1, cnt1, wordSize); 4704 eor(tmp1, tmp1, tmp2); 4705 cbnz(tmp1, DONE); 4706 } br(GT, NEXT_WORD); 4707 // Last longword. In the case where length == 4 we compare the 4708 // same longword twice, but that's still faster than another 4709 // conditional branch. 4710 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 4711 // length == 4. 4712 ldr(tmp1, Address(a1, cnt1)); 4713 ldr(tmp2, Address(a2, cnt1)); 4714 eor(tmp2, tmp1, tmp2); 4715 cbnz(tmp2, DONE); 4716 b(SAME); 4717 4718 bind(SHORT); 4719 Label TAIL03, TAIL01; 4720 4721 tbz(cnt1, 2, TAIL03); // 0-7 bytes left. 4722 { 4723 ldrw(tmp1, Address(post(a1, 4))); 4724 ldrw(tmp2, Address(post(a2, 4))); 4725 eorw(tmp1, tmp1, tmp2); 4726 cbnzw(tmp1, DONE); 4727 } 4728 bind(TAIL03); 4729 tbz(cnt1, 1, TAIL01); // 0-3 bytes left. 4730 { 4731 ldrh(tmp1, Address(post(a1, 2))); 4732 ldrh(tmp2, Address(post(a2, 2))); 4733 eorw(tmp1, tmp1, tmp2); 4734 cbnzw(tmp1, DONE); 4735 } 4736 bind(TAIL01); 4737 if (elem_size == 1) { // Only needed when comparing 1-byte elements 4738 tbz(cnt1, 0, SAME); // 0-1 bytes left. 4739 { 4740 ldrb(tmp1, a1); 4741 ldrb(tmp2, a2); 4742 eorw(tmp1, tmp1, tmp2); 4743 cbnzw(tmp1, DONE); 4744 } 4745 } 4746 // Arrays are equal. 4747 bind(SAME); 4748 mov(result, true); 4749 4750 // That's it. 4751 bind(DONE); 4752 BLOCK_COMMENT("} string_equals"); 4753 } 4754 4755 4756 // The size of the blocks erased by the zero_blocks stub. We must 4757 // handle anything smaller than this ourselves in zero_words(). 4758 const int MacroAssembler::zero_words_block_size = 8; 4759 4760 // zero_words() is used by C2 ClearArray patterns. It is as small as 4761 // possible, handling small word counts locally and delegating 4762 // anything larger to the zero_blocks stub. It is expanded many times 4763 // in compiled code, so it is important to keep it short. 4764 4765 // ptr: Address of a buffer to be zeroed. 4766 // cnt: Count in HeapWords. 4767 // 4768 // ptr, cnt, rscratch1, and rscratch2 are clobbered. 4769 void MacroAssembler::zero_words(Register ptr, Register cnt) 4770 { 4771 assert(is_power_of_2(zero_words_block_size), "adjust this"); 4772 assert(ptr == r10 && cnt == r11, "mismatch in register usage"); 4773 4774 BLOCK_COMMENT("zero_words {"); 4775 cmp(cnt, (u1)zero_words_block_size); 4776 Label around; 4777 br(LO, around); 4778 { 4779 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); 4780 assert(zero_blocks.target() != NULL, "zero_blocks stub has not been generated"); 4781 if (StubRoutines::aarch64::complete()) { 4782 trampoline_call(zero_blocks); 4783 } else { 4784 bl(zero_blocks); 4785 } 4786 } 4787 bind(around); 4788 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) { 4789 Label l; 4790 tbz(cnt, exact_log2(i), l); 4791 for (int j = 0; j < i; j += 2) { 4792 stp(zr, zr, post(ptr, 16)); 4793 } 4794 bind(l); 4795 } 4796 { 4797 Label l; 4798 tbz(cnt, 0, l); 4799 str(zr, Address(ptr)); 4800 bind(l); 4801 } 4802 BLOCK_COMMENT("} zero_words"); 4803 } 4804 4805 // base: Address of a buffer to be zeroed, 8 bytes aligned. 4806 // cnt: Immediate count in HeapWords. 4807 #define SmallArraySize (18 * BytesPerLong) 4808 void MacroAssembler::zero_words(Register base, uint64_t cnt) 4809 { 4810 BLOCK_COMMENT("zero_words {"); 4811 int i = cnt & 1; // store any odd word to start 4812 if (i) str(zr, Address(base)); 4813 4814 if (cnt <= SmallArraySize / BytesPerLong) { 4815 for (; i < (int)cnt; i += 2) 4816 stp(zr, zr, Address(base, i * wordSize)); 4817 } else { 4818 const int unroll = 4; // Number of stp(zr, zr) instructions we'll unroll 4819 int remainder = cnt % (2 * unroll); 4820 for (; i < remainder; i += 2) 4821 stp(zr, zr, Address(base, i * wordSize)); 4822 4823 Label loop; 4824 Register cnt_reg = rscratch1; 4825 Register loop_base = rscratch2; 4826 cnt = cnt - remainder; 4827 mov(cnt_reg, cnt); 4828 // adjust base and prebias by -2 * wordSize so we can pre-increment 4829 add(loop_base, base, (remainder - 2) * wordSize); 4830 bind(loop); 4831 sub(cnt_reg, cnt_reg, 2 * unroll); 4832 for (i = 1; i < unroll; i++) 4833 stp(zr, zr, Address(loop_base, 2 * i * wordSize)); 4834 stp(zr, zr, Address(pre(loop_base, 2 * unroll * wordSize))); 4835 cbnz(cnt_reg, loop); 4836 } 4837 BLOCK_COMMENT("} zero_words"); 4838 } 4839 4840 // Zero blocks of memory by using DC ZVA. 4841 // 4842 // Aligns the base address first sufficently for DC ZVA, then uses 4843 // DC ZVA repeatedly for every full block. cnt is the size to be 4844 // zeroed in HeapWords. Returns the count of words left to be zeroed 4845 // in cnt. 4846 // 4847 // NOTE: This is intended to be used in the zero_blocks() stub. If 4848 // you want to use it elsewhere, note that cnt must be >= 2*zva_length. 4849 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) { 4850 Register tmp = rscratch1; 4851 Register tmp2 = rscratch2; 4852 int zva_length = VM_Version::zva_length(); 4853 Label initial_table_end, loop_zva; 4854 Label fini; 4855 4856 // Base must be 16 byte aligned. If not just return and let caller handle it 4857 tst(base, 0x0f); 4858 br(Assembler::NE, fini); 4859 // Align base with ZVA length. 4860 neg(tmp, base); 4861 andr(tmp, tmp, zva_length - 1); 4862 4863 // tmp: the number of bytes to be filled to align the base with ZVA length. 4864 add(base, base, tmp); 4865 sub(cnt, cnt, tmp, Assembler::ASR, 3); 4866 adr(tmp2, initial_table_end); 4867 sub(tmp2, tmp2, tmp, Assembler::LSR, 2); 4868 br(tmp2); 4869 4870 for (int i = -zva_length + 16; i < 0; i += 16) 4871 stp(zr, zr, Address(base, i)); 4872 bind(initial_table_end); 4873 4874 sub(cnt, cnt, zva_length >> 3); 4875 bind(loop_zva); 4876 dc(Assembler::ZVA, base); 4877 subs(cnt, cnt, zva_length >> 3); 4878 add(base, base, zva_length); 4879 br(Assembler::GE, loop_zva); 4880 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA 4881 bind(fini); 4882 } 4883 4884 // base: Address of a buffer to be filled, 8 bytes aligned. 4885 // cnt: Count in 8-byte unit. 4886 // value: Value to be filled with. 4887 // base will point to the end of the buffer after filling. 4888 void MacroAssembler::fill_words(Register base, Register cnt, Register value) 4889 { 4890 // Algorithm: 4891 // 4892 // scratch1 = cnt & 7; 4893 // cnt -= scratch1; 4894 // p += scratch1; 4895 // switch (scratch1) { 4896 // do { 4897 // cnt -= 8; 4898 // p[-8] = v; 4899 // case 7: 4900 // p[-7] = v; 4901 // case 6: 4902 // p[-6] = v; 4903 // // ... 4904 // case 1: 4905 // p[-1] = v; 4906 // case 0: 4907 // p += 8; 4908 // } while (cnt); 4909 // } 4910 4911 assert_different_registers(base, cnt, value, rscratch1, rscratch2); 4912 4913 Label fini, skip, entry, loop; 4914 const int unroll = 8; // Number of stp instructions we'll unroll 4915 4916 cbz(cnt, fini); 4917 tbz(base, 3, skip); 4918 str(value, Address(post(base, 8))); 4919 sub(cnt, cnt, 1); 4920 bind(skip); 4921 4922 andr(rscratch1, cnt, (unroll-1) * 2); 4923 sub(cnt, cnt, rscratch1); 4924 add(base, base, rscratch1, Assembler::LSL, 3); 4925 adr(rscratch2, entry); 4926 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1); 4927 br(rscratch2); 4928 4929 bind(loop); 4930 add(base, base, unroll * 16); 4931 for (int i = -unroll; i < 0; i++) 4932 stp(value, value, Address(base, i * 16)); 4933 bind(entry); 4934 subs(cnt, cnt, unroll * 2); 4935 br(Assembler::GE, loop); 4936 4937 tbz(cnt, 0, fini); 4938 str(value, Address(post(base, 8))); 4939 bind(fini); 4940 } 4941 4942 // Intrinsic for sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray and 4943 // java/lang/StringUTF16.compress. 4944 void MacroAssembler::encode_iso_array(Register src, Register dst, 4945 Register len, Register result, 4946 FloatRegister Vtmp1, FloatRegister Vtmp2, 4947 FloatRegister Vtmp3, FloatRegister Vtmp4) 4948 { 4949 Label DONE, SET_RESULT, NEXT_32, NEXT_32_PRFM, LOOP_8, NEXT_8, LOOP_1, NEXT_1, 4950 NEXT_32_START, NEXT_32_PRFM_START; 4951 Register tmp1 = rscratch1, tmp2 = rscratch2; 4952 4953 mov(result, len); // Save initial len 4954 4955 cmp(len, (u1)8); // handle shortest strings first 4956 br(LT, LOOP_1); 4957 cmp(len, (u1)32); 4958 br(LT, NEXT_8); 4959 // The following code uses the SIMD 'uzp1' and 'uzp2' instructions 4960 // to convert chars to bytes 4961 if (SoftwarePrefetchHintDistance >= 0) { 4962 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4963 subs(tmp2, len, SoftwarePrefetchHintDistance/2 + 16); 4964 br(LE, NEXT_32_START); 4965 b(NEXT_32_PRFM_START); 4966 BIND(NEXT_32_PRFM); 4967 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4968 BIND(NEXT_32_PRFM_START); 4969 prfm(Address(src, SoftwarePrefetchHintDistance)); 4970 orr(v4, T16B, Vtmp1, Vtmp2); 4971 orr(v5, T16B, Vtmp3, Vtmp4); 4972 uzp1(Vtmp1, T16B, Vtmp1, Vtmp2); 4973 uzp1(Vtmp3, T16B, Vtmp3, Vtmp4); 4974 uzp2(v5, T16B, v4, v5); // high bytes 4975 umov(tmp2, v5, D, 1); 4976 fmovd(tmp1, v5); 4977 orr(tmp1, tmp1, tmp2); 4978 cbnz(tmp1, LOOP_8); 4979 stpq(Vtmp1, Vtmp3, dst); 4980 sub(len, len, 32); 4981 add(dst, dst, 32); 4982 add(src, src, 64); 4983 subs(tmp2, len, SoftwarePrefetchHintDistance/2 + 16); 4984 br(GE, NEXT_32_PRFM); 4985 cmp(len, (u1)32); 4986 br(LT, LOOP_8); 4987 BIND(NEXT_32); 4988 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4989 BIND(NEXT_32_START); 4990 } else { 4991 BIND(NEXT_32); 4992 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4993 } 4994 prfm(Address(src, SoftwarePrefetchHintDistance)); 4995 uzp1(v4, T16B, Vtmp1, Vtmp2); 4996 uzp1(v5, T16B, Vtmp3, Vtmp4); 4997 orr(Vtmp1, T16B, Vtmp1, Vtmp2); 4998 orr(Vtmp3, T16B, Vtmp3, Vtmp4); 4999 uzp2(Vtmp1, T16B, Vtmp1, Vtmp3); // high bytes 5000 umov(tmp2, Vtmp1, D, 1); 5001 fmovd(tmp1, Vtmp1); 5002 orr(tmp1, tmp1, tmp2); 5003 cbnz(tmp1, LOOP_8); 5004 stpq(v4, v5, dst); 5005 sub(len, len, 32); 5006 add(dst, dst, 32); 5007 add(src, src, 64); 5008 cmp(len, (u1)32); 5009 br(GE, NEXT_32); 5010 cbz(len, DONE); 5011 5012 BIND(LOOP_8); 5013 cmp(len, (u1)8); 5014 br(LT, LOOP_1); 5015 BIND(NEXT_8); 5016 ld1(Vtmp1, T8H, src); 5017 uzp1(Vtmp2, T16B, Vtmp1, Vtmp1); // low bytes 5018 uzp2(Vtmp3, T16B, Vtmp1, Vtmp1); // high bytes 5019 fmovd(tmp1, Vtmp3); 5020 cbnz(tmp1, NEXT_1); 5021 strd(Vtmp2, dst); 5022 5023 sub(len, len, 8); 5024 add(dst, dst, 8); 5025 add(src, src, 16); 5026 cmp(len, (u1)8); 5027 br(GE, NEXT_8); 5028 5029 BIND(LOOP_1); 5030 5031 cbz(len, DONE); 5032 BIND(NEXT_1); 5033 ldrh(tmp1, Address(post(src, 2))); 5034 tst(tmp1, 0xff00); 5035 br(NE, SET_RESULT); 5036 strb(tmp1, Address(post(dst, 1))); 5037 subs(len, len, 1); 5038 br(GT, NEXT_1); 5039 5040 BIND(SET_RESULT); 5041 sub(result, result, len); // Return index where we stopped 5042 // Return len == 0 if we processed all 5043 // characters 5044 BIND(DONE); 5045 } 5046 5047 5048 // Inflate byte[] array to char[]. 5049 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 5050 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, 5051 Register tmp4) { 5052 Label big, done, after_init, to_stub; 5053 5054 assert_different_registers(src, dst, len, tmp4, rscratch1); 5055 5056 fmovd(vtmp1, zr); 5057 lsrw(tmp4, len, 3); 5058 bind(after_init); 5059 cbnzw(tmp4, big); 5060 // Short string: less than 8 bytes. 5061 { 5062 Label loop, tiny; 5063 5064 cmpw(len, 4); 5065 br(LT, tiny); 5066 // Use SIMD to do 4 bytes. 5067 ldrs(vtmp2, post(src, 4)); 5068 zip1(vtmp3, T8B, vtmp2, vtmp1); 5069 subw(len, len, 4); 5070 strd(vtmp3, post(dst, 8)); 5071 5072 cbzw(len, done); 5073 5074 // Do the remaining bytes by steam. 5075 bind(loop); 5076 ldrb(tmp4, post(src, 1)); 5077 strh(tmp4, post(dst, 2)); 5078 subw(len, len, 1); 5079 5080 bind(tiny); 5081 cbnz(len, loop); 5082 5083 b(done); 5084 } 5085 5086 if (SoftwarePrefetchHintDistance >= 0) { 5087 bind(to_stub); 5088 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate()); 5089 assert(stub.target() != NULL, "large_byte_array_inflate stub has not been generated"); 5090 trampoline_call(stub); 5091 b(after_init); 5092 } 5093 5094 // Unpack the bytes 8 at a time. 5095 bind(big); 5096 { 5097 Label loop, around, loop_last, loop_start; 5098 5099 if (SoftwarePrefetchHintDistance >= 0) { 5100 const int large_loop_threshold = (64 + 16)/8; 5101 ldrd(vtmp2, post(src, 8)); 5102 andw(len, len, 7); 5103 cmp(tmp4, (u1)large_loop_threshold); 5104 br(GE, to_stub); 5105 b(loop_start); 5106 5107 bind(loop); 5108 ldrd(vtmp2, post(src, 8)); 5109 bind(loop_start); 5110 subs(tmp4, tmp4, 1); 5111 br(EQ, loop_last); 5112 zip1(vtmp2, T16B, vtmp2, vtmp1); 5113 ldrd(vtmp3, post(src, 8)); 5114 st1(vtmp2, T8H, post(dst, 16)); 5115 subs(tmp4, tmp4, 1); 5116 zip1(vtmp3, T16B, vtmp3, vtmp1); 5117 st1(vtmp3, T8H, post(dst, 16)); 5118 br(NE, loop); 5119 b(around); 5120 bind(loop_last); 5121 zip1(vtmp2, T16B, vtmp2, vtmp1); 5122 st1(vtmp2, T8H, post(dst, 16)); 5123 bind(around); 5124 cbz(len, done); 5125 } else { 5126 andw(len, len, 7); 5127 bind(loop); 5128 ldrd(vtmp2, post(src, 8)); 5129 sub(tmp4, tmp4, 1); 5130 zip1(vtmp3, T16B, vtmp2, vtmp1); 5131 st1(vtmp3, T8H, post(dst, 16)); 5132 cbnz(tmp4, loop); 5133 } 5134 } 5135 5136 // Do the tail of up to 8 bytes. 5137 add(src, src, len); 5138 ldrd(vtmp3, Address(src, -8)); 5139 add(dst, dst, len, ext::uxtw, 1); 5140 zip1(vtmp3, T16B, vtmp3, vtmp1); 5141 strq(vtmp3, Address(dst, -16)); 5142 5143 bind(done); 5144 } 5145 5146 // Compress char[] array to byte[]. 5147 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 5148 FloatRegister tmp1Reg, FloatRegister tmp2Reg, 5149 FloatRegister tmp3Reg, FloatRegister tmp4Reg, 5150 Register result) { 5151 encode_iso_array(src, dst, len, result, 5152 tmp1Reg, tmp2Reg, tmp3Reg, tmp4Reg); 5153 cmp(len, zr); 5154 csel(result, result, zr, EQ); 5155 } 5156 5157 // get_thread() can be called anywhere inside generated code so we 5158 // need to save whatever non-callee save context might get clobbered 5159 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 5160 // the call setup code. 5161 // 5162 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 5163 // 5164 void MacroAssembler::get_thread(Register dst) { 5165 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 5166 push(saved_regs, sp); 5167 5168 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 5169 blr(lr); 5170 if (dst != c_rarg0) { 5171 mov(dst, c_rarg0); 5172 } 5173 5174 pop(saved_regs, sp); 5175 } 5176 5177 void MacroAssembler::cache_wb(Address line) { 5178 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset"); 5179 assert(line.index() == noreg, "index should be noreg"); 5180 assert(line.offset() == 0, "offset should be 0"); 5181 // would like to assert this 5182 // assert(line._ext.shift == 0, "shift should be zero"); 5183 if (VM_Version::supports_dcpop()) { 5184 // writeback using clear virtual address to point of persistence 5185 dc(Assembler::CVAP, line.base()); 5186 } else { 5187 // no need to generate anything as Unsafe.writebackMemory should 5188 // never invoke this stub 5189 } 5190 } 5191 5192 void MacroAssembler::cache_wbsync(bool is_pre) { 5193 // we only need a barrier post sync 5194 if (!is_pre) { 5195 membar(Assembler::AnyAny); 5196 } 5197 }